{"meta":{"query_hash":"9213d3870a3a","filters":{"topic":"VLSI and FPGA Design Techniques"},"cohort_total":673,"direct_labels_cover":0,"predictions_cover":673,"exported":673,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/9213d3870a3a","api":"https://metacan.xera.ac/api/v1/cohort?topic=VLSI+and+FPGA+Design+Techniques"},"results":[{"id":"W1013700976","doi":"10.1007/978-3-319-20071-2_1","title":"Sizing Digital Circuits Using Convex Optimization Techniques","year":2015,"lang":"en","type":"book-chapter","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Sizing; Regular polygon; Electronic circuit; Computer science; Digital electronics; Electronic engineering; Mathematics; Electrical engineering; Engineering; Chemistry; Geometry","score_opus":0.0478437612850758,"score_gpt":0.23195979614192846,"score_spread":0.18411603485685266,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1013700976","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[8.1134925e-7,0.0005147349,0.42682153,0.0000020138232,0.00007929355,0.0002044094,0.000021853126,0.0025001008,0.5698553],"genre_scores_gemma":[0.06972173,0.0019106374,0.19630049,0.00021902434,0.0021437446,0.000078793215,0.0009217149,0.001942637,0.7267612],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9989737,0.0000029400594,0.00033225317,0.0002383037,0.00023683978,0.00021593276],"domain_scores_gemma":[0.9993823,0.000019084817,0.000066621484,0.00028884696,0.00014064173,0.00010249054],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00009284585,0.00038510017,0.00037743457,0.00024278654,0.000037106904,0.00014929437,0.00017407947,0.0005528207,0.00033276333],"category_scores_gemma":[0.000010629638,0.00040504616,0.0000980908,0.000033076845,0.000045068686,0.00035698118,0.000049182927,0.00029057072,0.00004047286],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001095059,0.00004946813,0.000020471214,0.0011087978,0.00081050943,0.00026062145,0.00036982386,0.08070248,0.0065153637,0.1460023,0.08473451,0.6794147],"study_design_scores_gemma":[0.0003460121,0.00021222698,3.2886248e-7,0.001620339,0.0002454978,0.00023291368,0.000029892957,0.31267226,0.01936875,0.04329712,0.61794025,0.004034447],"about_ca_topic_score_codex":0.0000024655462,"about_ca_topic_score_gemma":3.716137e-7,"teacher_disagreement_score":0.6753803,"about_ca_system_score_codex":0.00023028062,"about_ca_system_score_gemma":0.000039775525,"threshold_uncertainty_score":0.99984014},"labels":[],"label_agreement":null},{"id":"W10199753","doi":"10.1210/jcem.84.4.5617","title":"The Steiner Ratio for Obstacle-Avoiding Rectilinear Steiner Trees","year":2008,"lang":"en","type":"article","venue":"Canadian Conference on Computational Geometry","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Obstacle; Combinatorics; Mathematics; Set (abstract data type); Computer science; Discrete mathematics; Mathematical optimization; Geography","score_opus":0.04271413218695374,"score_gpt":0.23622477898947547,"score_spread":0.19351064680252172,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W10199753","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3581877,0.0012707169,0.6048782,0.0027590839,0.0018861139,0.0018179185,0.0005404605,0.00127643,0.027383413],"genre_scores_gemma":[0.9957785,0.000046798774,0.0024201933,0.00025286252,0.00017560604,0.000074355296,0.00007533205,0.000034551573,0.0011417927],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990236,0.00002987431,0.00022428119,0.00018915148,0.00018463147,0.000348466],"domain_scores_gemma":[0.99886876,0.00050021627,0.00003089206,0.00016925632,0.00021312949,0.0002177669],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018150425,0.0001707198,0.00014842619,0.0002726692,0.0005596302,0.000092475886,0.00021316248,0.00009100174,0.00005851818],"category_scores_gemma":[0.00012742655,0.00014707475,0.000066369474,0.00030441975,0.00007203888,0.0000981013,0.000007447068,0.00020882214,0.000039868017],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007247236,0.000057836092,0.0022422152,0.00010807244,0.0003570464,0.00009283508,0.0011223084,0.4268127,0.0024156608,0.21880485,0.19854376,0.14937025],"study_design_scores_gemma":[0.0007027058,0.00025082642,0.008589248,0.00007348262,0.000018798213,0.000057866368,0.000272223,0.8845611,0.0025290558,0.009102995,0.093097724,0.00074392935],"about_ca_topic_score_codex":0.00066185213,"about_ca_topic_score_gemma":0.0048584323,"teacher_disagreement_score":0.6375908,"about_ca_system_score_codex":0.00018135401,"about_ca_system_score_gemma":0.00033957994,"threshold_uncertainty_score":0.5997534},"labels":[],"label_agreement":null},{"id":"W114833178","doi":"","title":"An addition structure on incidence matrices of a BIB design.","year":2006,"lang":"en","type":"article","venue":"Ars Combinatoria","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Mathematics; Pure mathematics","score_opus":0.0063139874599083224,"score_gpt":0.21114655383359515,"score_spread":0.20483256637368683,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W114833178","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.99206936,0.00019282564,0.0051894546,0.00000609344,0.00040074575,0.00021079533,0.000030785224,0.00063408585,0.0012658578],"genre_scores_gemma":[0.9971345,0.0000216211,0.0027558068,0.000009343072,0.000014952329,0.000011808581,0.00002210477,0.000022855398,0.000006986845],"study_design_codex":"bench_or_experimental","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9994037,0.000032390177,0.00016294654,0.00011501539,0.00015274946,0.00013319081],"domain_scores_gemma":[0.9996175,0.000053077947,0.000041441293,0.00021721543,0.000039881113,0.00003087537],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000076891425,0.00011625059,0.00013066106,0.00013853311,0.000029927212,0.000020111922,0.00016069149,0.000099656696,0.000052086438],"category_scores_gemma":[0.00000817551,0.0001142377,0.000026695529,0.00025441864,0.000020197664,0.00017758126,0.0000072382886,0.000104005165,0.000007154463],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000051119274,0.0002482231,0.0018140407,0.00019389241,0.0000433477,0.00005214021,0.0002376114,0.014720082,0.48917964,0.43732533,0.04491569,0.011218884],"study_design_scores_gemma":[0.0002481949,0.00032305933,0.005565729,0.00006284966,0.000013827513,0.000004739026,0.000010037213,0.005740779,0.44451845,0.543092,0.00020225054,0.00021809865],"about_ca_topic_score_codex":0.000038220212,"about_ca_topic_score_gemma":0.0000026575008,"teacher_disagreement_score":0.10576667,"about_ca_system_score_codex":0.00003810411,"about_ca_system_score_gemma":0.000009091174,"threshold_uncertainty_score":0.46584782},"labels":[],"label_agreement":null},{"id":"W117982534","doi":"","title":"Inducing regularization of graphs, multigraphs and pseudographs.","year":2002,"lang":"en","type":"article","venue":"Ars Combinatoria","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Mathematics; Regularization (linguistics); Combinatorics; Artificial intelligence; Computer science","score_opus":0.009950917027663106,"score_gpt":0.1897302259514448,"score_spread":0.1797793089237817,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W117982534","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.99374336,0.0015777223,0.0005169195,0.000013384345,0.0003349793,0.0001612127,0.0000029139676,0.0004724388,0.0031770973],"genre_scores_gemma":[0.99835,0.00048492366,0.0010950577,0.000008852726,0.0000020201928,0.000010866727,0.0000028437469,0.000022516828,0.000022884058],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9994377,0.000017941877,0.0001817993,0.000119961944,0.00010402454,0.00013859397],"domain_scores_gemma":[0.9996692,0.000026852113,0.00003321595,0.00018704483,0.00003496501,0.000048743423],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000088298184,0.00011208368,0.00014973705,0.00020810527,0.000037695547,0.00001496241,0.000083377614,0.00010253173,0.00001925196],"category_scores_gemma":[0.000014290689,0.00012044305,0.000042389896,0.0003887075,0.00005020183,0.00012743713,0.000014806934,0.000102888174,0.0000018029262],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005841205,0.00018436609,0.041320536,0.0003338048,0.00017497783,0.000012051403,0.0021455048,0.00009763733,0.1207792,0.7753761,0.008980697,0.050589275],"study_design_scores_gemma":[0.0014532456,0.00023496714,0.020292543,0.00020756236,0.00007092687,0.00002757448,0.000101639176,0.026564132,0.20042697,0.7492393,0.00065435626,0.00072677765],"about_ca_topic_score_codex":0.000009995723,"about_ca_topic_score_gemma":7.975618e-7,"teacher_disagreement_score":0.079647765,"about_ca_system_score_codex":0.000007641213,"about_ca_system_score_gemma":0.0000012361749,"threshold_uncertainty_score":0.4911525},"labels":[],"label_agreement":null},{"id":"W139568493","doi":"10.1023/a:1019258807615","title":"A Graphical Approach to Allocating Class Fragments in Distributed Objectbase Systems","year":2001,"lang":"en","type":"article","venue":"Distributed and Parallel Databases","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Overhead (engineering); Scheme (mathematics); Mathematical optimization; Optimization algorithm; Mathematics","score_opus":0.025049053546780962,"score_gpt":0.24733264465686508,"score_spread":0.2222835911100841,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W139568493","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21910393,0.0015577812,0.77146506,0.000062209416,0.00010699677,0.00068127865,0.0054412954,0.0007171545,0.0008642562],"genre_scores_gemma":[0.98839736,0.00047013117,0.0026468474,0.00004536405,0.000057363468,0.00024943711,0.008095315,0.000029691268,0.000008514507],"study_design_codex":"observational","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984839,0.00006437889,0.000389978,0.00037311207,0.0001960115,0.0004926412],"domain_scores_gemma":[0.99914235,0.00008332727,0.000033637712,0.00046556565,0.00003514919,0.00023996315],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00021980454,0.0002842884,0.00034607737,0.00016615853,0.000092494476,0.00008481353,0.0002599589,0.0001026073,0.0000073503998],"category_scores_gemma":[0.00010372447,0.00027488515,0.0000446763,0.00068910135,0.000042274944,0.00020307497,0.00011043875,0.00025428357,0.000009318905],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00076552073,0.0032065688,0.4057593,0.0029463132,0.0007766916,0.0014177934,0.0012827634,0.27019915,0.019607047,0.040826812,0.24173059,0.011481429],"study_design_scores_gemma":[0.005092418,0.0003566656,0.06481698,0.0014705197,0.00017385563,0.0005141491,0.0032607024,0.7205172,0.0017082458,0.0005848915,0.19767517,0.0038291868],"about_ca_topic_score_codex":0.00034792803,"about_ca_topic_score_gemma":0.00004910807,"teacher_disagreement_score":0.7692934,"about_ca_system_score_codex":0.000074946285,"about_ca_system_score_gemma":0.0000150769,"threshold_uncertainty_score":0.9999703},"labels":[],"label_agreement":null},{"id":"W147160966","doi":"10.1007/978-1-4419-0739-4_3","title":"Measuring the Gap","year":2010,"lang":"en","type":"book-chapter","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Application-specific integrated circuit; Block (permutation group theory); Power consumption; Dimension (graph theory); Computer science; Power (physics); Architecture; Bandgap voltage reference; Measure (data warehouse); Key (lock); Process (computing); Electronic engineering; Embedded system; Engineering; Electrical engineering; Mathematics; Data mining; Computer security","score_opus":0.03896632148578915,"score_gpt":0.19272237947438048,"score_spread":0.15375605798859132,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W147160966","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0000022135064,0.00045379356,0.010225901,0.000028988046,0.0002577026,0.00013632305,0.0000030299816,0.0012458744,0.98764616],"genre_scores_gemma":[0.011286095,0.0004740987,0.0024355808,0.00011030026,0.00052795705,0.000019307938,0.0000056600143,0.00016051323,0.98498046],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"not_applicable","domain_scores_codex":[0.99953145,0.0000015672848,0.00012279348,0.000098714416,0.00012502255,0.00012042637],"domain_scores_gemma":[0.999559,0.000024130373,0.000015408046,0.0003498458,0.000020233847,0.00003141334],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00009269613,0.0001862788,0.00013842556,0.00004899007,0.000040312818,0.000030485447,0.00022289602,0.00031515548,0.001224753],"category_scores_gemma":[0.000002983473,0.00012221187,0.00008656738,0.000006781827,0.00003081966,0.000025861995,0.000026835763,0.000628393,0.00035798777],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000002043842,0.000003966185,0.0000027365058,0.00016294292,0.00022288556,0.00003147464,0.00014765648,0.000033098593,0.019233815,0.7868652,0.07678218,0.11651203],"study_design_scores_gemma":[0.000023692419,0.0000066651396,0.0000021139865,0.00004547749,0.00002123884,0.000011947347,0.0000011416716,0.00013296059,0.012926393,0.041570444,0.9449973,0.00026060414],"about_ca_topic_score_codex":0.0000030742954,"about_ca_topic_score_gemma":0.00001779698,"teacher_disagreement_score":0.86821514,"about_ca_system_score_codex":0.000018737293,"about_ca_system_score_gemma":0.000006421701,"threshold_uncertainty_score":0.99968827},"labels":[],"label_agreement":null},{"id":"W1480203124","doi":"10.1109/fpt.2002.1188684","title":"Power-aware technology mapping for LUT-based FPGAs","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":65,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Lookup table; Computer science; Field-programmable gate array; Routing (electronic design automation); Replication (statistics); Logic gate; Power (physics); Logic synthesis; Computer architecture; Embedded system; Algorithm","score_opus":0.010276351642210182,"score_gpt":0.20837335737935833,"score_spread":0.19809700573714814,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1480203124","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004550197,0.00014885039,0.96210533,0.00011714966,0.00011414822,0.0002781254,0.0000047648,0.0027314436,0.029949978],"genre_scores_gemma":[0.9381806,0.0000057919424,0.061227925,0.000111512505,0.000010576076,0.00011905245,0.0000030708352,0.000034679288,0.0003067791],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994481,0.000005392457,0.00013160054,0.0001230367,0.000047492056,0.00024435672],"domain_scores_gemma":[0.99969226,0.000030026189,0.000011001396,0.00020174395,0.00003199441,0.000032960772],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000088108216,0.00011556278,0.00012605265,0.00020158578,0.000038773665,0.00001357914,0.00010433698,0.00015279377,0.00017018802],"category_scores_gemma":[0.000029023413,0.00011201661,0.00005066316,0.00021499276,0.000018900204,0.000039771323,0.0000051636616,0.000085591106,0.000025236215],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019759053,0.00023949578,0.0028972416,0.0008966133,0.00023225448,0.00005374429,0.0003726229,0.0065897065,0.4127663,0.27847943,0.23347367,0.06397917],"study_design_scores_gemma":[0.00046836663,0.00011267818,0.000024453,0.00003842733,0.0000073833507,0.000010841218,0.00020124554,0.01672536,0.6998399,0.008431645,0.27373794,0.00040176368],"about_ca_topic_score_codex":8.0165313e-7,"about_ca_topic_score_gemma":0.0000012545203,"teacher_disagreement_score":0.9336304,"about_ca_system_score_codex":0.000035790148,"about_ca_system_score_gemma":0.00001335654,"threshold_uncertainty_score":0.45679048},"labels":[],"label_agreement":null},{"id":"W1481821439","doi":"10.1109/fpt.2002.1188685","title":"Synthesizing datapath circuits for FPGAs with emphasis on area minimization","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Datapath; Computer science; Field-programmable gate array; Overhead (engineering); Reconfigurability; Routing (electronic design automation); Algorithm; Parallel computing; High-level synthesis; Logic synthesis; Minification; Logic gate; Computer hardware; Embedded system; Telecommunications","score_opus":0.026393417415445077,"score_gpt":0.21226093705659838,"score_spread":0.1858675196411533,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1481821439","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008054045,0.000050471033,0.9407437,0.000013195283,0.000048175498,0.00033217168,0.0000132369305,0.0008083003,0.049936738],"genre_scores_gemma":[0.9770849,0.000029450408,0.022418717,0.00007046363,0.000019694566,0.00009068885,0.000017126229,0.000043085918,0.00022586933],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995047,0.000010057886,0.00010286598,0.00013888835,0.000078534904,0.00016495395],"domain_scores_gemma":[0.99965286,0.000079018144,0.0000139788435,0.00018895855,0.000026020318,0.000039166254],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008448665,0.00011714883,0.00010899613,0.0000710625,0.000041956104,0.000029268258,0.00006665828,0.000053556778,0.000059365804],"category_scores_gemma":[0.000044170178,0.000095605654,0.000023426493,0.000098862474,0.000007951328,0.000105079096,0.0000022488587,0.000038569848,0.0000072543553],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000762996,0.00046165576,0.0025873752,0.00089616864,0.00050163816,0.000045972076,0.0014865991,0.047531314,0.07115882,0.09235229,0.092110634,0.69079125],"study_design_scores_gemma":[0.0006529773,0.00032012435,0.00014445087,0.00020910906,0.000060443777,0.000024186587,0.00016063305,0.035431497,0.9072025,0.0007783625,0.05435185,0.0006638532],"about_ca_topic_score_codex":0.000001419808,"about_ca_topic_score_gemma":0.0000036187225,"teacher_disagreement_score":0.96903086,"about_ca_system_score_codex":0.000031449887,"about_ca_system_score_gemma":0.00000861664,"threshold_uncertainty_score":0.38986853},"labels":[],"label_agreement":null},{"id":"W1487603704","doi":"10.1109/fpt.2003.1275743","title":"Placement and routing for FPGA architectures supporting wide shallow memories","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Computer science; Block (permutation group theory); Routing (electronic design automation); Overhead (engineering); Embedded system; Logic block; Parallel computing; Computer architecture; Computer hardware; Operating system","score_opus":0.00990387147175848,"score_gpt":0.23488831309120417,"score_spread":0.2249844416194457,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1487603704","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.27707967,0.0001426018,0.7151448,0.00014956474,0.000073973424,0.00038463596,0.0000049532496,0.001097269,0.0059225145],"genre_scores_gemma":[0.944913,0.000009594023,0.054744408,0.00009857416,0.000056210505,0.000049477476,0.0000042369434,0.000025113604,0.000099383906],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993864,0.0000033074211,0.00017445954,0.00012330296,0.000067910216,0.00024461898],"domain_scores_gemma":[0.99976873,0.000064359476,0.00001931046,0.000086749074,0.000013167816,0.000047689642],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015240234,0.00011892219,0.00012140674,0.00004767714,0.00006822363,0.000041621573,0.000058491634,0.000044074128,0.000018186709],"category_scores_gemma":[0.00004966641,0.00010461549,0.000033800447,0.000038975606,0.0000184259,0.000041754913,0.000021106622,0.00006842331,0.0000012725861],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001603514,0.00017328553,0.018222619,0.0025626032,0.0006943049,0.00008226862,0.025324529,0.32788032,0.22664869,0.038140614,0.009159105,0.3509513],"study_design_scores_gemma":[0.0011700331,0.0002558062,0.0014245748,0.00013263081,0.0000405684,0.000033067176,0.0010362163,0.014565591,0.9536069,0.024820324,0.0022459123,0.00066836504],"about_ca_topic_score_codex":0.000011371192,"about_ca_topic_score_gemma":0.00003634885,"teacher_disagreement_score":0.7269582,"about_ca_system_score_codex":0.00003181288,"about_ca_system_score_gemma":0.00000885378,"threshold_uncertainty_score":0.42660958},"labels":[],"label_agreement":null},{"id":"W1489478894","doi":"10.1007/978-3-540-72586-2_37","title":"Formal Verification of Analog and Mixed Signal Designs in Mathematica","year":2007,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Correctness; Computer science; Formal verification; Stability (learning theory); SIGNAL (programming language); Theoretical computer science; Algorithm; Programming language","score_opus":0.029025233853063846,"score_gpt":0.24249520464161056,"score_spread":0.2134699707885467,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1489478894","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0012224203,0.0002789484,0.99554586,0.000007211372,0.000085134634,0.00020160941,0.0000026590303,0.00007725289,0.0025789218],"genre_scores_gemma":[0.80057,0.00005221773,0.19927189,0.00002706821,0.000044215452,0.000003788458,0.0000026272073,0.000018720813,0.000009479145],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989343,0.000006687942,0.00032879726,0.000253619,0.00023099664,0.00024557332],"domain_scores_gemma":[0.99945664,0.00016617708,0.00006360179,0.00023015482,0.0000408084,0.000042602678],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00058963796,0.00019013617,0.00027149744,0.0005852088,0.000025746169,0.000031416123,0.00030069816,0.00020476914,0.000011544953],"category_scores_gemma":[0.000013992144,0.0001812821,0.00003031687,0.00019891642,0.00022630191,0.00015555722,0.00006407791,0.00028251123,0.0000017337305],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007787168,0.000017345486,0.00010499313,0.00029243276,0.000008988619,0.00002391443,0.00082877674,0.017005894,0.009996118,0.0069298465,0.000010418621,0.9647735],"study_design_scores_gemma":[0.00024399308,0.00021010637,0.0009353254,0.00086084346,0.000013222334,0.000045876677,6.11351e-7,0.7298267,0.1269465,0.14018025,0.00011698098,0.0006196016],"about_ca_topic_score_codex":0.0000041139742,"about_ca_topic_score_gemma":0.000019369772,"teacher_disagreement_score":0.9641539,"about_ca_system_score_codex":0.000078130346,"about_ca_system_score_gemma":0.000035526627,"threshold_uncertainty_score":0.7392469},"labels":[],"label_agreement":null},{"id":"W1491808832","doi":"10.1007/3-540-46117-5_16","title":"On Optimum Designs of Universal Switch Blocks","year":2002,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"USB; Routing (electronic design automation); Computer science; Field-programmable gate array; Crossbar switch; Topology (electrical circuits); Router; Disjoint sets; Block (permutation group theory); Parallel computing; Embedded system; Discrete mathematics; Mathematics; Combinatorics; Computer network; Telecommunications; Software; Operating system","score_opus":0.0181107179656469,"score_gpt":0.21278239772383703,"score_spread":0.19467167975819014,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1491808832","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00009962551,0.00019014617,0.97521484,0.00002684699,0.00038219892,0.00018918322,0.0000054541424,0.00025825476,0.023633456],"genre_scores_gemma":[0.82117265,0.00017689652,0.17738895,0.0002395962,0.0002569523,0.0000042805505,0.0000036254796,0.000087231485,0.00066980434],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986524,0.000006806038,0.000245969,0.00040917605,0.00038206278,0.0003036158],"domain_scores_gemma":[0.9991193,0.00019467236,0.00006247441,0.00048847334,0.00006491914,0.00007020417],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00017686514,0.0003143721,0.0003397235,0.0005612786,0.000044712364,0.000039695715,0.00073070585,0.0002925991,0.00010535446],"category_scores_gemma":[0.0000143879515,0.00030144362,0.000079726306,0.00021393785,0.0002587881,0.00008796546,0.00009963185,0.00052200997,0.000014149634],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008345464,0.000030166282,0.000009938464,0.000096077165,0.000028882592,0.00011676656,0.00052812335,0.5849656,0.0034303924,0.00797725,0.00052070036,0.40228778],"study_design_scores_gemma":[0.00026491118,0.00050677557,0.000011431297,0.0008501547,0.000020634378,0.000032376483,1.3900507e-7,0.85474306,0.05162975,0.08994472,0.001111084,0.00088497606],"about_ca_topic_score_codex":0.0000046957666,"about_ca_topic_score_gemma":0.000003271673,"teacher_disagreement_score":0.82107306,"about_ca_system_score_codex":0.00017724685,"about_ca_system_score_gemma":0.000045281056,"threshold_uncertainty_score":0.9999438},"labels":[],"label_agreement":null},{"id":"W1495668040","doi":"10.1109/iwsoc.2004.9","title":"A fully automated approach for analog circuit reuse","year":2004,"lang":"en","type":"article","venue":"IEEE International Workshop on System-on-Chip for Real-Time Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Parasitic extraction; Computer science; Matching (statistics); Reuse; Electronic engineering; Electronic design automation; Computer engineering; Engineering; Embedded system","score_opus":0.02889572553905778,"score_gpt":0.2860026249815629,"score_spread":0.25710689944250514,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1495668040","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0029180094,0.000023753028,0.9134878,0.00033760568,0.0003769566,0.0045925966,0.00092094194,0.005222102,0.07212027],"genre_scores_gemma":[0.96271884,0.000028081158,0.01846235,0.00014780382,0.0007371845,0.015755044,0.00088092155,0.00017870418,0.0010910388],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979855,0.000022527682,0.000627379,0.0005785839,0.00038619072,0.00039982906],"domain_scores_gemma":[0.99808437,0.00042601489,0.00016223629,0.0009418559,0.0002343652,0.00015114964],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003215068,0.0003837562,0.0003802782,0.0004438137,0.00021486578,0.00012854546,0.0009399396,0.0002604344,0.000014285129],"category_scores_gemma":[0.00005457984,0.0003843523,0.00028504248,0.00035972457,0.00004473974,0.000104409126,0.000022055576,0.00020640569,0.00026318224],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00032976322,0.0011873036,0.000024212331,0.00067015813,0.0010274885,0.0000068238232,0.00041761092,0.38523266,0.039261095,0.45165166,0.11231946,0.007871753],"study_design_scores_gemma":[0.011616647,0.0017699724,0.00061120343,0.0034698457,0.00052159134,0.00026470158,0.0008455712,0.7610293,0.08595799,0.033356644,0.095614366,0.004942186],"about_ca_topic_score_codex":0.00001332522,"about_ca_topic_score_gemma":0.0000018144743,"teacher_disagreement_score":0.95980084,"about_ca_system_score_codex":0.00065929967,"about_ca_system_score_gemma":0.000049335682,"threshold_uncertainty_score":0.9998608},"labels":[],"label_agreement":null},{"id":"W1506142730","doi":"10.1109/fpl.2005.1515716","title":"Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Logic block; Computer science; Routing (electronic design automation); Block (permutation group theory); Computer hardware; SIGNAL (programming language); Digital signal processing; Process (computing); Computer architecture; Embedded system; Parallel computing","score_opus":0.04143324172942033,"score_gpt":0.25040704558706095,"score_spread":0.2089738038576406,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1506142730","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.37163377,0.00034319892,0.62655085,0.000055817865,0.000018127146,0.00030646467,0.0000046329724,0.00035351526,0.0007335966],"genre_scores_gemma":[0.9670792,0.0000146039465,0.03259288,0.000037795508,0.00017616659,0.00004531515,0.000004337125,0.00003135297,0.000018305025],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991567,0.000034951194,0.00022751301,0.00020761235,0.00010804285,0.00026513933],"domain_scores_gemma":[0.9991811,0.000576383,0.000042501146,0.000081992555,0.00004892376,0.00006908712],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00060834154,0.00017545439,0.00019660506,0.000083088744,0.00036924978,0.00012452457,0.000056392466,0.00010694014,0.000013387918],"category_scores_gemma":[0.000034387213,0.00015212236,0.00004118755,0.000071034905,0.000043588316,0.00030691898,0.00003503767,0.00021096421,5.494232e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000838264,0.000049700746,0.07043644,0.0002623171,0.00042832096,0.0000065926597,0.0044659674,0.052710038,0.3995011,0.010511933,0.00025775767,0.46128604],"study_design_scores_gemma":[0.0007713239,0.00009231197,0.007637713,0.00015368425,0.00008023906,0.00003053251,0.0004468822,0.8817855,0.10792366,0.0005562687,0.00018791223,0.00033395053],"about_ca_topic_score_codex":0.000026859621,"about_ca_topic_score_gemma":0.000018173272,"teacher_disagreement_score":0.8290755,"about_ca_system_score_codex":0.00006291483,"about_ca_system_score_gemma":0.000007876464,"threshold_uncertainty_score":0.620337},"labels":[],"label_agreement":null},{"id":"W1506990881","doi":"","title":"Search for quasi-optimal current return paths in a composite environment","year":2011,"lang":"en","type":"preprint","venue":"HAL (Le Centre pour la Communication Scientifique Directe)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Safran Electronics (Canada)","funders":"","keywords":"Fuselage; Ground; Computer science; Lightning (connector); Composite number; Lightning strike; Current (fluid); Set (abstract data type); Path (computing); Reliability engineering; Engineering; Electrical engineering; Aerospace engineering; Computer network; Algorithm","score_opus":0.02353851625463755,"score_gpt":0.23498265044788272,"score_spread":0.21144413419324518,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1506990881","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09732459,0.004173797,0.8863194,0.0004344464,0.0002529211,0.0013720846,0.0001567256,0.0006611557,0.009304872],"genre_scores_gemma":[0.8980225,0.003548306,0.09663262,0.000014146835,0.000033081094,0.0005470549,0.0005862759,0.000111751644,0.0005042841],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9968463,0.0012943791,0.0005393945,0.0005890766,0.00028317934,0.00044764104],"domain_scores_gemma":[0.99753284,0.000451791,0.00013184371,0.0014367834,0.00029610403,0.00015064218],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.003169223,0.0003699242,0.00041727463,0.00026601338,0.00010898123,0.00014694114,0.00093486434,0.00031405417,0.00007462569],"category_scores_gemma":[0.000079177975,0.00041960314,0.00021005132,0.00013970926,0.000115474366,0.00008789754,0.0006649375,0.0008950762,0.000027515176],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000109411354,0.0041454607,0.009899193,0.004051389,0.00036909422,0.000028022487,0.06357057,0.0055186404,0.056942694,0.047018703,0.005449235,0.8028976],"study_design_scores_gemma":[0.0012959337,0.0000033566193,0.0030053714,0.004951906,0.00009099171,0.000010906014,0.00013006682,0.34435964,0.60941577,0.0069628363,0.028071819,0.0017014199],"about_ca_topic_score_codex":0.00024670837,"about_ca_topic_score_gemma":0.000111108275,"teacher_disagreement_score":0.80119616,"about_ca_system_score_codex":0.0002554386,"about_ca_system_score_gemma":0.000072325536,"threshold_uncertainty_score":0.9998256},"labels":[],"label_agreement":null},{"id":"W1508131846","doi":"","title":"Modeling of flip chip bump patterns to minimize crosstalk on a BU-BGA package design.","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"STMicroelectronics (Canada)","funders":"","keywords":"Flip chip; Ball grid array; Crosstalk; Chip-scale package; Computer science; Interconnection; Package design; Package on package; Integrated circuit design; Die (integrated circuit); Integrated circuit packaging; Electronic engineering; Chip; Embedded system; Computer architecture; Engineering; Electrical engineering; Engineering drawing; Materials science; Telecommunications; Operating system; Soldering","score_opus":0.027331205766830045,"score_gpt":0.2419917204332337,"score_spread":0.21466051466640365,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1508131846","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18140945,0.000033624932,0.8133412,0.000046177425,0.000058411064,0.00025160992,0.000011227821,0.0006639314,0.004184352],"genre_scores_gemma":[0.96133953,0.000025576599,0.038015924,0.0002917733,0.000055715893,0.000018786837,0.0000036685942,0.000034686458,0.00021431065],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990314,0.000019227246,0.0002852447,0.00019422105,0.00017167733,0.00029821723],"domain_scores_gemma":[0.99946827,0.00003694827,0.00001593988,0.0003349742,0.00003423728,0.000109649394],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001474461,0.00020353645,0.00024858056,0.00014581818,0.000029400058,0.00003478385,0.00019069863,0.00010615748,0.00008907621],"category_scores_gemma":[0.000021001015,0.00018498325,0.00008190126,0.00013410693,0.0000071118448,0.000082212515,0.000015267107,0.00012413168,0.00003502289],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011709731,0.00020640157,0.00017340663,0.00010213248,0.00006271659,0.000039339135,0.0015222817,0.5936532,0.35657632,0.0008263117,0.0049397484,0.04178102],"study_design_scores_gemma":[0.0003433649,0.00037926927,0.0003735478,0.00014857155,0.000013560816,0.000004427275,0.00006784455,0.51068944,0.48633507,0.0011812956,0.000054256518,0.00040939104],"about_ca_topic_score_codex":0.000032962063,"about_ca_topic_score_gemma":0.0000028441682,"teacher_disagreement_score":0.7799301,"about_ca_system_score_codex":0.000038320733,"about_ca_system_score_gemma":0.000008229276,"threshold_uncertainty_score":0.7543398},"labels":[],"label_agreement":null},{"id":"W1522095270","doi":"10.1109/fpt.2003.1275756","title":"Performance-driven recursive multi-level clustering","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Cluster analysis; Netlist; Computer science; Benchmark (surveying); Field-programmable gate array; Parallel computing; Node (physics); Overhead (engineering); Algorithm; Minification; Cluster (spacecraft); Embedded system; Engineering; Artificial intelligence; Computer network","score_opus":0.038291347616171395,"score_gpt":0.23351299292682404,"score_spread":0.19522164531065264,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1522095270","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1315732,0.00005372505,0.8422134,0.00003221211,0.00020022517,0.00018296124,0.0000041908947,0.0017131121,0.024026973],"genre_scores_gemma":[0.8823796,0.00011919199,0.117099114,0.000039113696,0.00004228332,0.000017977942,0.0000027477647,0.000024630577,0.00027532643],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995409,0.0000027799028,0.000110689296,0.000093308445,0.00006494418,0.00018733772],"domain_scores_gemma":[0.9997876,0.0000051760253,0.000008583472,0.00013278458,0.00001822973,0.000047602512],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003253602,0.00010541858,0.00009261183,0.00006214202,0.000036522863,0.000015486465,0.00010667513,0.00006470949,0.00005198916],"category_scores_gemma":[0.0000034822608,0.00009850229,0.00003183318,0.00007913928,0.000013833754,0.0001449122,0.000022863282,0.00010004574,0.00012279645],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023301307,0.00016772121,0.0032171975,0.00049595686,0.00018620926,0.00006856535,0.0039271177,0.49316543,0.1719501,0.002128599,0.005456901,0.3192129],"study_design_scores_gemma":[0.0019610696,0.0002454025,0.01324355,0.00030171426,0.00002736648,0.000076859986,0.00021914988,0.42913204,0.5491962,0.00043126696,0.0040563485,0.0011090273],"about_ca_topic_score_codex":0.000011365634,"about_ca_topic_score_gemma":0.00002206989,"teacher_disagreement_score":0.7508064,"about_ca_system_score_codex":0.00008038538,"about_ca_system_score_gemma":0.0000074645054,"threshold_uncertainty_score":0.40168068},"labels":[],"label_agreement":null},{"id":"W1525466953","doi":"10.1109/mwscas.2002.1187292","title":"Congestion based mathematical programming models for global routing","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Routing (electronic design automation); Flexibility (engineering); Computer science; Mathematical optimization; Channel (broadcasting); Multipath routing; Static routing; Distributed computing; Routing protocol; Computer network; Mathematics","score_opus":0.026407556137569087,"score_gpt":0.25168891983740815,"score_spread":0.22528136369983906,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1525466953","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0009756421,0.000024799183,0.96715105,0.000012259062,0.00003176832,0.00032463818,0.0000017898254,0.0010620562,0.030415986],"genre_scores_gemma":[0.68500024,5.521404e-7,0.31485143,0.000017458377,0.000009497232,0.00007593494,0.0000022261386,0.000010948218,0.000031716554],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995361,0.000008255259,0.0001274681,0.000083134044,0.00006198092,0.0001830378],"domain_scores_gemma":[0.9998012,0.000038815546,0.000009107723,0.00008594455,0.000024649697,0.000040252675],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016736268,0.00008370539,0.00009296631,0.000014685962,0.00002885507,0.000031918047,0.00004100817,0.00006527461,0.000020175703],"category_scores_gemma":[0.0000397231,0.00007649458,0.000042485182,0.00006337345,0.000008765715,0.00007800893,0.000002429022,0.000035044286,0.000004590596],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000030123329,0.00003873529,0.00007822382,0.00015829744,0.000016064334,0.0000013574775,0.000032836197,0.022961129,0.00066668907,0.93046516,0.0005518407,0.045026645],"study_design_scores_gemma":[0.00017057364,0.000027718721,0.000003894635,0.000026438436,0.000010482924,0.000004232047,0.00002018934,0.9265395,0.009200401,0.063128926,0.00074403366,0.00012365093],"about_ca_topic_score_codex":7.8477245e-7,"about_ca_topic_score_gemma":8.614466e-7,"teacher_disagreement_score":0.90357834,"about_ca_system_score_codex":0.00004783089,"about_ca_system_score_gemma":0.000008665824,"threshold_uncertainty_score":0.31193584},"labels":[],"label_agreement":null},{"id":"W1525696892","doi":"10.1109/iccad.2004.1382639","title":"Unification of partitioning, placement and floorplanning","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":170,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Advanced Micro Devices (Canada)","funders":"","keywords":"Floorplan; Computer science; Scalability; Application-specific integrated circuit; Placement; Integrated circuit layout; Physical design; Macro; Parallel computing; Very-large-scale integration; Undo; Computer engineering; Algorithm; Integrated circuit; Circuit design; Embedded system","score_opus":0.009212084357099467,"score_gpt":0.2125116465322438,"score_spread":0.20329956217514433,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1525696892","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.46565363,0.0005728325,0.42897588,0.000097762924,0.000033731078,0.00015353586,0.0000026214382,0.00077941583,0.103730604],"genre_scores_gemma":[0.98651195,0.000049939805,0.0132529875,0.00001137003,0.000016060227,0.0000059486356,0.0000026287591,0.00000394645,0.00014519185],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99982566,0.0000023936286,0.0000697639,0.000031362404,0.00002907055,0.000041765314],"domain_scores_gemma":[0.9999237,0.000005492399,0.0000070445776,0.00004367523,0.000007103267,0.000012953176],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004455288,0.000028007067,0.00003407963,0.000024916635,0.000009497179,0.000004582857,0.000015879014,0.000016469048,0.000067104076],"category_scores_gemma":[0.0000016743696,0.00002694696,0.00000515867,0.00002451487,0.0000068996,0.00004705871,0.0000032139826,0.00001864477,0.0000047626136],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012187518,0.00008255281,0.009777831,0.00026550656,0.00008587725,0.0000015230067,0.0029501908,0.06312608,0.605272,0.05824671,0.05094843,0.20923112],"study_design_scores_gemma":[0.00021346081,0.000050525003,0.004233479,0.000041947642,0.000011261653,0.000004409307,0.00015849118,0.14108688,0.83586293,0.00035969372,0.017813588,0.00016334522],"about_ca_topic_score_codex":0.0000018042471,"about_ca_topic_score_gemma":0.0000014940731,"teacher_disagreement_score":0.5208583,"about_ca_system_score_codex":0.000007337231,"about_ca_system_score_gemma":0.000001083899,"threshold_uncertainty_score":0.10988652},"labels":[],"label_agreement":null},{"id":"W1531949859","doi":"10.1109/icm.2004.1434259","title":"A genetic local search hybrid architecture for VLSI circuit partitioning","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Very-large-scale integration; Computer science; Speedup; Genetic algorithm; Computer architecture; Parallel computing; Software; Computer engineering; Embedded system","score_opus":0.015238657689246616,"score_gpt":0.22280336025368694,"score_spread":0.20756470256444032,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1531949859","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021125445,0.00022026253,0.9707279,0.00008969519,0.00003115356,0.00024381478,0.000008069851,0.000865519,0.0066881482],"genre_scores_gemma":[0.96197,0.000017681557,0.037269164,0.00013024783,0.00022375528,0.000095083866,0.000006835161,0.000033595737,0.0002536444],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99935967,0.000008627059,0.00013194299,0.00012730948,0.00009285823,0.00027957745],"domain_scores_gemma":[0.9997241,0.000035787893,0.000005505225,0.00014207738,0.00002323884,0.0000692885],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000077342964,0.00010352436,0.00009997493,0.00006852243,0.000050611263,0.000032544107,0.00009946635,0.000043874592,0.00018093933],"category_scores_gemma":[0.000004967453,0.00009915119,0.000057818415,0.0000612681,0.000025764046,0.000046690035,0.000011325233,0.000116568415,0.000051779018],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000047685166,0.000023048116,0.000117553376,0.00010131697,0.00003512019,0.000006660914,0.00022289768,0.17453438,0.01783391,0.0014656064,0.014675697,0.790979],"study_design_scores_gemma":[0.00050350017,0.00014802108,0.00060728675,0.000048067985,0.000024047738,0.00010370271,0.00004959008,0.51999104,0.38119757,0.0068880077,0.08990525,0.00053393736],"about_ca_topic_score_codex":0.0000064105966,"about_ca_topic_score_gemma":0.00001759834,"teacher_disagreement_score":0.94084454,"about_ca_system_score_codex":0.000045642922,"about_ca_system_score_gemma":0.000010214149,"threshold_uncertainty_score":0.40432683},"labels":[],"label_agreement":null},{"id":"W1536432301","doi":"10.1007/s00453-001-0050-6","title":"Grade of Service Steiner Minimum Trees in the Euclidean Plane","year":2001,"lang":"en","type":"article","venue":"Algorithmica","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Steiner tree problem; Combinatorics; Mathematics; Euclidean geometry; Euclidean distance; Approximation algorithm; Generalization; Path (computing); Spanning tree; Terminal (telecommunication); Discrete mathematics; Point (geometry); Computer science; Geometry","score_opus":0.015221349186748603,"score_gpt":0.22216447856601942,"score_spread":0.2069431293792708,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1536432301","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9643119,0.0010424637,0.010402874,0.0020686646,0.00025098145,0.00060023513,0.000044770382,0.0007677412,0.020510346],"genre_scores_gemma":[0.99762756,0.000087564265,0.001852685,0.00022275979,0.00008962265,0.000018566134,0.000012258101,0.000020094878,0.00006888965],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993891,0.00002822833,0.00019034932,0.00009149097,0.00012475622,0.00017603551],"domain_scores_gemma":[0.9996346,0.000078058656,0.000019768488,0.00022936564,0.000015018258,0.00002316957],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013642125,0.00010582075,0.00014030548,0.00007929237,0.000014446864,0.000010464709,0.0002577003,0.000065160086,0.000031686515],"category_scores_gemma":[0.000005105235,0.00007884363,0.000031667627,0.00029995365,0.000016542734,0.0000583817,0.000014090371,0.00012740605,0.000016591172],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009243035,0.001097266,0.008294899,0.00055947196,0.00040667935,0.0010046758,0.019712618,0.0053856377,0.44386002,0.0049145496,0.09348953,0.42118225],"study_design_scores_gemma":[0.0047116857,0.0009804132,0.06002128,0.0006003001,0.00021422029,0.0007458843,0.0044007627,0.26947668,0.39910775,0.016446102,0.24055684,0.0027380795],"about_ca_topic_score_codex":0.00014421086,"about_ca_topic_score_gemma":0.00014928074,"teacher_disagreement_score":0.41844416,"about_ca_system_score_codex":0.0000123036125,"about_ca_system_score_gemma":0.000004626245,"threshold_uncertainty_score":0.321515},"labels":[],"label_agreement":null},{"id":"W1552511991","doi":"10.1007/978-3-540-30205-6_7","title":"Crosstalk Cancellation for Realistic PCB Buses","year":2004,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Crosstalk; Bandwidth (computing); Electronic engineering; Linear programming; Algorithm; Telecommunications; Engineering","score_opus":0.017302427688834044,"score_gpt":0.24195073129676462,"score_spread":0.22464830360793056,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1552511991","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000038153077,0.00037316492,0.9918787,0.000034638077,0.00068245723,0.00039305683,0.000026089676,0.000386401,0.0061873435],"genre_scores_gemma":[0.77748626,0.00014187131,0.22105522,0.00019291799,0.00071928726,0.000033253626,0.000023265151,0.00008901407,0.00025888975],"study_design_codex":"simulation_or_modeling","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9987426,0.0000025936026,0.0002394227,0.0004114449,0.00029397773,0.0003099904],"domain_scores_gemma":[0.9992788,0.00014423091,0.000054183325,0.0003391421,0.00012756909,0.00005606362],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00022023708,0.00027265388,0.00025461294,0.00027817173,0.00009449346,0.0001389688,0.00041879187,0.00023324137,0.00001911147],"category_scores_gemma":[0.00003674443,0.00026755076,0.00006373527,0.00012962623,0.0002241744,0.00011409968,0.000054116204,0.00025118026,0.000004776763],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000046400205,0.0000050924677,0.000013464297,0.00021184325,0.000008935282,0.000011775042,0.00028146195,0.60898334,0.0014673624,0.0067246775,0.0001101042,0.3821773],"study_design_scores_gemma":[0.00030126024,0.00017041252,0.00008105794,0.00085614325,0.000020131509,0.000023594042,7.7316265e-8,0.37941277,0.022429543,0.5908237,0.0049652136,0.0009161058],"about_ca_topic_score_codex":0.000041449977,"about_ca_topic_score_gemma":0.00013578724,"teacher_disagreement_score":0.7774481,"about_ca_system_score_codex":0.00050405774,"about_ca_system_score_gemma":0.00019630133,"threshold_uncertainty_score":0.99997765},"labels":[],"label_agreement":null},{"id":"W1565289258","doi":"10.1023/a:1014847925683","title":"A Novel Eigenvector Technique for Large Scale Combinatorial Problems in VLSI Layout","year":2002,"lang":"en","type":"article","venue":"Journal of Combinatorial Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Mathematics","score_opus":0.012512469230286226,"score_gpt":0.2189235804871578,"score_spread":0.20641111125687156,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1565289258","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0016324415,0.0002856099,0.9915534,0.000049559276,0.0045317328,0.0009829742,0.000018767454,0.00015851746,0.0007869524],"genre_scores_gemma":[0.9046152,0.00021604309,0.09388969,0.00002139616,0.0009875926,0.00013691615,0.000012529681,0.000094815645,0.000025797599],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984489,0.00004167154,0.0007630328,0.00013288995,0.00029836685,0.00031510196],"domain_scores_gemma":[0.9991118,0.00007765838,0.0002440058,0.0001548124,0.0003117042,0.000100043304],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0006799777,0.00021126286,0.00042451377,0.00037515914,0.000059820868,0.0000638744,0.0002511227,0.00028574117,0.00005149354],"category_scores_gemma":[0.00011253121,0.00021297122,0.00014998855,0.0004104615,0.00001694903,0.00044929178,0.000020536836,0.00033168503,0.0000018382574],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00022078937,0.0025549983,0.0009657817,0.00049211725,0.00017533648,0.000018025816,0.002168451,0.8906484,0.070491925,0.018216196,0.013242485,0.000805478],"study_design_scores_gemma":[0.016984776,0.001911585,0.00008628922,0.0005945019,0.0001239354,0.00011971711,0.00008826172,0.89196604,0.05851888,0.018260505,0.010311625,0.0010338895],"about_ca_topic_score_codex":0.0000029932828,"about_ca_topic_score_gemma":9.373739e-7,"teacher_disagreement_score":0.9029828,"about_ca_system_score_codex":0.00022696893,"about_ca_system_score_gemma":0.000027762735,"threshold_uncertainty_score":0.8684714},"labels":[],"label_agreement":null},{"id":"W1566266975","doi":"10.1109/sbac-pad.2004.18","title":"Graph Partitioning with the Party Library: Helpful-Sets in Practice","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Graph partition; Graph; Partition (number theory); Theoretical computer science; Heuristic; Permutation (music); Algorithm; Mathematics; Combinatorics; Artificial intelligence","score_opus":0.00670996929657694,"score_gpt":0.20202801468888962,"score_spread":0.19531804539231268,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1566266975","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.19695537,0.0013081142,0.28804174,0.015605718,0.00016872083,0.0011130136,0.000008689271,0.0065085716,0.49029008],"genre_scores_gemma":[0.9874856,0.000100798214,0.011702992,0.0005409811,0.00002086838,0.000054424298,0.0000037449433,0.000021424587,0.000069163085],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99957466,0.000017692459,0.000086506116,0.00008324412,0.000080880156,0.00015703612],"domain_scores_gemma":[0.9997579,0.000050102906,0.000013053815,0.00014139236,0.000008529205,0.000029022794],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008862953,0.000082383645,0.00006733855,0.000045794128,0.00003839832,0.000056787245,0.000086087566,0.00003711498,0.000053789016],"category_scores_gemma":[0.0000086852315,0.00005068374,0.000016375037,0.00025899705,0.000023148257,0.00060195074,0.000011162055,0.00014700867,0.000023893885],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00025410202,0.00074717705,0.023187734,0.00024725776,0.00052746385,0.0009084935,0.011470372,0.25911897,0.011716902,0.49025035,0.16085756,0.04071361],"study_design_scores_gemma":[0.004737583,0.0011009688,0.025957288,0.00078572315,0.00019280783,0.000456152,0.0050732605,0.0076247915,0.50671625,0.085320696,0.35931173,0.002722765],"about_ca_topic_score_codex":0.000034559736,"about_ca_topic_score_gemma":0.000057172085,"teacher_disagreement_score":0.7905302,"about_ca_system_score_codex":0.000013825734,"about_ca_system_score_gemma":0.000012749539,"threshold_uncertainty_score":0.20668228},"labels":[],"label_agreement":null},{"id":"W1569525708","doi":"10.1109/fpt.2002.1188686","title":"The effect of cluster packing and node duplication control in delay driven clustering","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Benchmark (surveying); Computer science; Cluster analysis; Node (physics); Cluster (spacecraft); Set (abstract data type); Algorithm; Degradation (telecommunications); Logic gate; Parallel computing; Cluster size; Computer network; Engineering; Artificial intelligence","score_opus":0.00350512009967066,"score_gpt":0.20304698058741644,"score_spread":0.19954186048774578,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1569525708","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.373957,0.00039470007,0.6171875,0.00004282373,0.00004900453,0.00046311595,7.6886727e-7,0.00018091722,0.0077241696],"genre_scores_gemma":[0.999093,0.000052631905,0.0007647061,0.000019831145,0.000005980075,0.00003670153,2.9979066e-7,0.000011141836,0.000015727555],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996164,0.000046124453,0.00012820888,0.0000625567,0.000041688872,0.00010505542],"domain_scores_gemma":[0.9996594,0.0001938173,0.000014753386,0.00010912496,0.0000073853653,0.000015480684],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00028383284,0.00006671146,0.00009897245,0.000033985543,0.000023526367,0.000015271644,0.000044477943,0.000042694217,0.00000316676],"category_scores_gemma":[0.000025455683,0.000044513596,0.000016802938,0.000052714717,0.000015396809,0.000049121492,0.00000720483,0.00006238969,0.0000011813593],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014864118,0.000029151168,0.30424362,0.0007242281,0.00018661174,0.000009588923,0.0012363025,0.08856504,0.43206477,0.0047303415,0.0016061333,0.16645554],"study_design_scores_gemma":[0.0015751865,0.0001365971,0.00654243,0.00008244011,0.000020534624,0.000016458089,0.000029505813,0.8570445,0.13261722,0.00023042603,0.0014891456,0.00021552181],"about_ca_topic_score_codex":0.000008660059,"about_ca_topic_score_gemma":0.000033916804,"teacher_disagreement_score":0.7684795,"about_ca_system_score_codex":0.000017535622,"about_ca_system_score_gemma":0.0000014168514,"threshold_uncertainty_score":0.18152118},"labels":[],"label_agreement":null},{"id":"W1570456368","doi":"10.1109/ccece.2001.933590","title":"An efficient rectilinear Steiner tree algorithm for VLSI global routing","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Guelph","funders":"","keywords":"Steiner tree problem; Routing (electronic design automation); Very-large-scale integration; Heuristics; Computer science; Algorithm; Tree (set theory); Spanning tree; Integrated circuit layout; Mathematics; Topology (electrical circuits); Mathematical optimization; Discrete mathematics; Combinatorics; Integrated circuit; Computer network","score_opus":0.015681855594630686,"score_gpt":0.23717898243789454,"score_spread":0.22149712684326384,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1570456368","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008317015,0.00015201338,0.9615506,0.000018992054,0.00018196797,0.00027424892,0.000020817803,0.0019138836,0.027570456],"genre_scores_gemma":[0.78460467,0.000012904969,0.21443386,0.00005764982,0.00024966456,0.000044479955,0.000007682346,0.00003634293,0.0005527529],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99928254,0.000010137451,0.00016982525,0.00016729551,0.000097994074,0.00027223246],"domain_scores_gemma":[0.9996453,0.000021210279,0.000012979917,0.00020779652,0.000034633576,0.00007810469],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011434794,0.00013583172,0.00013199815,0.000032368996,0.000051004998,0.000041043902,0.000122505,0.00008610395,0.00011359275],"category_scores_gemma":[0.0000098545115,0.00012212795,0.00006365863,0.00013937702,0.0000111635845,0.00006487969,0.00000983482,0.00006247031,0.000030123476],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000013196034,0.00006282231,0.000048156104,0.000012741067,0.000018368704,0.000003262359,0.000080976526,0.004343472,0.0018808226,0.0004272123,0.006734548,0.9863863],"study_design_scores_gemma":[0.00021244481,0.00010401862,0.0000517312,0.000007662858,0.000009238879,0.0000067771794,0.000036798814,0.98251486,0.013369377,0.000052663498,0.0034623672,0.00017206065],"about_ca_topic_score_codex":0.000014001047,"about_ca_topic_score_gemma":0.00000829903,"teacher_disagreement_score":0.9862142,"about_ca_system_score_codex":0.00007223519,"about_ca_system_score_gemma":0.0000022335255,"threshold_uncertainty_score":0.49802336},"labels":[],"label_agreement":null},{"id":"W1590281904","doi":"10.1109/fccm.2015.33","title":"Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Multiplexer; Lookup table; Computer science; Field-programmable gate array; Transistor; Process (computing); Electronic engineering; Computer hardware; Electrical engineering; Multiplexing; Engineering; Voltage; Telecommunications","score_opus":0.0735690504194493,"score_gpt":0.2430810140555435,"score_spread":0.1695119636360942,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1590281904","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.48232302,0.000827052,0.46038896,0.00019319888,0.0003460909,0.0005856126,0.000009300469,0.001144508,0.054182265],"genre_scores_gemma":[0.9811279,0.0000065524846,0.018701438,0.000026447571,0.000032532447,0.000027020444,0.0000018033804,0.000024863937,0.00005139602],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991883,0.000025118537,0.00029749624,0.00010971142,0.00018110116,0.00019824473],"domain_scores_gemma":[0.99947935,0.00013974239,0.000035857287,0.00024171176,0.000044813463,0.000058513568],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00039471433,0.00013600536,0.00020041698,0.00008756516,0.000020156953,0.000018848392,0.00021645198,0.00006595407,0.000026833553],"category_scores_gemma":[0.0001768995,0.000098191944,0.000051135936,0.00016793102,0.00002829334,0.00014754769,0.00001685873,0.00014897712,0.0000051584475],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000144146,0.00042535222,0.016467901,0.0012475427,0.0003338049,0.00010464094,0.04389445,0.4499975,0.15429553,0.0012681378,0.04814821,0.28367275],"study_design_scores_gemma":[0.0008524464,0.00009240164,0.0011100309,0.00035218705,0.000036404344,0.000020543079,0.0010471303,0.85672927,0.13546097,0.0025179966,0.0012642649,0.00051637687],"about_ca_topic_score_codex":0.00008985919,"about_ca_topic_score_gemma":0.000066337154,"teacher_disagreement_score":0.49880493,"about_ca_system_score_codex":0.00006380239,"about_ca_system_score_gemma":0.000026323272,"threshold_uncertainty_score":0.40041512},"labels":[],"label_agreement":null},{"id":"W1598286413","doi":"10.1002/9780470932025.ch14","title":"Case Study: Multirate Decimators and Interpolators","year":2011,"lang":"en","type":"other","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Polyphase system; Mathematics; Graph; Implementation; Algorithm; Arithmetic; Computer science; Discrete mathematics; Electronic engineering; Engineering; Programming language","score_opus":0.018275716998225725,"score_gpt":0.22559755946600518,"score_spread":0.20732184246777946,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1598286413","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.006245081,0.000713481,0.011045705,3.4365974e-7,0.00029662205,0.00061500707,0.00001184289,0.004276558,0.9767954],"genre_scores_gemma":[0.6702749,0.0002572321,0.008781897,0.0000248084,0.0001484227,0.000094711526,0.0000030409124,0.0014118921,0.31900308],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99951386,0.000012295555,0.00012777091,0.00016316304,0.0000466642,0.00013623305],"domain_scores_gemma":[0.99967355,0.000008552008,0.000021856225,0.00022270043,0.0000050913673,0.00006826433],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00004816311,0.00023468946,0.00022805341,0.00022662869,0.000012745835,0.000021220636,0.000075773896,0.0001855481,0.0012626222],"category_scores_gemma":[0.0000023852356,0.00019957406,0.000027331342,0.000050679708,0.000020889533,0.000026405989,0.00003605818,0.00013556312,0.000072071816],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000020834998,0.00008553349,0.0025625508,0.00020532087,0.00037645068,0.005394012,0.0014167922,4.2154565e-7,0.00005498839,0.00019204056,0.9580243,0.031685464],"study_design_scores_gemma":[0.001931442,0.0007682739,0.00014586914,0.000674494,0.00048205035,0.0076180943,0.0048426394,0.004805606,0.0024544054,0.00028006855,0.97145355,0.0045434916],"about_ca_topic_score_codex":0.00090433634,"about_ca_topic_score_gemma":0.0005348637,"teacher_disagreement_score":0.66402984,"about_ca_system_score_codex":0.0000149783245,"about_ca_system_score_gemma":0.0000035911228,"threshold_uncertainty_score":0.99965036},"labels":[],"label_agreement":null},{"id":"W1600237807","doi":"10.1109/ccece.2015.7129165","title":"Enhanced placement algorithm for FPGAs using sparse circuit","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Field-programmable gate array; Simulated annealing; Computer science; Placement; Logic block; Gate array; Logic synthesis; Logic gate; Block (permutation group theory); Parallel computing; Algorithm; Electronic engineering; Circuit design; Computer hardware; Physical design; Embedded system; Engineering; Mathematics","score_opus":0.07382310947229188,"score_gpt":0.27171638198452064,"score_spread":0.19789327251222877,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1600237807","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0038700511,0.000089458386,0.9805861,0.000004122641,0.00020112563,0.0003030306,0.000005994918,0.000718183,0.014221909],"genre_scores_gemma":[0.6394755,0.000015075494,0.35895872,0.00008091001,0.0002279617,0.00011133321,0.000011818551,0.000059946116,0.0010587237],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99946016,0.000005358103,0.0001304803,0.00010692583,0.0000945928,0.00020249473],"domain_scores_gemma":[0.99970406,0.0000149776315,0.000012178887,0.00013380907,0.000047795016,0.00008714689],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014037608,0.00010405043,0.000115170034,0.000049931357,0.000020546204,0.000022303764,0.00007676192,0.000057958674,0.000048419784],"category_scores_gemma":[0.000008169856,0.00010089388,0.000036044115,0.000062252155,0.000008388474,0.00008392125,0.000012158384,0.000043807067,0.000019482768],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012137131,0.00009266443,0.000013139136,0.00012131922,0.00014992365,0.0000094035995,0.001182496,0.024268556,0.26136547,0.002566266,0.0491488,0.6610698],"study_design_scores_gemma":[0.00040326762,0.000060020506,0.0000016498494,0.000016806194,0.000013698171,0.000004061271,0.00009769037,0.50704646,0.48524237,0.0014178761,0.005493622,0.00020249771],"about_ca_topic_score_codex":0.00000888879,"about_ca_topic_score_gemma":0.000001953436,"teacher_disagreement_score":0.66086733,"about_ca_system_score_codex":0.00010042047,"about_ca_system_score_gemma":0.000016756976,"threshold_uncertainty_score":0.4114333},"labels":[],"label_agreement":null},{"id":"W1600592838","doi":"10.1007/978-3-540-24855-2_123","title":"An Island-Based GA Implementation for VLSI Standard-Cell Placement","year":2004,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Speedup; Computer science; Asynchronous communication; Parallel computing; Very-large-scale integration; Scheme (mathematics); Convergence (economics); Computation; Algorithm; Embedded system; Mathematics; Telecommunications","score_opus":0.011983564087182179,"score_gpt":0.26375240782384834,"score_spread":0.2517688437366662,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1600592838","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00012214876,0.00013817982,0.9972134,0.000034374367,0.0004067635,0.0007643828,0.00009084229,0.00030937855,0.0009205005],"genre_scores_gemma":[0.60996294,0.000029545143,0.3889627,0.00040573342,0.00034236044,0.00006673944,0.00011535375,0.0000834951,0.000031164174],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99846905,0.0000065843037,0.00029258485,0.00047993445,0.00038358127,0.00036824564],"domain_scores_gemma":[0.9992951,0.00007906932,0.00006768756,0.0003886827,0.00009055567,0.00007885998],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00035330316,0.00031885935,0.00026559297,0.0003602512,0.00009840426,0.00015361232,0.00047812148,0.00017533705,0.0000843608],"category_scores_gemma":[0.00000362764,0.00031043254,0.00006937197,0.000107574015,0.00010276007,0.00015318542,0.000035715726,0.00023884368,0.0000033316062],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000021589718,0.00001972107,0.000019229576,0.0002219748,0.000009534717,0.000011136523,0.00043065372,0.65466857,0.004044557,0.0010843583,0.00020005192,0.33926862],"study_design_scores_gemma":[0.0019439943,0.0016410765,0.0000150159585,0.0004200781,0.000035171513,0.0000059874305,0.0000011777242,0.57571405,0.3233959,0.09064846,0.004902711,0.0012763783],"about_ca_topic_score_codex":0.000008670717,"about_ca_topic_score_gemma":0.000109151304,"teacher_disagreement_score":0.6098408,"about_ca_system_score_codex":0.0005118738,"about_ca_system_score_gemma":0.00022924169,"threshold_uncertainty_score":0.9999348},"labels":[],"label_agreement":null},{"id":"W1601965867","doi":"","title":"Proceedings of the 2003 international workshop on System-level interconnect prediction","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Interconnection; IBM; Computer science; Microarchitecture; Architecture; Chip; Field-programmable gate array; Computer architecture; Embedded system; Engineering; Telecommunications","score_opus":0.017311693925840015,"score_gpt":0.20437045416639313,"score_spread":0.18705876024055312,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1601965867","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07452843,0.000048809365,0.04540039,0.000048358634,0.0015468764,0.00039670672,0.000018941562,0.00090947736,0.877102],"genre_scores_gemma":[0.99772125,0.000012302295,0.0009630702,0.000021926624,0.00003563863,0.000024924437,7.999044e-7,0.000013406184,0.0012066496],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995668,0.000004500275,0.00014933398,0.00007772076,0.000121889156,0.00007978292],"domain_scores_gemma":[0.99978274,0.000012959989,0.000023207951,0.00006989789,0.00009410024,0.00001708241],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012128837,0.00007503574,0.000071706956,0.000058542017,0.000017774286,0.000016469947,0.00013452799,0.00005841237,0.000058139663],"category_scores_gemma":[0.000060559116,0.000051296352,0.000032920947,0.00017259411,0.000012375162,0.00008208577,0.000009667189,0.00009592095,0.0000063928615],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000026958924,0.00012324794,0.007716449,0.00040426207,0.00026517754,0.000001343762,0.0007842574,0.0011196784,0.07841333,0.7364298,0.1570463,0.01766919],"study_design_scores_gemma":[0.00054060546,0.00009962952,0.004720848,0.001129488,0.000034587716,0.000053528336,0.00201689,0.025777046,0.939559,0.0006994104,0.025015026,0.0003539503],"about_ca_topic_score_codex":0.0000022984373,"about_ca_topic_score_gemma":7.775327e-7,"teacher_disagreement_score":0.92319286,"about_ca_system_score_codex":0.000074292046,"about_ca_system_score_gemma":0.0000054969946,"threshold_uncertainty_score":0.20918044},"labels":[],"label_agreement":null},{"id":"W1607353855","doi":"10.1109/iccad.2004.1382642","title":"Engineering details of a stable force-directed placer","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":61,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Placer mining; Computation; Computer science; Stability (learning theory); Computational science; Placement; Computer engineering; Physical design; Simulation; Parallel computing; Mathematical optimization; Algorithm; Geology; Mathematics; Circuit design; Embedded system","score_opus":0.005709059116641306,"score_gpt":0.18109443212711526,"score_spread":0.17538537301047397,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1607353855","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20038648,0.0010216688,0.6655496,0.000046841156,0.00014891443,0.00042907306,0.000012221834,0.009383779,0.12302143],"genre_scores_gemma":[0.95023024,0.000035492503,0.047998603,0.0000115296625,0.000043719076,0.000016102436,0.0000019158094,0.000028900748,0.0016335078],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995257,0.000003113389,0.00015458684,0.000069894515,0.000073387455,0.00017331577],"domain_scores_gemma":[0.9997674,0.000026468566,0.000010012577,0.00013469059,0.00002162812,0.00003975994],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000065666696,0.00009362731,0.00013012758,0.00008394122,0.0000084819585,0.000008582937,0.000076690056,0.000058282993,0.00040978278],"category_scores_gemma":[0.000010989651,0.000089757086,0.000036258363,0.0001269008,0.000005463163,0.00012273251,0.000010752138,0.000067729416,0.00002969244],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008331465,0.000038060112,0.00036471747,0.00019938419,0.000103515806,0.0000030844406,0.0003038929,0.09848584,0.844999,0.002109661,0.02673524,0.026649248],"study_design_scores_gemma":[0.00011281216,0.000012508823,0.00012966871,0.000018504976,0.00000660379,0.0000028318736,0.0000069930497,0.322139,0.66517043,0.00003054065,0.012241604,0.00012849476],"about_ca_topic_score_codex":0.000008337735,"about_ca_topic_score_gemma":0.000008545295,"teacher_disagreement_score":0.7498438,"about_ca_system_score_codex":0.0000325983,"about_ca_system_score_gemma":0.000004887294,"threshold_uncertainty_score":0.44868338},"labels":[],"label_agreement":null},{"id":"W1608848694","doi":"10.1109/iscas.1995.521446","title":"Floorplanning with datapath optimization","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Datapath; Floorplan; Computer science; Routing (electronic design automation); High-level synthesis; Schedule; Network topology; Parallel computing; Placement; Critical path method; Path (computing); Field-programmable gate array; Mathematical optimization; Physical design; Embedded system; Engineering; Circuit design; Mathematics; Computer network","score_opus":0.011565315885679793,"score_gpt":0.15727271957349406,"score_spread":0.14570740368781426,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1608848694","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00073623995,0.0000840782,0.8776137,0.00000981615,0.000017614415,0.000044130138,0.0000012970934,0.001076805,0.12041627],"genre_scores_gemma":[0.7888825,0.00008666953,0.2097178,0.000053871125,0.00004095348,0.000011151433,0.00001360937,0.000026889315,0.0011665712],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99977344,0.000002272213,0.000046400237,0.00005282918,0.00004531463,0.00007971955],"domain_scores_gemma":[0.99986756,0.000004186194,0.00000398972,0.00009609798,0.0000070749707,0.00002110989],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000018414832,0.000051195188,0.000042790944,0.00003131482,0.000016604932,0.000017597997,0.000045205565,0.000022715563,0.0008562025],"category_scores_gemma":[0.000001276548,0.000040010884,0.0000056333056,0.00006999566,0.000005158353,0.00011898258,0.0000041573016,0.000037950587,0.00003506327],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000018332338,0.00001821852,0.0005465552,0.000029149058,0.00002525526,0.000021003363,0.00025145576,0.89793926,0.0014661779,0.0005490464,0.07976363,0.019388406],"study_design_scores_gemma":[0.000068212554,0.000022916623,0.00002074271,0.000010621893,0.000003514802,0.000009898976,0.000011728756,0.992358,0.004634574,0.0000060637503,0.0027620047,0.000091683105],"about_ca_topic_score_codex":0.0000017446647,"about_ca_topic_score_gemma":5.51024e-7,"teacher_disagreement_score":0.78814626,"about_ca_system_score_codex":0.000007756583,"about_ca_system_score_gemma":4.736962e-7,"threshold_uncertainty_score":0.9374817},"labels":[],"label_agreement":null},{"id":"W1624781543","doi":"10.1109/ccece.2003.1226354","title":"A new partitioning method for LUT-based FPGAS","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"","keywords":"Lookup table; Field-programmable gate array; Benchmark (surveying); Computer science; Combinational logic; Parallel computing; XOR gate; Boolean function; Programmable logic array; Electronic circuit; Path (computing); Gate array; Algorithm; Functional decomposition; Logic gate; Computer engineering; Computer hardware; Engineering","score_opus":0.01600305731224017,"score_gpt":0.27043342273614907,"score_spread":0.2544303654239089,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1624781543","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00019166876,0.000051891857,0.99093556,0.00017678627,0.000056122528,0.00016077084,0.0000021686155,0.0012612757,0.007163749],"genre_scores_gemma":[0.11104804,0.0000024406952,0.88836056,0.00019029267,0.00007168104,0.00005545911,0.000005350461,0.000021708523,0.00024445512],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996276,0.0000040032555,0.000095457486,0.00007995474,0.00004603604,0.00014697172],"domain_scores_gemma":[0.99979085,0.000034322253,0.000007144185,0.00009846011,0.000013475136,0.0000557527],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000089284535,0.000073877854,0.0000824671,0.0000435014,0.000029055402,0.000022649987,0.00005446114,0.00004856209,0.00010431062],"category_scores_gemma":[0.000011484156,0.00007047878,0.000052392923,0.00007252626,0.0000032396802,0.000057590212,0.0000031803324,0.00004295848,0.00001876506],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000021247646,0.00004799563,0.00004785057,0.00019725195,0.00006757158,0.000008331883,0.000374121,0.50349075,0.12644526,0.09151379,0.088522725,0.18926308],"study_design_scores_gemma":[0.0007485736,0.00008217135,0.000025095092,0.000038845097,0.000017813,0.0000033611955,0.000016919403,0.07981208,0.8590912,0.03645243,0.023484085,0.00022741278],"about_ca_topic_score_codex":0.00005254095,"about_ca_topic_score_gemma":0.000019747997,"teacher_disagreement_score":0.7326459,"about_ca_system_score_codex":0.00003864171,"about_ca_system_score_gemma":0.000024646846,"threshold_uncertainty_score":0.28740412},"labels":[],"label_agreement":null},{"id":"W1636696700","doi":"10.1109/iscas.1999.780103","title":"VLSI concentric partitioning using interior point quadratic programming","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Quadratic programming; Very-large-scale integration; Quadratic equation; Mathematical optimization; Computer science; Fixed point; Point (geometry); Moment (physics); Boundary (topology); Algorithm; Mathematics; Parallel computing; Embedded system; Geometry; Mathematical analysis","score_opus":0.018500592423677846,"score_gpt":0.2361099254195097,"score_spread":0.21760933299583185,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1636696700","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14267372,0.00048123454,0.8440286,0.000009361398,0.00020004116,0.00027878545,5.254182e-7,0.0014084184,0.010919335],"genre_scores_gemma":[0.94966394,0.000012958442,0.050153207,0.000037509926,0.000025264468,0.000023948305,0.000001125175,0.000025789117,0.000056229695],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993221,0.000025604337,0.0002045631,0.00011063433,0.00007788916,0.0002592072],"domain_scores_gemma":[0.9997574,0.000014904413,0.000019239398,0.00012349109,0.000023684914,0.00006125663],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013143927,0.00011805219,0.00012804214,0.00005277388,0.000058780817,0.00007789866,0.000056340083,0.000051432344,0.00021042401],"category_scores_gemma":[0.000030800024,0.00011314981,0.000044906228,0.00019055353,0.000020760455,0.0001682773,0.000008273745,0.00009379441,0.000027097578],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019177043,0.00026741027,0.02640987,0.0013620408,0.00047461945,0.00028797484,0.0054560727,0.013978276,0.5979279,0.09589748,0.006476322,0.25144282],"study_design_scores_gemma":[0.00079982384,0.00018456735,0.00018462888,0.0004950628,0.00008795933,0.0002337995,0.0012676021,0.20423909,0.7605371,0.0028520136,0.027831854,0.0012865341],"about_ca_topic_score_codex":0.00001153041,"about_ca_topic_score_gemma":0.000004166689,"teacher_disagreement_score":0.80699027,"about_ca_system_score_codex":0.00007942427,"about_ca_system_score_gemma":0.000012136958,"threshold_uncertainty_score":0.46141154},"labels":[],"label_agreement":null},{"id":"W1642572343","doi":"10.1007/3-540-70734-4_18","title":"A Local Refinement Algorithm for Data Partitioning","year":2001,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Workload; Context (archaeology); Algorithm; Space partitioning; Graph partition; Parallel computing; Enhanced Data Rates for GSM Evolution; Metis; Theoretical computer science; Graph; Artificial intelligence","score_opus":0.03256385869187683,"score_gpt":0.25787329483221677,"score_spread":0.22530943614033994,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1642572343","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[7.2040973e-7,0.0005083954,0.9947286,0.00005748922,0.0005049707,0.00031019136,0.000042199925,0.00032924686,0.0035181744],"genre_scores_gemma":[0.0062091057,0.0001671069,0.99231964,0.00033492435,0.00057251775,0.000032619162,0.00012928253,0.000060673712,0.00017412148],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985171,0.0000037913057,0.00026443668,0.0005766311,0.00028231775,0.00035570047],"domain_scores_gemma":[0.99892765,0.00010997908,0.000043661465,0.00079424697,0.000059036338,0.00006541107],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00037719114,0.000260547,0.00025241438,0.00024168823,0.000090448375,0.00011450822,0.0009945476,0.00018297191,0.000033358305],"category_scores_gemma":[0.0000130607805,0.00025395193,0.00004193458,0.00013350692,0.00020208399,0.00017375048,0.00028837408,0.00030981773,0.000008848694],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[6.192432e-7,0.000003964254,9.681004e-7,0.000025075731,0.000006531694,0.000013897261,0.00003034102,0.016849631,0.000030323716,0.00040086682,0.00039105935,0.9822467],"study_design_scores_gemma":[0.000096174634,0.000062045474,0.0000014527773,0.00022952112,0.000008674828,0.000020043337,5.541547e-8,0.9369728,0.0012117381,0.028244175,0.03285417,0.00029917323],"about_ca_topic_score_codex":0.000009548564,"about_ca_topic_score_gemma":0.000036374535,"teacher_disagreement_score":0.98194754,"about_ca_system_score_codex":0.00016597871,"about_ca_system_score_gemma":0.00006396738,"threshold_uncertainty_score":0.9999913},"labels":[],"label_agreement":null},{"id":"W1648726702","doi":"10.1007/s10589-015-9779-8","title":"Eigenvalue, quadratic programming, and semidefinite programming relaxations for a cut minimization problem","year":2015,"lang":"en","type":"article","venue":"Computational Optimization and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Air Force Office of Scientific Research; Natural Sciences and Engineering Research Council of Canada; Pacific Institute for the Mathematical Sciences","keywords":"Mathematics; Semidefinite programming; Maximum cut; Eigenvalues and eigenvectors; Quadratic programming; Adjacency matrix; Graph partition; Combinatorics; Laplacian matrix; Vertex (graph theory); Quadratic equation; Mathematical optimization; Graph","score_opus":0.02330850243936596,"score_gpt":0.2572272012488267,"score_spread":0.23391869880946073,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1648726702","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00020562985,0.00037239736,0.99604416,0.0001883607,0.000022553346,0.0017573648,0.00002659024,0.0006107082,0.00077221665],"genre_scores_gemma":[0.09691165,0.000092807284,0.8991252,0.00007879864,0.00007337723,0.0027655521,0.00081014785,0.000045177912,0.000097268974],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991293,0.000019650084,0.00032075372,0.00023439132,0.00013506466,0.00016084513],"domain_scores_gemma":[0.9992577,0.000110541885,0.00008615823,0.00010378895,0.00029440626,0.00014742471],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013777988,0.00015600541,0.00014073963,0.00014593994,0.0002094732,0.00015379731,0.00006449102,0.00008798767,0.0000038734825],"category_scores_gemma":[0.000031255036,0.000170099,0.00002728208,0.00034307133,0.00006823007,0.00022507024,0.000019667654,0.00006885027,0.000003075233],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000035806027,0.00004630533,0.00016709248,0.000087148466,0.000022317432,1.1001493e-7,0.0004817412,0.93932223,0.000009079987,0.031020453,0.0008103662,0.028029567],"study_design_scores_gemma":[0.0004611123,0.00005740945,0.000037580176,0.000024277851,0.000041067604,0.000012871833,0.00020393681,0.96456975,0.00003105199,0.011197895,0.023143293,0.0002197767],"about_ca_topic_score_codex":0.0000021225856,"about_ca_topic_score_gemma":0.0000023903306,"teacher_disagreement_score":0.096918955,"about_ca_system_score_codex":0.000041989617,"about_ca_system_score_gemma":0.000052052143,"threshold_uncertainty_score":0.69364357},"labels":[],"label_agreement":null},{"id":"W1669114967","doi":"10.1109/fpl.2015.7293955","title":"Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":21,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Verilog; Computer science; FPGA prototype; Bitstream; Embedded system; Routing (electronic design automation); Application-specific integrated circuit; Computer architecture; Computer hardware","score_opus":0.018248094371866,"score_gpt":0.20826393290052303,"score_spread":0.19001583852865703,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1669114967","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007020632,0.0013224472,0.7991359,0.00041703542,0.00053582346,0.0004945805,0.000030253786,0.0028388547,0.18820447],"genre_scores_gemma":[0.97268355,0.000039320155,0.022051102,0.00047228317,0.00015345703,0.000062926076,0.000009415158,0.000073930474,0.0044540362],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.998995,0.000028134522,0.00019371066,0.00016846802,0.00020361313,0.00041108188],"domain_scores_gemma":[0.9993609,0.000070025475,0.00001639159,0.0003407337,0.00005018602,0.00016174605],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00044280916,0.00017892363,0.00018086136,0.000045454046,0.000084829284,0.00008682914,0.00030939255,0.0000972832,0.00011185363],"category_scores_gemma":[0.00009742252,0.00012915731,0.000044154607,0.0002507584,0.000019985138,0.00015183011,0.000058843485,0.00016913701,0.0003170421],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005211027,0.000020275205,0.00028468677,0.000020590995,0.00004035238,0.000005403866,0.0004727406,0.012128155,0.011559459,0.00049944944,0.9559714,0.018992247],"study_design_scores_gemma":[0.00021698035,0.0000896147,0.000029591483,0.00003349767,0.000030158411,0.000013596013,0.00050798396,0.2176873,0.33417925,0.00096675806,0.44562143,0.00062382687],"about_ca_topic_score_codex":0.0001526256,"about_ca_topic_score_gemma":0.000012251921,"teacher_disagreement_score":0.9656629,"about_ca_system_score_codex":0.00009162849,"about_ca_system_score_gemma":0.000021767379,"threshold_uncertainty_score":0.5266883},"labels":[],"label_agreement":null},{"id":"W1669973258","doi":"10.1109/fpl.2015.7294008","title":"Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Benchmark (surveying); Routing (electronic design automation); Computer science; Field-programmable gate array; Lookup table; Parallel computing; CAD; Very-large-scale integration; Suite; Path (computing); Electronic design automation; Design flow; Embedded system; Engineering","score_opus":0.042004343270136545,"score_gpt":0.2853053944184735,"score_spread":0.24330105114833697,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1669973258","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.27033386,0.00038800694,0.6992479,0.000058763115,0.00016702991,0.0015214393,0.000023327804,0.00047548863,0.027784217],"genre_scores_gemma":[0.9746415,0.0000030334247,0.025054792,0.000014948486,0.000053851807,0.00016249066,0.000022511824,0.000015791204,0.000031071322],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992209,0.000044405733,0.00020822634,0.00012324174,0.0002665759,0.0001366639],"domain_scores_gemma":[0.99940616,0.0000474843,0.000025155368,0.00024606741,0.00022616198,0.000048984],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0012815302,0.00010617955,0.0001690428,0.00005414055,0.000012357735,0.000010807894,0.00009246696,0.00008950582,0.00017197714],"category_scores_gemma":[0.00018248899,0.0000885909,0.00006170538,0.000085287444,0.000021517993,0.000072862,0.000011698899,0.000073876196,0.0000015737374],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00013354786,0.00012683072,0.003376452,0.00036819067,0.00013719405,3.4604315e-7,0.002465791,0.026075711,0.036023915,0.0008358401,0.020493058,0.90996313],"study_design_scores_gemma":[0.0028543388,0.00060656294,0.003481975,0.00007319235,0.00022815834,0.000010221954,0.00026799005,0.6368546,0.29218432,0.053708676,0.009019592,0.00071038556],"about_ca_topic_score_codex":0.000009686113,"about_ca_topic_score_gemma":0.000014469136,"teacher_disagreement_score":0.90925276,"about_ca_system_score_codex":0.00007673459,"about_ca_system_score_gemma":0.00004744378,"threshold_uncertainty_score":0.36126322},"labels":[],"label_agreement":null},{"id":"W1719971006","doi":"10.3233/ica-2005-12406","title":"Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing","year":2005,"lang":"en","type":"article","venue":"Integrated Computer-Aided Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Simulated annealing; Macro; Algorithm; Genetic algorithm; Computer science; Electronic engineering; Engineering; Machine learning; Programming language","score_opus":0.01192997485710373,"score_gpt":0.2155752214681823,"score_spread":0.20364524661107858,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1719971006","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2245324,0.00019058463,0.7729549,0.000005064381,0.0001455497,0.0005053107,0.0000371179,0.001606232,0.000022836364],"genre_scores_gemma":[0.56843364,0.0000102168715,0.43100217,0.000020703252,0.00033366922,0.000034616394,0.000039633193,0.00011800146,0.000007365041],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99822813,0.000020211433,0.00042561212,0.00041765207,0.00020647534,0.00070189114],"domain_scores_gemma":[0.999184,0.00012273484,0.00005658025,0.00031812178,0.00013691829,0.00018160672],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00011376548,0.0005455483,0.00048150992,0.000308668,0.00008485906,0.00013117059,0.00028468136,0.00011281859,0.0000080992395],"category_scores_gemma":[0.00000544892,0.0005178768,0.00013729978,0.00040466382,0.00002299088,0.00019715821,0.00003466493,0.00036290067,0.000007708071],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000145111835,0.000049358932,0.0000055976025,0.000083455525,0.00012007921,0.00003591615,0.00013802807,0.9193756,0.04889804,0.000011118455,0.00021623794,0.031052044],"study_design_scores_gemma":[0.0007258898,0.00025563705,0.000008172226,0.00015298188,0.00006319147,0.000058829515,0.000012011627,0.8311507,0.16620399,0.000020974749,0.0008033869,0.00054420345],"about_ca_topic_score_codex":0.000024222794,"about_ca_topic_score_gemma":0.0000012289264,"teacher_disagreement_score":0.34390122,"about_ca_system_score_codex":0.00033968003,"about_ca_system_score_gemma":0.000038396713,"threshold_uncertainty_score":0.9997273},"labels":[],"label_agreement":null},{"id":"W1727049600","doi":"10.1002/9780470050118.ecse312","title":"<scp>VLSI</scp>Circuit Layout","year":2008,"lang":"en","type":"other","venue":"Wiley Encyclopedia of Computer Science and Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":21,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Very-large-scale integration; Floorplan; Physical design; Routing (electronic design automation); Computer science; Computer architecture; Process (computing); Electronic engineering; Circuit design; Computer engineering; Engineering; Embedded system","score_opus":0.006744121841082527,"score_gpt":0.18103792858716716,"score_spread":0.17429380674608463,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1727049600","genre_codex":"other","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0016534505,0.007900399,0.3666991,0.0000037534041,0.002241588,0.0004286585,0.000032695854,0.0028571351,0.6181832],"genre_scores_gemma":[0.0921312,0.2875177,0.41061792,0.00046343755,0.015666973,0.0004908045,0.00012095533,0.0063253413,0.18666567],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9983998,0.0000053396107,0.00028099105,0.0003735207,0.00045560082,0.00048474237],"domain_scores_gemma":[0.9992439,0.00005538797,0.00006212095,0.00039468397,0.00005413003,0.00018975022],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00018376854,0.00037759522,0.0004458129,0.0007413868,0.000045506094,0.000048317394,0.00055746746,0.00022961739,0.0000143423795],"category_scores_gemma":[0.000035161745,0.00038854763,0.00006211237,0.00056857866,0.00019367736,0.00020074242,0.00012070732,0.00026619647,0.000019369587],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[2.5292104e-7,0.000030685824,0.00025467505,0.000894064,0.00008433422,0.000062012725,0.0011128725,0.007956531,0.0015084905,0.00058817526,0.92684007,0.06066786],"study_design_scores_gemma":[0.00013523143,0.00005662452,0.00031459722,0.00067515863,0.0000193413,0.000059585243,0.0000059770314,0.061694026,0.00069259695,0.000031489122,0.93600464,0.0003107176],"about_ca_topic_score_codex":0.000021868185,"about_ca_topic_score_gemma":0.0000018148291,"teacher_disagreement_score":0.43151754,"about_ca_system_score_codex":0.00004555406,"about_ca_system_score_gemma":0.000070860726,"threshold_uncertainty_score":0.99985665},"labels":[],"label_agreement":null},{"id":"W1734210446","doi":"10.1109/ccece.2001.933559","title":"Unified simulator: an alternative to traditional simulation techniques","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor; Toronto Metropolitan University","funders":"","keywords":"Computer science; Component (thermodynamics); Electronic circuit simulation; Electronic circuit; Point (geometry); Simple (philosophy); Circuit extraction; Analogue electronics; Electronic engineering; Simulation modeling; Simulation; Computer engineering; Equivalent circuit; Engineering; Electrical engineering; Mathematics","score_opus":0.06586304742031587,"score_gpt":0.26363719960755355,"score_spread":0.19777415218723768,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1734210446","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.045199826,0.000025587713,0.8801387,0.000060693317,0.00009586847,0.0004062013,0.000020695994,0.004210571,0.06984187],"genre_scores_gemma":[0.985025,0.000008176175,0.014330905,0.00018716644,0.00015442797,0.00002998227,0.000011558687,0.000027710268,0.00022508782],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994312,0.000014393753,0.00014255401,0.00013422275,0.00013619252,0.00014145594],"domain_scores_gemma":[0.99965316,0.00004656449,0.000009926565,0.00015655353,0.00003717418,0.00009661165],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000058894053,0.000117350464,0.00009646432,0.0001322423,0.00003541231,0.000031604297,0.0001123315,0.00006809023,0.00071851246],"category_scores_gemma":[0.000008663113,0.00011637816,0.000030009433,0.00012902044,0.000010647559,0.00026852422,0.0000074288737,0.00008012049,0.000079014826],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008195171,0.00014946391,0.00007199165,0.000020846444,0.00004146559,0.000011613387,0.0009218411,0.7853642,0.027450448,0.017869595,0.012117367,0.15597299],"study_design_scores_gemma":[0.00006519395,0.00012175101,0.00013649334,0.000008865912,0.000003710992,0.0000014845272,0.000009995661,0.9073497,0.08224115,0.00304454,0.006816432,0.00020070978],"about_ca_topic_score_codex":0.000006517942,"about_ca_topic_score_gemma":0.000002774109,"teacher_disagreement_score":0.9398252,"about_ca_system_score_codex":0.000057821417,"about_ca_system_score_gemma":0.0000014785903,"threshold_uncertainty_score":0.78672075},"labels":[],"label_agreement":null},{"id":"W1750273152","doi":"10.1109/iscas.1993.394055","title":"Circuit partitioning using a Tabu search approach","year":2002,"lang":"en","type":"article","venue":"1993 IEEE International Symposium on Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Tabu search; Netlist; Simulated annealing; Guided Local Search; Hill climbing; Computer science; Mathematical optimization; Job shop scheduling; Algorithm; Theoretical computer science; Mathematics; Schedule","score_opus":0.08049535451018379,"score_gpt":0.2574485584508043,"score_spread":0.17695320394062047,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1750273152","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5028975,0.0019064358,0.20237243,0.000133291,0.004816778,0.001117055,0.00014863361,0.0015457764,0.28506207],"genre_scores_gemma":[0.9984671,0.00019152516,0.00004956617,0.000041439493,0.0005682271,0.000057953992,0.000013234235,0.00004353922,0.00056742824],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986631,0.00004393108,0.00032414641,0.0002758367,0.00041670122,0.0002762411],"domain_scores_gemma":[0.9995524,0.000049077018,0.00004304711,0.00017405793,0.000074912634,0.00010649337],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00024531607,0.00019229228,0.00021188012,0.0001503139,0.000119228316,0.00024143327,0.00019541898,0.00011745813,0.000053144366],"category_scores_gemma":[0.000005475154,0.00019138564,0.00005956294,0.00012226269,0.00003547666,0.00020524592,0.00001285495,0.00019955928,0.000042517055],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011634098,0.00055427116,0.00833828,0.00096003135,0.00090048806,0.00013773135,0.0055467985,0.36142159,0.543219,0.043722495,0.013665178,0.021522503],"study_design_scores_gemma":[0.00032462695,0.00005713344,0.00016251409,0.00020197168,0.00001626558,0.00021498809,0.000116169795,0.99016327,0.0035449916,0.000057799785,0.004777967,0.00036227764],"about_ca_topic_score_codex":0.0000888254,"about_ca_topic_score_gemma":9.792974e-7,"teacher_disagreement_score":0.6287417,"about_ca_system_score_codex":0.00015767553,"about_ca_system_score_gemma":0.000004571578,"threshold_uncertainty_score":0.78044796},"labels":[],"label_agreement":null},{"id":"W175193922","doi":"","title":"Further constructions for BIB designs with nested rows and columns.","year":2008,"lang":"en","type":"article","venue":"Ars Combinatoria","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Mathematics; Row; Row and column spaces; Arithmetic; Computer science; Programming language","score_opus":0.017321915887473123,"score_gpt":0.2063566414762262,"score_spread":0.1890347255887531,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W175193922","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.97999334,0.00030582366,0.014662155,0.000049325197,0.00043515253,0.00064460206,0.000012703726,0.00097188755,0.0029249825],"genre_scores_gemma":[0.9935407,0.00007307703,0.0060907253,0.00002039123,0.000008400294,0.000121362325,0.000004514693,0.000038771526,0.00010202469],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9995088,0.000011559987,0.00011100104,0.0001245419,0.000068005706,0.00017609437],"domain_scores_gemma":[0.9996591,0.00005800126,0.000018670813,0.0001457895,0.000051955172,0.000066434404],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000048739512,0.0001202966,0.00014702564,0.00007439935,0.000114611204,0.000019641331,0.00006409534,0.00007708788,0.0000133042395],"category_scores_gemma":[0.000008636137,0.000115314826,0.00002405934,0.00017125237,0.000094990224,0.000104306884,0.000008290381,0.00008007154,0.0000045058027],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00026043007,0.0004896317,0.077471115,0.00058125425,0.0009867348,0.00028283606,0.0064060763,0.00073370134,0.067807354,0.6402755,0.1766708,0.028034575],"study_design_scores_gemma":[0.020018898,0.0045714444,0.062015776,0.00047599987,0.0005552907,0.0033039083,0.0014935489,0.032157484,0.1892842,0.60097086,0.07996244,0.0051901634],"about_ca_topic_score_codex":0.000010741121,"about_ca_topic_score_gemma":0.0000059196464,"teacher_disagreement_score":0.12147686,"about_ca_system_score_codex":0.000023397557,"about_ca_system_score_gemma":0.00002025715,"threshold_uncertainty_score":0.4702402},"labels":[],"label_agreement":null},{"id":"W177835669","doi":"10.1007/978-3-319-05960-0_7","title":"Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry","year":2014,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Debugging; Field-programmable gate array; Computer science; Observability; Embedded system; Background debug mode interface; Process (computing); TRACE (psycholinguistics); Construct (python library); Computer hardware; Operating system; Programming language","score_opus":0.010258751835662924,"score_gpt":0.2026206263339288,"score_spread":0.19236187449826586,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W177835669","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0034553164,0.00018437408,0.9902343,0.000023147106,0.0006636144,0.00036385894,0.000004612725,0.00053525885,0.0045355177],"genre_scores_gemma":[0.9520523,0.00002982518,0.04688255,0.00030815828,0.00031311857,0.0000134745405,0.0000057657517,0.000112463276,0.00028232913],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99766624,0.0000068896416,0.00035653694,0.00074967643,0.00064023095,0.00058041594],"domain_scores_gemma":[0.99888545,0.00011853966,0.0000934322,0.00067824346,0.00009075488,0.00013355818],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003418779,0.0005336001,0.00046305233,0.000505553,0.00012012732,0.00024056796,0.0009283058,0.00035459767,0.000038843707],"category_scores_gemma":[0.00001152478,0.0004550436,0.00007418743,0.00025979793,0.00034614155,0.0001760668,0.00014639243,0.0007858409,0.000034113713],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008314434,0.00001721018,0.00028410007,0.00017290133,0.000033333596,0.00004933293,0.0004206955,0.40134168,0.0015831349,0.0006097699,0.00004691146,0.59543264],"study_design_scores_gemma":[0.0005590643,0.0003289978,0.0001682839,0.0014220255,0.000037674818,0.00012504408,3.4202597e-7,0.9555058,0.029425899,0.0050311484,0.0057898904,0.001605848],"about_ca_topic_score_codex":0.000004556646,"about_ca_topic_score_gemma":0.00001857814,"teacher_disagreement_score":0.948597,"about_ca_system_score_codex":0.00022752628,"about_ca_system_score_gemma":0.00008538633,"threshold_uncertainty_score":0.99979013},"labels":[],"label_agreement":null},{"id":"W1827007993","doi":"10.1109/isqed.2005.125","title":"Toward Quality EDA Tools and Tool Flows Through High-Performance Computing","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Binghamton University; University of Waterloo; Purdue University","keywords":"Computer science; Leverage (statistics); Bottleneck; Electronic design automation; Automation; Turnaround time; Quality (philosophy); Time to market; Design flow; Pareto principle; Computer engineering; Software engineering; Embedded system; Operating system; Engineering","score_opus":0.04092748868379135,"score_gpt":0.2640521434784959,"score_spread":0.22312465479470459,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1827007993","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8118842,0.0001820433,0.1711159,0.00008814972,0.000085021486,0.00013084228,0.0000046799737,0.0012088941,0.015300258],"genre_scores_gemma":[0.9218061,0.0001659116,0.077523984,0.00019912113,0.0001792958,0.0000059411623,0.0000047349154,0.000017805552,0.000097101736],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99928564,0.000013410155,0.00024272774,0.00013982502,0.00010123311,0.00021716004],"domain_scores_gemma":[0.99971926,0.00005057566,0.000016656553,0.0001647023,0.000018277005,0.000030508763],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018465573,0.00013375023,0.00017272985,0.000022705652,0.00005027423,0.00006187843,0.00009645684,0.00007649683,0.00007972567],"category_scores_gemma":[0.000010915603,0.00012070189,0.000023190178,0.000072821036,0.000016763146,0.0004501918,0.00003708851,0.00012464625,0.000040085673],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000009326058,0.00003432553,0.0017087141,0.00029365468,0.00005167987,0.0000032480486,0.0014010015,0.009949556,0.019261139,0.010766036,0.0065705297,0.9499508],"study_design_scores_gemma":[0.0010875375,0.00016020397,0.03628941,0.00014455499,0.000028597728,0.00003989959,0.00017718313,0.4534875,0.45260936,0.0012925965,0.05318513,0.0014980349],"about_ca_topic_score_codex":0.000028504024,"about_ca_topic_score_gemma":0.0000058625533,"teacher_disagreement_score":0.9484528,"about_ca_system_score_codex":0.00003617205,"about_ca_system_score_gemma":0.00000513103,"threshold_uncertainty_score":0.49220803},"labels":[],"label_agreement":null},{"id":"W1827532909","doi":"10.1007/s00453-002-0964-7","title":"Budget Management with Applications","year":2002,"lang":"en","type":"article","venue":"Algorithmica","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Computer science; Theory of computation; Directed graph; Vertex (graph theory); Directed acyclic graph; Graph; Set (abstract data type); Mathematical optimization; Path (computing); Transitive relation; Sensitivity (control systems); Mathematics; Algorithm; Theoretical computer science; Combinatorics","score_opus":0.005821349516441284,"score_gpt":0.17402018645245723,"score_spread":0.16819883693601595,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1827532909","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00017322782,0.000330787,0.8282007,0.00007743479,0.000025963458,0.0003312123,0.000005872693,0.0012989938,0.16955584],"genre_scores_gemma":[0.7413628,0.00048786058,0.25347826,0.00016747319,0.00018565118,0.0008957156,0.000014369843,0.00007756037,0.0033303075],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9996253,0.0000028866423,0.000069471316,0.0000959075,0.00007398983,0.0001324156],"domain_scores_gemma":[0.99974185,0.000006040245,0.0000068146337,0.00019833379,0.000009678175,0.00003728897],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000018932664,0.00007883005,0.00006210784,0.000048673857,0.000032162978,0.000015717016,0.000103303006,0.000027743434,0.000138235],"category_scores_gemma":[1.8924467e-7,0.00006999549,0.00001599627,0.00013936695,0.000016125136,0.000045073735,0.000010435546,0.000059136262,0.00024453964],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[9.509502e-7,0.000059840077,0.000029549816,0.00006684951,0.000104095416,0.000027103979,0.00009707339,0.00024436467,0.00041448727,0.007908257,0.054957807,0.93608963],"study_design_scores_gemma":[0.00042674295,0.00008578825,0.00026690797,0.00003209231,0.000059545473,0.000045319262,0.000057689074,0.06971344,0.013667573,0.002614813,0.9124728,0.0005572756],"about_ca_topic_score_codex":0.00000101949,"about_ca_topic_score_gemma":3.6631786e-7,"teacher_disagreement_score":0.93553233,"about_ca_system_score_codex":0.000019308987,"about_ca_system_score_gemma":4.628373e-7,"threshold_uncertainty_score":0.3143144},"labels":[],"label_agreement":null},{"id":"W1857907604","doi":"10.1109/ccece.2000.849631","title":"Genetic algorithm for the assignment of cells to switches in personal communication networks","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Computer science; Convergence (economics); Heuristic; Genetic algorithm; Mathematical optimization; Adaptation (eye); Resolution (logic); Distributed computing; Artificial intelligence; Mathematics; Machine learning","score_opus":0.01725618145104338,"score_gpt":0.2049110638133634,"score_spread":0.18765488236232003,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1857907604","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0016618912,0.0011449584,0.9958463,0.000081389655,0.00002599868,0.00031671597,0.0000020193158,0.00006461883,0.0008561083],"genre_scores_gemma":[0.9178626,0.00041554618,0.081390865,0.00005639657,0.000020763715,0.00010950047,6.77563e-7,0.000010755905,0.00013292814],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99968696,0.000007905647,0.000114323964,0.000046783847,0.000049719325,0.00009430839],"domain_scores_gemma":[0.9997305,0.00008823479,0.000009697542,0.00014362387,0.000010902574,0.00001702954],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000093865616,0.000052655872,0.000067143774,0.00002729882,0.000017848814,0.000007823095,0.00012669661,0.000035157682,0.00006664691],"category_scores_gemma":[0.0000016207181,0.000039333452,0.000024907684,0.00006870833,0.000009428892,0.000017198718,0.000014571425,0.000050456445,0.0000028997713],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000014608894,0.0000442666,0.00012653689,0.000016838983,0.000024446159,2.2720171e-7,0.0011162263,0.0625077,0.008043257,0.00006113385,0.019129418,0.9089285],"study_design_scores_gemma":[0.00007234846,0.000029108798,0.00051691616,0.0000114221,0.000004491129,3.45675e-7,0.00008454478,0.9820938,0.015743854,0.00004556554,0.0013420751,0.00005554245],"about_ca_topic_score_codex":0.000020344369,"about_ca_topic_score_gemma":0.000010395371,"teacher_disagreement_score":0.91958606,"about_ca_system_score_codex":0.000025397552,"about_ca_system_score_gemma":9.747911e-7,"threshold_uncertainty_score":0.16039716},"labels":[],"label_agreement":null},{"id":"W1890393032","doi":"10.1109/newcas.2004.1359111","title":"A fast adaptive heuristic for FPGA placement","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Simulated annealing; Heuristic; Computation; Routing (electronic design automation); Placement; Compiler; Compile time; Parallel computing; Convergence (economics); Embedded system; Computer engineering; Algorithm; Physical design; Artificial intelligence; Circuit design","score_opus":0.033041792017859124,"score_gpt":0.2513717674783745,"score_spread":0.21832997546051536,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1890393032","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13727434,0.025951393,0.79801995,0.00093466975,0.005765771,0.010171524,0.0023575777,0.0035053436,0.016019434],"genre_scores_gemma":[0.99655867,0.00019462692,0.00008661805,0.00016260987,0.00089335005,0.0004181162,0.00002762846,0.00013419533,0.0015241926],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99741685,0.0000895297,0.0006779446,0.0005338523,0.00044277133,0.0008390397],"domain_scores_gemma":[0.9985884,0.00024674152,0.0001384217,0.0005663969,0.00017672463,0.00028331732],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00057652453,0.0005967291,0.00063892745,0.00018543913,0.00042340826,0.00019247872,0.00037547344,0.00026357247,0.000016712092],"category_scores_gemma":[0.00002983054,0.00044874498,0.00016612907,0.00032235103,0.00014245923,0.0002005595,0.000025199954,0.00043793352,0.00006543215],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003056313,0.00047982202,0.00009406762,0.0007452911,0.00066779007,0.00012446869,0.009412989,0.8551292,0.0007451864,0.0070708706,0.04494499,0.08027971],"study_design_scores_gemma":[0.056610808,0.017622873,0.003909463,0.03016131,0.003716472,0.0058059883,0.17568752,0.27120775,0.014070414,0.02194221,0.371578,0.027687168],"about_ca_topic_score_codex":0.00012257554,"about_ca_topic_score_gemma":0.00008670638,"teacher_disagreement_score":0.85928434,"about_ca_system_score_codex":0.0002464924,"about_ca_system_score_gemma":0.00007713465,"threshold_uncertainty_score":0.99979645},"labels":[],"label_agreement":null},{"id":"W1894282346","doi":"10.1002/nme.5003","title":"A multilevel tabu search algorithm for balanced partitioning of unstructured grids","year":2015,"lang":"en","type":"article","venue":"International Journal for Numerical Methods in Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Tabu search; Partition (number theory); Grid; Algorithm; Cluster analysis; Unstructured grid; Computer science; Graph partition; Iterative method; Search algorithm; Mathematical optimization; Mathematics; Theoretical computer science; Combinatorics; Geometry; Graph","score_opus":0.05758514904295582,"score_gpt":0.4068624143791758,"score_spread":0.34927726533622,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1894282346","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0012522958,0.00020243698,0.99589735,0.000032424232,0.0022001674,0.00020858792,0.00004617563,0.0001180426,0.00004253876],"genre_scores_gemma":[0.09900352,0.000027040613,0.9004302,0.000012610578,0.00038394693,0.00007792097,0.0000099003255,0.00004199843,0.000012839514],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99888104,0.00003381833,0.00046381023,0.00012085162,0.00024052971,0.0002599399],"domain_scores_gemma":[0.9990596,0.0003729719,0.000055407017,0.00007648521,0.00031070824,0.00012478768],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00089345407,0.0001459162,0.00027099752,0.00028262063,0.00001939502,0.00004152656,0.00029259844,0.0000924385,0.000008052244],"category_scores_gemma":[0.00049981975,0.00014552374,0.00013081684,0.00013527242,0.000015623506,0.00016948949,0.000026269416,0.0002674098,3.6884572e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004132778,0.000029389403,0.00013202596,0.000054096086,0.00014171966,0.000007994211,0.00033046663,0.4239415,0.03395318,0.0006099179,0.0003395716,0.54041886],"study_design_scores_gemma":[0.0008438828,0.00007595491,0.00013619626,0.00009388558,0.000008146048,0.00006435904,0.000040465027,0.92406857,0.06917624,0.0025168213,0.0028210445,0.000154457],"about_ca_topic_score_codex":0.0000048433944,"about_ca_topic_score_gemma":1.5691623e-7,"teacher_disagreement_score":0.54026437,"about_ca_system_score_codex":0.00021230328,"about_ca_system_score_gemma":0.000030790543,"threshold_uncertainty_score":0.5934286},"labels":[],"label_agreement":null},{"id":"W1899813288","doi":"10.1109/iscas.2004.1329462","title":"A placement algorithm for implementation of analog LSI/VLSI systems","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Simulated annealing; Nondeterministic algorithm; Computer science; Very-large-scale integration; Algorithm; Analogue electronics; Placement; Adder; Floorplan; Electronic circuit; Mathematical optimization; Physical design; Circuit design; Mathematics; Engineering; Embedded system","score_opus":0.011896560394724249,"score_gpt":0.2670548869184798,"score_spread":0.25515832652375553,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1899813288","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0052393535,0.00011986238,0.99262,0.000009506471,0.00009540372,0.00048463425,0.000033840483,0.00027465227,0.0011227338],"genre_scores_gemma":[0.9376979,0.000029850706,0.06193015,0.000012030459,0.000045200082,0.00018126657,0.000026207174,0.000017316526,0.00006010571],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99955696,0.0000033125234,0.00018454783,0.00006616222,0.00007308662,0.00011593646],"domain_scores_gemma":[0.99983305,0.000009732906,0.000020879095,0.00008246393,0.000030701434,0.000023193285],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008769566,0.00006788096,0.00010226125,0.00006168605,0.000014391338,0.000010270753,0.00004891537,0.00003172674,0.000025742786],"category_scores_gemma":[8.3040436e-7,0.00006292748,0.000034338223,0.00006130014,0.000005377595,0.00005491309,0.0000054160705,0.000020614338,0.000002650307],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014564411,0.00015153873,0.00048383747,0.001351333,0.0005974259,0.000007611968,0.0019763391,0.051431634,0.16296487,0.053234164,0.023598183,0.7041885],"study_design_scores_gemma":[0.0025546507,0.00065520604,0.00037008326,0.00008266827,0.00006300274,0.000009509212,0.0022031749,0.076990925,0.9089742,0.0018763208,0.005783697,0.00043660295],"about_ca_topic_score_codex":0.00014415108,"about_ca_topic_score_gemma":0.000016779428,"teacher_disagreement_score":0.9324585,"about_ca_system_score_codex":0.000066059925,"about_ca_system_score_gemma":0.0000103640805,"threshold_uncertainty_score":0.25661084},"labels":[],"label_agreement":null},{"id":"W1912498744","doi":"10.1109/cicc.1998.694976","title":"Computational field programmable architecture","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Architecture; Computer architecture; Field-programmable gate array; Computer science; Space-based architecture; Field (mathematics); Applications architecture; Reference architecture; Database-centric architecture; Embedded system; Signal processing; Computer hardware; Software architecture; Digital signal processing; Software; Operating system","score_opus":0.009117569358791003,"score_gpt":0.19043217393903963,"score_spread":0.18131460458024862,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1912498744","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019981018,0.00017529275,0.8156003,0.00025579796,0.000046151396,0.000101526515,8.47528e-7,0.0016268577,0.18019515],"genre_scores_gemma":[0.93380886,0.000010571493,0.06464762,0.00018925797,0.000040702736,0.000015323636,0.0000023659895,0.000010555391,0.0012747229],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99975246,0.0000026523714,0.000053518168,0.00004680599,0.000051293206,0.000093275616],"domain_scores_gemma":[0.9998901,0.000020728728,0.0000028342558,0.00005504368,0.0000071629183,0.000024117857],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000015250438,0.00004813469,0.00004216899,0.000028166449,0.000016209491,0.00001677937,0.000046326917,0.000033321077,0.00094095175],"category_scores_gemma":[0.0000027075455,0.000041845215,0.00001986466,0.000056939858,0.0000058244427,0.000026876383,0.0000048296074,0.00006832623,0.000078487246],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000011443911,0.000033503984,0.0002474785,0.000043855016,0.00002709278,0.000010175914,0.00021139745,0.05715198,0.00069677085,0.0047460664,0.2522276,0.6846029],"study_design_scores_gemma":[0.00020849078,0.00012304551,0.00010856377,0.000015999747,0.000006219086,0.00003553946,0.000011027174,0.78193945,0.017359735,0.021216456,0.17865355,0.00032190283],"about_ca_topic_score_codex":0.0000024229266,"about_ca_topic_score_gemma":0.000001156257,"teacher_disagreement_score":0.9318108,"about_ca_system_score_codex":0.000005463505,"about_ca_system_score_gemma":6.0130105e-7,"threshold_uncertainty_score":0.99997234},"labels":[],"label_agreement":null},{"id":"W1917545295","doi":"10.1109/ismvl.1998.679449","title":"Multiple-valued logic minimization using universal literals and cost tables","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"St. Francis Xavier University","funders":"","keywords":"Minification; Computer science; Table (database); Simulated annealing; Truth table; Logic synthesis; Algorithm; Mathematical optimization; Logic gate; Mathematics; Data mining; Programming language","score_opus":0.0377711171309873,"score_gpt":0.227321084198357,"score_spread":0.1895499670673697,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1917545295","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10935819,0.0010184272,0.87049633,0.00003314696,0.00010231731,0.00037714723,0.000015098097,0.0013725572,0.017226806],"genre_scores_gemma":[0.9563182,0.00019118575,0.042878147,0.00004812153,0.000027638136,0.0000027962753,0.0000065509416,0.000016285145,0.0005111048],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99965644,0.000011546507,0.00008679357,0.00008447082,0.0000445526,0.00011622197],"domain_scores_gemma":[0.9998411,0.000023283405,0.000010127925,0.0000720265,0.000017334678,0.00003610728],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000029517576,0.00008077594,0.00008257267,0.00006612239,0.000034353165,0.000036608995,0.00003666106,0.000058116017,0.00026629178],"category_scores_gemma":[0.000011153737,0.000076170785,0.000013627718,0.00008946934,0.000016509443,0.00017315311,0.000011151056,0.000038966686,0.000006086045],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004022176,0.00029854372,0.02836883,0.0006550659,0.0002919735,0.00015728718,0.005921896,0.120271996,0.55179167,0.021636419,0.07771321,0.1928529],"study_design_scores_gemma":[0.00020215055,0.000013259476,0.000099062636,0.000017127542,0.000008081307,0.0000079816955,0.000035329413,0.98937,0.007332741,0.00011582938,0.0026746579,0.00012379544],"about_ca_topic_score_codex":0.000022151677,"about_ca_topic_score_gemma":0.0000037792995,"teacher_disagreement_score":0.869098,"about_ca_system_score_codex":0.000027091413,"about_ca_system_score_gemma":0.0000010653869,"threshold_uncertainty_score":0.31061545},"labels":[],"label_agreement":null},{"id":"W1940302780","doi":"10.1109/iscas.1999.777927","title":"PARC: a new pyramidal FPGA architecture based on a RISC processor","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; VHDL; Computer science; Routing (electronic design automation); Reduced instruction set computing; Embedded system; Logic synthesis; Electronic design automation; Computer architecture; Clock rate; Place and route; Controller (irrigation); Computer hardware; Logic gate; Instruction set; Chip","score_opus":0.008156673063613229,"score_gpt":0.20201550860394196,"score_spread":0.19385883554032873,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1940302780","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0041079978,0.00010327327,0.75975376,0.00018893974,0.00008243682,0.00033243117,0.000003557495,0.0023017193,0.23312587],"genre_scores_gemma":[0.9730253,0.0000056177805,0.024187945,0.0004173691,0.00006381838,0.000039086037,0.0000030142576,0.00004603074,0.0022117996],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993159,0.00001679593,0.00012216662,0.0001565736,0.00014071507,0.00024783658],"domain_scores_gemma":[0.99961215,0.00003417406,0.000011136167,0.00021711577,0.000012950835,0.00011245846],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007628096,0.00016701783,0.00013343644,0.00009951352,0.000028051696,0.000033356228,0.00011017952,0.00009606342,0.00061669905],"category_scores_gemma":[0.000037550693,0.00013451511,0.000054767606,0.00017889989,0.000014325572,0.00003583747,0.0000041047533,0.0002006383,0.000098264514],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000138366,0.00047668978,0.001652703,0.0008392237,0.00013461971,0.00014320534,0.0011259766,0.19027488,0.05175683,0.014036154,0.41688448,0.32253686],"study_design_scores_gemma":[0.0013200234,0.0004122011,0.00047246847,0.00013318255,0.000031128497,0.000026241163,0.000036437952,0.061611045,0.6872146,0.016569544,0.23114581,0.001027324],"about_ca_topic_score_codex":0.00001134845,"about_ca_topic_score_gemma":0.000011677122,"teacher_disagreement_score":0.9689173,"about_ca_system_score_codex":0.000027040975,"about_ca_system_score_gemma":0.000038571467,"threshold_uncertainty_score":0.67524225},"labels":[],"label_agreement":null},{"id":"W1963318846","doi":"10.1109/mwscas.1993.343096","title":"Odd-cycle inequalities, via minimization and LP-completeness","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Wilfrid Laurier University","funders":"","keywords":"Relaxation (psychology); Planar graph; Minification; Mathematics; Combinatorics; Time complexity; Graph; Running time; Discrete mathematics; Planar; Linear programming relaxation; Linear programming; Plane (geometry); Mathematical optimization; Computer science; Geometry","score_opus":0.021101018426208165,"score_gpt":0.1913923561511974,"score_spread":0.17029133772498922,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1963318846","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06832794,0.0010904057,0.85274404,0.00010847237,0.00014772924,0.0002126737,0.000008638477,0.0023032178,0.075056896],"genre_scores_gemma":[0.9939984,0.00017158764,0.00504266,0.00008163774,0.000040030493,0.000012006846,0.0000054650213,0.000018598324,0.00062962004],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996292,0.000009701013,0.00011429248,0.00007802643,0.000055676755,0.00011312414],"domain_scores_gemma":[0.9998258,0.00002058432,0.000007968181,0.00009710064,0.000012458944,0.000036132315],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000035218833,0.00007800943,0.00008804577,0.00004871529,0.000027147007,0.00002375716,0.000044313343,0.0000481922,0.00047036866],"category_scores_gemma":[0.0000045773304,0.000074418305,0.000013009064,0.0000714111,0.0000135199225,0.000106523825,0.00001073159,0.00003894252,0.000023670511],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000106744,0.00017633007,0.0047157104,0.0008110091,0.00015025138,0.00003615083,0.00501669,0.005200241,0.07098211,0.030093273,0.12269337,0.7601142],"study_design_scores_gemma":[0.00035615423,0.00005891666,0.0012627632,0.000026758113,0.00001357333,0.000024283918,0.000098113924,0.9437728,0.025410036,0.0039464133,0.024559947,0.00047026513],"about_ca_topic_score_codex":0.000021653512,"about_ca_topic_score_gemma":0.000004715949,"teacher_disagreement_score":0.9385725,"about_ca_system_score_codex":0.000012753927,"about_ca_system_score_gemma":6.9013527e-7,"threshold_uncertainty_score":0.51502067},"labels":[],"label_agreement":null},{"id":"W1963695813","doi":"10.1007/s10878-012-9591-7","title":"Algorithms for the minimum diameter terminal Steiner tree problem","year":2013,"lang":"en","type":"article","venue":"Journal of Combinatorial Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Brock University","funders":"University of Alberta","keywords":"Steiner tree problem; Terminal (telecommunication); Theory of computation; Combinatorics; Mathematics; Computer science; Tree (set theory); Mathematical optimization; Discrete mathematics; Algorithm; Computer network","score_opus":0.010906366297011227,"score_gpt":0.2224046219714752,"score_spread":0.21149825567446398,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1963695813","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.001026027,0.00023271867,0.9948063,0.0002293066,0.0024587966,0.00054365856,0.000002129555,0.00007327763,0.0006277663],"genre_scores_gemma":[0.48551694,0.0003142317,0.5109392,0.00008544885,0.0025929532,0.00017117996,0.000007686416,0.00010057731,0.00027182634],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99918616,0.000024263292,0.00039758632,0.000058451347,0.00018603374,0.00014750434],"domain_scores_gemma":[0.9992187,0.00015501885,0.00015249905,0.000109009045,0.0003111794,0.000053569554],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002595202,0.00011756735,0.00018445191,0.00009359956,0.0000553109,0.00010394442,0.00019491256,0.00009126303,0.000046418656],"category_scores_gemma":[0.000043995216,0.00007761211,0.00011360623,0.00011335906,0.00002094948,0.00039916456,0.000011090678,0.00013950287,0.000002700106],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015190899,0.0003064897,0.00016232941,0.00018936543,0.00048075704,0.000012392674,0.0008534987,0.6229569,0.009330449,0.002688723,0.14463054,0.21823668],"study_design_scores_gemma":[0.0021691595,0.00080695096,0.00010195063,0.00007634549,0.00013642419,0.000053386288,0.000056482066,0.9710824,0.007813041,0.009707447,0.007722992,0.00027345004],"about_ca_topic_score_codex":0.0000023629298,"about_ca_topic_score_gemma":7.598026e-8,"teacher_disagreement_score":0.4844909,"about_ca_system_score_codex":0.00004978506,"about_ca_system_score_gemma":0.000021511061,"threshold_uncertainty_score":0.316493},"labels":[],"label_agreement":null},{"id":"W1963908543","doi":"10.1145/1233501.1233643","title":"Un/DoPack","year":2006,"lang":"en","type":"article","venue":"Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":33,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Interconnection; Computer science; Benchmark (surveying); Routing (electronic design automation); Place and route; Field-programmable gate array; Electronic circuit; Electronic design automation; Logic synthesis; Design flow; Channel (broadcasting); Physical design; Electronic engineering; Logic gate; Embedded system; Circuit design; Electrical engineering; Engineering; Telecommunications; Algorithm","score_opus":0.0304033614034512,"score_gpt":0.25759690438206634,"score_spread":0.22719354297861513,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1963908543","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022964077,0.00041496276,0.07329414,0.0020766356,0.002307319,0.0030259548,0.00032292723,0.006828092,0.8887659],"genre_scores_gemma":[0.96722436,0.00038533003,0.031282153,0.0001923051,0.00035573044,0.00015141883,0.000082766455,0.00013626768,0.00018968264],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99471045,0.00016495648,0.0018905605,0.0010039477,0.0014167578,0.00081333885],"domain_scores_gemma":[0.9962205,0.00097250496,0.00050822564,0.0015424523,0.00047366568,0.00028264098],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00069938344,0.00093253865,0.0012844005,0.0006018418,0.000122008954,0.00011247389,0.0030145792,0.0008086553,0.00039282485],"category_scores_gemma":[0.00027496286,0.0008820832,0.0006332699,0.0006289573,0.00066937215,0.00030528856,0.0003410579,0.0010972132,0.00005932669],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001950434,0.0007886106,0.0003203517,0.00009730151,0.00014354143,0.000065182525,0.000012954343,0.0049100094,0.9329592,0.049089175,0.005441115,0.0059775137],"study_design_scores_gemma":[0.0044172658,0.0055828276,0.050325733,0.0030988536,0.00032497264,0.00038126076,0.000049204642,0.005922259,0.88397306,0.027009133,0.014490286,0.004425114],"about_ca_topic_score_codex":0.00007013543,"about_ca_topic_score_gemma":0.00002264437,"teacher_disagreement_score":0.94426024,"about_ca_system_score_codex":0.0004198495,"about_ca_system_score_gemma":0.00013645059,"threshold_uncertainty_score":0.999363},"labels":[],"label_agreement":null},{"id":"W1965195759","doi":"10.1145/1391732.1391733","title":"On the trade-off between power and flexibility of FPGA clock networks","year":2008,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Clock network; Field-programmable gate array; Computer science; Flexibility (engineering); CPU multiplier; Digital clock manager; Clock gating; Clock domain crossing; Embedded system; Clock rate; Clock skew; Synchronous circuit; Clock drift; Clock signal; Telecommunications","score_opus":0.02241358689475075,"score_gpt":0.22132394189350213,"score_spread":0.19891035499875137,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1965195759","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9012282,0.0051039555,0.086477175,0.00087702856,0.0003009902,0.0008084555,0.000048358215,0.0012757186,0.003880114],"genre_scores_gemma":[0.9983956,0.0012724926,0.000073780124,0.000021959839,0.000012293651,0.00008326378,0.0000014020662,0.000021074775,0.00011808826],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991005,0.000052798787,0.0003219756,0.0002241269,0.00008081375,0.00021979715],"domain_scores_gemma":[0.99897593,0.00034070073,0.00004675363,0.0005730474,0.000019702535,0.00004385299],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002570531,0.00018299407,0.00033822685,0.0002492725,0.0002283329,0.000011432755,0.00021351386,0.00043141452,0.000032413114],"category_scores_gemma":[0.000020485142,0.00013892405,0.000051241357,0.00031729531,0.0002664866,0.000057700756,0.000002201127,0.0005261147,0.0000035157016],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003047316,0.0006832163,0.010834877,0.0009835629,0.00248228,0.00008254627,0.0023766272,0.06812322,0.012831991,0.057482533,0.010396638,0.8334178],"study_design_scores_gemma":[0.006557338,0.009378178,0.03189471,0.003115098,0.000880958,0.0031311722,0.0062432587,0.12575477,0.6627471,0.08326706,0.061269406,0.0057609635],"about_ca_topic_score_codex":0.000014827125,"about_ca_topic_score_gemma":0.0000033168817,"teacher_disagreement_score":0.8276568,"about_ca_system_score_codex":0.000022540587,"about_ca_system_score_gemma":0.000008401228,"threshold_uncertainty_score":0.5665158},"labels":[],"label_agreement":null},{"id":"W1966105387","doi":"10.1145/2566668","title":"Accelerating FPGA debug","year":2014,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Debugging; Multiplexer; Field-programmable gate array; Embedded system; Computer hardware; Routing (electronic design automation); TRACE (psycholinguistics); Real-time computing; Multiplexing; Operating system","score_opus":0.020995923484247735,"score_gpt":0.2264472093870163,"score_spread":0.20545128590276857,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1966105387","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0034333488,0.00022975916,0.99274206,0.000026789137,0.00020726184,0.00045566654,0.0000027198707,0.001434782,0.00146764],"genre_scores_gemma":[0.98975044,0.0000584641,0.009742033,0.000015024976,0.00004838231,0.00018451703,0.000004031216,0.000045563105,0.00015153899],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986462,0.00015468422,0.0004536854,0.00017523966,0.00023144769,0.00033873424],"domain_scores_gemma":[0.99901825,0.0002954968,0.00008708704,0.00048005546,0.000068147616,0.000050964773],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005484635,0.00019291928,0.000266442,0.00024878845,0.00009993382,0.000047188096,0.00028258693,0.00014293048,0.000059859733],"category_scores_gemma":[0.000036500016,0.00019697058,0.00008276147,0.00029492477,0.000019731833,0.00020871848,0.0000014568022,0.00021664423,0.00005419723],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001963601,0.00009056008,0.000007089056,0.00028229726,0.00018697008,5.958716e-7,0.00033131352,0.7443129,0.08609031,0.0040312908,0.0014020696,0.163245],"study_design_scores_gemma":[0.00031532746,0.0003581395,0.00003569058,0.000119765224,0.00003427072,0.000019662153,0.00003770214,0.79323053,0.20316395,0.0012962312,0.0011346572,0.0002540848],"about_ca_topic_score_codex":0.000014825411,"about_ca_topic_score_gemma":0.000002791971,"teacher_disagreement_score":0.9863171,"about_ca_system_score_codex":0.00017485743,"about_ca_system_score_gemma":0.000035683,"threshold_uncertainty_score":0.8032227},"labels":[],"label_agreement":null},{"id":"W1966460368","doi":"10.1145/2554688.2554783","title":"Towards interconnect-adaptive packing for FPGAs","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":31,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Speedup; Computer science; Interconnection; Field-programmable gate array; Software; Lookup table; Path (computing); Computer architecture; Parallel computing; Computer engineering; Embedded system; Operating system; Computer network","score_opus":0.01697004714207424,"score_gpt":0.22348065476349585,"score_spread":0.20651060762142162,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1966460368","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0020250161,0.000036429512,0.8929218,0.000036163223,0.000120451856,0.00013805316,0.000002165402,0.0010061263,0.10371377],"genre_scores_gemma":[0.9643775,0.000008071896,0.035074692,0.000110621826,0.00011297776,0.000052282707,0.00000214342,0.000025963114,0.00023570287],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996094,0.000007915367,0.00009492923,0.00009035481,0.000043559467,0.00015381862],"domain_scores_gemma":[0.9997654,0.00004953019,0.000007946865,0.0001122136,0.000027666665,0.000037267193],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013139917,0.00008910929,0.00010633373,0.000044799057,0.000021254727,0.000020408103,0.00008648211,0.000053194235,0.00006489703],"category_scores_gemma":[0.00002997267,0.00007833815,0.000053113567,0.000040388957,0.000009351943,0.00007334292,0.000012483323,0.00005238715,0.000021037724],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012181727,0.000014890569,0.000035852387,0.000090620546,0.00006130604,9.0907395e-7,0.00047845,0.00046501862,0.0174286,0.13191949,0.025432806,0.8240599],"study_design_scores_gemma":[0.00044062527,0.00029916753,0.0001206619,0.00007566119,0.000021358073,0.000005851076,0.00014253418,0.37305075,0.48035166,0.04037573,0.10461019,0.0005058236],"about_ca_topic_score_codex":0.000008973182,"about_ca_topic_score_gemma":0.000008488566,"teacher_disagreement_score":0.9623525,"about_ca_system_score_codex":0.00002495625,"about_ca_system_score_gemma":0.0000029593832,"threshold_uncertainty_score":0.3194537},"labels":[],"label_agreement":null},{"id":"W1967128905","doi":"10.1109/fpt.2012.6412139","title":"VersaPower: Power estimation for diverse FPGA architectures","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":48,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Computer science; Routing (electronic design automation); Embedded system; Spice; CAD; Computer architecture; Power (physics); Gate array; Logic gate; Interconnection; Logic synthesis; Architecture; Electronic engineering; Engineering; Telecommunications","score_opus":0.011969027675170664,"score_gpt":0.23785888493443672,"score_spread":0.22588985725926605,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1967128905","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.033388402,0.00016092494,0.93522245,0.000024569363,0.00031410184,0.00025616927,0.000008945904,0.0011615094,0.029462907],"genre_scores_gemma":[0.9597791,0.0000032432768,0.03989144,0.000050013336,0.00005166846,0.000029710476,0.000006282589,0.00001654023,0.0001720052],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99964297,0.0000037363648,0.000068942936,0.00004861041,0.000053573698,0.0001821965],"domain_scores_gemma":[0.99980384,0.00003345866,0.0000069936564,0.000094623414,0.000010329394,0.000050772924],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006983195,0.0000762198,0.00006382522,0.000052101503,0.000028224347,0.000011284813,0.000054449498,0.000047755606,0.00021880254],"category_scores_gemma":[0.00001478409,0.00006606268,0.000040842835,0.000038161434,0.000009740907,0.0000845,0.000009237832,0.000042937416,0.00006797608],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006686696,0.00017706682,0.002308885,0.00029091357,0.00022283802,0.0000024673482,0.005457827,0.02022581,0.04396763,0.022964073,0.48182663,0.42248902],"study_design_scores_gemma":[0.001325105,0.0002457422,0.0065584322,0.000052696538,0.00010515443,0.000025296884,0.00038270126,0.12351516,0.66763675,0.010145474,0.18862915,0.0013783427],"about_ca_topic_score_codex":0.0000033176975,"about_ca_topic_score_gemma":8.1885537e-7,"teacher_disagreement_score":0.9263907,"about_ca_system_score_codex":0.000021032305,"about_ca_system_score_gemma":0.0000018758753,"threshold_uncertainty_score":0.2693958},"labels":[],"label_agreement":null},{"id":"W1967526445","doi":"10.1109/fpl.2009.5272331","title":"Improving the memory footprint and runtime scalability of FPGA CAD algorithms","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Scalability; Computer science; Memory footprint; Field-programmable gate array; Embedded system; Workstation; CAD; FPGA prototype; Footprint; Computer architecture; Operating system; Engineering","score_opus":0.006805681439527634,"score_gpt":0.1995599858790898,"score_spread":0.19275430443956215,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1967526445","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7460551,0.00095724966,0.22176181,0.0002627425,0.00011341846,0.0005766207,0.0000049927357,0.0012158873,0.02905217],"genre_scores_gemma":[0.99316984,0.000026291542,0.0066540632,0.000033349268,0.000027598591,0.000004977777,3.2844508e-7,0.0000074623376,0.000076064505],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99953395,0.000010458846,0.00015326537,0.00010067503,0.00007773314,0.00012390495],"domain_scores_gemma":[0.9996743,0.000029938172,0.000015799409,0.0002259846,0.000022532633,0.00003143541],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00024142934,0.00008625944,0.00011789684,0.000027176324,0.000029205761,0.000014976252,0.00010133425,0.00005254361,0.000017880571],"category_scores_gemma":[0.000016431217,0.00005757427,0.00003304147,0.00006698782,0.000041512736,0.00004054903,0.000023484345,0.00009963782,0.0000014578476],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000021470476,0.000018926337,0.00021982982,0.00004042046,0.000011243567,7.545283e-7,0.00018344536,0.00008402628,0.14379098,0.00040425113,0.00018107083,0.8550629],"study_design_scores_gemma":[0.00017048926,0.00011754219,0.0267368,0.000016127051,0.000017784214,0.000009403409,0.00010426599,0.036501136,0.9329275,0.0029792292,0.00021711276,0.00020264972],"about_ca_topic_score_codex":0.00007843509,"about_ca_topic_score_gemma":0.0000041899116,"teacher_disagreement_score":0.85486025,"about_ca_system_score_codex":0.000016249574,"about_ca_system_score_gemma":0.0000051736865,"threshold_uncertainty_score":0.23478106},"labels":[],"label_agreement":null},{"id":"W1967786783","doi":"10.5555/644108.644154","title":"Packing Steiner trees","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":204,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Steiner tree problem; Combinatorics; Disjoint sets; Graph; Packing problems; Mathematics; Enhanced Data Rates for GSM Evolution; Discrete mathematics; Computer science","score_opus":0.009445759865425845,"score_gpt":0.19082485218655057,"score_spread":0.18137909232112473,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1967786783","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021465674,0.0002871007,0.2194748,0.000010793785,0.000105158535,0.00006265509,5.004215e-7,0.0017650999,0.7568282],"genre_scores_gemma":[0.9920401,0.000022953001,0.0064665577,0.000033498844,0.00001691628,0.000005483971,4.1636025e-7,0.000013699478,0.001400406],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997591,0.0000054850007,0.000055689685,0.000044369703,0.0000380919,0.000097261276],"domain_scores_gemma":[0.9998739,0.000008845458,0.0000026745242,0.00008666836,0.000005784673,0.000022135191],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000043529395,0.00005185704,0.00004918806,0.000028242328,0.000011895175,0.000012650451,0.000032577864,0.000029283188,0.00031692474],"category_scores_gemma":[0.0000059375056,0.00004329966,0.000018911898,0.000054610344,0.0000046295736,0.000048462392,0.000002158578,0.00003795332,0.000050744664],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000002200045,0.000058620877,0.0075062825,0.000085316344,0.00010858336,0.000042009702,0.00053452194,0.0026206817,0.38257092,0.25887457,0.18400939,0.16358693],"study_design_scores_gemma":[0.00018777743,0.000035108966,0.00075921207,0.000017110131,0.000008240558,0.000014066852,0.00007951547,0.0041049863,0.755017,0.004540285,0.23487733,0.00035938204],"about_ca_topic_score_codex":0.000001957482,"about_ca_topic_score_gemma":0.000004629467,"teacher_disagreement_score":0.9705744,"about_ca_system_score_codex":0.00000919786,"about_ca_system_score_gemma":0.000001696396,"threshold_uncertainty_score":0.34701037},"labels":[],"label_agreement":null},{"id":"W1970788183","doi":"10.1109/82.933810","title":"Some space considerations of VLSI systolic array mappings","year":2001,"lang":"en","type":"article","venue":"IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Regina","funders":"","keywords":"Systolic array; Nested loop join; Loop (graph theory); Transformation (genetics); Very-large-scale integration; Algorithm; Computer science; Space (punctuation); Transformation matrix; Matrix (chemical analysis); Variable (mathematics); Array data structure; Mathematics; Parallel computing; Combinatorics; Mathematical analysis; Physics","score_opus":0.01961833748466359,"score_gpt":0.21210389494820767,"score_spread":0.19248555746354407,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1970788183","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06662747,0.0043922085,0.92328817,0.00003596155,0.000113858514,0.0002477106,0.0000500232,0.00035218857,0.0048924065],"genre_scores_gemma":[0.9993732,0.00024500655,0.00002483277,0.000021029862,0.00006610633,0.000024106917,0.0000023974405,0.000025221154,0.00021808555],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990469,0.00001559891,0.00034687456,0.00021274728,0.0001589869,0.0002188567],"domain_scores_gemma":[0.99958915,0.000064222964,0.00006182709,0.000091806505,0.00007084121,0.00012218438],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010190759,0.00019989445,0.0003168718,0.00020666081,0.00033102356,0.00027444682,0.000044012497,0.00011451276,0.0000060851235],"category_scores_gemma":[0.0000027493973,0.00018627697,0.000053199718,0.00017726164,0.00009674321,0.0006642023,8.5445646e-7,0.00015639141,0.0000015311068],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000034847482,0.0005560219,0.0005405972,0.0047328766,0.0005451733,0.00011835654,0.0059748623,0.043242775,0.29783356,0.007194737,0.0006007609,0.63862544],"study_design_scores_gemma":[0.008117946,0.0047360943,0.0013392414,0.015808053,0.0012965064,0.010727912,0.0122541115,0.6489154,0.23088722,0.040287044,0.01639084,0.009239647],"about_ca_topic_score_codex":0.000022944789,"about_ca_topic_score_gemma":0.0000038745634,"teacher_disagreement_score":0.93274575,"about_ca_system_score_codex":0.00002566068,"about_ca_system_score_gemma":0.000030869425,"threshold_uncertainty_score":0.7596154},"labels":[],"label_agreement":null},{"id":"W1972041243","doi":"10.1145/1230800.1230811","title":"The exact channel density and compound design for generic universal switch blocks","year":2007,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; Wilfrid Laurier University","funders":"","keywords":"USB; Block (permutation group theory); USB hub; Computer science; eXtensible Host Controller Interface (xHCI); Routing (electronic design automation); Channel (broadcasting); Disjoint sets; Combinatorics; Discrete mathematics; Topology (electrical circuits); Physics; Mathematics; Embedded system; Computer network; Operating system; Software","score_opus":0.02187675245786297,"score_gpt":0.23029956350674152,"score_spread":0.20842281104887855,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1972041243","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0069911666,0.0010793017,0.9899744,0.000036584916,0.00019758695,0.001151235,0.0000038510807,0.0005087256,0.00005717385],"genre_scores_gemma":[0.9918937,0.00028280687,0.007513945,0.0000073839133,0.00003838283,0.00010424755,0.0000029151308,0.000036416157,0.00012017219],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99874496,0.00009747839,0.0003727251,0.00018346474,0.00018482207,0.00041651956],"domain_scores_gemma":[0.9983469,0.0010395009,0.000097453245,0.00034860577,0.0001059014,0.000061629886],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0012669833,0.00019573903,0.00023114536,0.00018854323,0.00029490684,0.00005030951,0.00022835996,0.00014746384,0.0000031592597],"category_scores_gemma":[0.000021861726,0.00017085281,0.00007055118,0.0002523321,0.000049277947,0.00013005671,0.0000021034732,0.00016758015,0.000002480306],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0007821337,0.00027040523,0.000012705916,0.0005171024,0.0012649469,0.00000935498,0.0016217993,0.6558017,0.20599525,0.0047437553,0.004279223,0.1247016],"study_design_scores_gemma":[0.0007187224,0.0007193556,0.000075059535,0.00007040144,0.00010361919,0.00008009152,0.00028161512,0.75966793,0.23522353,0.001839855,0.0009006619,0.0003191581],"about_ca_topic_score_codex":0.00002092336,"about_ca_topic_score_gemma":0.00001203631,"teacher_disagreement_score":0.98490256,"about_ca_system_score_codex":0.000265067,"about_ca_system_score_gemma":0.00006235671,"threshold_uncertainty_score":0.69671756},"labels":[],"label_agreement":null},{"id":"W1972437065","doi":"10.1109/tvlsi.2012.2202326","title":"Combined Architecture/Algorithm Approach to Fast FPGA Routing","year":2012,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Field-programmable gate array; Routing (electronic design automation); Logic block; Router; Multipath routing; Parallel computing; Static routing; Algorithm; Embedded system; Computer network; Routing protocol","score_opus":0.011929404047669444,"score_gpt":0.21617838698975392,"score_spread":0.20424898294208446,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1972437065","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0050397646,0.0001224956,0.9838908,0.000023207438,0.002554752,0.00095647,0.0001792244,0.0015819577,0.005651378],"genre_scores_gemma":[0.9868439,0.000017737366,0.011240232,0.00006596684,0.00035531382,0.00053591863,0.000039791557,0.000100943325,0.00080022844],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9978293,0.00014592907,0.0005839164,0.0003383825,0.00041080776,0.00069165323],"domain_scores_gemma":[0.99898875,0.000074775504,0.00006409175,0.00047039153,0.00010003023,0.000301947],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005383338,0.00042030893,0.00042976014,0.00042769403,0.00027895346,0.00015971021,0.00024891933,0.000284882,0.000035081655],"category_scores_gemma":[0.000005844396,0.0003897337,0.00020638583,0.00055545237,0.000028435321,0.00041781046,0.0000021266503,0.0006186671,0.00018898488],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017844653,0.002984065,0.00014795514,0.00068935583,0.00068255176,0.000009010251,0.022783004,0.4210949,0.073845655,0.0016354158,0.010406738,0.4655429],"study_design_scores_gemma":[0.0012717613,0.0004032169,0.00016546596,0.0005496844,0.00014356455,0.00012750746,0.0041974997,0.7166884,0.26588857,0.000050146926,0.00894018,0.0015739944],"about_ca_topic_score_codex":0.00006701957,"about_ca_topic_score_gemma":0.00002284739,"teacher_disagreement_score":0.98180413,"about_ca_system_score_codex":0.0002882482,"about_ca_system_score_gemma":0.000019701663,"threshold_uncertainty_score":0.99985546},"labels":[],"label_agreement":null},{"id":"W1973454118","doi":"10.1145/611817.611865","title":"Recursive circuit clustering for minimum delay and area","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Cluster analysis; Netlist; Computer science; Field-programmable gate array; Node (physics); Cluster (spacecraft); Parallel computing; Reduction (mathematics); Algorithm; Minification; Mathematics; Embedded system; Engineering; Artificial intelligence; Computer network","score_opus":0.023671383990914813,"score_gpt":0.2174573416257733,"score_spread":0.19378595763485848,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1973454118","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014543132,0.00030741037,0.92829084,0.000010573922,0.00009979896,0.00023722176,0.0000039856686,0.00042218558,0.05608485],"genre_scores_gemma":[0.98088264,0.00006969284,0.01838289,0.00005802763,0.000019987428,0.000055179593,0.0000019110764,0.000024137164,0.00050550204],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996379,0.0000048276447,0.00008703268,0.00009205791,0.000031324627,0.00014685873],"domain_scores_gemma":[0.99980587,0.00004266009,0.0000070758265,0.00008544109,0.00001629288,0.000042632917],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007149096,0.000081040875,0.0000877145,0.000039057682,0.000027293256,0.000019435953,0.000036055408,0.000057043075,0.000037389058],"category_scores_gemma":[0.000019764406,0.00007780743,0.000023423057,0.000038250808,0.000009766326,0.00005867261,0.000005070817,0.00003955918,0.0000028296176],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005733961,0.00015193482,0.0030826232,0.0016764998,0.0005865115,0.000082817205,0.0056881635,0.0033300098,0.3118388,0.19318004,0.22270164,0.2576236],"study_design_scores_gemma":[0.0024797542,0.0006617486,0.00042305075,0.00023089799,0.00012587741,0.00034253908,0.0009987255,0.12315433,0.53177136,0.08393632,0.2536854,0.0021900008],"about_ca_topic_score_codex":0.0000017230426,"about_ca_topic_score_gemma":0.0000064365386,"teacher_disagreement_score":0.9663395,"about_ca_system_score_codex":0.00001703215,"about_ca_system_score_gemma":0.0000033996496,"threshold_uncertainty_score":0.3172895},"labels":[],"label_agreement":null},{"id":"W1976209959","doi":"10.1109/icmel.2008.4559325","title":"A new computer-aided multi-dimensional device modeling algorithm based on binning concepts","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Algorithm; Black box; Generality; Set (abstract data type); Context (archaeology); Simplicity; Simple (philosophy); Artificial intelligence","score_opus":0.03864097638677234,"score_gpt":0.25932493042111315,"score_spread":0.22068395403434082,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1976209959","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007943296,0.00009878949,0.9892479,0.000023380026,0.00014410302,0.00014403534,0.0000026387038,0.0016185049,0.00077735574],"genre_scores_gemma":[0.3613697,0.000005699863,0.6379474,0.00041224674,0.000105180385,0.0000064740625,0.000009349233,0.00003181227,0.000112152724],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99911577,0.000017642402,0.00021508349,0.00020688002,0.0001940836,0.0002505346],"domain_scores_gemma":[0.9995661,0.000059773713,0.00001566052,0.00018459871,0.00004368313,0.0001302351],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000073555835,0.00019489395,0.00019150307,0.00012155526,0.00008705894,0.00001743883,0.00011854213,0.00009809628,0.00009857138],"category_scores_gemma":[0.0000050184553,0.0001847141,0.000067970344,0.00014795297,0.000013448573,0.00009969995,0.000020274389,0.00017695778,0.00006124034],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000037139873,0.000028554094,0.0000309951,0.000010473683,0.000015565747,0.000046186666,0.00009250737,0.94668937,0.003012693,0.00003474546,0.0062607564,0.043774456],"study_design_scores_gemma":[0.0005664361,0.000057208308,0.00003265351,0.00006110291,0.000004619036,0.000016876222,0.0000044225526,0.98914826,0.009544645,0.000019448406,0.00030599502,0.00023832773],"about_ca_topic_score_codex":0.00009312455,"about_ca_topic_score_gemma":0.0000022983713,"teacher_disagreement_score":0.3534264,"about_ca_system_score_codex":0.000050660045,"about_ca_system_score_gemma":0.000041628602,"threshold_uncertainty_score":0.75324225},"labels":[],"label_agreement":null},{"id":"W1977406187","doi":"10.1145/1723112.1723157","title":"The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Application-specific integrated circuit; Interconnection; Routing (electronic design automation); Computer science; Field-programmable gate array; Embedded system; Computer network","score_opus":0.00483226911727936,"score_gpt":0.23628357229029442,"score_spread":0.23145130317301507,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1977406187","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8945436,0.00007686205,0.088656895,0.00007325211,0.00042926555,0.00045052805,0.00001360418,0.0011202554,0.014635736],"genre_scores_gemma":[0.997435,0.000011723892,0.002377891,0.000012669097,0.00007547919,0.000013274767,0.0000036691304,0.000028418614,0.00004192076],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99942154,0.000015045777,0.00015426017,0.00009517184,0.000098354154,0.00021565062],"domain_scores_gemma":[0.9994188,0.000111816895,0.000024038303,0.00035986982,0.000028018108,0.000057480527],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011677347,0.00015298494,0.00013861209,0.00005559319,0.0000391191,0.0000329302,0.00024984687,0.00011624967,0.000112234084],"category_scores_gemma":[0.000032976284,0.00008141513,0.0001399429,0.00010920685,0.000054815257,0.00002822764,0.000019044734,0.00043176988,0.0000057013613],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025730063,0.000017520846,0.00019028195,0.000015566815,0.00010112874,0.0000020313084,0.00023437261,0.00084067887,0.2895339,0.0017461756,0.0022300836,0.7050625],"study_design_scores_gemma":[0.00046380865,0.0008009154,0.005870657,0.00002937961,0.000022514258,0.000047968588,0.000056696415,0.018128034,0.923222,0.046488356,0.0043724477,0.00049721356],"about_ca_topic_score_codex":0.00004678478,"about_ca_topic_score_gemma":0.000270328,"teacher_disagreement_score":0.7045653,"about_ca_system_score_codex":0.000017536193,"about_ca_system_score_gemma":0.000009637255,"threshold_uncertainty_score":0.33200127},"labels":[],"label_agreement":null},{"id":"W1978104777","doi":"10.1109/ictai.2010.25","title":"An Effective Multilevel Memetic Algorithm for Balanced Graph Partitioning","year":2010,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Angers Loire Métropole","keywords":"Memetic algorithm; Computer science; Operator (biology); Graph; Graph partition; Algorithm; Local search (optimization); Combinatorics; Mathematics; Theoretical computer science","score_opus":0.011153185135786135,"score_gpt":0.2622558178298913,"score_spread":0.2511026326941052,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1978104777","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004782025,0.00008615481,0.9890131,0.0000056539566,0.0007812641,0.0015323816,0.00014185283,0.0023788975,0.0012786879],"genre_scores_gemma":[0.5448582,0.00003798631,0.452143,0.000027111086,0.00026034768,0.0023654136,0.00018193775,0.00008268232,0.000043331052],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989634,0.00002602966,0.00023529059,0.0003671321,0.00011014422,0.00029796292],"domain_scores_gemma":[0.9991974,0.00010665118,0.000043737477,0.00045003576,0.00010082165,0.0001013257],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00023391267,0.0003135222,0.00035122465,0.00015514295,0.00006524811,0.00008658046,0.00025166062,0.00052390055,0.000064084634],"category_scores_gemma":[0.000021844975,0.00030950824,0.00016523432,0.000051456867,0.000031943702,0.00009193396,0.000054807435,0.0006488648,0.000008473663],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050860717,0.000068292095,0.000046744586,0.00041397076,0.00017557728,0.000003614019,0.00026678338,0.005704511,0.04046785,0.00059118797,0.0016916316,0.95056474],"study_design_scores_gemma":[0.00027011204,0.0000787575,0.00073432515,0.00009920981,0.000051740277,0.0000022794497,0.000012328521,0.8165545,0.16531603,0.015960433,0.00042096208,0.00049933395],"about_ca_topic_score_codex":0.000037546455,"about_ca_topic_score_gemma":0.000019493718,"teacher_disagreement_score":0.95006543,"about_ca_system_score_codex":0.000045668537,"about_ca_system_score_gemma":0.000012074882,"threshold_uncertainty_score":0.9999357},"labels":[],"label_agreement":null},{"id":"W1978440339","doi":"10.1007/s10878-008-9148-y","title":"A nonlinear optimization methodology for VLSI fixed-outline floorplanning","year":2008,"lang":"en","type":"article","venue":"Journal of Combinatorial Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Waterloo","funders":"","keywords":"Floorplan; Very-large-scale integration; Mathematical optimization; Nonlinear programming; Sizing; Computer science; Optimization problem; Nonlinear system; Mathematics","score_opus":0.03905878121476061,"score_gpt":0.2762490240574581,"score_spread":0.2371902428426975,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1978440339","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030991656,0.00026562705,0.9929583,0.00005205987,0.0029986822,0.00023651085,0.0000062117756,0.00016568339,0.00021776576],"genre_scores_gemma":[0.04156905,0.0004775142,0.95664203,0.000033086166,0.0011509313,0.00001140239,0.000035816873,0.00005699383,0.000023186747],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987662,0.00009173511,0.0006452203,0.00009933468,0.00020698125,0.00019055155],"domain_scores_gemma":[0.9987901,0.00021954055,0.00027431312,0.00011506944,0.0005169568,0.0000840331],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0006165267,0.00016393625,0.00039042527,0.00027514508,0.00010407838,0.000026040161,0.00016843168,0.0002039499,0.000024541161],"category_scores_gemma":[0.00037318605,0.00016052242,0.00013741326,0.00024925024,0.000029241713,0.00036702253,0.000013215567,0.0002052443,8.0160464e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010183167,0.000052098112,0.00005523991,0.000025771269,0.000051948045,0.000010235194,0.00018684249,0.995799,0.0007461821,0.00025374678,0.002203915,0.00051315886],"study_design_scores_gemma":[0.0018574805,0.00045994774,0.000008124551,0.000043971424,0.00006416592,0.00016293867,0.000030316149,0.9846958,0.010547998,0.00062014186,0.0013152639,0.00019388551],"about_ca_topic_score_codex":0.0000013894381,"about_ca_topic_score_gemma":5.5137274e-8,"teacher_disagreement_score":0.038469885,"about_ca_system_score_codex":0.000087720604,"about_ca_system_score_gemma":0.00006276011,"threshold_uncertainty_score":0.65459144},"labels":[],"label_agreement":null},{"id":"W1980284003","doi":"10.5555/1899721.1899786","title":"Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts","year":2010,"lang":"en","type":"article","venue":"Asia and South Pacific Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Transitive closure; Computer science; Representation (politics); Graph; Symmetry (geometry); Integrated circuit layout; Algorithm; Computational complexity theory; Time complexity; Topology (electrical circuits); Set (abstract data type); Mathematics; Theoretical computer science; Discrete mathematics; Integrated circuit; Combinatorics; Geometry","score_opus":0.07935021048947266,"score_gpt":0.2639427336879957,"score_spread":0.18459252319852304,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1980284003","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015817736,0.000019045594,0.99433106,0.000041071482,0.00021083117,0.0013794309,0.000103300314,0.0012058027,0.0011276657],"genre_scores_gemma":[0.88192314,0.000004899912,0.11752836,0.00005384612,0.000031132317,0.000259997,0.00010595227,0.000043750417,0.00004891496],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99842817,0.00012201053,0.0004232602,0.000390767,0.00022224839,0.00041353304],"domain_scores_gemma":[0.9988817,0.00033596833,0.000113671675,0.00032047325,0.00016553924,0.00018265149],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006099639,0.00034770492,0.00034995205,0.00022619624,0.00019839776,0.00021321898,0.00020345715,0.0002689815,0.00021761633],"category_scores_gemma":[0.00005511442,0.00034921584,0.00007286776,0.00017720282,0.0001943053,0.00016398,0.000013789728,0.00025130162,0.000029060227],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003296909,0.00070683163,0.0029099945,0.0015581397,0.00077173783,0.000048811642,0.011957449,0.021640971,0.65058094,0.11628611,0.012417908,0.18079141],"study_design_scores_gemma":[0.0015322318,0.0002250703,0.0022087672,0.00007722243,0.00005980057,0.000012018423,0.0013034405,0.9825305,0.009217367,0.0020298867,0.00020061956,0.0006030824],"about_ca_topic_score_codex":0.0000025176257,"about_ca_topic_score_gemma":0.00000358115,"teacher_disagreement_score":0.9608895,"about_ca_system_score_codex":0.000043131025,"about_ca_system_score_gemma":0.00009745564,"threshold_uncertainty_score":0.999896},"labels":[],"label_agreement":null},{"id":"W1981233168","doi":"10.1109/sips.2006.352557","title":"A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits","year":2006,"lang":"en","type":"article","venue":"SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Benchmark (surveying); Computer science; Data mining; Correlation clustering; Electronic circuit; Suite; Clustering high-dimensional data; Artificial intelligence; Engineering","score_opus":0.03488152956401719,"score_gpt":0.3033113079713055,"score_spread":0.2684297784072883,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1981233168","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08302258,0.0007417152,0.9120577,0.000009832107,0.0001412234,0.0034088176,0.00003312202,0.00047699094,0.000108031614],"genre_scores_gemma":[0.99479425,0.000014449432,0.0035671752,0.000026288746,0.00022978352,0.0011915349,0.00003046575,0.00007799372,0.00006804086],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982409,0.00011398601,0.00055917614,0.00040587326,0.00023527662,0.00044479963],"domain_scores_gemma":[0.99942833,0.00013545963,0.00012578136,0.00013277054,0.00008772675,0.000089924615],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00072376087,0.00033306092,0.00035382397,0.0002316704,0.00040373096,0.00039540624,0.0001117611,0.00012811772,0.000007830398],"category_scores_gemma":[0.0000035897576,0.0003192165,0.000038984053,0.000225161,0.00002819791,0.00034788874,0.000017224651,0.00016532434,9.884379e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00033065907,0.0004186122,0.0061570867,0.0049219187,0.00029530155,0.000039292932,0.011322732,0.035288945,0.594568,0.00044383857,0.013945286,0.33226833],"study_design_scores_gemma":[0.008101924,0.0020885963,0.0032162443,0.0016206518,0.000324389,0.0002603542,0.023280878,0.8744033,0.08146699,0.0013816616,0.001144041,0.0027109773],"about_ca_topic_score_codex":0.000025123712,"about_ca_topic_score_gemma":0.000028002667,"teacher_disagreement_score":0.9117717,"about_ca_system_score_codex":0.000089507055,"about_ca_system_score_gemma":0.000027448163,"threshold_uncertainty_score":0.999926},"labels":[],"label_agreement":null},{"id":"W1981519894","doi":"10.1109/ccece.2008.4564891","title":"FPGA placement optimization methodology survey","year":2008,"lang":"en","type":"article","venue":"Conference proceedings - Canadian Conference on Electrical and Computer Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":18,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Simulated annealing; Field-programmable gate array; Computer science; Gate array; Genetic algorithm; MATLAB; Logic synthesis; Digital electronics; Adaptive simulated annealing; Logic gate; Programmable logic device; Parallel computing; Algorithm; Computer engineering; Computer hardware; Embedded system; Electronic circuit; Engineering; Electrical engineering","score_opus":0.05992395512680344,"score_gpt":0.22383134137445607,"score_spread":0.16390738624765264,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1981519894","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.039763525,0.00014420677,0.9562972,0.000107733154,0.00021364713,0.00031727835,0.000014690886,0.00072313094,0.0024185532],"genre_scores_gemma":[0.9825622,0.00047501424,0.01655899,0.0001400752,0.00010046304,0.000051734132,0.000019942278,0.000040066527,0.000051529285],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985125,0.000019554669,0.00027550806,0.00038314622,0.0001637533,0.00064551213],"domain_scores_gemma":[0.9990665,0.00008702171,0.000031889864,0.00010500684,0.00021094785,0.0004986591],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00023365094,0.00033657122,0.00036365126,0.00044050193,0.00012858088,0.00012328957,0.0002543418,0.00021009563,0.00006789918],"category_scores_gemma":[0.00005162731,0.00035428244,0.000037037495,0.00040225298,0.00004698643,0.00017303119,0.000027884851,0.00041466302,0.00001016213],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020633348,0.0002595262,0.023471432,0.00081761566,0.000793425,0.0003670789,0.005541995,0.5030723,0.010981554,0.17559336,0.034295,0.24460034],"study_design_scores_gemma":[0.00019086075,0.00022059954,0.004911279,0.000047413945,0.000008111639,0.00007404165,0.0000067003552,0.9922167,0.001257983,0.00011112387,0.000508697,0.0004464875],"about_ca_topic_score_codex":0.0012676734,"about_ca_topic_score_gemma":0.0003816044,"teacher_disagreement_score":0.9427987,"about_ca_system_score_codex":0.00016650431,"about_ca_system_score_gemma":0.00015994106,"threshold_uncertainty_score":0.9998909},"labels":[],"label_agreement":null},{"id":"W1981813514","doi":"10.1016/j.disopt.2005.03.005","title":"Multiroute flows: Cut-trees and realizability","year":2005,"lang":"en","type":"article","venue":"Discrete Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Realizability; Mathematics; Characterization (materials science); Combinatorics; Diagonal; Simple (philosophy); Context (archaeology); Discrete mathematics; Tree (set theory); Matrix (chemical analysis); Flow network; Integer (computer science); Algorithm; Computer science","score_opus":0.006429571201527289,"score_gpt":0.215421699780067,"score_spread":0.20899212857853972,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1981813514","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019249482,0.00033304686,0.97055316,0.00009936393,0.00005399534,0.00021644078,0.00001708346,0.00095099374,0.008526454],"genre_scores_gemma":[0.8721289,0.0004564991,0.12716143,0.00002778643,0.00006866045,0.000021361564,0.00005810302,0.00002563605,0.000051636747],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995159,0.000015819951,0.00014209894,0.00013269928,0.000069465226,0.00012401615],"domain_scores_gemma":[0.9997468,0.00001346098,0.000015226174,0.00015473607,0.000021916625,0.00004789005],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007608257,0.00010616337,0.00009789769,0.00004492513,0.00004173977,0.00003726056,0.000053213196,0.000071742106,0.00005255138],"category_scores_gemma":[0.000016168953,0.00010246002,0.000023307355,0.00008184054,0.000021414367,0.00025392967,0.000015313879,0.00005678135,0.0000052490745],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000040033956,0.000008283042,0.0006006711,0.000022567743,0.000010195658,5.130915e-7,0.00027553912,0.97563165,0.00077517546,0.00015061755,0.0004176386,0.02210313],"study_design_scores_gemma":[0.00012468547,0.000013614938,0.0007799493,0.000012764358,0.000009498379,0.0000018372291,0.000019886638,0.9952716,0.002500131,0.00006635375,0.0010651917,0.00013447601],"about_ca_topic_score_codex":0.00001607108,"about_ca_topic_score_gemma":0.000033670185,"teacher_disagreement_score":0.8528794,"about_ca_system_score_codex":0.000033114982,"about_ca_system_score_gemma":0.0000029705936,"threshold_uncertainty_score":0.41781983},"labels":[],"label_agreement":null},{"id":"W1982429141","doi":"10.1016/j.dam.2012.12.010","title":"Graph models and their efficient implementation for sparse Jacobian matrix determination","year":2013,"lang":"en","type":"article","venue":"Discrete Applied Mathematics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge","funders":"","keywords":"Jacobian matrix and determinant; Mathematics; Sparse matrix; Graph; Matrix (chemical analysis); Mathematical optimization; Algorithm; Combinatorics; Applied mathematics","score_opus":0.016980310951542593,"score_gpt":0.2596519545351472,"score_spread":0.24267164358360463,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1982429141","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.114496134,0.000042621166,0.8823118,0.0000142806475,0.000022541333,0.001261134,0.000026529002,0.00030635123,0.0015185658],"genre_scores_gemma":[0.89122355,0.00002546986,0.10793397,0.000012668813,0.000019691055,0.0006977564,0.00003538828,0.00004097049,0.0000105436075],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99935615,0.0000029867288,0.00024633255,0.00012357075,0.00007669668,0.00019424858],"domain_scores_gemma":[0.99965835,0.000055047843,0.00004882636,0.00015959614,0.00002827307,0.00004993322],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000115312505,0.00016062787,0.0001616454,0.00008485154,0.000058475973,0.00007068361,0.00008011167,0.00006165388,0.000019255369],"category_scores_gemma":[0.0000022418528,0.00013387263,0.00004160477,0.00006944842,0.000021067499,0.00009064167,0.00001965944,0.000047224054,0.000007636966],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010283594,0.0001280128,0.000010234323,0.0025409625,0.00014084241,7.2937416e-7,0.017139189,0.015037396,0.43997654,0.30498928,0.0038645407,0.216162],"study_design_scores_gemma":[0.00026957365,0.00002419086,0.000013913475,0.000019487334,0.000022732895,0.0000023986868,0.001627062,0.7721706,0.059729625,0.16585977,0.00004884957,0.00021177957],"about_ca_topic_score_codex":0.0000031828786,"about_ca_topic_score_gemma":0.0000022309357,"teacher_disagreement_score":0.7767274,"about_ca_system_score_codex":0.000022357452,"about_ca_system_score_gemma":0.0000033909346,"threshold_uncertainty_score":0.54591674},"labels":[],"label_agreement":null},{"id":"W1983950263","doi":"10.1145/348019.348101","title":"Timing-driven routing for symmetrical array-based FPGAs","year":2000,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":46,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"University of Toronto; National Science Council; University of Texas at Austin","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Router; Static routing; Multipath routing; Equal-cost multi-path routing; Link-state routing protocol; Placement; Dynamic Source Routing; Parallel computing; Computer network; Embedded system; Routing protocol; Physical design; Circuit design","score_opus":0.026798628100344363,"score_gpt":0.24811098958298666,"score_spread":0.2213123614826423,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1983950263","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0024566674,0.00017796767,0.99448884,0.00004709656,0.000115870425,0.0010197684,0.00001593124,0.0011804389,0.00049740606],"genre_scores_gemma":[0.97226936,0.00003840262,0.02690162,0.00001693652,0.000043533473,0.00045832986,0.000012932871,0.000056492685,0.0002024262],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985086,0.00009666873,0.0005112887,0.000218996,0.00023961114,0.0004248401],"domain_scores_gemma":[0.9988631,0.0005071472,0.000078810364,0.00041425123,0.00007551805,0.00006117994],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00040246974,0.00021593059,0.00031491398,0.00035694652,0.00011974143,0.000040893618,0.00027681122,0.00017981656,0.00012084075],"category_scores_gemma":[0.000031245294,0.00022715729,0.00015603022,0.0004977072,0.00002280448,0.00014536828,4.6877116e-7,0.000193145,0.000040501996],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004282939,0.00008265226,0.0000023760495,0.00014306442,0.00009067004,4.0461842e-7,0.00008985311,0.9320243,0.016103446,0.00032646832,0.00047265735,0.05062126],"study_design_scores_gemma":[0.00054677477,0.0004898149,0.000011572024,0.00012827906,0.00006119904,0.000009448078,0.000019723715,0.87752736,0.11952486,0.00028957485,0.001157742,0.00023365217],"about_ca_topic_score_codex":0.000012159581,"about_ca_topic_score_gemma":0.0000012016832,"teacher_disagreement_score":0.96981263,"about_ca_system_score_codex":0.00030883757,"about_ca_system_score_gemma":0.000078283236,"threshold_uncertainty_score":0.92632055},"labels":[],"label_agreement":null},{"id":"W1983992983","doi":"10.1002/cta.332","title":"A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs","year":2005,"lang":"en","type":"article","venue":"International Journal of Circuit Theory and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"KU Leuven; Carnegie Mellon University","keywords":"Simulated annealing; Algorithm; Computer science; Integrated circuit layout; Placement; Representation (politics); Genetic algorithm; Electronic circuit; Integrated circuit; Circuit design; Physical design; Embedded system; Engineering","score_opus":0.01838131401153997,"score_gpt":0.2563521510000683,"score_spread":0.23797083698852833,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1983992983","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0020371764,0.000861604,0.99499255,0.00004924796,0.00012294171,0.0002999378,0.00022102051,0.00009581038,0.0013196835],"genre_scores_gemma":[0.99255216,0.00029919972,0.0058045965,0.00015164223,0.0007510127,0.00019421977,0.00007461536,0.000026750691,0.00014577915],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9990807,0.00003939267,0.00041496925,0.000121144316,0.00020102868,0.00014277588],"domain_scores_gemma":[0.9991229,0.00019989128,0.00012527994,0.000110976755,0.00035099336,0.00008996185],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005132781,0.00013474342,0.0001628313,0.00022113272,0.0000768948,0.000050359027,0.00032435753,0.00005411667,0.00007008341],"category_scores_gemma":[0.000026029278,0.00012949546,0.00010497145,0.00007268315,0.00005877727,0.00028324002,0.000015529165,0.00016850396,0.000008704798],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000027061695,0.00014620191,0.000029396217,0.000012452362,0.00034707267,0.0000052582186,0.0001582953,0.003699189,0.0066594784,0.44605935,0.0027894645,0.5400668],"study_design_scores_gemma":[0.0017082833,0.00021031626,0.0003245481,0.00014518105,0.00016931236,0.0009018109,0.00031925036,0.03495488,0.020993222,0.72355354,0.21616402,0.0005556219],"about_ca_topic_score_codex":9.632438e-7,"about_ca_topic_score_gemma":5.711237e-7,"teacher_disagreement_score":0.990515,"about_ca_system_score_codex":0.00016121441,"about_ca_system_score_gemma":0.000047422865,"threshold_uncertainty_score":0.5280671},"labels":[],"label_agreement":null},{"id":"W1984131666","doi":"10.1080/03052150801901475","title":"VLSI floorplan repair using dynamic white-space management, constraint graphs, and linear programming","year":2008,"lang":"en","type":"article","venue":"Engineering Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Floorplan; Very-large-scale integration; White spaces; Computer science; Constraint (computer-aided design); Mathematical optimization; Linear programming; Integrated circuit layout; Range (aeronautics); High-level synthesis; Computer engineering; Algorithm; Integrated circuit; Mathematics; Engineering; Embedded system","score_opus":0.008025436742093614,"score_gpt":0.19664174856651265,"score_spread":0.18861631182441904,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1984131666","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024331735,0.0003923563,0.9712886,0.000009244738,0.00013531065,0.000316414,0.000004312203,0.003234513,0.00028748802],"genre_scores_gemma":[0.36306962,0.0004932521,0.6362468,0.0000073659203,0.000020100742,0.000022739167,0.000029433948,0.00006330073,0.0000473987],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99920815,0.00000860124,0.00020548757,0.00020245448,0.00011203729,0.00026325838],"domain_scores_gemma":[0.9996852,0.000012336056,0.000025886817,0.00017353793,0.000026450121,0.00007656975],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000092175396,0.00020948281,0.00016246962,0.00025088538,0.000086999535,0.000027151096,0.00006740309,0.00010020929,0.000009353656],"category_scores_gemma":[0.000010711521,0.0002447253,0.000049441995,0.00031164725,0.000033829325,0.00018611242,0.000025411171,0.00014101411,0.0000014218687],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000015431681,0.000008168585,0.0003750362,0.00013529217,0.000044933848,0.000031866002,0.00013628857,0.9977192,0.0005477637,0.00017836486,0.00007937531,0.000742139],"study_design_scores_gemma":[0.00017415207,0.00001972644,0.00022479313,0.00007939102,0.00002227244,0.000096433,0.000028671739,0.9982121,0.00032434033,0.0000065685394,0.000542362,0.00026918805],"about_ca_topic_score_codex":0.0000031917416,"about_ca_topic_score_gemma":3.7153032e-7,"teacher_disagreement_score":0.3387379,"about_ca_system_score_codex":0.00006353595,"about_ca_system_score_gemma":0.0000052602186,"threshold_uncertainty_score":0.99796075},"labels":[],"label_agreement":null},{"id":"W1984142551","doi":"10.1109/newcas.2012.6328998","title":"GPU Approach to FPGA placement based on star+","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Simulated annealing; Parallel computing; Swap (finance); Multi-core processor; Embedded system; Computer architecture; Algorithm","score_opus":0.021027957655504827,"score_gpt":0.21786835494549617,"score_spread":0.19684039728999134,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1984142551","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004540049,0.000027168127,0.6251043,0.000028194765,0.000093019094,0.00024324449,0.0000029959485,0.00094289565,0.3690181],"genre_scores_gemma":[0.9521054,0.0000016796552,0.046711437,0.00043592142,0.00007823601,0.00007424109,0.0000061343776,0.000023164099,0.0005637815],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99947107,0.000008535793,0.000084242965,0.00007774101,0.000117357864,0.00024103757],"domain_scores_gemma":[0.9996702,0.000014991477,0.0000042981724,0.00018684154,0.0000071670634,0.000116509014],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013160838,0.000099094694,0.00007926865,0.00007384728,0.000017596483,0.000012692976,0.00007663307,0.00004282979,0.00019322801],"category_scores_gemma":[0.000004174524,0.00008386839,0.000025065181,0.00008350048,0.0000035485862,0.0000529146,0.000010189022,0.000064551714,0.00017855596],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007658736,0.00114246,0.0017229387,0.00030461673,0.00009188328,0.000002677133,0.0014658073,0.110677406,0.03301534,0.015406057,0.7862348,0.04985945],"study_design_scores_gemma":[0.00069251034,0.00039742823,0.002311372,0.00004644942,0.000024302952,0.000002604872,0.00022196515,0.2939316,0.4703763,0.00008807157,0.23086786,0.0010395272],"about_ca_topic_score_codex":0.0000045620927,"about_ca_topic_score_gemma":3.2595455e-7,"teacher_disagreement_score":0.9475654,"about_ca_system_score_codex":0.00005652,"about_ca_system_score_gemma":0.0000030809508,"threshold_uncertainty_score":0.34200537},"labels":[],"label_agreement":null},{"id":"W1984337894","doi":"10.1155/2009/537341","title":"A Multilevel Congestion-Based Global Router","year":2009,"lang":"en","type":"article","venue":"VLSI design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Hierarchical routing; Routing (electronic design automation); Router; Mathematical optimization; Distributed computing; Static routing; Computer network; Routing protocol; Mathematics","score_opus":0.019516569084140994,"score_gpt":0.22890199833658068,"score_spread":0.2093854292524397,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1984337894","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0020583721,0.00015287836,0.9907619,0.00010706598,0.000119153985,0.00026139716,0.000012293488,0.0017154827,0.0048114727],"genre_scores_gemma":[0.93728083,0.000009162943,0.06210311,0.00039916844,0.000069326685,0.000025666,0.0000061611904,0.000017140916,0.000089427325],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992554,0.000033591048,0.00016367176,0.00015700904,0.00013086741,0.00025944965],"domain_scores_gemma":[0.9995967,0.00004719625,0.000016698317,0.00021813535,0.00003428174,0.00008696761],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012774262,0.00017295193,0.00015005334,0.000053599895,0.00003841389,0.00004469096,0.0001523206,0.00012375938,0.00006584019],"category_scores_gemma":[0.00002114075,0.00016932003,0.000057757672,0.00014142672,0.000018178049,0.00009616163,0.0000038841317,0.000097284385,0.000117073956],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006852723,0.00021417007,0.0007900674,0.00005706836,0.00007134964,0.00015312008,0.00017215419,0.097272165,0.054515768,0.0036856916,0.13014732,0.7128526],"study_design_scores_gemma":[0.001504895,0.0005172513,0.01978705,0.00013331282,0.00005746263,0.000031047075,0.000009843671,0.84379023,0.11625233,0.0076519703,0.00915564,0.001108953],"about_ca_topic_score_codex":0.000005266945,"about_ca_topic_score_gemma":7.5880416e-7,"teacher_disagreement_score":0.93522245,"about_ca_system_score_codex":0.00009704481,"about_ca_system_score_gemma":0.00002355283,"threshold_uncertainty_score":0.69046706},"labels":[],"label_agreement":null},{"id":"W1984586534","doi":"10.1007/s002360000042","title":"The class Steiner minimal tree problem: a lower bound and test problem generation","year":2000,"lang":"en","type":"article","venue":"Acta Informatica","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Steiner tree problem; Mathematics; Upper and lower bounds; Linear programming relaxation; Theory of computation; Subgradient method; k-minimum spanning tree; Combinatorics; Discrete mathematics; Approximation algorithm; Time complexity; Integer programming; Tree (set theory); Heuristic; K-ary tree; Mathematical optimization; Algorithm; Binary tree; Tree structure","score_opus":0.007904042051019923,"score_gpt":0.19120084342983149,"score_spread":0.18329680137881157,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1984586534","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.523075,0.00037304658,0.0010763952,0.0013614185,0.00012033166,0.0015194709,0.00001947223,0.0013025374,0.47115234],"genre_scores_gemma":[0.9940793,0.00027022706,0.00413308,0.00012875773,0.00008149973,0.00011229175,0.000011420564,0.000020814685,0.0011626455],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99924004,0.000008122824,0.0003140474,0.0000667221,0.0001321091,0.00023896505],"domain_scores_gemma":[0.9996155,0.00008816999,0.000028413293,0.00018627764,0.000024955867,0.000056704273],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015672075,0.00014035063,0.00010871695,0.000035105073,0.00015170002,0.0002411721,0.00012686111,0.00008192207,0.00008892612],"category_scores_gemma":[0.000017529988,0.000095738775,0.000027059159,0.00009230849,0.000053764885,0.0005356526,0.00001716446,0.00013240689,0.000065159606],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000035114892,0.000092602124,0.00024523528,0.00038724838,0.00012161951,0.0000066630496,0.004076261,0.00023581862,0.028218692,0.0035015068,0.23360524,0.729474],"study_design_scores_gemma":[0.0007558152,0.0005757498,0.0008173962,0.00010411658,0.00005495672,0.00008255637,0.00012924308,0.20729996,0.010709154,0.0013735659,0.77740216,0.00069533853],"about_ca_topic_score_codex":0.0000037066316,"about_ca_topic_score_gemma":0.000019443773,"teacher_disagreement_score":0.72877866,"about_ca_system_score_codex":0.000027163353,"about_ca_system_score_gemma":0.000014842808,"threshold_uncertainty_score":0.3904114},"labels":[],"label_agreement":null},{"id":"W1986768612","doi":"10.1109/ccece.2012.6334856","title":"A formal and empirical analysis of recombination for genetic algorithm-based approaches to the FPGA placement problem","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Subspace topology; Genetic algorithm; Operator (biology); Computer science; Algorithm; Recombination; Quality (philosophy); Field (mathematics); Gate array; Mathematics; Artificial intelligence; Machine learning; Physics; Computer hardware","score_opus":0.07498597463990726,"score_gpt":0.2616243703525226,"score_spread":0.18663839571261537,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1986768612","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.023834959,0.00009519683,0.9748438,0.00012843944,0.000016152231,0.0005137377,0.000008408165,0.00008705705,0.0004722588],"genre_scores_gemma":[0.7553053,0.000003647629,0.24435481,0.000041992553,0.000015494375,0.00023032779,0.000011706796,0.000007987878,0.000028764913],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99954045,0.000012202789,0.00014554356,0.000067014254,0.00007466133,0.00016011528],"domain_scores_gemma":[0.9997772,0.000046423098,0.000016583675,0.000099653356,0.000016068396,0.0000440479],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00027974162,0.00007017338,0.00011889871,0.00013599158,0.000028102237,0.000011134225,0.000054751028,0.00003735876,0.000012209598],"category_scores_gemma":[0.000004572388,0.00004765159,0.000050380808,0.00024580263,0.000008314232,0.00006162517,0.000012520405,0.000027546246,6.096694e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003001113,0.00026011196,0.009064304,0.00024069888,0.0009095744,1.0771147e-7,0.0024599675,0.075847454,0.00081658806,0.001108976,0.0061633275,0.9030989],"study_design_scores_gemma":[0.00018864677,0.00012927178,0.010264418,0.000004273447,0.00026370634,3.724643e-7,0.000082835584,0.9700005,0.017255947,0.000091485956,0.0016110278,0.00010751832],"about_ca_topic_score_codex":0.0000043286796,"about_ca_topic_score_gemma":0.000005305579,"teacher_disagreement_score":0.90299135,"about_ca_system_score_codex":0.000022730508,"about_ca_system_score_gemma":0.0000041985836,"threshold_uncertainty_score":0.19431755},"labels":[],"label_agreement":null},{"id":"W198687945","doi":"10.1007/978-1-4614-4325-4_5","title":"Results in Gray Codes and Universal Cycles for Designs","year":2012,"lang":"en","type":"book-chapter","venue":"CMS books in mathematics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Gray (unit); Gray code; Computer science; Arithmetic; Mathematics; Algorithm; Medicine","score_opus":0.04630054837356974,"score_gpt":0.24611902980329334,"score_spread":0.19981848142972358,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W198687945","genre_codex":"other","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00042423903,0.003857058,0.102328725,0.000022390126,0.00023875496,0.0020443923,0.0003114814,0.00077870436,0.88999426],"genre_scores_gemma":[0.15778922,0.008427598,0.5235093,0.00006903612,0.0008529126,0.0003976374,0.0002805707,0.0013149896,0.3073587],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9990546,0.0000065696695,0.00042441644,0.00016538307,0.00010026355,0.00024877914],"domain_scores_gemma":[0.999344,0.00024835093,0.00007928679,0.0002534211,0.000020289122,0.000054671073],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00035134412,0.00029556974,0.00044153864,0.00026913395,0.00002035642,0.000024039036,0.00014881301,0.00037653692,0.000008599618],"category_scores_gemma":[0.000030545005,0.00030066815,0.0000575418,0.00001680354,0.0000724568,0.000068245696,0.00003484018,0.00026770975,0.0000063331436],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000485902,0.00007227522,0.00003076391,0.0042868634,0.00012495907,0.000042793567,0.006100223,0.00017663284,0.0015538534,0.95537835,0.008470436,0.023714231],"study_design_scores_gemma":[0.0012447343,0.00012655374,0.000026168174,0.0032494578,0.00012336955,0.000026503001,0.00019570344,0.010749181,0.00265986,0.9339688,0.046346627,0.0012830764],"about_ca_topic_score_codex":0.0000026957146,"about_ca_topic_score_gemma":0.000030424417,"teacher_disagreement_score":0.5826355,"about_ca_system_score_codex":0.00010611533,"about_ca_system_score_gemma":0.000014597878,"threshold_uncertainty_score":0.99994457},"labels":[],"label_agreement":null},{"id":"W1988714784","doi":"10.1145/512161.512197","title":"Finding shortest paths in large network systems","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Dijkstra's algorithm; Suurballe's algorithm; Shortest path problem; Pathfinding; Computer science; Yen's algorithm; Floyd–Warshall algorithm; Shortest Path Faster Algorithm; K shortest path routing; Graph; A* search algorithm; Algorithm; Scalability; Theoretical computer science","score_opus":0.01381417334087049,"score_gpt":0.21817233968009103,"score_spread":0.20435816633922055,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1988714784","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17299226,0.0027373543,0.4799739,0.000023381665,0.0008957432,0.00055961864,0.0000054510438,0.0036871282,0.33912516],"genre_scores_gemma":[0.9985185,0.00017405402,0.00058331096,0.000022988663,0.00015431625,0.000027760918,0.0000039788843,0.000020899248,0.0004941583],"study_design_codex":"observational","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993982,0.00001053444,0.00015223431,0.00008397146,0.000061071805,0.00029403172],"domain_scores_gemma":[0.9998068,0.000024380635,0.0000070945525,0.00012042952,0.000006259034,0.000035012603],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001859647,0.000085580825,0.00011747977,0.00005723288,0.000021084084,0.00002813212,0.00007690095,0.00007317089,0.00009266758],"category_scores_gemma":[0.000004272762,0.000080903636,0.0000210068,0.0002151094,0.0000031825525,0.00007509631,0.000012402719,0.000103301056,0.000042260515],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008540859,0.00012026524,0.65202266,0.00016254274,0.00006170455,0.00062584353,0.000528414,0.14913167,0.004349867,0.03276767,0.13874874,0.021472113],"study_design_scores_gemma":[0.0005234788,0.00006906429,0.025657162,0.00033954505,0.000011746766,0.0000849874,0.0002590558,0.85585815,0.0010186182,0.00093082467,0.11440305,0.00084434194],"about_ca_topic_score_codex":0.00002508249,"about_ca_topic_score_gemma":0.000054592594,"teacher_disagreement_score":0.8255263,"about_ca_system_score_codex":0.000039688228,"about_ca_system_score_gemma":0.0000027502265,"threshold_uncertainty_score":0.32991546},"labels":[],"label_agreement":null},{"id":"W1989477191","doi":"10.1145/1344671.1344694","title":"Modeling routing demand for early-stage FPGA architecture development","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":47,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer architecture; Computer science; Benchmark (surveying); Architecture; Field-programmable gate array; Routing (electronic design automation); Simple (philosophy); Embedded system; Space-based architecture; Interconnection; Reference architecture; Computer network; Software architecture; Operating system; Software","score_opus":0.025888929128111807,"score_gpt":0.2199167076937532,"score_spread":0.1940277785656414,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1989477191","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2963392,0.00005816071,0.70013005,0.0000058989112,0.000031129497,0.00016955081,0.000001315093,0.0007401217,0.0025245398],"genre_scores_gemma":[0.8523575,0.000015895823,0.1468345,0.000029519619,0.000049285114,0.000050928764,0.0000042448264,0.00003182464,0.00062629976],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993411,0.0000046453833,0.00018465762,0.00012844206,0.00008599458,0.00025521332],"domain_scores_gemma":[0.9997845,0.00002131201,0.00000874668,0.00010968481,0.000022525215,0.00005320134],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010237763,0.00013083442,0.00012551025,0.000064555235,0.00012442352,0.000015992777,0.00009507574,0.000072978204,0.000019001829],"category_scores_gemma":[0.000009261326,0.00011766499,0.000044524633,0.000057458437,0.0000081661165,0.000058669084,0.00001768509,0.00010115098,0.00000763953],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019181194,0.000031794127,0.0011811246,0.00022321116,0.00011683539,0.000023593931,0.006385929,0.9132438,0.012182691,0.00076162355,0.0012707441,0.064559475],"study_design_scores_gemma":[0.0002709017,0.000026983666,0.00025674322,0.000034476394,0.0000058333653,0.00001590557,0.000042438627,0.8905969,0.10423076,0.00033788924,0.003808987,0.00037216005],"about_ca_topic_score_codex":0.000011617232,"about_ca_topic_score_gemma":0.000009596656,"teacher_disagreement_score":0.5560183,"about_ca_system_score_codex":0.00003435015,"about_ca_system_score_gemma":0.000015725265,"threshold_uncertainty_score":0.47982392},"labels":[],"label_agreement":null},{"id":"W1990050178","doi":"10.1109/rsp.2014.6966895","title":"System-on-chip processor using different FPGA architectures in the VTR CAD flow","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"CMC Microsystems","keywords":"Field-programmable gate array; Verilog; Adder; Computer science; Routing (electronic design automation); Embedded system; Block (permutation group theory); Design flow; Computer architecture; Computer hardware; Electronic design automation; FPGA prototype; Gate array","score_opus":0.014417388132131774,"score_gpt":0.22027569951759637,"score_spread":0.2058583113854646,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1990050178","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7692187,0.0000986882,0.20477629,0.00006139068,0.00013709233,0.000439337,0.0000036665772,0.0009754601,0.024289416],"genre_scores_gemma":[0.9983748,0.0000024697063,0.0012904982,0.00010543747,0.00012366379,0.000047874622,0.0000014453094,0.000026189362,0.000027616783],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99926794,0.000060822917,0.00016345698,0.00012977165,0.00015690736,0.00022113306],"domain_scores_gemma":[0.9996154,0.000092563416,0.000014807979,0.00023688034,0.000009316846,0.00003107302],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018711457,0.00016146616,0.000164435,0.0001027268,0.000044204444,0.000045699453,0.0002173176,0.00006805533,0.000009672519],"category_scores_gemma":[0.000018663886,0.000091524045,0.00004188504,0.0001050326,0.000014955595,0.000019426468,0.0000132721425,0.00019893289,0.000009143618],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011409072,0.000501004,0.007263748,0.006343071,0.00022880692,0.000083789804,0.014094439,0.49369293,0.10340928,0.030664159,0.008136793,0.33546788],"study_design_scores_gemma":[0.00034955412,0.0001249955,0.003951833,0.00036893506,0.000020662808,0.000041711934,0.00024058144,0.9080805,0.08408322,0.0016496641,0.00063205144,0.00045628345],"about_ca_topic_score_codex":0.000030799227,"about_ca_topic_score_gemma":0.00004827593,"teacher_disagreement_score":0.41438758,"about_ca_system_score_codex":0.00004516388,"about_ca_system_score_gemma":0.000003977745,"threshold_uncertainty_score":0.37322423},"labels":[],"label_agreement":null},{"id":"W1990444741","doi":"10.1142/s0219622013500119","title":"GRAPH BISECTION MODELED AS CARDINALITY CONSTRAINED BINARY QUADRATIC TASK ALLOCATION","year":2013,"lang":"en","type":"article","venue":"International Journal of Information Technology & Decision Making","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Mathematics; Combinatorics; Mathematical optimization; Graph; Computer science","score_opus":0.006764768802241577,"score_gpt":0.25778903216362187,"score_spread":0.2510242633613803,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1990444741","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3311762,0.00012441188,0.6657576,0.00037667257,0.0008597562,0.00019506874,0.0000050440394,0.00033190812,0.0011733585],"genre_scores_gemma":[0.97215533,0.00017698419,0.027412709,0.00012728477,0.000071802264,0.000027347029,0.00001054929,0.000012393687,0.0000055818077],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.998114,0.000025241916,0.0010594254,0.00008129168,0.0005564387,0.00016362207],"domain_scores_gemma":[0.99799,0.0001005017,0.00046478887,0.00017681606,0.0012195408,0.000048328264],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00043052618,0.00016787302,0.0002402837,0.0019094014,0.00006981933,0.00016762197,0.0005286536,0.00025128,0.00013360832],"category_scores_gemma":[0.00029454526,0.00015491806,0.00013863578,0.000459669,0.00007243137,0.0024203903,0.00005349741,0.0003729447,0.00012474126],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009573445,0.00005265311,0.00095136074,0.000029855191,0.00035855052,0.000018334833,0.00044043915,0.030803619,0.029810973,0.011960634,0.00641972,0.91905814],"study_design_scores_gemma":[0.0024809318,0.0007631618,0.005948369,0.0014051315,0.0001232793,0.0019121213,0.0027073107,0.39951077,0.045018602,0.53221506,0.006879068,0.0010362242],"about_ca_topic_score_codex":0.000007890893,"about_ca_topic_score_gemma":7.898312e-7,"teacher_disagreement_score":0.9180219,"about_ca_system_score_codex":0.00022221392,"about_ca_system_score_gemma":0.0000543924,"threshold_uncertainty_score":0.63173753},"labels":[],"label_agreement":null},{"id":"W1990600294","doi":"10.1145/968280.968295","title":"A synthesis oriented omniscient manual editor","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Xilinx","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Context (archaeology); Set (abstract data type); Logic synthesis; Logic optimization; Physical design; Logic gate; Placement; Digital electronics; Computer architecture; Theoretical computer science; Electronic circuit; Embedded system; Algorithm; Circuit design; Engineering; Programming language","score_opus":0.004850994993209914,"score_gpt":0.20448528227777193,"score_spread":0.19963428728456203,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1990600294","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.059116103,0.000110162684,0.8342357,0.0002324219,0.0042633773,0.0003025604,0.000014672627,0.005433628,0.09629135],"genre_scores_gemma":[0.98314804,0.000016867541,0.01549345,0.000044896482,0.00092809804,0.00004825938,0.0000013321684,0.000020751748,0.0002983299],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99951786,0.00000351283,0.000104391605,0.00009324523,0.000117476346,0.00016350116],"domain_scores_gemma":[0.99977136,0.000015855201,0.000006167082,0.00013492588,0.000015314925,0.0000563912],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000068530426,0.00008177626,0.00007630091,0.00006233183,0.000029169021,0.00001744588,0.00008518399,0.000049943195,0.00015604006],"category_scores_gemma":[0.00001730242,0.00006937282,0.00003359979,0.00011408148,0.000017147002,0.00007324237,0.000013852165,0.000056537094,0.00015880729],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018808301,0.00032687807,0.00034546154,0.00018047066,0.00015254541,0.000092119735,0.0011172838,0.007679118,0.1790393,0.055805538,0.698457,0.056785487],"study_design_scores_gemma":[0.00019126333,0.00005045172,0.00015380331,0.000040073992,0.000013862348,0.000013561219,0.00009538587,0.0014305459,0.86301565,0.0013305338,0.13335323,0.00031161236],"about_ca_topic_score_codex":0.000013133344,"about_ca_topic_score_gemma":0.0000042463967,"teacher_disagreement_score":0.9240319,"about_ca_system_score_codex":0.000059900678,"about_ca_system_score_gemma":0.000008256048,"threshold_uncertainty_score":0.28289416},"labels":[],"label_agreement":null},{"id":"W1990780443","doi":"10.1109/fpt.2013.6718324","title":"Maximum flow algorithms for maximum observability during FPGA debug","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Semiconductor Research Corporation","keywords":"Observability; Field-programmable gate array; Computer science; Tracing; TRACE (psycholinguistics); Routing (electronic design automation); Debugging; Algorithm; Maximum flow problem; Embedded system; Parallel computing; Mathematics; Mathematical optimization","score_opus":0.02032556772293232,"score_gpt":0.2214809940092736,"score_spread":0.20115542628634128,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1990780443","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11068877,0.00018975456,0.875736,0.00018701547,0.00039642863,0.0014138628,0.000024429313,0.003983058,0.00738068],"genre_scores_gemma":[0.75490665,0.000047224687,0.24256907,0.000101651065,0.00022895102,0.00086595764,0.000020606632,0.00010075773,0.0011591244],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988986,0.000014649607,0.0002758408,0.00024924675,0.000119315686,0.0004423332],"domain_scores_gemma":[0.99932575,0.000064876425,0.000017071194,0.00039113182,0.000079027035,0.00012214623],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001619315,0.0002196218,0.00022504626,0.000060924525,0.000077690325,0.000073727286,0.00021936963,0.00014732163,0.00064194144],"category_scores_gemma":[0.000031253425,0.00019892765,0.00012461175,0.000111203095,0.00002611543,0.0003171765,0.000040175088,0.00012851314,0.00015669712],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002425964,0.00019637366,0.0029525128,0.0013720333,0.00021338103,0.000011879946,0.00047323765,0.0029226032,0.17194356,0.0002918615,0.06374465,0.75585365],"study_design_scores_gemma":[0.0009023088,0.00011929406,0.012838096,0.000046921763,0.000031451043,0.000019775254,0.000099320016,0.53620243,0.38622555,0.053372703,0.009111384,0.0010307524],"about_ca_topic_score_codex":0.00007104836,"about_ca_topic_score_gemma":0.000010959996,"teacher_disagreement_score":0.7548229,"about_ca_system_score_codex":0.000085436055,"about_ca_system_score_gemma":0.0000082937495,"threshold_uncertainty_score":0.8112034},"labels":[],"label_agreement":null},{"id":"W1991121783","doi":"10.1109/fpt.2010.5681424","title":"Accelerating FPGA design space exploration using circuit similarity-based placement","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Field-programmable gate array; Computer science; Similarity (geometry); Design space exploration; Space (punctuation); Circuit design; Computer architecture; Embedded system; Artificial intelligence; Operating system","score_opus":0.10837972324426946,"score_gpt":0.26629689368180587,"score_spread":0.1579171704375364,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1991121783","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01701786,0.000012011089,0.97642916,0.00005037076,0.000209439,0.00032971197,0.0000015327863,0.001228841,0.0047210758],"genre_scores_gemma":[0.7951718,0.0000029252715,0.20451985,0.00008604624,0.00010066214,0.00003603578,0.00000633594,0.000037377362,0.00003895408],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992121,0.000027614444,0.00019836464,0.00016272014,0.0001590488,0.00024019134],"domain_scores_gemma":[0.9995607,0.000062328014,0.00002823325,0.00023374344,0.00004584652,0.00006915255],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00031907603,0.00016661137,0.00013023391,0.00010561217,0.00010863263,0.00011906744,0.00011592584,0.00013035905,0.0002630307],"category_scores_gemma":[0.000027956537,0.00016952299,0.000038341565,0.00014463661,0.00001601679,0.0003544395,0.000013324483,0.0002683891,0.00001794486],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000344097,0.000022462726,0.00007236061,0.000033060354,0.000011395502,0.000004160537,0.00014868441,0.122612946,0.87077284,0.0010359446,0.0015413809,0.0037413102],"study_design_scores_gemma":[0.00012636972,0.00002316075,0.000008346309,0.000011185495,0.000007666433,0.0000015666864,0.000037653852,0.4683046,0.53037363,0.0004925606,0.00044562682,0.00016764243],"about_ca_topic_score_codex":0.000014090798,"about_ca_topic_score_gemma":0.00001533834,"teacher_disagreement_score":0.77815396,"about_ca_system_score_codex":0.000054506803,"about_ca_system_score_gemma":0.000033240187,"threshold_uncertainty_score":0.69129467},"labels":[],"label_agreement":null},{"id":"W1991343829","doi":"10.1155/2012/395260","title":"A New Length‐Based Algebraic Multigrid Clustering Algorithm","year":2012,"lang":"en","type":"article","venue":"VLSI design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada; Alberta Innovates; Alberta Innovates - Technology Futures; Western Canada Research Grid; Compute Canada","keywords":"Multigrid method; Cluster analysis; Algorithm; Computer science; Algebraic number; Mathematics; Artificial intelligence","score_opus":0.02468681697919865,"score_gpt":0.22419740696303606,"score_spread":0.19951058998383742,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1991343829","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00031156972,0.0011506965,0.99371535,0.000024927498,0.0005090236,0.0003520465,0.0000048174284,0.0020478966,0.0018836716],"genre_scores_gemma":[0.3455165,0.000054484284,0.65296423,0.0001488877,0.00065560074,0.000072036,0.000008664162,0.00011776276,0.00046186347],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986967,0.000058392045,0.00025112528,0.00017936545,0.000196022,0.0006184226],"domain_scores_gemma":[0.99921054,0.000110876135,0.000030024194,0.00033332186,0.000021277772,0.00029394118],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003238668,0.00027810218,0.00023548144,0.00017484877,0.00006581115,0.000051698153,0.00022672857,0.00016656489,0.00028571728],"category_scores_gemma":[0.000021602837,0.0002804971,0.000094541254,0.00023331861,0.000017989609,0.00033208446,0.000026921225,0.00021844127,0.00026633582],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010592561,0.00006234837,0.00017881127,0.000079359794,0.00007476873,0.000018272183,0.0005415748,0.0063780993,0.04712515,0.000088372886,0.0679799,0.87746274],"study_design_scores_gemma":[0.0008980404,0.00012772555,0.0005505524,0.00009608828,0.000056716282,0.00003570064,0.000033968256,0.67815995,0.28163546,0.00017218299,0.037307348,0.0009262466],"about_ca_topic_score_codex":0.00002935369,"about_ca_topic_score_gemma":0.0000015330526,"teacher_disagreement_score":0.8765365,"about_ca_system_score_codex":0.00009039071,"about_ca_system_score_gemma":0.00003151472,"threshold_uncertainty_score":0.9999647},"labels":[],"label_agreement":null},{"id":"W1992264801","doi":"10.1109/fpl.2013.6645626","title":"From Quartus to VPR: Converting HDL to BLIF with the Titan flow","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Titan (rocket family); Field-programmable gate array; Computer science; CAD; Design flow; Computer architecture; Architecture; Electronic design automation; Embedded system; Engineering; Engineering drawing; Aerospace engineering","score_opus":0.004584349897902414,"score_gpt":0.17318848933148245,"score_spread":0.16860413943358005,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1992264801","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.39951596,0.000057340465,0.5501014,0.0029524711,0.00014467895,0.000813649,0.000008009244,0.0019054861,0.04450102],"genre_scores_gemma":[0.97198254,0.0000015586612,0.025528332,0.0011474489,0.00012458711,0.000106832915,0.000002224942,0.000030032563,0.0010764162],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994786,0.0000071157096,0.00009915457,0.00011737565,0.00010043521,0.00019733058],"domain_scores_gemma":[0.99956685,0.000045064076,0.0000066653447,0.00024598313,0.00003167602,0.00010375511],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00005373579,0.00010848095,0.0001000666,0.000038629027,0.000036731057,0.00006838552,0.0001622032,0.00003725262,0.0007426898],"category_scores_gemma":[0.0000079163565,0.00006495923,0.000019993244,0.000133839,0.000007705228,0.00008955483,0.000022768763,0.000077926656,0.0012664184],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011320559,0.000021323784,0.000649771,0.000020237487,0.00010136958,0.0000083494815,0.0046366886,0.0033727891,0.15562037,0.00062020734,0.7119467,0.12299087],"study_design_scores_gemma":[0.00080831663,0.000903124,0.011205947,0.00024065346,0.000072186696,0.000012611266,0.0048873518,0.2243156,0.55257225,0.0032306905,0.19970185,0.0020494168],"about_ca_topic_score_codex":0.00077328697,"about_ca_topic_score_gemma":0.000156549,"teacher_disagreement_score":0.5724666,"about_ca_system_score_codex":0.00002515473,"about_ca_system_score_gemma":0.0000037465256,"threshold_uncertainty_score":0.9995112},"labels":[],"label_agreement":null},{"id":"W1993004594","doi":"10.1109/tvlsi.2002.808463","title":"Probability-based approach to rectilinear Steiner tree problems","year":2002,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Very-large-scale integration; Computer science; Class (philosophy); Interconnection; Tree (set theory); Integrated circuit layout; Algorithm; Mathematical optimization; Integrated circuit; Theoretical computer science; Mathematics; Artificial intelligence; Combinatorics; Embedded system","score_opus":0.032060161823195536,"score_gpt":0.2112050610018799,"score_spread":0.17914489917868437,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1993004594","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.006426369,0.00013261379,0.97743344,0.00006687709,0.0011639689,0.0019297916,0.00014426938,0.001971008,0.0107316645],"genre_scores_gemma":[0.9895096,0.000023113875,0.00626941,0.000081995044,0.0001504204,0.001532126,0.000025445206,0.00010440675,0.0023035114],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976119,0.00017553035,0.0007096358,0.00054518523,0.0004610993,0.0004966938],"domain_scores_gemma":[0.9987664,0.000076545744,0.00006373634,0.0006873845,0.00018697901,0.00021895314],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00047239626,0.00043828355,0.0004534154,0.00045694425,0.00021372687,0.0001726737,0.00026987903,0.00033052964,0.00011136413],"category_scores_gemma":[0.000009868206,0.00039632132,0.00023733181,0.000778854,0.000038990187,0.00034238445,0.0000011049036,0.00054536195,0.00027843495],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006498491,0.0017322659,0.000028746379,0.00074277876,0.00014016608,0.000004223147,0.002298605,0.9240201,0.031417154,0.00019974643,0.01358222,0.025769014],"study_design_scores_gemma":[0.00061782537,0.0003196313,0.000009792984,0.00028393822,0.000048479622,0.000018257351,0.0002860005,0.91146725,0.07389844,0.000026907908,0.012447076,0.0005764154],"about_ca_topic_score_codex":0.000056847774,"about_ca_topic_score_gemma":0.00017561886,"teacher_disagreement_score":0.9830832,"about_ca_system_score_codex":0.00035007708,"about_ca_system_score_gemma":0.000020675394,"threshold_uncertainty_score":0.99984884},"labels":[],"label_agreement":null},{"id":"W1993072227","doi":"10.5555/1015090.1015284","title":"Interconnect capacitance estimation for FPGAs","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Capacitance; Field-programmable gate array; Routing (electronic design automation); Noise (video); Dynamic demand; Electronic engineering; Computer science; CMOS; Bounding overwatch; Interconnection; Power (physics); Lookup table; Parasitic capacitance; Minimum bounding box; Engineering; Embedded system; Telecommunications; Artificial intelligence","score_opus":0.009835024715061765,"score_gpt":0.21483163952893491,"score_spread":0.20499661481387316,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1993072227","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012639677,0.000057875655,0.9770157,0.00005401618,0.00007669467,0.00014673435,0.0000022130766,0.0008904747,0.009116631],"genre_scores_gemma":[0.8601247,0.0000075171274,0.1396713,0.000039271974,0.000021760328,0.000050395825,0.0000030189192,0.000011587467,0.00007042818],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99976647,0.0000011920548,0.00006912911,0.000052290598,0.000025966585,0.00008495419],"domain_scores_gemma":[0.9998795,0.000014477024,0.00000475471,0.00007089942,0.000013187404,0.000017215236],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000040319406,0.00005194258,0.000052152285,0.000028458999,0.000014645001,0.000011905232,0.00004341855,0.000031555883,0.000017993923],"category_scores_gemma":[0.000014296178,0.000048338392,0.00002426007,0.00003608923,0.000006096119,0.00009488012,0.0000014248501,0.00002816514,0.000020122878],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013244122,0.00004980838,0.000022368897,0.00039405873,0.00006764716,0.0000046843184,0.001378516,0.17338084,0.24464779,0.24477997,0.016350288,0.3189108],"study_design_scores_gemma":[0.00028399803,0.000057134705,0.000024066409,0.00004669442,0.00000570482,0.000005988756,0.000026986465,0.08253003,0.842624,0.072598636,0.0016310263,0.00016571127],"about_ca_topic_score_codex":0.0000058749633,"about_ca_topic_score_gemma":0.00000983841,"teacher_disagreement_score":0.84748507,"about_ca_system_score_codex":0.00004259703,"about_ca_system_score_gemma":0.0000029366802,"threshold_uncertainty_score":0.19711825},"labels":[],"label_agreement":null},{"id":"W1993422730","doi":"10.1109/ds-rt.2012.38","title":"An Offline Road Network Partitioning Solution in Distributed Transportation Simulation","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":33,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Scalability; Graph partition; Computer science; Flow network; Graph; Space partitioning; Distributed computing; Partition (number theory); Graph theory; Theoretical computer science; Algorithm; Mathematical optimization; Database; Mathematics","score_opus":0.015821559524481138,"score_gpt":0.2518407162627888,"score_spread":0.23601915673830767,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1993422730","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21349813,0.000074729985,0.7853893,0.0000068651552,0.00007294476,0.00009962129,0.000006857708,0.00054471596,0.00030680627],"genre_scores_gemma":[0.9956744,0.000009442547,0.003580483,0.000012270852,0.0001601035,0.00001847931,0.00052820885,0.000012097631,0.0000045711126],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99949205,0.000016097129,0.00017114641,0.000058002854,0.000059604696,0.00020307505],"domain_scores_gemma":[0.9998405,0.000012081981,0.000014354806,0.000073325,0.000014578958,0.00004513519],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016000164,0.0000682939,0.00007083669,0.000035870693,0.000028659759,0.000010930013,0.000027467839,0.00006787341,0.000057104382],"category_scores_gemma":[0.0000033731462,0.00007236856,0.000016818654,0.00016410189,0.0000052625946,0.00048755223,7.207496e-7,0.00006310903,0.0000072761873],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000003845952,0.000025815154,0.02588265,0.000008360252,0.0000029422695,3.0477705e-7,0.00013477789,0.96345764,0.0024481658,0.00052400824,0.0001922053,0.0073192664],"study_design_scores_gemma":[0.0000957524,0.000014495671,0.21138051,0.000012151653,0.0000051267684,1.7174034e-7,0.000012640536,0.7857548,0.002028525,0.00025597148,0.0003440459,0.00009579044],"about_ca_topic_score_codex":0.00003839319,"about_ca_topic_score_gemma":0.0001134454,"teacher_disagreement_score":0.7821762,"about_ca_system_score_codex":0.000043245123,"about_ca_system_score_gemma":0.0000021071169,"threshold_uncertainty_score":0.2951104},"labels":[],"label_agreement":null},{"id":"W1995613452","doi":"10.1049/iet-cdt:20070120","title":"SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays","year":2008,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Design space exploration; Computer science; Gate array; Field-programmable gate array; Field (mathematics); Genetic algorithm; Computer Aided Design; Design tool; Computer architecture; Space exploration; Core (optical fiber); Space (punctuation); Embedded system; Multi-core processor; Computer engineering; Computer hardware; Parallel computing; Engineering; Aerospace engineering; Operating system","score_opus":0.04922049004676316,"score_gpt":0.25872247149558575,"score_spread":0.2095019814488226,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1995613452","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0027828615,0.000110768764,0.99044126,0.000047926664,0.0001367867,0.0031497772,0.00003601332,0.0032059439,0.00008868132],"genre_scores_gemma":[0.34811464,0.000053368065,0.65095204,0.000045200173,0.00013882916,0.0005462658,0.000052183153,0.00007607584,0.000021364787],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9981446,0.00003786865,0.0005869342,0.0003938044,0.00022005664,0.0006167313],"domain_scores_gemma":[0.9987247,0.00038556845,0.00017742196,0.00032812275,0.00027514677,0.00010906991],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00024748393,0.00041941038,0.00053054746,0.00024300959,0.00016077436,0.00025620498,0.00039833225,0.00022028219,0.0000013597939],"category_scores_gemma":[0.000045529025,0.00043465305,0.0002102217,0.00030845747,0.00009545463,0.0014762208,0.000053183223,0.00014858128,8.455383e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000851699,0.00053850806,0.00018281926,0.0015500104,0.00029776894,0.000042769392,0.0030345672,0.052442417,0.04070648,0.0016239075,0.09550616,0.8032229],"study_design_scores_gemma":[0.0005548648,0.0017973972,0.000012559375,0.00041394506,0.000031596555,0.00003839859,0.00002989013,0.38031948,0.6047333,0.008725984,0.0027168526,0.00062572764],"about_ca_topic_score_codex":0.000004508902,"about_ca_topic_score_gemma":4.4958367e-7,"teacher_disagreement_score":0.80259717,"about_ca_system_score_codex":0.000072600735,"about_ca_system_score_gemma":0.00008094771,"threshold_uncertainty_score":0.9998105},"labels":[],"label_agreement":null},{"id":"W1996309908","doi":"10.1137/s1064827502401953","title":"Permuting Sparse Rectangular Matrices into Block-Diagonal Form","year":2004,"lang":"en","type":"article","venue":"SIAM Journal on Scientific Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":155,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Hypergraph; Mathematics; Diagonal; Bipartite graph; Sparse matrix; Block matrix; Factorization; Combinatorics; Vertex (graph theory); Graph; Algorithm; Eigenvalues and eigenvectors; Gaussian","score_opus":0.0130859972809326,"score_gpt":0.2427284259525517,"score_spread":0.2296424286716191,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1996309908","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9315506,0.0010151936,0.060228493,0.00012357876,0.0027322553,0.0001537074,0.000002227171,0.00068682426,0.0035071191],"genre_scores_gemma":[0.9810358,0.000026593396,0.018160366,0.00004687679,0.00061566714,0.0000010123371,0.0000027299093,0.000040909777,0.00006998938],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979899,0.000034346478,0.0005274065,0.00030370895,0.00058339554,0.0005612358],"domain_scores_gemma":[0.9991723,0.000083482526,0.0001427401,0.0002583978,0.00013076917,0.00021234567],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0016604263,0.00023784759,0.00024331592,0.0005031791,0.00081555377,0.0007559576,0.00043654485,0.00009307417,0.000037845344],"category_scores_gemma":[0.00008109077,0.0002191888,0.00017406873,0.00071097934,0.00007994679,0.00026841418,0.00007598732,0.0006403809,0.000105928986],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000038357954,0.00029279524,0.000940425,0.00030920553,0.00022096407,0.0010050146,0.013345033,0.4022429,0.18190013,0.004212248,0.013275109,0.38221782],"study_design_scores_gemma":[0.0048939036,0.0011291391,0.0030891863,0.0057040127,0.00021490718,0.007980947,0.0032685937,0.4212023,0.3741685,0.07890786,0.094877824,0.004562846],"about_ca_topic_score_codex":0.000004712422,"about_ca_topic_score_gemma":0.000004040577,"teacher_disagreement_score":0.37765497,"about_ca_system_score_codex":0.0003286074,"about_ca_system_score_gemma":0.00007803552,"threshold_uncertainty_score":0.893826},"labels":[],"label_agreement":null},{"id":"W1996678568","doi":"10.1145/368434.368600","title":"Analytical minimization of half-perimeter wirelength","year":2000,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":43,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"University of Texas at Austin","keywords":"Minification; Perimeter; Computer science; Mathematics; Mathematical optimization; Algorithm; Geometry","score_opus":0.008589669774032426,"score_gpt":0.2104882135888069,"score_spread":0.20189854381477448,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1996678568","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.39722613,0.00013579005,0.08467325,0.000050807485,0.00005116523,0.00014961048,0.0000030063788,0.0011940196,0.5165162],"genre_scores_gemma":[0.99152166,0.000058179576,0.007093689,0.000021199437,0.000017903267,0.000002703375,0.000002828204,0.000011382981,0.0012704834],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99969345,0.0000054728216,0.000115107265,0.000052750056,0.000056059034,0.000077135104],"domain_scores_gemma":[0.9998511,0.000011940168,0.0000041504713,0.00009765964,0.000010914592,0.000024214341],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000026559454,0.00005291457,0.000082900086,0.000037622074,0.000006292655,0.00000519705,0.000046330362,0.000045541237,0.002818661],"category_scores_gemma":[0.0000028583545,0.000046426696,0.000028850034,0.00008682842,0.000014172891,0.00005266812,0.0000023731857,0.00003313365,0.00004261271],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002825639,0.00015321185,0.0020150258,0.00013747596,0.00014276392,0.000009568303,0.00041856585,0.008867495,0.023811465,0.010600742,0.056134563,0.8976809],"study_design_scores_gemma":[0.000225213,0.00008703322,0.0016990382,0.000020854957,0.000026347609,0.000006013749,0.0000144719315,0.6646045,0.30981553,0.00036646947,0.022878341,0.00025620166],"about_ca_topic_score_codex":0.0000069409152,"about_ca_topic_score_gemma":5.4947316e-7,"teacher_disagreement_score":0.89742464,"about_ca_system_score_codex":0.000007413594,"about_ca_system_score_gemma":0.0000024548633,"threshold_uncertainty_score":0.9980929},"labels":[],"label_agreement":null},{"id":"W1998393880","doi":"10.1145/1810479.1810515","title":"Brief announcement","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Computer science; Reinforcement learning; Load balancing (electrical power); Parallel computing; Very-large-scale integration; Distributed computing; Algorithm; Artificial intelligence; Embedded system","score_opus":0.004605202365633554,"score_gpt":0.18870149348796086,"score_spread":0.1840962911223273,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1998393880","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.070530295,0.000034840206,0.14620858,0.00007199134,0.00049148564,0.000108723514,0.000002436092,0.0026470907,0.77990454],"genre_scores_gemma":[0.9904447,0.000008899445,0.0085559115,0.00007389774,0.000058785867,0.000008502318,0.0000015594313,0.000008002636,0.00083971705],"study_design_codex":"bench_or_experimental","study_design_gemma":"not_applicable","domain_scores_codex":[0.99980605,8.2493784e-7,0.000043578933,0.00003701533,0.000038507267,0.000074050506],"domain_scores_gemma":[0.9998666,0.0000034712873,0.0000018973152,0.00009765594,0.000007291301,0.000023062776],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003550171,0.000037036145,0.000031139738,0.00001636626,0.000009941852,0.000011416094,0.00004809646,0.0000293246,0.0005390782],"category_scores_gemma":[0.0000019364127,0.000032155644,0.000011566553,0.000029481374,0.000006620427,0.000036439375,0.0000053298522,0.000074547715,0.00006870773],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[4.9598464e-7,0.000012058181,0.00039732907,0.000010712115,0.000009060473,0.0000032643861,0.000051964453,0.00002426245,0.7904011,0.021997254,0.13039066,0.05670182],"study_design_scores_gemma":[0.0000766797,0.00001910799,0.0007422435,0.0000021548099,0.0000022706602,0.0000057516986,0.0000065596637,0.0051863138,0.32435292,0.0015902652,0.6678711,0.00014463457],"about_ca_topic_score_codex":0.0000056330155,"about_ca_topic_score_gemma":0.000010477216,"teacher_disagreement_score":0.9199144,"about_ca_system_score_codex":0.0000037405844,"about_ca_system_score_gemma":0.0000017867507,"threshold_uncertainty_score":0.5902529},"labels":[],"label_agreement":null},{"id":"W1999062853","doi":"10.1145/360276.360302","title":"Mixing buffers and pass transistors in FPGA routing architectures","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Interconnection; Field-programmable gate array; Application-specific integrated circuit; Transistor; Computer science; Topology (electrical circuits); CMOS; Parallel computing; Electrical engineering; Engineering; Embedded system; Computer network; Voltage","score_opus":0.007826181841910824,"score_gpt":0.19569805599612988,"score_spread":0.18787187415421905,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1999062853","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8988458,0.00033709581,0.07649975,0.000070981536,0.000046589026,0.00010791381,6.010201e-7,0.0007169588,0.023374323],"genre_scores_gemma":[0.99712527,0.00006741755,0.002649902,0.000046064062,0.000025023633,0.0000077228315,6.333309e-7,0.000018037495,0.00005992321],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995335,0.000011479594,0.00011910861,0.00009989227,0.00005266819,0.00018334988],"domain_scores_gemma":[0.99984807,0.000033469183,0.000005577534,0.00007135745,0.0000034934287,0.000038041333],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008965567,0.00009575169,0.00010658197,0.00010853799,0.000022030026,0.000017289407,0.000049869068,0.000053572563,0.000024375177],"category_scores_gemma":[0.0000070518267,0.000088350615,0.00002188927,0.00010814935,0.000015038514,0.000033418797,0.0000059626436,0.00012174315,0.0000013723038],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000033143893,0.00005410987,0.08537524,0.00023578582,0.000076650875,0.0002077766,0.008224165,0.017310577,0.118606016,0.0013383336,0.001613523,0.7669247],"study_design_scores_gemma":[0.0036021345,0.00038926039,0.30380324,0.0007814072,0.000089090165,0.000475393,0.002584121,0.31071523,0.33543253,0.013174843,0.02498811,0.0039646495],"about_ca_topic_score_codex":0.00010002565,"about_ca_topic_score_gemma":0.00017069514,"teacher_disagreement_score":0.76296,"about_ca_system_score_codex":0.000027104512,"about_ca_system_score_gemma":0.0000023312239,"threshold_uncertainty_score":0.36028334},"labels":[],"label_agreement":null},{"id":"W1999343232","doi":"10.1145/1027084.1027090","title":"Segmented channel routability via satisfiability","year":2004,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":22,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; Université de Montréal","funders":"","keywords":"Routing (electronic design automation); Computer science; Channel (broadcasting); Field-programmable gate array; Satisfiability; Constraint (computer-aided design); Boolean satisfiability problem; Algorithm; Electronic design automation; Network routing; Parallel computing; Embedded system; Mathematics; Computer network","score_opus":0.013728378803189613,"score_gpt":0.22085256443908233,"score_spread":0.20712418563589272,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1999343232","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.015693953,0.00025031753,0.98109514,0.00005167388,0.00021724912,0.0010619827,0.000014491496,0.0014721825,0.00014298531],"genre_scores_gemma":[0.9943501,0.000051670304,0.0051859645,0.000008805564,0.000021483638,0.0003110746,0.0000080508735,0.000038340222,0.000024543862],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9983281,0.00014848898,0.00058415293,0.00025868518,0.00029298794,0.00038756948],"domain_scores_gemma":[0.99888015,0.00015836388,0.00009378704,0.00070194755,0.00009648148,0.00006929478],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00064984156,0.00023898718,0.00033176012,0.00021676459,0.000093065944,0.000025796757,0.00026879174,0.00018107399,0.00005059176],"category_scores_gemma":[0.00002881829,0.0002470028,0.00011988706,0.00041983777,0.00004659118,0.00024357483,0.0000020136972,0.00025308126,0.00003863248],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000031194166,0.00021249997,0.0000089370105,0.00025296237,0.00014807274,7.2500745e-7,0.0003841136,0.945714,0.039796967,0.0004859198,0.000048760074,0.012915876],"study_design_scores_gemma":[0.0016081599,0.0011886216,0.00063794124,0.000258016,0.00011231682,0.00005820886,0.00015017271,0.47451806,0.50000364,0.020640722,0.00011902516,0.00070513535],"about_ca_topic_score_codex":0.00009702417,"about_ca_topic_score_gemma":0.000012972047,"teacher_disagreement_score":0.9786561,"about_ca_system_score_codex":0.0007958916,"about_ca_system_score_gemma":0.00008749927,"threshold_uncertainty_score":0.9999982},"labels":[],"label_agreement":null},{"id":"W1999993900","doi":"10.1007/s10479-011-0983-3","title":"An efficient memetic algorithm for the graph partitioning problem","year":2011,"lang":"en","type":"article","venue":"Annals of Operations Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":68,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Memetic algorithm; Crossover; Graph partition; Tabu search; Theory of computation; Computer science; Partition (number theory); Mathematical optimization; Vertex (graph theory); Graph; Operator (biology); Algorithm; Mathematics; Local search (optimization); Theoretical computer science; Combinatorics; Artificial intelligence","score_opus":0.2813694063939959,"score_gpt":0.4229850109156691,"score_spread":0.1416156045216732,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1999993900","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018202206,0.0006909059,0.9758065,0.0002322979,0.000044566845,0.0011222358,0.000039542974,0.00017934294,0.0036824094],"genre_scores_gemma":[0.94457376,0.0002558506,0.054366093,0.000018412167,0.000041941516,0.0006407353,0.000010884209,0.000018480921,0.00007381877],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99922943,0.00006272864,0.00016567785,0.00010015029,0.00020185397,0.00024018256],"domain_scores_gemma":[0.9991231,0.00008397788,0.000005315881,0.00025531565,0.0004830297,0.000049248178],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0012029229,0.00005816322,0.000073307725,0.00016216114,0.0002889748,0.00005355705,0.00022042533,0.000038065235,0.00008303539],"category_scores_gemma":[0.00003301184,0.00004283642,0.000042522424,0.00031343524,0.00009213248,0.000105070074,0.000016064037,0.00012649262,0.000008248219],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000028492364,0.00093616766,0.00010763223,0.00022328859,0.00032172113,0.000005417849,0.011578718,0.35236743,0.05111108,0.09277878,0.027864264,0.462677],"study_design_scores_gemma":[0.00007189998,0.00026856823,0.00023335709,0.00002344878,0.0000051488396,0.0000013025083,0.00028018595,0.8035454,0.19273143,0.0019189008,0.00083934126,0.00008099098],"about_ca_topic_score_codex":0.00010503489,"about_ca_topic_score_gemma":0.00002964633,"teacher_disagreement_score":0.9263716,"about_ca_system_score_codex":0.0000059127055,"about_ca_system_score_gemma":0.00002461622,"threshold_uncertainty_score":0.22225899},"labels":[],"label_agreement":null},{"id":"W2000205915","doi":"10.1007/s10470-009-9312-z","title":"Performance-driven circuit and layout co-optimization for deep-submicron analog circuits","year":2009,"lang":"en","type":"article","venue":"Analog Integrated Circuits and Signal Processing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Parasitic extraction; Schematic; Physical design; Computer science; Electronic engineering; Netlist; Integrated circuit layout; Design flow; Circuit extraction; Process (computing); Circuit design; Integrated circuit; Engineering; Equivalent circuit; Embedded system; Electrical engineering","score_opus":0.015482122001024343,"score_gpt":0.22576752686041557,"score_spread":0.21028540485939123,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2000205915","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15361804,0.0030477396,0.8349042,0.000040804658,0.000052447253,0.00059559755,0.000037378213,0.00081989577,0.006883901],"genre_scores_gemma":[0.9981574,0.00054375915,0.0007198474,0.00021158895,0.0001025156,0.00003349512,0.00014274193,0.000050532803,0.00003810736],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985,0.00002646151,0.000420065,0.00040709725,0.00016433568,0.000482071],"domain_scores_gemma":[0.99937713,0.000042955395,0.00009693077,0.00012703994,0.00019315862,0.00016277308],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00022467035,0.00036412038,0.00040390645,0.00030089243,0.00033157898,0.0002648033,0.00015461605,0.00026600953,0.00003664234],"category_scores_gemma":[0.00001664609,0.00033815924,0.00006054012,0.00035420674,0.00008955125,0.0005568324,0.000007768533,0.0003018987,0.0000020252407],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007662168,0.00003476267,0.0014687375,0.0003064533,0.000049512513,0.000007196894,0.00068898423,0.012170808,0.03476472,0.00018002358,0.00027838792,0.9500427],"study_design_scores_gemma":[0.00062894274,0.0004313568,0.0020663985,0.00036331036,0.00011092446,0.00007455194,0.0002190467,0.9849688,0.009238628,0.0008446231,0.0004071714,0.0006462521],"about_ca_topic_score_codex":0.0000069791545,"about_ca_topic_score_gemma":0.000005038775,"teacher_disagreement_score":0.972798,"about_ca_system_score_codex":0.000075939715,"about_ca_system_score_gemma":0.00005988315,"threshold_uncertainty_score":0.999907},"labels":[],"label_agreement":null},{"id":"W2000383438","doi":"10.1145/1123008.1123051","title":"Net cluster","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Benchmark (surveying); Computer science; Digital electronics; Reduction (mathematics); Cluster (spacecraft); Algorithm; Suite; Electronic circuit; Logic gate; Computer engineering; Mathematics; Artificial intelligence; Engineering","score_opus":0.0034570407955953515,"score_gpt":0.16798952766693995,"score_spread":0.16453248687134459,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2000383438","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011006254,0.00008947266,0.300243,0.00003698649,0.00006176174,0.000048961283,6.5662266e-7,0.0016758192,0.68683714],"genre_scores_gemma":[0.9908719,0.000004072661,0.0057939105,0.0000731011,0.000075755655,0.000004887321,0.0000022289153,0.000009593699,0.0031645594],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99983054,0.0000015829212,0.000044655535,0.000029569377,0.000025318255,0.0000683427],"domain_scores_gemma":[0.9999235,0.0000043527357,0.0000015628138,0.000058355712,0.0000033362185,0.000008854368],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000017757757,0.000034020424,0.000030355945,0.000017685437,0.0000063240623,0.000009264907,0.00002993962,0.000024515457,0.0001643988],"category_scores_gemma":[3.6940946e-7,0.000029113868,0.000012201544,0.000028403281,0.0000034744908,0.000032075342,0.0000038038545,0.000024589783,0.000096571435],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[5.9975997e-7,0.000007840873,0.00054667576,0.00001221223,0.0000041633784,0.0000029451212,0.000010858887,0.0017724513,0.0144191515,0.008459924,0.9643896,0.01037358],"study_design_scores_gemma":[0.00032381451,0.000035701443,0.0054960717,0.000011534404,0.000008541816,0.000016313235,0.000009766824,0.09537869,0.2856445,0.017798137,0.5947975,0.00047943546],"about_ca_topic_score_codex":0.000020868767,"about_ca_topic_score_gemma":0.000008578749,"teacher_disagreement_score":0.9798656,"about_ca_system_score_codex":0.0000064232345,"about_ca_system_score_gemma":6.2025254e-7,"threshold_uncertainty_score":0.18000516},"labels":[],"label_agreement":null},{"id":"W2001180691","doi":"10.1142/s0218126608004526","title":"A FAST AND EFFECTIVE TIMING-DRIVEN PLACEMENT TOOL FOR FPGAs","year":2008,"lang":"en","type":"article","venue":"Journal of Circuits Systems and Computers","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Benchmark (surveying); Field-programmable gate array; Routing (electronic design automation); Computer science; Process (computing); Quadratic equation; Path (computing); Electronic circuit; Microelectronics; Chip; Algorithm; Mathematics; Embedded system; Engineering; Electrical engineering; Telecommunications; Geometry","score_opus":0.014504904275145782,"score_gpt":0.21083176085781655,"score_spread":0.19632685658267077,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2001180691","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.32161695,0.001085997,0.67635185,0.000009987618,0.00039400658,0.00036023156,0.0000035713842,0.00004471059,0.00013268428],"genre_scores_gemma":[0.99852085,0.00015708464,0.0010434136,0.000016791097,0.00021134499,0.000016654596,4.0271894e-7,0.00001463367,0.000018818651],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99941546,0.000021360565,0.00026053164,0.0000739213,0.000105936975,0.00012279573],"domain_scores_gemma":[0.9996141,0.00010750075,0.00009104926,0.000053059102,0.00006621941,0.00006803412],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016439974,0.00010705403,0.00026427183,0.00009918746,0.00006005455,0.000040765044,0.000058447586,0.000048263802,4.4098206e-7],"category_scores_gemma":[0.0000058833903,0.00009095225,0.000051454714,0.00003753421,0.000020856738,0.000111207664,0.000010403437,0.00008442554,2.938559e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015161143,0.00025586388,0.011412063,0.005404047,0.002577144,0.00063240225,0.020667652,0.2515128,0.054870386,0.0033696003,0.07834634,0.5708001],"study_design_scores_gemma":[0.011040515,0.006269633,0.02873683,0.005059187,0.00040279765,0.018209081,0.0012889263,0.89079624,0.009062775,0.0004690098,0.02659238,0.0020726386],"about_ca_topic_score_codex":0.0000017255187,"about_ca_topic_score_gemma":1.1842543e-7,"teacher_disagreement_score":0.6769039,"about_ca_system_score_codex":0.000039912502,"about_ca_system_score_gemma":0.000009778927,"threshold_uncertainty_score":0.37089252},"labels":[],"label_agreement":null},{"id":"W2002528607","doi":"10.1109/fpl.2012.6339245","title":"On the difficulty of pin-to-wire routing in FPGAs","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Router; Computer science; Modular design; Very-large-scale integration; Control reconfiguration; Block (permutation group theory); Embedded system; Path (computing); Place and route; Computer network","score_opus":0.015020525938502805,"score_gpt":0.2166773981920934,"score_spread":0.20165687225359058,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2002528607","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9366153,0.00003214953,0.013422647,0.000102687874,0.00006581396,0.00015582876,0.0000013213798,0.00026492865,0.04933934],"genre_scores_gemma":[0.9992076,0.000003646732,0.00054002804,0.00008793347,0.000029910614,0.000011239367,4.4868983e-7,0.000010370153,0.0001087778],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996256,0.000011052417,0.00010497575,0.000040167553,0.00006281734,0.00015539321],"domain_scores_gemma":[0.9997694,0.00006509629,0.000007798943,0.0001233709,0.0000061468245,0.000028184855],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015410427,0.00006052526,0.00007399269,0.000038776016,0.000011620622,0.00000460997,0.00008249522,0.000033448134,0.0000721245],"category_scores_gemma":[0.000030079398,0.000037245958,0.00002138232,0.000112179434,0.0000060932903,0.000038033515,0.000014916878,0.000077526034,0.00003176642],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000021896,0.00037870038,0.031355284,0.00014884287,0.00007197236,0.000004627024,0.010423673,0.0077945106,0.4332485,0.3685837,0.07447456,0.07349371],"study_design_scores_gemma":[0.00028112257,0.00011555693,0.08911378,0.00023017825,0.000009929218,0.000004111564,0.00071586657,0.019078022,0.8861688,0.0011863792,0.0026040187,0.0004922386],"about_ca_topic_score_codex":0.00002213915,"about_ca_topic_score_gemma":0.0000077909535,"teacher_disagreement_score":0.4529203,"about_ca_system_score_codex":0.00002160753,"about_ca_system_score_gemma":0.0000013378439,"threshold_uncertainty_score":0.1518846},"labels":[],"label_agreement":null},{"id":"W2002849997","doi":"10.1007/s10878-015-9880-z","title":"An approximation algorithm for the balanced Max-3-Uncut problem using complex semidefinite programming rounding","year":2015,"lang":"en","type":"article","venue":"Journal of Combinatorial Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"Beijing University of Technology; Natural Sciences and Engineering Research Council of Canada; National Natural Science Foundation of China","keywords":"Rounding; Semidefinite programming; Randomized rounding; Univariate; Approximation algorithm; Maximum cut; Theory of computation; Linear programming; Bivariate analysis; Mathematics; Partition (number theory); Semidefinite embedding; Mathematical optimization; Algorithm; Graph partition; Graph; Computer science; Discrete mathematics; Combinatorics; Quadratically constrained quadratic program; Quadratic programming","score_opus":0.04340661387300668,"score_gpt":0.28112499689139314,"score_spread":0.23771838301838646,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2002849997","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00074291765,0.0001398813,0.99673676,0.000026442905,0.001583874,0.00053046405,0.000003220722,0.00014530095,0.00009111175],"genre_scores_gemma":[0.15474495,0.00003353388,0.844399,0.0000113467195,0.0007212977,0.000021417043,0.00002247387,0.000043600576,0.0000023684015],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99886304,0.00005923603,0.0004964704,0.00008465983,0.00030596947,0.00019064818],"domain_scores_gemma":[0.99888366,0.00008133126,0.00030662795,0.00012474973,0.00050666556,0.00009694426],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010147801,0.00014346102,0.00023616779,0.00013402039,0.00012254085,0.00020744157,0.00019825889,0.00010428252,0.000002659618],"category_scores_gemma":[0.00005722478,0.0001145304,0.000075137155,0.00023518392,0.00002116599,0.000759688,0.000011254777,0.00016275838,2.6745826e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000031506843,0.00005139133,0.000028881363,0.000030258812,0.000046825822,0.000001314262,0.0003300216,0.9644042,0.0014216438,0.0011314397,0.00032252268,0.032199983],"study_design_scores_gemma":[0.0011568302,0.0002916508,0.000004597237,0.0000573363,0.0000681361,0.000034317283,0.00014544518,0.9919748,0.0012007502,0.0037254747,0.0012003748,0.00014034384],"about_ca_topic_score_codex":0.0000040872264,"about_ca_topic_score_gemma":1.03110914e-7,"teacher_disagreement_score":0.15400204,"about_ca_system_score_codex":0.00023808955,"about_ca_system_score_gemma":0.00006351552,"threshold_uncertainty_score":0.46704143},"labels":[],"label_agreement":null},{"id":"W2003258276","doi":"10.1109/fpt.2008.4762362","title":"A system-level stochastic circuit generator for FPGA architecture evaluation","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Electronic circuit; Generator (circuit theory); Field-programmable gate array; Dataflow; Benchmark (surveying); Digital pattern generator; Sequential logic; Circuit design; Design flow; Computer architecture; Electronic engineering; Computer hardware; Embedded system; Parallel computing; Logic gate; Engineering; Electrical engineering; Power (physics); Algorithm","score_opus":0.06698503212614257,"score_gpt":0.24620833593829197,"score_spread":0.1792233038121494,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2003258276","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012980377,0.00024452098,0.9815499,0.00000933421,0.00016997958,0.0007995897,0.000026785912,0.0010835739,0.0031359324],"genre_scores_gemma":[0.9878097,0.0000028163577,0.011185537,0.000029703368,0.00020206363,0.00048341235,0.000020455085,0.000037671434,0.00022861527],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993124,0.000016701448,0.00016164746,0.00013807266,0.00018522216,0.00018592701],"domain_scores_gemma":[0.9996289,0.000039417802,0.000016055385,0.00017592739,0.00008519505,0.000054523207],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018454736,0.00012739569,0.000139544,0.00009113844,0.000076473705,0.000013299713,0.000091510985,0.000086629036,0.00004072408],"category_scores_gemma":[0.000028821474,0.00011394872,0.00005949638,0.00008997149,0.0000130671315,0.000045516725,0.0000063616767,0.000070260365,0.000019443147],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003688824,0.00009888396,0.000054856337,0.0013408342,0.00035783212,0.000020478437,0.0025675644,0.39398664,0.269962,0.013089726,0.0812146,0.23726968],"study_design_scores_gemma":[0.0009927009,0.00014083667,0.00028722564,0.00008732041,0.000093286326,0.00020641228,0.00007555213,0.9288804,0.0654738,0.0018009507,0.0013657713,0.0005957384],"about_ca_topic_score_codex":0.0000053826157,"about_ca_topic_score_gemma":0.0000045260167,"teacher_disagreement_score":0.9748294,"about_ca_system_score_codex":0.000110289846,"about_ca_system_score_gemma":0.00003373665,"threshold_uncertainty_score":0.4646694},"labels":[],"label_agreement":null},{"id":"W2003452683","doi":"10.1145/360276.360292","title":"A crosstalk-aware timing-driven router for FPGAs","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":28,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Crosstalk; Router; Field-programmable gate array; Computer science; Network routing; Electronic circuit; Application-specific integrated circuit; Embedded system; Routing (electronic design automation); Electronic engineering; Computer architecture; Computer network; Engineering; Electrical engineering","score_opus":0.026533057123853076,"score_gpt":0.2533236222733968,"score_spread":0.2267905651495437,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2003452683","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014638351,0.000046681245,0.9582994,0.000066715904,0.000095561685,0.00026918898,0.000009490337,0.0015610489,0.025013583],"genre_scores_gemma":[0.9765515,0.000032269803,0.01893318,0.00013238311,0.000117944706,0.00010326372,0.00001185995,0.000040921244,0.004076717],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9995237,0.0000028160916,0.00010868522,0.00010363908,0.000052581105,0.0002085715],"domain_scores_gemma":[0.99975336,0.00002202927,0.000007605287,0.0001447498,0.000026656906,0.000045611745],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000039164366,0.00010190629,0.00010141258,0.000044445736,0.00003679553,0.00004074264,0.0000943049,0.00007078496,0.00021680705],"category_scores_gemma":[0.00000426553,0.000091766095,0.00006152296,0.000061706705,0.000011239636,0.00010181446,0.000012757202,0.000050517792,0.000047235128],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007073197,0.00016876495,0.0056692534,0.00048946904,0.00028014733,0.00011990414,0.0017014877,0.012773316,0.06173971,0.0064576124,0.6603845,0.25014514],"study_design_scores_gemma":[0.00097594113,0.00019798563,0.00079620705,0.00007582272,0.00003778273,0.000067319044,0.00009363693,0.43365237,0.09746872,0.0030380492,0.4627174,0.00087873294],"about_ca_topic_score_codex":0.0000078316425,"about_ca_topic_score_gemma":0.000011868321,"teacher_disagreement_score":0.9619131,"about_ca_system_score_codex":0.000027670696,"about_ca_system_score_gemma":0.0000041521075,"threshold_uncertainty_score":0.37421125},"labels":[],"label_agreement":null},{"id":"W2003514664","doi":"10.1109/newcas.2008.4606338","title":"An interconnection network for a novel reconfigurable circuit board","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université du Québec à Montréal; Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Interconnection; Crossbar switch; Multiplexer; Computer science; Netlist; CMOS; Integrated circuit; Reticle; Embedded system; Electronic circuit; Electronic engineering; Engineering; Electrical engineering; Multiplexing; Wafer; Computer network; Telecommunications","score_opus":0.0373521198387689,"score_gpt":0.22806556701699535,"score_spread":0.19071344717822644,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2003514664","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019773064,0.000050307495,0.9413357,0.000011659704,0.00026655447,0.00021992216,0.0000036558267,0.0014879019,0.036851246],"genre_scores_gemma":[0.98161584,0.00004235633,0.017199479,0.000098061486,0.0002677376,0.000091923896,0.0000104967885,0.000031546417,0.0006425522],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995374,0.0000040199043,0.00012238964,0.00011084173,0.00003614446,0.00018921205],"domain_scores_gemma":[0.9997451,0.000025616775,0.00001018422,0.00014603262,0.000026063519,0.00004705738],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008386861,0.00008625677,0.000105009225,0.000037841444,0.00006446798,0.000015665957,0.00007819239,0.00007538636,0.000116062016],"category_scores_gemma":[0.0000059185677,0.00008597836,0.00004476723,0.00007494324,0.000009717569,0.0001684,0.0000017841035,0.0000623633,0.000014147923],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000041560954,0.00016537313,0.001156346,0.00015303303,0.00015323776,0.000007827416,0.0009959603,0.025570432,0.47299924,0.02168008,0.38515863,0.09191829],"study_design_scores_gemma":[0.0014220683,0.0010160331,0.0018579741,0.00010246084,0.000041292886,0.00021863978,0.00017155168,0.4003899,0.39023373,0.014125387,0.18910363,0.001317346],"about_ca_topic_score_codex":0.00003316497,"about_ca_topic_score_gemma":0.000027194075,"teacher_disagreement_score":0.9618428,"about_ca_system_score_codex":0.00003221124,"about_ca_system_score_gemma":0.0000056734657,"threshold_uncertainty_score":0.35060957},"labels":[],"label_agreement":null},{"id":"W2004141433","doi":"10.1145/1231996.1232020","title":"An effective clustering algorithm for mixed-size placement","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Computer science; Benchmark (surveying); Preprocessor; Algorithm; Very-large-scale integration; Data mining; Correlation clustering; Computer engineering; Artificial intelligence; Embedded system","score_opus":0.006215602005690232,"score_gpt":0.24861659169032685,"score_spread":0.2424009896846366,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2004141433","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.006031716,0.00003667343,0.9861154,0.0000030047138,0.00021223216,0.00057807274,0.000005493192,0.0010993488,0.0059180385],"genre_scores_gemma":[0.6833671,0.0000066590874,0.31602767,0.000057544,0.00016997932,0.00014092612,0.0000059424483,0.00003984564,0.00018436892],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994343,0.0000065504973,0.00012657272,0.000119966746,0.00006757313,0.00024501525],"domain_scores_gemma":[0.99962604,0.00013979906,0.000009268433,0.00013305814,0.00002229763,0.00006951113],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00033484725,0.000112222646,0.000106306856,0.00004814276,0.000036400776,0.000021508382,0.00008099396,0.000067431996,0.00003467221],"category_scores_gemma":[0.000007387148,0.000105852014,0.000039622202,0.000055976885,0.00000817909,0.00009632614,0.000011023903,0.000057653924,0.000007837097],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000009572656,0.000025300067,0.000023080662,0.00003945427,0.000030398433,0.0000037461361,0.00012862773,0.0007301952,0.029868713,0.00013285877,0.0021430145,0.96686506],"study_design_scores_gemma":[0.0005469868,0.00039490082,0.0009816414,0.00002003201,0.000014667048,0.0000072448233,0.00016502952,0.4236698,0.56780607,0.00032329807,0.005750413,0.00031994152],"about_ca_topic_score_codex":0.0000078205885,"about_ca_topic_score_gemma":0.000023704519,"teacher_disagreement_score":0.9665451,"about_ca_system_score_codex":0.000072541574,"about_ca_system_score_gemma":0.0000018899397,"threshold_uncertainty_score":0.43165198},"labels":[],"label_agreement":null},{"id":"W2004853491","doi":"10.1109/iscas.2007.377864","title":"A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Computer science; Physical design; Schematic; Integrated circuit layout; Electronic circuit; Topology optimization; Electronic engineering; Analogue electronics; Integrated circuit design; Circuit extraction; Mixed-signal integrated circuit; Circuit design; Integrated circuit; Engineering; Embedded system; Equivalent circuit; Electrical engineering","score_opus":0.014088080614889885,"score_gpt":0.23145113838060938,"score_spread":0.2173630577657195,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2004853491","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004742432,0.000018182589,0.9800936,0.0000039677984,0.00011167889,0.00020658535,0.0000038477856,0.0007800981,0.014039604],"genre_scores_gemma":[0.8372928,0.00003218499,0.16234435,0.000025937843,0.00009203535,0.000015291564,0.000030898267,0.00001990909,0.00014662817],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995783,0.0000024140281,0.00012194621,0.00007574337,0.00006064395,0.00016092818],"domain_scores_gemma":[0.99981034,0.00001945176,0.000014034745,0.00007781539,0.000040283838,0.000038075363],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012235636,0.00007573938,0.00007967874,0.00009266169,0.00004227107,0.0000151194445,0.000049884224,0.0000640617,0.000038459708],"category_scores_gemma":[0.00000281958,0.00007481035,0.000028492042,0.00011049225,0.000007515703,0.00015310285,0.0000034431457,0.000048725007,0.0000066657035],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000002414135,0.000019549216,0.0006865156,0.00004489107,0.000026133073,9.865487e-7,0.00011617928,0.30239376,0.0033037867,0.00010127272,0.002572795,0.6907317],"study_design_scores_gemma":[0.00013224994,0.000047377624,0.0008588922,0.000008934512,0.0000067569285,0.000004111805,0.00001701913,0.9818641,0.016164284,0.000013961057,0.00077840744,0.00010393828],"about_ca_topic_score_codex":0.0000036023603,"about_ca_topic_score_gemma":0.000003074937,"teacher_disagreement_score":0.83255035,"about_ca_system_score_codex":0.000054468896,"about_ca_system_score_gemma":0.0000037685695,"threshold_uncertainty_score":0.30506775},"labels":[],"label_agreement":null},{"id":"W2004889232","doi":"10.1016/s0167-8396(02)00147-4","title":"Adjusting control points to achieve continuity","year":2002,"lang":"en","type":"article","venue":"Computer Aided Geometric Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Mathematics; Control (management); Algebra over a field; Pure mathematics; Calculus (dental); Computer science; Artificial intelligence","score_opus":0.025877979061212152,"score_gpt":0.20456243658526488,"score_spread":0.17868445752405274,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2004889232","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.002328176,0.00059096393,0.9914223,0.00008152505,0.00050071225,0.0006688589,0.000008679335,0.001778168,0.0026206092],"genre_scores_gemma":[0.86187476,0.000039181083,0.1368548,0.00059131964,0.0003411951,0.00005732944,0.0000019372749,0.000060240258,0.00017925215],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982351,0.000106091335,0.00041661315,0.00036031377,0.00028355114,0.00059830066],"domain_scores_gemma":[0.9986221,0.0005371201,0.00004906473,0.00042106336,0.0001018393,0.00026878636],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00057435594,0.00031347392,0.00043836358,0.0010892247,0.000085424086,0.00012722169,0.00045491676,0.00014310164,0.00017551868],"category_scores_gemma":[0.00013420645,0.00032306835,0.00011271862,0.0021327818,0.000021953432,0.00019051718,0.00006854864,0.00027350715,0.0006914604],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019990703,0.000084319225,0.00027290173,0.000055883553,0.00011313101,0.000073076466,0.00027959654,0.030587113,0.0016415832,0.000117377276,0.15806834,0.8086867],"study_design_scores_gemma":[0.0020803215,0.0011111341,0.0043456918,0.00012613801,0.000079776335,0.000078187586,0.000010679918,0.96962655,0.008977148,0.0008793402,0.011419479,0.0012655662],"about_ca_topic_score_codex":0.000005027645,"about_ca_topic_score_gemma":3.2881923e-7,"teacher_disagreement_score":0.9390394,"about_ca_system_score_codex":0.00010996447,"about_ca_system_score_gemma":0.0000056116296,"threshold_uncertainty_score":0.99992216},"labels":[],"label_agreement":null},{"id":"W2005275470","doi":"10.1109/fpl.2009.5272519","title":"An analytical model relating FPGA architecture and place and route runtime","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Simulated annealing; Router; Architecture; Computer science; Bounding overwatch; Parallel computing; Computer architecture; Function (biology); Embedded system; Algorithm; Artificial intelligence; Computer network","score_opus":0.008682102570983872,"score_gpt":0.22696931461758227,"score_spread":0.2182872120465984,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2005275470","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.44022948,0.00023228668,0.5299146,0.00017964271,0.000008898439,0.00012409477,0.000003541532,0.0011232143,0.028184203],"genre_scores_gemma":[0.95669335,0.00002083002,0.042869505,0.00010734542,0.000023428147,0.0000013306945,0.000002113199,0.000012248281,0.0002698293],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995488,0.000007816091,0.00010033474,0.00013490752,0.00006037145,0.00014775369],"domain_scores_gemma":[0.9997601,0.000018300107,0.0000067354026,0.00011839484,0.000006971359,0.00008948888],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007909464,0.000107213295,0.00011567545,0.000055630553,0.000037212798,0.00004522268,0.000045704583,0.0000839776,0.000008330546],"category_scores_gemma":[0.000006744918,0.000092251496,0.00001406398,0.00005415126,0.000017411909,0.00011652584,0.000009360118,0.00015871246,0.0000011502169],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004284808,0.000082010454,0.002408551,0.00010483958,0.000084337815,0.00004377278,0.0025138692,0.4571943,0.06556035,0.02377146,0.0048186663,0.443375],"study_design_scores_gemma":[0.000098194,0.00006143969,0.0009193368,0.000010908315,0.000010687368,0.00001776129,0.0000112300095,0.99354243,0.0013435162,0.003774467,0.00007388626,0.0001361535],"about_ca_topic_score_codex":0.000004361379,"about_ca_topic_score_gemma":0.0000038235407,"teacher_disagreement_score":0.5363481,"about_ca_system_score_codex":0.000010430605,"about_ca_system_score_gemma":0.000003483358,"threshold_uncertainty_score":0.3761907},"labels":[],"label_agreement":null},{"id":"W2005283161","doi":"10.1109/pads.2012.28","title":"Offline Road Network Partitioning in Distributed Transportation Simulation","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Graph partition; Graph; Flow network; Distributed computing; Graph theory; Space partitioning; Intelligent transportation system; Theoretical computer science; Algorithm; Mathematical optimization; Engineering","score_opus":0.014067868415996368,"score_gpt":0.23591936161437835,"score_spread":0.221851493198382,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2005283161","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17791842,0.00016051711,0.8197385,0.0000102380645,0.00008944209,0.00010445166,0.0000072823677,0.0005799703,0.0013911459],"genre_scores_gemma":[0.997342,0.000011982323,0.0022653344,0.0000145658905,0.000118922246,0.000015546288,0.0002078672,0.000010221411,0.000013577447],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995814,0.000007953696,0.00014863441,0.00004186526,0.0000484091,0.00017173935],"domain_scores_gemma":[0.99987894,0.00001768974,0.000010161537,0.000052190455,0.000009685943,0.000031344283],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010588889,0.000057658457,0.00006569965,0.000026949769,0.00001630256,0.000007095252,0.000021444579,0.000049713104,0.000087573855],"category_scores_gemma":[0.000004162391,0.000058809495,0.000016891025,0.00015541793,0.0000038751296,0.00021880012,8.2147307e-7,0.000055845376,0.000011298607],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000022761797,0.000012720779,0.036530107,0.000009415235,0.0000036531965,4.5161923e-7,0.00010478954,0.9559363,0.00041714706,0.0007288696,0.00052154914,0.0057326783],"study_design_scores_gemma":[0.00015399884,0.000009876036,0.3235552,0.00002559736,0.0000070672527,2.4744216e-7,0.00001712136,0.67044747,0.0027545623,0.000492553,0.0023903572,0.00014594285],"about_ca_topic_score_codex":0.00001674435,"about_ca_topic_score_gemma":0.000043877553,"teacher_disagreement_score":0.81942356,"about_ca_system_score_codex":0.000026926242,"about_ca_system_score_gemma":0.00000142934,"threshold_uncertainty_score":0.23981817},"labels":[],"label_agreement":null},{"id":"W2005602803","doi":"10.1145/2617593","title":"VTR 7.0","year":2014,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":362,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of British Columbia; University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; Texas Instruments; Semiconductor Research Corporation","keywords":"Computer science; Netlist; Adder; Verilog; Design flow; Computer architecture; Static timing analysis; Field-programmable gate array; Compiler; Routing (electronic design automation); Embedded system; Electronic design automation; Electronic circuit; Architecture; Operating system","score_opus":0.01091939259929031,"score_gpt":0.2032694107926043,"score_spread":0.192350018193314,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2005602803","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.054217983,0.0018929511,0.8906686,0.0006301847,0.0010503734,0.0005089177,0.000017577742,0.0067040036,0.04430946],"genre_scores_gemma":[0.9980326,0.00029036554,0.0006097318,0.000027641656,0.000021175298,0.00013771553,0.0000012829142,0.000025618976,0.0008538351],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99931556,0.000024657667,0.00019959235,0.00018285251,0.000057262507,0.00022009337],"domain_scores_gemma":[0.99935627,0.00007394087,0.000020383595,0.00047938884,0.000023049673,0.000046957546],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017270782,0.0001493441,0.00022041684,0.00045365075,0.00013225939,0.000029656056,0.00020304047,0.0003315021,0.00005000022],"category_scores_gemma":[0.000014990225,0.00014260989,0.000033082422,0.0002907206,0.000070264396,0.00007400882,0.0000010792435,0.00031031857,0.00008060407],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014392563,0.000068749665,0.00028204074,0.0003120829,0.00019833712,0.000008479079,0.000110543006,0.004666308,0.02856763,0.027115108,0.0023588089,0.93629754],"study_design_scores_gemma":[0.0019154508,0.0013434438,0.00033373138,0.00070178794,0.00016801606,0.0009789389,0.0011623488,0.10884487,0.47986227,0.060388234,0.34211007,0.002190828],"about_ca_topic_score_codex":0.000011467597,"about_ca_topic_score_gemma":0.000004772993,"teacher_disagreement_score":0.94381464,"about_ca_system_score_codex":0.000021684988,"about_ca_system_score_gemma":0.000004287764,"threshold_uncertainty_score":0.58154625},"labels":[],"label_agreement":null},{"id":"W2007109372","doi":"10.1109/tvlsi.2009.2031318","title":"Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Sizing; Computer architecture; Embedded system; Transistor; Circuit design; Design space exploration; Architecture; Engineering; Electrical engineering","score_opus":0.03155522727447946,"score_gpt":0.2092796363849271,"score_spread":0.17772440911044765,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2007109372","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.097950436,0.00040411155,0.8990822,0.000075412725,0.0002226967,0.0006392351,0.000038996757,0.0013881703,0.00019875397],"genre_scores_gemma":[0.9952318,0.0002947977,0.0040753507,0.00004218201,0.000031209383,0.00023600606,0.0000065392614,0.000044390803,0.000037721948],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99860346,0.00012868406,0.0003956259,0.00032998426,0.00022117366,0.00032107727],"domain_scores_gemma":[0.9994865,0.000098131306,0.000037193982,0.00020699341,0.000047547856,0.00012363563],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00027946092,0.00033232357,0.00036059727,0.00044059867,0.00013133668,0.00010929157,0.00008492968,0.00017548296,0.0000052323517],"category_scores_gemma":[0.0000029705486,0.00028272142,0.00005364551,0.00036540424,0.000040152976,0.00052712153,2.994316e-7,0.00042591072,0.0000024871717],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0006634822,0.0005640324,0.00003437138,0.00035134933,0.00021790226,0.00015119772,0.018482668,0.7812236,0.09679043,0.00017753588,0.000536475,0.100806944],"study_design_scores_gemma":[0.001983937,0.0011568886,0.000421824,0.0013410759,0.000121781726,0.0005278449,0.002396882,0.8822933,0.10785616,0.00006229582,0.00087429915,0.0009637393],"about_ca_topic_score_codex":0.00004401484,"about_ca_topic_score_gemma":0.00019011229,"teacher_disagreement_score":0.89728135,"about_ca_system_score_codex":0.00013456674,"about_ca_system_score_gemma":0.00001968226,"threshold_uncertainty_score":0.9999625},"labels":[],"label_agreement":null},{"id":"W2007585924","doi":"10.1109/iscas.2010.5537954","title":"Rapid design space exploration for multi parametric optimization of VLSI designs","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Design space exploration; Computer science; Maximization; Minification; Parametric statistics; Multi-objective optimization; Very-large-scale integration; Process (computing); Pareto principle; Acceleration; Mathematical optimization; Embedded system; Machine learning; Mathematics","score_opus":0.10578131260809866,"score_gpt":0.27499697947881796,"score_spread":0.16921566687071932,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2007585924","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00062655756,0.00006027807,0.9974333,0.000016944063,0.00014364335,0.0006651261,0.0000032321104,0.00056890864,0.00048200221],"genre_scores_gemma":[0.3360006,0.00007978994,0.6636796,0.000006527693,0.000026299484,0.000106254585,0.000009201281,0.000025122838,0.00006659],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999453,0.000018586361,0.00019636443,0.000111764944,0.00007919407,0.0001410789],"domain_scores_gemma":[0.99951947,0.0001314304,0.000038302216,0.0001727477,0.000096686905,0.000041354986],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002667514,0.00011126845,0.00013731564,0.00021383144,0.000029743129,0.000021443991,0.00009481766,0.00012819788,0.000073408344],"category_scores_gemma":[0.00012386421,0.0001057486,0.00004735812,0.00029847395,0.000017753377,0.00027678255,0.000005942155,0.00008393782,0.000004350372],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020115825,0.00007180941,0.000039011386,0.000083655155,0.0000301718,4.0062906e-7,0.00019501749,0.69325155,0.26707283,0.0021172762,0.0045519397,0.032566234],"study_design_scores_gemma":[0.0001672662,0.000066608656,0.000009549864,0.000003674793,0.000008763793,5.61667e-7,0.000016485295,0.6058491,0.3933897,0.0001877349,0.00021304961,0.00008753117],"about_ca_topic_score_codex":0.000004302695,"about_ca_topic_score_gemma":0.0000025245936,"teacher_disagreement_score":0.33537403,"about_ca_system_score_codex":0.0000135439805,"about_ca_system_score_gemma":0.000012105517,"threshold_uncertainty_score":0.43123028},"labels":[],"label_agreement":null},{"id":"W2007959382","doi":"10.1145/2331147.2331152","title":"Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation","year":2012,"lang":"en","type":"article","venue":"ACM Transactions on Embedded Computing Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University; University of British Columbia","funders":"","keywords":"Computer science; Benchmark (surveying); Electronic circuit; Dataflow; Field-programmable gate array; Generator (circuit theory); Computer architecture; Parallel computing; Embedded system; Computer engineering; Computer hardware; Power (physics); Electrical engineering; Engineering","score_opus":0.050136347844918536,"score_gpt":0.28097832139972867,"score_spread":0.23084197355481012,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2007959382","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03141987,0.0004456149,0.96340597,0.00003108792,0.0019021918,0.0011294341,0.000022618937,0.00082480075,0.0008184163],"genre_scores_gemma":[0.9861425,0.000008518845,0.012405384,0.000035913126,0.00096959004,0.00027979916,0.0000629434,0.000057083067,0.000038236252],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99847215,0.00014374714,0.00038296334,0.00023955602,0.0003381228,0.00042347616],"domain_scores_gemma":[0.99898297,0.00024832287,0.000053724947,0.0004973193,0.00009714683,0.000120527446],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0009237059,0.00022964853,0.00023662052,0.00021674034,0.00025430627,0.00007790911,0.00022055305,0.00019232127,0.000023241173],"category_scores_gemma":[0.000043382966,0.00023236079,0.00013089605,0.00021382139,0.000020467063,0.00013557235,0.0000029468179,0.00030181397,0.000014928382],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001185066,0.000107848995,0.00002042102,0.00020077192,0.00014393996,3.9266223e-7,0.002481972,0.64095074,0.02821871,0.0006200395,0.0014524566,0.32579085],"study_design_scores_gemma":[0.0005833872,0.00013149828,0.000074824,0.00011935664,0.00011729036,0.00004782069,0.00014488088,0.97788066,0.017584007,0.000796886,0.0020824603,0.00043693726],"about_ca_topic_score_codex":0.000007647656,"about_ca_topic_score_gemma":0.0000020696586,"teacher_disagreement_score":0.95472264,"about_ca_system_score_codex":0.00019262491,"about_ca_system_score_gemma":0.000024002358,"threshold_uncertainty_score":0.9475398},"labels":[],"label_agreement":null},{"id":"W2008705031","doi":"10.1109/cec.2009.4983014","title":"Discrete and continuous particle swarm optimization for FPGA placement","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Field-programmable gate array; Particle swarm optimization; Simulated annealing; Computer science; Multi-swarm optimization; Domain (mathematical analysis); Placement; Algorithm; Mathematical optimization; Swarm behaviour; Parallel computing; Embedded system; Mathematics; Artificial intelligence; Physical design","score_opus":0.008001580646048728,"score_gpt":0.22099257699464994,"score_spread":0.21299099634860122,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2008705031","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019043278,0.00012803864,0.9767858,0.00012722063,0.000024316654,0.00026309505,0.0000026264463,0.0005183336,0.003107322],"genre_scores_gemma":[0.9586086,0.000054918477,0.04094234,0.000094296935,0.000022788756,0.000025392259,0.000005201829,0.000008345114,0.00023809834],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996992,0.0000028832044,0.00008466224,0.00006750805,0.00003396176,0.00011181593],"domain_scores_gemma":[0.99987453,0.000012136763,0.0000067748438,0.00006099053,0.0000117393165,0.000033812754],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000051929615,0.000058876147,0.00006786115,0.000013903322,0.000024018394,0.000026074144,0.000025487914,0.000027150014,0.000020226198],"category_scores_gemma":[0.0000052313085,0.0000518425,0.000014149424,0.000029210994,0.000005752754,0.00007033264,0.0000035089788,0.000019528756,7.139506e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010496092,0.00011649688,0.00037706114,0.00013667581,0.00008777748,0.000005725885,0.0010485363,0.573157,0.062323272,0.018566445,0.041812878,0.30226317],"study_design_scores_gemma":[0.0003879829,0.00020529452,0.000094942276,0.000008967258,0.00001168301,0.0000018012371,0.000046058434,0.80836356,0.1888268,0.00051956356,0.0013946684,0.0001386808],"about_ca_topic_score_codex":0.0000010903095,"about_ca_topic_score_gemma":6.1323755e-7,"teacher_disagreement_score":0.93956536,"about_ca_system_score_codex":0.000010693655,"about_ca_system_score_gemma":0.0000011376666,"threshold_uncertainty_score":0.21140757},"labels":[],"label_agreement":null},{"id":"W2010480731","doi":"10.1002/cta.551","title":"Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits","year":2008,"lang":"en","type":"article","venue":"International Journal of Circuit Theory and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Transitive closure; Analogue electronics; Representation (politics); Algorithm; Transitive relation; Topology (electrical circuits); Computer science; Graph; Mathematics; Analog computer; Set (abstract data type); Electronic circuit; Theoretical computer science; Discrete mathematics; Combinatorics; Engineering","score_opus":0.02705385555040781,"score_gpt":0.28247698988882064,"score_spread":0.25542313433841285,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2010480731","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.020183912,0.00037667953,0.978326,0.00001501848,0.0001419256,0.00030034778,0.00014597077,0.00006183784,0.00044828304],"genre_scores_gemma":[0.9978196,0.0003992929,0.0012710871,0.000059261973,0.00029171008,0.000063686086,0.000048801947,0.000020769201,0.000025811767],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.99913114,0.000051169125,0.0003826322,0.000119043645,0.00020546347,0.00011053462],"domain_scores_gemma":[0.99903834,0.00020249159,0.00013836841,0.00008726608,0.00046650937,0.00006704675],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00035316433,0.00012047851,0.00017006029,0.0002768614,0.00010714377,0.000031766853,0.00019829084,0.00007191339,0.000018886509],"category_scores_gemma":[0.000023181256,0.00011688039,0.00011816901,0.00018240644,0.00007516487,0.00021893429,0.0000070532865,0.00015426305,8.7581964e-7],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017676098,0.0003541811,0.0010579274,0.00007854372,0.0019250182,0.00007090828,0.002914184,0.0063842186,0.06503218,0.36783245,0.0012247615,0.5529489],"study_design_scores_gemma":[0.004917823,0.00058896403,0.003877041,0.00049577706,0.000602947,0.0042148735,0.004018107,0.019793889,0.11594408,0.8319661,0.0123207895,0.0012596282],"about_ca_topic_score_codex":0.000002406393,"about_ca_topic_score_gemma":5.773086e-7,"teacher_disagreement_score":0.9776357,"about_ca_system_score_codex":0.0000786862,"about_ca_system_score_gemma":0.00003926856,"threshold_uncertainty_score":0.47662437},"labels":[],"label_agreement":null},{"id":"W2011011346","doi":"10.5430/air.v1n2p38","title":"A enhanced algorithm for floorplan design using evolutionary technique","year":2012,"lang":"en","type":"article","venue":"Artificial Intelligence Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Floorplan; Placement; Very-large-scale integration; Computer science; Genetic algorithm; Reliability (semiconductor); Physical design; Bounding overwatch; Domain (mathematical analysis); Chip; Scale (ratio); Mathematical optimization; Integrated circuit layout; Reliability engineering; Circuit design; Integrated circuit; Engineering; Mathematics; Embedded system; Artificial intelligence; Machine learning","score_opus":0.2746751030610162,"score_gpt":0.4215272742641248,"score_spread":0.14685217120310856,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2011011346","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010861399,0.00057623116,0.99578196,0.000018674393,0.00020582772,0.0013713441,0.000015223766,0.00047150653,0.00047310613],"genre_scores_gemma":[0.63231176,0.00008271632,0.36637214,0.0000062319946,0.0004440992,0.0006823814,0.0000069269518,0.000048943406,0.000044771954],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9979576,0.00015639771,0.00032912122,0.00021439942,0.0003680406,0.0009744416],"domain_scores_gemma":[0.9988389,0.00042896008,0.000019614386,0.00027672603,0.00025504557,0.00018075494],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.002326421,0.0001645648,0.00017410774,0.00036791095,0.00026710785,0.000055024848,0.0003011462,0.00019373286,0.00009713856],"category_scores_gemma":[0.00014775067,0.00016967577,0.00007473939,0.0006151458,0.00014537456,0.00031737186,0.000053687614,0.00037921395,0.00012824788],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017736147,0.000065137785,0.000003714638,0.000037681883,0.000020364305,0.0000020320733,0.00031045094,0.0019415698,0.57034147,0.003264968,0.0011047634,0.4228901],"study_design_scores_gemma":[0.000007179805,0.00007240241,0.0000017303533,0.000029519713,0.00000382083,0.000008341556,0.00015598867,0.3154464,0.66514164,0.01845894,0.0005295595,0.00014448303],"about_ca_topic_score_codex":0.000049132243,"about_ca_topic_score_gemma":0.0000022310342,"teacher_disagreement_score":0.63122565,"about_ca_system_score_codex":0.00033175712,"about_ca_system_score_gemma":0.00008200478,"threshold_uncertainty_score":0.6919177},"labels":[],"label_agreement":null},{"id":"W2011407463","doi":"10.1162/1063656041774947","title":"Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering","year":2004,"lang":"en","type":"article","venue":"Evolutionary Computation","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":54,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Memetic algorithm; Local search (optimization); Cluster analysis; Computer science; Very-large-scale integration; Algorithm; sort; Population; Genetic algorithm; Tabu search; Constructive; Evolutionary algorithm; Mathematical optimization; Mathematics; Artificial intelligence; Machine learning; Process (computing)","score_opus":0.050586100689397985,"score_gpt":0.28790428891801184,"score_spread":0.23731818822861386,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2011407463","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019203209,0.0005851784,0.9946311,0.00003358817,0.0003490764,0.0015806291,0.00003472888,0.0008302969,0.000035096105],"genre_scores_gemma":[0.4869851,0.000015916585,0.5125206,0.000016998732,0.00011809701,0.00023933688,0.000047630427,0.00004267523,0.000013628125],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99864376,0.000081250866,0.00030724326,0.00032331367,0.00025724157,0.00038720146],"domain_scores_gemma":[0.9993624,0.00019333255,0.000034468576,0.00013541637,0.00017443552,0.000099918616],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00026255942,0.00024727624,0.00021617049,0.00023200458,0.00018747184,0.000036729678,0.00014656186,0.00014825012,0.0000059135273],"category_scores_gemma":[0.000020924203,0.0002784049,0.00009656926,0.00027621715,0.00007400846,0.00020819872,0.000039125167,0.0001782821,0.00004046664],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013698406,0.000049754388,0.00000891306,0.000072447496,0.000037519196,0.000007278313,0.00022800686,0.8079615,0.0019073802,0.000028844186,0.00019912743,0.18948548],"study_design_scores_gemma":[0.0011753581,0.00029182684,0.008049383,0.00006465291,0.000025939155,0.000052917723,0.00005235766,0.9815669,0.006271571,0.0020760307,0.000054743057,0.0003183415],"about_ca_topic_score_codex":0.000030606665,"about_ca_topic_score_gemma":0.000004070431,"teacher_disagreement_score":0.48506477,"about_ca_system_score_codex":0.0006367581,"about_ca_system_score_gemma":0.000062940686,"threshold_uncertainty_score":0.9999668},"labels":[],"label_agreement":null},{"id":"W2011527102","doi":"10.1145/503048.503061","title":"EVE","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Field-programmable gate array; Event (particle physics); Sequential logic; Place and route; Electronic circuit; Path (computing); Virtex; Critical path method; Digital electronics; Set (abstract data type); State (computer science); Computer architecture; Design flow; High-level synthesis; Parallel computing; Computer engineering; Embedded system; Logic gate; Algorithm; Operating system; Electrical engineering; Programming language","score_opus":0.013334471921745757,"score_gpt":0.15506935054961363,"score_spread":0.14173487862786788,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2011527102","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0038062884,0.00023775038,0.042026505,0.000029470979,0.00003411282,0.000026258756,1.9135383e-7,0.0017587582,0.95208067],"genre_scores_gemma":[0.99513614,0.000051047107,0.0017459636,0.000056975376,0.000021844471,0.0000035129274,1.3768003e-7,0.000006420827,0.0029779503],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99987435,9.625369e-7,0.000028320106,0.000022699778,0.000021380323,0.00005226296],"domain_scores_gemma":[0.99992615,0.0000033529534,9.1747677e-7,0.00005332062,0.0000024731291,0.000013797132],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000009214929,0.000025292818,0.000023640208,0.000014174228,0.0000052809673,0.0000047343424,0.000027729344,0.000017155024,0.0016554748],"category_scores_gemma":[0.0000010194966,0.000022018892,0.000009736396,0.0000291211,0.000002548059,0.000026860464,0.0000022039885,0.000023073111,0.00042223433],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[1.1714713e-7,0.000009985374,0.0002670252,0.000012059275,0.000009893506,0.000006197452,0.00011003958,0.000074355245,0.0145246,0.004312828,0.89354175,0.087131165],"study_design_scores_gemma":[0.00020766065,0.000037843,0.0009908497,0.000013869369,0.000007550419,0.000021124291,0.000021251233,0.35443854,0.21906425,0.0037341097,0.4209714,0.0004915534],"about_ca_topic_score_codex":6.220411e-7,"about_ca_topic_score_gemma":2.0767074e-7,"teacher_disagreement_score":0.99132985,"about_ca_system_score_codex":0.000004770771,"about_ca_system_score_gemma":1.0407919e-7,"threshold_uncertainty_score":0.99925715},"labels":[],"label_agreement":null},{"id":"W2014316444","doi":"10.1145/2068716.2068718","title":"VPR 5.0","year":2011,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":70,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Toronto","funders":"","keywords":"Computer science; Logic block; Computer architecture; Routing (electronic design automation); Field-programmable gate array; Robustness (evolution); Granularity; Architecture; Block (permutation group theory); Software; Key (lock); Embedded system; Computer engineering; Distributed computing; Operating system","score_opus":0.028158768054671157,"score_gpt":0.20665786393279184,"score_spread":0.17849909587812068,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2014316444","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13573311,0.006269759,0.6631701,0.00029684015,0.0020716987,0.0012344965,0.00005399675,0.013551803,0.17761818],"genre_scores_gemma":[0.9974106,0.0004921768,0.0010802154,0.000015166102,0.000010080916,0.00016422494,8.749693e-7,0.000025846786,0.000800812],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99933356,0.000015439047,0.00020420618,0.0001756237,0.000048974514,0.00022218477],"domain_scores_gemma":[0.9994226,0.000028429864,0.000020618549,0.0004575275,0.000023664847,0.000047133417],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010955755,0.00015034381,0.00020207599,0.0004879705,0.0001122372,0.000015401332,0.00021843919,0.00033586158,0.00015832871],"category_scores_gemma":[0.000006109497,0.00014353228,0.00003377945,0.00030760266,0.00007919647,0.00009357664,0.0000011803713,0.00030436018,0.00008585497],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006588856,0.00028260282,0.0011579593,0.0005838305,0.00069029466,0.00010138966,0.0012092702,0.00072722073,0.04099264,0.042545103,0.0033281639,0.90831566],"study_design_scores_gemma":[0.0013358857,0.0011926802,0.00069013546,0.00052410155,0.00017584834,0.0012478274,0.0027368495,0.009417679,0.8811238,0.054278806,0.045490738,0.0017856404],"about_ca_topic_score_codex":0.000028491268,"about_ca_topic_score_gemma":0.000005927901,"teacher_disagreement_score":0.90653,"about_ca_system_score_codex":0.000021173577,"about_ca_system_score_gemma":0.000005796888,"threshold_uncertainty_score":0.58530766},"labels":[],"label_agreement":null},{"id":"W2015033143","doi":"10.1145/1118299.1118499","title":"TAPHS","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":45,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Queen's University","funders":"","keywords":"Floorplan; Physical design; Computer science; Thermal; Chip; Electronic engineering; Integrated circuit design; Voltage; Power (physics); Circuit design; Reliability engineering; Embedded system; Engineering; Electrical engineering","score_opus":0.002018548958097644,"score_gpt":0.14380518859818242,"score_spread":0.14178663964008478,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2015033143","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011839523,0.00010484454,0.16940238,0.000012030121,0.00004176049,0.000028712857,4.5344572e-7,0.0019116377,0.8166587],"genre_scores_gemma":[0.9931168,0.000004846513,0.005014264,0.000017277527,0.000041173094,0.0000036581578,0.0000011728449,0.000006818388,0.0017939808],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99986356,8.683257e-7,0.000034961486,0.000023649714,0.000021881207,0.00005507208],"domain_scores_gemma":[0.99993813,0.0000028396057,0.0000011630167,0.0000477829,0.000002895051,0.000007193058],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000012570693,0.000027032305,0.000024625038,0.000016565678,0.000005753742,0.000006155723,0.000025365125,0.000017891665,0.00015395501],"category_scores_gemma":[3.3638287e-7,0.000023679591,0.000010669071,0.00003115316,0.0000031038776,0.00002416265,0.000002099123,0.00001901822,0.00007903572],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[4.362283e-7,0.0000142517065,0.0011273867,0.000018048328,0.0000064589444,0.000008456111,0.0000138925925,0.0009954653,0.11519315,0.06499222,0.7902844,0.027345827],"study_design_scores_gemma":[0.00012180205,0.000018679928,0.004299654,0.000006134595,0.000004192341,0.000008218126,0.000007895363,0.016695961,0.69452006,0.027153106,0.25687793,0.00028638463],"about_ca_topic_score_codex":0.000017882354,"about_ca_topic_score_gemma":0.0000044215312,"teacher_disagreement_score":0.9812773,"about_ca_system_score_codex":0.0000050842796,"about_ca_system_score_gemma":5.543983e-7,"threshold_uncertainty_score":0.16856994},"labels":[],"label_agreement":null},{"id":"W2015243450","doi":"10.1145/1572471.1572480","title":"A pre-placement net length estimation technique for mixed-size circuits","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Net (polyhedron); A priori and a posteriori; Cluster analysis; Computer science; Length measurement; Electronic circuit; Estimation; Algorithm; Mathematics; Engineering; Artificial intelligence; Geometry","score_opus":0.010022441308021367,"score_gpt":0.24119067596860072,"score_spread":0.23116823466057934,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2015243450","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0017045478,0.000056945788,0.9834703,0.00006772795,0.00006253314,0.0011299492,0.0000066633147,0.0016325269,0.011868787],"genre_scores_gemma":[0.9022205,0.000023290318,0.0966707,0.00011071549,0.00004522046,0.00043026643,0.000014164025,0.000022273243,0.00046286095],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99936056,0.000008439008,0.00019073165,0.00013565719,0.00009256251,0.00021206021],"domain_scores_gemma":[0.99966466,0.000054365315,0.00001938163,0.00018517207,0.000028624614,0.000047796413],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017441864,0.00013898626,0.00013171736,0.00006065412,0.000037418245,0.000030817882,0.00010589586,0.00010563105,0.000053516003],"category_scores_gemma":[0.000031986205,0.00013291405,0.000049085796,0.00009009094,0.000006726176,0.00012974493,0.000005717214,0.000074520794,0.000008921879],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017584218,0.0001297718,0.000027490874,0.00020945746,0.00005034621,0.000003139368,0.00026617642,0.011037197,0.43549776,0.012905983,0.123959854,0.41589525],"study_design_scores_gemma":[0.00033338804,0.0003785631,0.0006076754,0.000052718187,0.000020837992,0.000010874518,0.000012736867,0.0910185,0.88995576,0.011047736,0.006207366,0.0003538646],"about_ca_topic_score_codex":0.000002749663,"about_ca_topic_score_gemma":0.0000016540916,"teacher_disagreement_score":0.900516,"about_ca_system_score_codex":0.000065393106,"about_ca_system_score_gemma":0.000008919468,"threshold_uncertainty_score":0.5420078},"labels":[],"label_agreement":null},{"id":"W2015590221","doi":"10.1145/611817.611841","title":"Design of FPGA interconnect for multilevel metalization","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Field-programmable gate array; Interconnection; Routing (electronic design automation); Computer science; Exploit; Topology (electrical circuits); Dimension (graph theory); Hierarchy; Embedded system; Scaling; Computer network; Electrical engineering; Engineering; Mathematics","score_opus":0.04161591048762313,"score_gpt":0.24606562240394603,"score_spread":0.20444971191632288,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2015590221","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0004157841,0.00009049108,0.995148,0.0000015434975,0.000057896043,0.00027099825,0.0000020077887,0.000271374,0.003741902],"genre_scores_gemma":[0.81112695,0.000019668241,0.1886,0.00001138261,0.000005249612,0.000047436093,0.0000022141458,0.000016345346,0.00017072927],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996925,0.00001475596,0.00012389812,0.00005636025,0.000032879558,0.00007960402],"domain_scores_gemma":[0.9997939,0.00006505983,0.000011996652,0.00008176968,0.00003207367,0.000015207819],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013998317,0.00006136134,0.000094591596,0.000052314943,0.0000089615605,0.0000050018143,0.00004389319,0.000041354288,0.00007632377],"category_scores_gemma":[0.000051815794,0.000054817378,0.000031126114,0.000047495247,0.000006594352,0.00006137003,0.0000021239227,0.000018013048,0.0000027024953],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019301617,0.00008457867,0.000049480983,0.00036372928,0.0001913598,9.629676e-7,0.00069970416,0.04684823,0.77280265,0.07909931,0.013487904,0.08635281],"study_design_scores_gemma":[0.00013510277,0.0000411754,0.0000048726483,0.000008257904,0.000009825265,0.000001047504,0.00001581243,0.13184017,0.8637488,0.0026725838,0.0014484755,0.00007390571],"about_ca_topic_score_codex":0.0000015396699,"about_ca_topic_score_gemma":4.4939938e-7,"teacher_disagreement_score":0.8107112,"about_ca_system_score_codex":0.000011065688,"about_ca_system_score_gemma":0.0000042911743,"threshold_uncertainty_score":0.22353879},"labels":[],"label_agreement":null},{"id":"W2018790177","doi":"10.1109/iscas.2012.6271714","title":"Fast parasitic-aware synthesis methodology for high-performance analog circuits","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Parasitic extraction; Computer science; CMOS; Analogue electronics; Electronic engineering; Electronic circuit; Sizing; Circuit extraction; Computer architecture; Equivalent circuit; Engineering; Electrical engineering","score_opus":0.059715030550403954,"score_gpt":0.2790983057995376,"score_spread":0.21938327524913365,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2018790177","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.111081235,0.00016399843,0.88157797,0.000024142637,0.00028375437,0.00022005248,0.00001762513,0.0009786903,0.00565252],"genre_scores_gemma":[0.9632242,0.000058465856,0.036052514,0.00006850016,0.00018364027,0.00021392872,0.0000066424504,0.00003631428,0.00015582582],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99921894,0.00003561964,0.00016629072,0.00010701839,0.000061779065,0.00041037274],"domain_scores_gemma":[0.99929655,0.00038668604,0.000017074224,0.00019023655,0.000028228336,0.00008120338],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00037809063,0.00014050232,0.00022206121,0.000090384325,0.00004840067,0.00001105866,0.00012871665,0.00012849135,0.0001613174],"category_scores_gemma":[0.000050831884,0.00012632812,0.000044559707,0.00009444317,0.00002129611,0.00019866129,0.000008309087,0.00007481341,0.000052283664],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014299712,0.0001034564,0.013391055,0.0006795269,0.0002732657,0.0000026570706,0.0004888665,0.0009795035,0.13115272,0.019812139,0.018134443,0.81496805],"study_design_scores_gemma":[0.00011086344,0.00006173045,0.010696332,0.000023073451,0.000055281726,0.000015829959,0.000047015288,0.0048092324,0.9818816,0.00045862567,0.0015053817,0.0003350176],"about_ca_topic_score_codex":0.000008294483,"about_ca_topic_score_gemma":0.000002118252,"teacher_disagreement_score":0.85214293,"about_ca_system_score_codex":0.00003568155,"about_ca_system_score_gemma":0.0000052398245,"threshold_uncertainty_score":0.51515114},"labels":[],"label_agreement":null},{"id":"W2021403474","doi":"10.1109/vlsi.design.2010.20","title":"A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Gate array; Placement; Parallel computing; Reduction (mathematics); Simple (philosophy); Graph; Algorithm; Circuit design; Embedded system; Mathematics; Physical design; Theoretical computer science","score_opus":0.02033673776125592,"score_gpt":0.30052020923725076,"score_spread":0.2801834714759948,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2021403474","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004362932,0.000013847051,0.99112654,0.000037076337,0.00008278757,0.0019538696,0.000016788163,0.0012857759,0.0011203783],"genre_scores_gemma":[0.2515849,0.000005951794,0.7460303,0.0000984328,0.000028497992,0.0018339684,0.000018495472,0.000061810344,0.00033768406],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9988536,0.00003702789,0.0002798802,0.00028713726,0.00016950135,0.00037282368],"domain_scores_gemma":[0.9990343,0.00020318953,0.00004347375,0.00051376945,0.000082526036,0.00012274721],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00065739226,0.0002849305,0.00027066047,0.000258494,0.000065658605,0.00007601316,0.00019282961,0.00016014728,0.0001702396],"category_scores_gemma":[0.00002924872,0.00021890327,0.00010590394,0.0002633539,0.00004723207,0.00014740466,0.000018570045,0.0002592649,0.000002719768],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002736955,0.0002418934,0.00093287847,0.00041251938,0.00032211724,0.00000828403,0.00016001954,0.010803272,0.95827204,0.0020903796,0.013110523,0.013372401],"study_design_scores_gemma":[0.00063366257,0.00047393082,0.0001127775,0.000040779534,0.00007817029,0.0000059359104,0.000022375174,0.057125576,0.93016535,0.00041526614,0.010507163,0.00041899108],"about_ca_topic_score_codex":0.000028806766,"about_ca_topic_score_gemma":0.000076096825,"teacher_disagreement_score":0.24722195,"about_ca_system_score_codex":0.000055211658,"about_ca_system_score_gemma":0.000035944664,"threshold_uncertainty_score":0.89266163},"labels":[],"label_agreement":null},{"id":"W2022113200","doi":"10.1016/j.compeleceng.2013.02.011","title":"A new a priori net length estimation technique for integrated circuits using radial basis functions","year":2013,"lang":"en","type":"article","venue":"Computers & Electrical Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada; Alberta Innovates - Technology Futures; Compute Canada","keywords":"Radial basis function; A priori and a posteriori; Benchmark (surveying); Robustness (evolution); Electronic circuit; Computer science; Basis (linear algebra); Algorithm; Digital electronics; Basis function; Mathematics; Artificial intelligence; Artificial neural network; Engineering","score_opus":0.0105482127751254,"score_gpt":0.2050367680231496,"score_spread":0.1944885552480242,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2022113200","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003148702,0.00021660236,0.9930941,0.000023437951,0.00037054633,0.0010808996,0.000004101049,0.0020076102,0.000054015054],"genre_scores_gemma":[0.5226904,0.00001531327,0.47645715,0.000030202378,0.00031701382,0.00032602856,0.000030589657,0.00010392583,0.00002934343],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987988,0.00001248698,0.0003219556,0.00025151626,0.0001251105,0.0004901408],"domain_scores_gemma":[0.99935687,0.00014695441,0.000031829397,0.00019959846,0.00006830687,0.00019641801],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00009471883,0.00029074732,0.0003041214,0.00038792024,0.000073947085,0.00011719687,0.0001971381,0.00019776786,0.000019314257],"category_scores_gemma":[0.00006385389,0.00031492437,0.00012007998,0.00074335805,0.0000087087665,0.00030037723,0.00002006657,0.00032721378,0.000011916707],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000036759284,0.000022173142,0.0000118945845,0.000083335864,0.0000891648,0.0000027153503,0.00006989311,0.41323325,0.21954687,0.0004281171,0.012307337,0.35420156],"study_design_scores_gemma":[0.00024699222,0.00010264583,0.000076244745,0.00006683557,0.0000306187,0.000032597767,0.0000013516182,0.96747726,0.029544994,0.00019040254,0.0018898649,0.00034017986],"about_ca_topic_score_codex":0.00005555243,"about_ca_topic_score_gemma":4.5500437e-7,"teacher_disagreement_score":0.55424404,"about_ca_system_score_codex":0.00033716162,"about_ca_system_score_gemma":0.00005873868,"threshold_uncertainty_score":0.99993026},"labels":[],"label_agreement":null},{"id":"W2023428606","doi":"10.1145/2629579","title":"Timing-Driven Titan","year":2015,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":98,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; Texas Instruments","keywords":"Stratix; Field-programmable gate array; Computer science; Titan (rocket family); Benchmark (surveying); Parallel computing; Computer architecture; Architecture; Embedded system","score_opus":0.038747666946998424,"score_gpt":0.23994230075965653,"score_spread":0.20119463381265812,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2023428606","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.119919315,0.0074765296,0.7601476,0.0016023751,0.0029251492,0.0015075683,0.00009474461,0.01418588,0.092140846],"genre_scores_gemma":[0.99749327,0.00019747327,0.0010484844,0.000017725146,0.000019789624,0.00013246924,0.0000025878883,0.000027698923,0.0010605],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99929786,0.000019416717,0.00020334257,0.00018030884,0.00007732939,0.00022174019],"domain_scores_gemma":[0.9993794,0.000036813843,0.000022802802,0.00043076972,0.00004440894,0.00008581849],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013964085,0.0001532123,0.0002210113,0.0004554969,0.00008978477,0.00003189329,0.00021504534,0.0003340421,0.000031442625],"category_scores_gemma":[0.000015090729,0.00014814002,0.000030000987,0.00032150073,0.000069712936,0.00010241263,0.0000016469554,0.0003065861,0.000106347274],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000118603275,0.00041397344,0.0019370399,0.0008981314,0.0012295063,0.00021592497,0.001701554,0.056870673,0.048226573,0.033507377,0.04708743,0.8077932],"study_design_scores_gemma":[0.0045017917,0.0028700938,0.00018952866,0.0012210329,0.00036552997,0.002763259,0.008919503,0.18303546,0.3665639,0.05008023,0.37577295,0.0037167317],"about_ca_topic_score_codex":0.0000151035565,"about_ca_topic_score_gemma":0.0000072879357,"teacher_disagreement_score":0.87757397,"about_ca_system_score_codex":0.000054706743,"about_ca_system_score_gemma":0.000014528091,"threshold_uncertainty_score":0.6040975},"labels":[],"label_agreement":null},{"id":"W2023461533","doi":"10.1109/fpl.2014.6927481","title":"A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Scalability; Parallel computing; CUDA; Field-programmable gate array; Routing (electronic design automation); Critical path method; Placement; Simulated annealing; Design flow; Embedded system; Physical design; Algorithm; Circuit design","score_opus":0.06483010504486024,"score_gpt":0.3121401575995601,"score_spread":0.24731005255469984,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2023461533","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.092174456,0.00014625472,0.90470076,0.00007818093,0.00015978186,0.00055625377,0.000020816919,0.00069375633,0.0014697445],"genre_scores_gemma":[0.6095406,0.000032001026,0.3894793,0.00012357705,0.000109852794,0.00017634085,0.000014311154,0.00003642631,0.00048762775],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987237,0.00016861169,0.00030453212,0.00028701956,0.00010609995,0.00041006997],"domain_scores_gemma":[0.9989247,0.0006194972,0.000036869173,0.00027659064,0.000037429385,0.00010492151],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010358669,0.00022180928,0.00038230457,0.000079605605,0.00007374651,0.00004158804,0.00014602576,0.00016352462,0.000061559804],"category_scores_gemma":[0.00015868405,0.00018944396,0.000059499722,0.000048003956,0.000046716974,0.000052121704,0.000060320603,0.00012551807,0.0000036283448],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0007510153,0.00021437433,0.0018517668,0.0020956716,0.0005523048,0.0000034542672,0.0018800118,0.15407349,0.5847161,0.08707339,0.015095026,0.15169339],"study_design_scores_gemma":[0.00499633,0.000814792,0.0042956444,0.00007404056,0.00014489269,0.00002340678,0.00012230375,0.54568547,0.2253908,0.20533459,0.011610092,0.0015076129],"about_ca_topic_score_codex":0.00011826681,"about_ca_topic_score_gemma":0.00008970559,"teacher_disagreement_score":0.5173661,"about_ca_system_score_codex":0.000029965757,"about_ca_system_score_gemma":0.000008722495,"threshold_uncertainty_score":0.7725301},"labels":[],"label_agreement":null},{"id":"W2023462222","doi":"10.1145/1344671.1344676","title":"High-quality, deterministic parallel placement for FPGAs on commodity hardware","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":62,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Alterra Power (Canada)","funders":"","keywords":"Computer science; Parallel computing; Field-programmable gate array; Reduction (mathematics); Embedded system; Mathematics","score_opus":0.06598406236287854,"score_gpt":0.28893522794220006,"score_spread":0.22295116557932151,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2023462222","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.098279685,0.00003681844,0.8857078,0.00011233754,0.00030503602,0.00079626084,0.00011085838,0.0020120344,0.012639152],"genre_scores_gemma":[0.9762853,0.000035275094,0.022153044,0.00021931178,0.00008715136,0.00018712314,0.000041698604,0.000031447216,0.0009596543],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992468,0.000018610477,0.00022333773,0.00014914566,0.00013436681,0.00022776265],"domain_scores_gemma":[0.9994949,0.00012960527,0.000020435877,0.00025832187,0.00002743294,0.00006930537],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012167458,0.00015700361,0.00020529698,0.000045970257,0.0000954298,0.0000147338515,0.00014080382,0.000078139106,0.00010148807],"category_scores_gemma":[0.000022002327,0.00014263233,0.00007234772,0.000038846687,0.000026436082,0.000045135843,0.00002018462,0.00008842042,0.000056187855],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003017946,0.000585362,0.0010282479,0.0009249403,0.00026870015,0.00010722804,0.0008334136,0.044194788,0.008650518,0.07820074,0.8403373,0.024567017],"study_design_scores_gemma":[0.011685161,0.0046476214,0.021067841,0.000448982,0.00020338556,0.00017103321,0.0002620678,0.19599319,0.46491075,0.038383648,0.25632912,0.0058972207],"about_ca_topic_score_codex":0.000017429848,"about_ca_topic_score_gemma":0.000012360262,"teacher_disagreement_score":0.8780056,"about_ca_system_score_codex":0.00006117072,"about_ca_system_score_gemma":0.000009087273,"threshold_uncertainty_score":0.5816378},"labels":[],"label_agreement":null},{"id":"W2023788229","doi":"10.1145/1723112.1723140","title":"Towards scalable placement for FPGAs","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":46,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Scalability; Placement; Simulated annealing; Speedup; Application-specific integrated circuit; Parallel computing; Context (archaeology); Computer architecture; Matching (statistics); Embedded system; Physical design; Algorithm; Circuit design; Database","score_opus":0.010242131005467073,"score_gpt":0.2300675408683493,"score_spread":0.21982540986288224,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2023788229","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022226157,0.00002972989,0.77346116,0.00009734069,0.0004420103,0.00036342535,0.000007216428,0.001597118,0.20177586],"genre_scores_gemma":[0.89246273,0.0000105177,0.1042262,0.00008092116,0.00012191925,0.00014232483,0.0000054630905,0.0000263402,0.0029235736],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996732,0.0000011910989,0.000073531926,0.000065226726,0.00004776467,0.00013912229],"domain_scores_gemma":[0.99980825,0.0000116788115,0.0000040645123,0.000119036944,0.000018387766,0.000038556747],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009020785,0.00006347483,0.000063002386,0.000028155262,0.000020879044,0.000018848956,0.000072505194,0.000055741053,0.00043886935],"category_scores_gemma":[0.000008232378,0.00005485982,0.000029315015,0.00003323354,0.0000073839074,0.000046698973,0.000008668387,0.000068870024,0.000033126675],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008317645,0.000039927185,0.00010521549,0.00012665155,0.000039511753,0.0000013191343,0.00010911978,0.00047870204,0.5127382,0.03130456,0.3450883,0.10996014],"study_design_scores_gemma":[0.00018963762,0.000039021914,0.00005935057,0.00000445343,0.0000058815726,0.0000022544564,0.000011539934,0.030834688,0.7616283,0.0025743137,0.20450097,0.00014957594],"about_ca_topic_score_codex":0.000007116607,"about_ca_topic_score_gemma":0.000013317664,"teacher_disagreement_score":0.8702366,"about_ca_system_score_codex":0.000009809293,"about_ca_system_score_gemma":0.00000569874,"threshold_uncertainty_score":0.48053116},"labels":[],"label_agreement":null},{"id":"W2024174517","doi":"10.1145/2499625.2499627","title":"Towards development of an analytical model relating FPGA architecture parameters to routability","year":2013,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Router; Computer science; Logic block; Block (permutation group theory); Routing (electronic design automation); Embedded system; FPGA prototype; Computer architecture; CAD; Design flow; Parallel computing; Computer hardware; Engineering; Engineering drawing; Computer network","score_opus":0.025796937541249773,"score_gpt":0.24346641330898858,"score_spread":0.21766947576773882,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2024174517","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5018417,0.000056158853,0.4961097,0.00012585214,0.00005422694,0.00040634844,0.0000075863077,0.0005748125,0.0008236005],"genre_scores_gemma":[0.944522,0.000006901586,0.05505778,0.000014247549,0.000003382322,0.00028649895,0.0000020403081,0.00002163705,0.000085491556],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988858,0.0000304377,0.00044543223,0.00026993846,0.00010339761,0.000264995],"domain_scores_gemma":[0.99921876,0.000056018063,0.000036462952,0.0005249789,0.000057058543,0.000106715976],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023919757,0.00018834347,0.0003386407,0.0005161791,0.00011567781,0.000027543972,0.00024940327,0.0003563914,0.000027960312],"category_scores_gemma":[0.000032535958,0.00017181823,0.000041485917,0.0003773286,0.00007179384,0.00011843773,0.0000035752628,0.0003890741,0.000012912691],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014338284,0.00008135454,0.000120791,0.00021310938,0.00013684719,0.0000015267916,0.00079250045,0.22440545,0.017069578,0.00050790556,0.00003319673,0.7566234],"study_design_scores_gemma":[0.00042495318,0.000461135,0.0005095683,0.00030857488,0.00006235831,0.00008503917,0.0013644536,0.68216115,0.29963523,0.013906582,0.00032563557,0.00075532484],"about_ca_topic_score_codex":0.00006729218,"about_ca_topic_score_gemma":0.000024902612,"teacher_disagreement_score":0.7558681,"about_ca_system_score_codex":0.00006185755,"about_ca_system_score_gemma":0.000029112909,"threshold_uncertainty_score":0.70065445},"labels":[],"label_agreement":null},{"id":"W2025476395","doi":"10.1016/j.vlsi.2010.11.003","title":"A pre-placement individual net length estimation model and an application for modern circuits","year":2010,"lang":"en","type":"article","venue":"Integration","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Benchmark (surveying); Interconnection; Electronic circuit; A priori and a posteriori; Estimation; Computer science; Integrated circuit; IBM; Net (polyhedron); Cluster analysis; Computer engineering; Electronic engineering; Reliability engineering; Engineering; Mathematics; Systems engineering; Machine learning; Telecommunications; Electrical engineering","score_opus":0.01818199883747231,"score_gpt":0.2712351910471546,"score_spread":0.2530531922096823,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2025476395","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.23104078,0.000014143685,0.76790696,0.000013938136,0.000042102496,0.00047506392,0.000029469567,0.0002923385,0.00018517787],"genre_scores_gemma":[0.96273524,0.000005700877,0.03635219,0.00001982516,0.000059379032,0.00047327954,0.00031388414,0.000019074856,0.000021403437],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99956024,0.0000056184026,0.00013138793,0.00012918314,0.000083373154,0.00009017312],"domain_scores_gemma":[0.9997488,0.000014720805,0.000025996664,0.00013103467,0.000043450156,0.00003597578],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015085973,0.00009182985,0.00006735692,0.00006250985,0.000046020366,0.000056025066,0.000056229463,0.000103229024,0.0000019414858],"category_scores_gemma":[0.000013969877,0.00008970252,0.000013602036,0.0000355062,0.000011025383,0.0003325052,0.000005027584,0.0001069702,0.0000011409652],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000047690714,0.000022039681,0.000029723875,0.00002216207,0.0000075723206,2.5896384e-8,0.0016624515,0.050410904,0.28506723,0.0050846366,0.00020943911,0.65747905],"study_design_scores_gemma":[0.00012140386,0.000052799485,0.00026088854,0.0000059615622,0.000013741787,0.0000013163117,0.000016295513,0.94391525,0.037988625,0.017465064,0.000062426516,0.00009621403],"about_ca_topic_score_codex":0.000008361205,"about_ca_topic_score_gemma":0.00009140364,"teacher_disagreement_score":0.8935044,"about_ca_system_score_codex":0.00002665332,"about_ca_system_score_gemma":0.000015170347,"threshold_uncertainty_score":0.36579624},"labels":[],"label_agreement":null},{"id":"W2026061728","doi":"10.1007/s10470-011-9648-z","title":"A new approach to sizing analog CMOS building blocks using pre-compiled neural network models","year":2011,"lang":"en","type":"article","venue":"Analog Integrated Circuits and Signal Processing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Automation; Electronic design automation; CMOS; Sizing; Electronic engineering; Computer science; Process (computing); Design flow; Amplifier; Engineering; Circuit design; Integrated circuit design; Embedded system","score_opus":0.04723845503049792,"score_gpt":0.24033086170360995,"score_spread":0.19309240667311203,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2026061728","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09069779,0.0022745826,0.89432913,0.0000039190168,0.000067669,0.00034924576,0.0000050114936,0.0007508002,0.011521877],"genre_scores_gemma":[0.958036,0.000032743646,0.041336473,0.00016308305,0.00024554046,0.000022995477,0.000012593732,0.0000915939,0.000058978127],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9977768,0.000058234953,0.00055212685,0.00057843287,0.00024172582,0.00079265493],"domain_scores_gemma":[0.99912786,0.000035370027,0.00010151335,0.00021363188,0.00014254557,0.00037905807],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003487605,0.0004851298,0.0005414849,0.0003057244,0.000330599,0.00027938836,0.00034572353,0.00026107824,0.000049842256],"category_scores_gemma":[0.0000115430075,0.000444749,0.00009943179,0.0010041937,0.000052700965,0.0006307054,0.000054587967,0.0005791343,0.0000018411082],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000039743478,0.00006822007,0.000780809,0.00023003643,0.00018368236,0.0000365353,0.004584414,0.46812207,0.05494149,0.0012484365,0.0009830778,0.46878147],"study_design_scores_gemma":[0.00023455203,0.000083949744,0.00018304466,0.0004081062,0.000107965,0.00008777912,0.0002101702,0.98821145,0.004029481,0.0057507586,0.000070776354,0.0006219654],"about_ca_topic_score_codex":0.00041811826,"about_ca_topic_score_gemma":0.000013394064,"teacher_disagreement_score":0.86733824,"about_ca_system_score_codex":0.0000918102,"about_ca_system_score_gemma":0.00010942073,"threshold_uncertainty_score":0.99980044},"labels":[],"label_agreement":null},{"id":"W2028739735","doi":"10.4028/www.scientific.net/amr.490-495.1511","title":"The Improvement of Pseudo-Boolean Satisfiability Algorithm for FPGA Routing","year":2012,"lang":"en","type":"article","venue":"Advanced materials research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"La Cité Collégiale","funders":"","keywords":"Routing (electronic design automation); Boolean satisfiability problem; Computer science; Algorithm; Field-programmable gate array; Satisfiability; Embedded system","score_opus":0.03568103232071959,"score_gpt":0.3483881086767109,"score_spread":0.31270707635599126,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2028739735","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.74614275,0.00093074597,0.24681972,0.00007550637,0.0010836466,0.003036106,0.00020039956,0.00050046004,0.0012106878],"genre_scores_gemma":[0.97299373,0.00025660067,0.025903879,0.0000044327853,0.00019332464,0.0005066312,0.000008700665,0.00003879472,0.00009391131],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9984898,0.00007595196,0.00035081065,0.00013382103,0.0002778409,0.0006717642],"domain_scores_gemma":[0.9989064,0.00044207816,0.000039362138,0.0003740357,0.0001643361,0.00007379098],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0030933414,0.00011381553,0.00019066675,0.00005290282,0.0001848747,0.000045000284,0.00024290092,0.000065595705,0.000033179174],"category_scores_gemma":[0.00019889302,0.00008459545,0.000039710347,0.00011875,0.00009952318,0.00018648061,0.00009004928,0.00011292131,0.000007614227],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000108040695,0.000013269561,0.000013568205,0.0000764484,0.000010641704,8.1290715e-8,0.00007539093,0.000011367655,0.6727438,0.00064498914,0.00017157522,0.32622805],"study_design_scores_gemma":[0.00017983647,0.00012015591,0.00019560837,0.000024111123,0.0000032226146,6.44122e-7,0.00012672023,0.00062678254,0.99255246,0.003530788,0.0025444727,0.00009520222],"about_ca_topic_score_codex":0.000024501285,"about_ca_topic_score_gemma":0.000002378206,"teacher_disagreement_score":0.32613286,"about_ca_system_score_codex":0.00009831202,"about_ca_system_score_gemma":0.00001558115,"threshold_uncertainty_score":0.34497023},"labels":[],"label_agreement":null},{"id":"W2031312330","doi":"10.1145/332357.332399","title":"Multilevel cooperative search","year":2000,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Citation; DEPT; Library science; Operations research; Computer science; Management; Engineering; Chemistry; Economics","score_opus":0.016400188672989518,"score_gpt":0.2343691095491157,"score_spread":0.21796892087612618,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2031312330","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.12150664,0.00010138051,0.106178865,0.00003432237,0.000035130815,0.00017937648,0.000006265957,0.0021312463,0.76982677],"genre_scores_gemma":[0.98369706,0.000072489966,0.0046976255,0.000056423556,0.000026068412,0.000010414043,0.000001998501,0.000012704487,0.011425216],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997282,0.0000062107592,0.000053791344,0.000054812266,0.00004838055,0.00010859068],"domain_scores_gemma":[0.9998677,0.00001087974,7.152462e-7,0.000077868695,0.000012120974,0.000030737963],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00003358278,0.00005264188,0.0000507221,0.000020443495,0.000019755433,0.000013670023,0.00005372272,0.000032011267,0.006995969],"category_scores_gemma":[0.0000011105362,0.000044317363,0.00001370187,0.000048007823,0.000010996101,0.00005673243,0.0000031687198,0.00006531279,0.0006440037],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004786319,0.000027145921,0.00009121147,0.000017229202,0.000027576438,0.000012385298,0.0006770528,0.008203834,0.03158002,0.0018387842,0.050001893,0.9075181],"study_design_scores_gemma":[0.00029529972,0.00006897053,0.0012603949,0.00001596148,0.000003913357,0.000010749732,0.000055266926,0.35953325,0.574894,0.00021839335,0.06328469,0.00035909106],"about_ca_topic_score_codex":0.000011593473,"about_ca_topic_score_gemma":0.0000019841343,"teacher_disagreement_score":0.907159,"about_ca_system_score_codex":0.000012058384,"about_ca_system_score_gemma":0.0000032746243,"threshold_uncertainty_score":0.99391174},"labels":[],"label_agreement":null},{"id":"W2035057034","doi":"10.1109/fpl.2014.6927418","title":"Incremental distributed trigger insertion for efficient FPGA debug","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Debugging; Computer science; Observability; Field-programmable gate array; Embedded system; Electronic circuit; Background debug mode interface; Spare part; Computer hardware; Computer architecture; Real-time computing; Engineering; Operating system; Electrical engineering","score_opus":0.009221593388612056,"score_gpt":0.210202706435551,"score_spread":0.20098111304693894,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2035057034","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09213811,0.00002281398,0.903593,0.000033603617,0.00009770415,0.0002489363,0.000015888023,0.00097230804,0.0028776205],"genre_scores_gemma":[0.9964502,0.0000037422958,0.0032318532,0.000049806556,0.00005398228,0.00007364662,0.000055840646,0.000017598926,0.000063360545],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99954957,0.000007938175,0.00012978645,0.000089206085,0.000069195514,0.0001543066],"domain_scores_gemma":[0.9997934,0.00002914543,0.000010203156,0.00010675717,0.000020755348,0.000039707746],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013722859,0.000086060005,0.000090606074,0.000041387666,0.000036823785,0.000018815823,0.00006511176,0.000054312397,0.000047316964],"category_scores_gemma":[0.00001927872,0.000074586605,0.000045487155,0.0000688832,0.00000835653,0.000033896387,0.000009678376,0.00004000427,0.000021885788],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008578844,0.00025144222,0.0005099899,0.00027782272,0.000108684646,0.0000014175212,0.00017335331,0.012588212,0.5765217,0.008706152,0.17441757,0.22635788],"study_design_scores_gemma":[0.00051833823,0.00009952116,0.0010032809,0.0000134019865,0.000013568895,0.0000018127446,0.000011882651,0.40300554,0.5575668,0.0004695895,0.037089255,0.0002069788],"about_ca_topic_score_codex":0.000007783616,"about_ca_topic_score_gemma":0.0000032225091,"teacher_disagreement_score":0.9043121,"about_ca_system_score_codex":0.00005194273,"about_ca_system_score_gemma":0.0000026542925,"threshold_uncertainty_score":0.30415535},"labels":[],"label_agreement":null},{"id":"W2036044594","doi":"10.1145/611817.611875","title":"Synthetic circuit generation using clustering and iteration","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Benchmark (surveying); Electronic circuit; Cluster analysis; Computer engineering; Netlist; Routing (electronic design automation); Path (computing); Algorithm; Embedded system; Engineering; Artificial intelligence","score_opus":0.038698831075028556,"score_gpt":0.21956467715342598,"score_spread":0.18086584607839742,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2036044594","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15804212,0.0001322421,0.83349043,0.000001944024,0.00006875187,0.00006229622,2.6294475e-7,0.00023468716,0.007967248],"genre_scores_gemma":[0.9879779,0.00002488081,0.011876078,0.000019481076,0.000030177034,0.0000042502425,0.000001099648,0.000012039316,0.00005408547],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99973637,0.000011344512,0.00007689541,0.00006830181,0.000034714216,0.00007237404],"domain_scores_gemma":[0.9998976,0.0000052749674,0.000005425416,0.00006330406,0.000008503358,0.000019897765],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000069776615,0.000054925218,0.000047034006,0.000040886927,0.000035728986,0.000048452293,0.000013395341,0.00003531499,0.000040175724],"category_scores_gemma":[0.0000063951634,0.000055311826,0.000008578341,0.000037734284,0.0000050671806,0.00011669976,0.0000027530207,0.00002922038,0.0000025240302],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[1.8978176e-7,0.0000035438043,0.00012388595,0.000027400605,0.000006454723,0.0000014808186,0.00016152843,0.008327964,0.97389776,0.0047835377,0.00011328136,0.012552958],"study_design_scores_gemma":[0.000049987768,0.00000838744,0.000026295145,0.000010491795,0.000005659136,0.000032240805,0.00001125696,0.7948695,0.2040077,0.00033661377,0.0005356269,0.00010624404],"about_ca_topic_score_codex":0.0000025313523,"about_ca_topic_score_gemma":0.0000036752908,"teacher_disagreement_score":0.8299358,"about_ca_system_score_codex":0.000021774078,"about_ca_system_score_gemma":0.0000023062005,"threshold_uncertainty_score":0.22555508},"labels":[],"label_agreement":null},{"id":"W2037455559","doi":"10.1109/tcad.2011.2165715","title":"Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010","year":2011,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":39,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Speedup; Computer science; Parallel computing; Field-programmable gate array; Router; Routing (electronic design automation); Overhead (engineering); Heuristic; Gate array; Heuristics; Embedded system; Computer network","score_opus":0.05512664828856144,"score_gpt":0.2195949649687447,"score_spread":0.16446831668018325,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2037455559","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.038548056,0.00008922076,0.9573806,0.0000017868267,0.0025238993,0.0005484068,0.00001497536,0.00040945588,0.00048362112],"genre_scores_gemma":[0.9947086,0.00023377132,0.00448543,0.000013049295,0.00040605408,0.000068011,0.000005003896,0.000049321286,0.0000307895],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985722,0.000089596084,0.0005689733,0.00031738484,0.0001863547,0.00026551558],"domain_scores_gemma":[0.9994249,0.00010192128,0.00011163955,0.00018173571,0.00010522152,0.00007463248],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00025652148,0.00032111377,0.00038193358,0.00022712548,0.00015529682,0.000102089005,0.000104043225,0.00022002359,0.000019232722],"category_scores_gemma":[0.000004504615,0.00030519158,0.000054115546,0.00025064996,0.000030188978,0.00031091983,0.0000013439698,0.00034266003,0.0000032010241],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010878662,0.00034368536,0.000075511976,0.0006133493,0.00059633184,0.000024069896,0.00657185,0.5783478,0.24426244,0.0011800936,0.0011363445,0.16673972],"study_design_scores_gemma":[0.000671005,0.000872333,0.00020221127,0.0009509692,0.000056730612,0.000049897128,0.00019483645,0.7516632,0.24468358,0.000055356584,0.00009521769,0.0005046567],"about_ca_topic_score_codex":0.00013730956,"about_ca_topic_score_gemma":0.0000045409192,"teacher_disagreement_score":0.9561605,"about_ca_system_score_codex":0.0000834629,"about_ca_system_score_gemma":0.000018045303,"threshold_uncertainty_score":0.99994004},"labels":[],"label_agreement":null},{"id":"W2037754626","doi":"10.1260/174830108788251773","title":"A Degree-Based Clustering Technique for VLSI Placement","year":2009,"lang":"en","type":"article","venue":"Journal of Algorithms & Computational Technology","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Preprocessor; Degree (music); Computer science; Benchmark (surveying); Very-large-scale integration; IBM; Data pre-processing; Data mining; Algorithm; Artificial intelligence","score_opus":0.020368278343021715,"score_gpt":0.2692007815564009,"score_spread":0.2488325032133792,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2037754626","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015667571,0.0003248242,0.99611604,0.0009072807,0.00015669285,0.0003698759,0.000008481384,0.00040760357,0.00014242234],"genre_scores_gemma":[0.39147598,0.000013651743,0.6082356,0.00010993614,0.00010038395,0.00003283717,0.0000050295184,0.000019647829,0.000006931279],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988592,0.000012803417,0.00054766185,0.000120731376,0.00021641991,0.00024315625],"domain_scores_gemma":[0.99924874,0.00009611067,0.00017506155,0.00011611613,0.00030570352,0.000058256563],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00032158502,0.00017763319,0.00030567232,0.00079648657,0.00006108633,0.000024368821,0.00029124497,0.00021556151,0.000009880711],"category_scores_gemma":[0.000038451537,0.00017330825,0.00013040742,0.00033350257,0.000043349966,0.000109090084,0.000015311736,0.0003120692,0.0000019221486],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008451813,0.00018946979,0.000041491203,0.000079653815,0.00012930288,0.00007827838,0.00004664141,0.66277397,0.039446242,0.0020056267,0.004876794,0.29024798],"study_design_scores_gemma":[0.0020125508,0.0026150448,0.00036978582,0.00025777196,0.000058651196,0.0008519051,0.000057368383,0.7875698,0.11880245,0.082024805,0.004886474,0.00049336033],"about_ca_topic_score_codex":2.816002e-7,"about_ca_topic_score_gemma":3.4664822e-7,"teacher_disagreement_score":0.38990924,"about_ca_system_score_codex":0.0001642659,"about_ca_system_score_gemma":0.00007087881,"threshold_uncertainty_score":0.7067305},"labels":[],"label_agreement":null},{"id":"W2039194939","doi":"10.1145/2501985","title":"Analyzing System-Level Information’s Correlation to FPGA Placement","year":2013,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Netlist; Computer science; Locality; Field-programmable gate array; Placement; Simulated annealing; Computer engineering; Verilog; Algorithm; Theoretical computer science; Embedded system; Physical design; Circuit design","score_opus":0.01392183303958959,"score_gpt":0.20595381848356248,"score_spread":0.19203198544397287,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2039194939","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.02361107,0.0002675265,0.9660368,0.00032863248,0.00058691856,0.0010823675,0.00003369871,0.002321746,0.00573122],"genre_scores_gemma":[0.9969844,0.000063146595,0.0015475082,0.000027580061,0.000012810138,0.00083143153,0.000008289365,0.000018175435,0.0005066235],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990455,0.000022159762,0.00042048894,0.0001577432,0.000095784875,0.00025836148],"domain_scores_gemma":[0.9992952,0.000055923054,0.000050547605,0.00042512163,0.000090195135,0.000083015984],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017335324,0.00018587286,0.0002472303,0.0010027301,0.00020000129,0.00010089509,0.00019932905,0.0003116875,0.00007892332],"category_scores_gemma":[0.000016100288,0.00018104982,0.000034903307,0.0005323902,0.000026646114,0.00044790067,0.0000027014448,0.000274124,0.0005074194],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000039176855,0.00008899441,0.00095549785,0.0014717181,0.0006192043,0.000006967229,0.0010833403,0.24456176,0.0125775235,0.012237981,0.012438732,0.7139191],"study_design_scores_gemma":[0.00391374,0.0020471057,0.003063471,0.003718764,0.00042415524,0.0011176975,0.028028999,0.70275795,0.18088138,0.0037910377,0.06589986,0.004355842],"about_ca_topic_score_codex":0.000098839315,"about_ca_topic_score_gemma":0.000007148881,"teacher_disagreement_score":0.97337335,"about_ca_system_score_codex":0.00014494827,"about_ca_system_score_gemma":0.000010995507,"threshold_uncertainty_score":0.7382997},"labels":[],"label_agreement":null},{"id":"W2039730318","doi":"10.1145/2003695.2003710","title":"Analog layout retargeting using geometric programming","year":2011,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Memorial University of Newfoundland","keywords":"Computer science; Geometric programming; Initialization; Retargeting; Transformation (genetics); Mathematical optimization; Convex optimization; Netlist; Nonlinear programming; Computer engineering; Algorithm; Nonlinear system; Regular polygon; Artificial intelligence; Computer hardware; Mathematics","score_opus":0.0525912628983535,"score_gpt":0.2403003780804701,"score_spread":0.1877091151821166,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2039730318","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013042983,0.0008116668,0.9837035,0.000002584482,0.00018121194,0.0006522966,0.0000037375867,0.0011720271,0.00042998334],"genre_scores_gemma":[0.949946,0.000056670382,0.049773112,0.000003495495,0.00002510532,0.000103116974,0.0000035765968,0.00005067924,0.00003824089],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99840945,0.00012547986,0.00054713094,0.0002075058,0.00025749893,0.000452958],"domain_scores_gemma":[0.9991407,0.00012720171,0.00014166966,0.00043388992,0.000096826334,0.000059739155],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00065697654,0.00021654078,0.00030137348,0.00078353623,0.000109713976,0.00003167572,0.00028570506,0.00016660948,0.00006596727],"category_scores_gemma":[0.00003359909,0.00022648119,0.0001090024,0.001080712,0.000027701568,0.00025110922,0.0000021782314,0.00024743206,0.000018515208],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008921194,0.00043959825,0.00021129381,0.0009652696,0.0009627054,0.0000130327135,0.0024649922,0.646629,0.07728231,0.0013146116,0.0002497117,0.26937827],"study_design_scores_gemma":[0.0003945071,0.0005873898,0.00014389247,0.000245817,0.00014517404,0.00007517545,0.00022554593,0.8299023,0.16699839,0.0005232634,0.0002725584,0.0004860153],"about_ca_topic_score_codex":0.00008561785,"about_ca_topic_score_gemma":0.0000023149503,"teacher_disagreement_score":0.936903,"about_ca_system_score_codex":0.00028733024,"about_ca_system_score_gemma":0.000055233577,"threshold_uncertainty_score":0.9235635},"labels":[],"label_agreement":null},{"id":"W2044141314","doi":"10.1007/s12065-014-0114-6","title":"Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators","year":2014,"lang":"en","type":"article","venue":"Evolutionary Intelligence","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Genetic algorithm; Field (mathematics); Gate array; Parallel computing; Algorithm; Field-programmable gate array; Computer hardware; Machine learning; Mathematics","score_opus":0.01663700403645227,"score_gpt":0.21228066336375362,"score_spread":0.19564365932730135,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2044141314","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0066202404,0.00017696021,0.9895117,0.00010507131,0.00016189794,0.00050970237,0.0000020129992,0.00050188537,0.0024104824],"genre_scores_gemma":[0.66483873,0.00005257627,0.33451548,0.000058795424,0.000064449916,0.00027706812,0.00000895592,0.000025559231,0.00015836049],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99893945,0.000033870987,0.00023053025,0.0002726624,0.00019347633,0.0003300045],"domain_scores_gemma":[0.99951726,0.000053914267,0.000027524406,0.00023497075,0.000056425542,0.00010988212],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017026765,0.00018498495,0.00014480273,0.00011097444,0.00009614225,0.000033307726,0.00018773964,0.00006898699,0.00006300372],"category_scores_gemma":[0.000029692312,0.00017321008,0.000029546667,0.00029226864,0.000021710437,0.00016893532,0.000021627153,0.00014248173,0.00007179],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002371103,0.000085583015,0.0001478617,0.00008166984,0.00003929892,0.0000026116336,0.0007201383,0.371918,0.007815051,0.00085089763,0.0013978053,0.6169174],"study_design_scores_gemma":[0.00009551075,0.0009948879,0.00021981208,0.0001624264,0.00001479689,0.000017705197,0.00027371524,0.3807939,0.6085218,0.0021820674,0.0061941063,0.0005292674],"about_ca_topic_score_codex":0.0000127443045,"about_ca_topic_score_gemma":0.000008747987,"teacher_disagreement_score":0.6582185,"about_ca_system_score_codex":0.00014628425,"about_ca_system_score_gemma":0.00002122353,"threshold_uncertainty_score":0.7063302},"labels":[],"label_agreement":null},{"id":"W204600454","doi":"","title":"Steiner tree and interconnect optimization in VLSI design.","year":2002,"lang":"en","type":"article","venue":"Scholarship at UWindsor (University of Windsor)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Very-large-scale integration; Interconnection; Computer science; Physical design; Mathematical optimization; Circuit design; Mathematics; Embedded system; Telecommunications","score_opus":0.023587805510588714,"score_gpt":0.17952450188296676,"score_spread":0.15593669637237806,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W204600454","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.91595346,0.00088326645,0.07538515,0.00017598964,0.00008640034,0.00037542242,0.000012515462,0.00043261115,0.006695201],"genre_scores_gemma":[0.9832827,0.00035454702,0.015654821,0.000022016233,0.000016676338,7.4650114e-7,0.0000061188007,0.000028601498,0.00063379377],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991013,0.00009698254,0.0001537116,0.0002387751,0.00015876406,0.00025050226],"domain_scores_gemma":[0.9995052,0.00007254981,0.000046866957,0.00023160281,0.000044782882,0.00009898314],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002981496,0.00017818193,0.0002516795,0.00038978606,0.00008995812,0.000025933185,0.00025318968,0.00020952937,0.0005005323],"category_scores_gemma":[0.000036688674,0.00022732501,0.00006214038,0.00035187087,0.00008266768,0.0007498618,0.00008405786,0.0002795113,0.000031584306],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0007460858,0.0009202616,0.18198362,0.0011949567,0.0007206177,0.0008736535,0.03251681,0.28678587,0.2249341,0.001136604,0.010285432,0.25790197],"study_design_scores_gemma":[0.009077368,0.0010771336,0.12356507,0.00093197974,0.0002751602,0.00014222237,0.0029522814,0.7989036,0.054284487,0.0012128431,0.004732782,0.0028450903],"about_ca_topic_score_codex":0.000018186043,"about_ca_topic_score_gemma":0.00008392038,"teacher_disagreement_score":0.5121177,"about_ca_system_score_codex":0.000106755855,"about_ca_system_score_gemma":0.000005296176,"threshold_uncertainty_score":0.9270045},"labels":[],"label_agreement":null},{"id":"W2046981406","doi":"10.1145/2744769.2744919","title":"Towards enhancing analog circuits sizing using SMT-based techniques","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Sizing; Biasing; Analogue electronics; Computer science; Electronic engineering; Amplifier; Cascode; Electronic circuit; Satisfiability modulo theories; Algorithm; CMOS; Voltage; Electrical engineering; Engineering","score_opus":0.04927790973757979,"score_gpt":0.26643219454661055,"score_spread":0.21715428480903076,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2046981406","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024949953,0.00032299868,0.9252919,0.000016825734,0.0001855979,0.00018975083,0.000002775917,0.0043077823,0.044732448],"genre_scores_gemma":[0.9174349,0.000009236353,0.08218066,0.00013528584,0.0001196244,0.0000186177,0.0000044487792,0.0000543562,0.000042883545],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99900043,0.000024485264,0.00025842153,0.00018204664,0.00020714877,0.00032748427],"domain_scores_gemma":[0.9994533,0.000023615094,0.000027092201,0.00025792897,0.00008851468,0.00014955761],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003808919,0.00019915425,0.00021872972,0.00021139602,0.000044288376,0.000060905797,0.00017181819,0.00014600772,0.000040942345],"category_scores_gemma":[0.00004545515,0.00019508433,0.00006555706,0.0002869543,0.000023983897,0.00020324357,0.000025820573,0.00016321905,0.0000147629935],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000025247664,0.000034677596,0.0003888787,0.0001263032,0.00003519855,0.000043181964,0.00029541785,0.0026649581,0.843423,0.000581963,0.003454481,0.14894938],"study_design_scores_gemma":[0.00010874248,0.00005139526,0.000051652467,0.00008101512,0.000015815158,0.000009264639,0.00006420935,0.05519301,0.9402875,0.00067947566,0.003120908,0.0003370231],"about_ca_topic_score_codex":0.0001170789,"about_ca_topic_score_gemma":0.000021103064,"teacher_disagreement_score":0.89248496,"about_ca_system_score_codex":0.00021537184,"about_ca_system_score_gemma":0.000080189006,"threshold_uncertainty_score":0.7955308},"labels":[],"label_agreement":null},{"id":"W2047041799","doi":"10.1007/s10898-005-4207-8","title":"Approximations and Lower Bounds for the Length of Minimal Euclidean Steiner Trees","year":2006,"lang":"en","type":"article","venue":"Journal of Global Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Mathematics; Upper and lower bounds; Combinatorics; Conjecture; Euclidean space; Euclidean geometry; Tree (set theory); Discrete mathematics; Space (punctuation); Topology (electrical circuits); Mathematical analysis; Geometry; Computer science","score_opus":0.00582047564380004,"score_gpt":0.2107929045233077,"score_spread":0.20497242887950767,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2047041799","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.02012637,0.00080438517,0.9773295,0.00015054112,0.00012116104,0.00012999156,0.000018920327,0.000029475765,0.0012896671],"genre_scores_gemma":[0.9137946,0.000119819226,0.08591913,0.000010537831,0.0001170385,0.0000031060695,0.0000031282102,0.000008548181,0.000024109057],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994879,0.000009289892,0.00029264792,0.000036268335,0.00010076034,0.00007316983],"domain_scores_gemma":[0.999622,0.000046852867,0.00012144515,0.000057317782,0.00013379652,0.000018594406],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014889057,0.000066000575,0.000116783645,0.000032558008,0.000037920538,0.00003260727,0.000069576075,0.000044593213,0.000006165167],"category_scores_gemma":[0.000025183526,0.00004627747,0.0000574445,0.000108064705,0.000028622862,0.0001714432,0.000006035507,0.000040953637,9.133147e-8],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003792551,0.000044207736,0.0007536155,0.000026631431,0.00005128859,8.921888e-7,0.000031424053,0.9843182,0.00067101687,0.0029802418,0.0072592143,0.0038253544],"study_design_scores_gemma":[0.0007805291,0.00033353054,0.0043177377,0.000055580895,0.0001435192,0.000053989734,0.000077003075,0.98855054,0.0012611178,0.0015997369,0.0026894652,0.00013726176],"about_ca_topic_score_codex":0.0000049502114,"about_ca_topic_score_gemma":0.000006521983,"teacher_disagreement_score":0.89366823,"about_ca_system_score_codex":0.000037394326,"about_ca_system_score_gemma":0.000013016767,"threshold_uncertainty_score":0.18871404},"labels":[],"label_agreement":null},{"id":"W2047143252","doi":"10.1145/1950413.1950441","title":"A CAD framework for Malibu","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Computer science; Verilog; Electronic circuit; Bitstream; CAD; Compiler; Multiplexing; Design flow; Computer architecture; Embedded system; Algorithm; Telecommunications; Electrical engineering; Engineering","score_opus":0.041434946229637046,"score_gpt":0.2342729925571768,"score_spread":0.19283804632753976,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2047143252","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015657179,0.00005730997,0.927117,0.000007127161,0.0000813041,0.00010885414,0.000002574726,0.0010588946,0.07000125],"genre_scores_gemma":[0.6091389,0.000012782958,0.3903105,0.000070094306,0.00004235484,0.000057520454,7.714517e-7,0.000017971695,0.00034911995],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.99976873,0.0000014593716,0.000055796772,0.000047563804,0.000021931484,0.00010450167],"domain_scores_gemma":[0.99984974,0.000016363672,0.0000034609245,0.00009716512,0.000008237335,0.000025031111],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003238297,0.000048922542,0.000051564737,0.00002135093,0.00001096481,0.000005164785,0.000061624,0.0000662351,0.00028563736],"category_scores_gemma":[0.000007379097,0.000042868855,0.000027743485,0.000032438664,0.0000053336666,0.000034776465,0.0000047574617,0.000043429227,0.000033059427],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010837229,0.000031577554,0.00064672565,0.00010960608,0.000053091066,0.0000049303935,0.0010615025,0.000010281855,0.0043278756,0.88271564,0.06167623,0.04935171],"study_design_scores_gemma":[0.00016467237,0.0001446273,0.0009909931,0.000043197575,0.00001947037,0.00000640478,0.000074802396,0.0063726692,0.45264518,0.49310496,0.045998782,0.00043424979],"about_ca_topic_score_codex":0.000006819973,"about_ca_topic_score_gemma":0.0000015104246,"teacher_disagreement_score":0.6075732,"about_ca_system_score_codex":0.000006238094,"about_ca_system_score_gemma":0.0000015454996,"threshold_uncertainty_score":0.31275287},"labels":[],"label_agreement":null},{"id":"W2048878923","doi":"10.1145/2007052.2007068","title":"Integrated design space exploration based on power-performance trade-off using genetic algorithm","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Computer science; Space (punctuation); Power (physics); Genetic algorithm; Algorithm design; Algorithm; Machine learning; Operating system","score_opus":0.05210946300318792,"score_gpt":0.2170636490770098,"score_spread":0.1649541860738219,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2048878923","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010737562,0.000051184114,0.98322064,0.000008320099,0.00012057035,0.00025366317,0.0000019388096,0.0010391872,0.0045669447],"genre_scores_gemma":[0.5761131,0.000033119068,0.42372024,0.000042368578,0.000013742111,0.000018614312,0.0000029359155,0.000033317225,0.000022557986],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992951,0.000036061658,0.00017628472,0.0001537611,0.00012292119,0.00021584664],"domain_scores_gemma":[0.9996634,0.000019562145,0.000021501732,0.00021365381,0.000021574135,0.00006027219],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011794777,0.00018550425,0.00013049747,0.00015231027,0.00004589395,0.000024187562,0.0001106191,0.00010397863,0.0001851705],"category_scores_gemma":[0.0000050466833,0.00016509273,0.000034224176,0.00022584634,0.000018744375,0.00023530205,0.0000048898146,0.00013417144,0.000034179982],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008294098,0.00024720564,0.00028154702,0.000088271714,0.000072075076,0.000055308137,0.0022368636,0.24540918,0.08327177,0.00021416658,0.0048796795,0.663161],"study_design_scores_gemma":[0.00010498005,0.00018376754,0.00021607737,0.000031955682,0.0000069027888,0.0000028244679,0.000032191827,0.7170043,0.28198633,0.000056099412,0.00020853561,0.00016603568],"about_ca_topic_score_codex":0.00001339257,"about_ca_topic_score_gemma":5.41501e-7,"teacher_disagreement_score":0.662995,"about_ca_system_score_codex":0.0000742514,"about_ca_system_score_gemma":0.000021529117,"threshold_uncertainty_score":0.6732286},"labels":[],"label_agreement":null},{"id":"W2050578892","doi":"10.1109/asicon.2009.5351226","title":"Transistor permutation for better transistor chaining","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Chaining; Transistor; Multiple-emitter transistor; Computer science; Key (lock); Electronic circuit; Electronic engineering; Transistor count; Logic gate; Permutation (music); Topology (electrical circuits); Algorithm; Electrical engineering; Engineering; Field-effect transistor; Physics","score_opus":0.009337012551341672,"score_gpt":0.20721241037458638,"score_spread":0.1978753978232447,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2050578892","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.020935366,0.00013856351,0.9683059,0.00042117172,0.0000828668,0.00023590875,0.0000056249105,0.0011407208,0.008733904],"genre_scores_gemma":[0.9669861,0.0000076033416,0.032140486,0.00047896765,0.000097760196,0.00003617725,0.000011542271,0.000019114917,0.00022220248],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99957716,0.0000041662042,0.00012342197,0.00009296865,0.000056047957,0.00014623228],"domain_scores_gemma":[0.9998488,0.000017254699,0.000006409563,0.00007656508,0.000017166998,0.00003382863],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006355221,0.00009248688,0.000102901155,0.00005940059,0.00003450625,0.0000137484985,0.00005231837,0.000062490355,0.000047243117],"category_scores_gemma":[0.0000028121533,0.00009014624,0.000071548835,0.000049661536,0.0000060695106,0.00009271914,3.5760814e-7,0.000049682327,0.000005210737],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000026970307,0.00003948508,0.000026601405,0.000109544046,0.00003904885,0.0000039565075,0.0033965223,0.00087248074,0.3197876,0.002816862,0.023087084,0.64979386],"study_design_scores_gemma":[0.002723853,0.0011887946,0.004299138,0.00011631584,0.0001779478,0.000025966372,0.00037707263,0.24632484,0.5599848,0.012091322,0.17075999,0.0019299642],"about_ca_topic_score_codex":0.0000012181016,"about_ca_topic_score_gemma":0.0000026350403,"teacher_disagreement_score":0.94605076,"about_ca_system_score_codex":0.000033555214,"about_ca_system_score_gemma":0.000003698309,"threshold_uncertainty_score":0.36760572},"labels":[],"label_agreement":null},{"id":"W2059553661","doi":"10.1109/fpl.2009.5272520","title":"Replace: An incremental placement algorithm for field programmable gate arrays","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Floorplan; Field-programmable gate array; Simulated annealing; Placement; Parallel computing; Process (computing); Grid; Key (lock); Algorithm; Embedded system; Circuit design; Physical design; Mathematics","score_opus":0.012258809701748367,"score_gpt":0.25283369731650535,"score_spread":0.24057488761475698,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2059553661","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0034996818,0.000057104575,0.9802668,0.00008078929,0.00009131426,0.0007269192,0.000006395779,0.0015993089,0.013671704],"genre_scores_gemma":[0.3207503,0.000052180207,0.67615473,0.0006926211,0.00022648337,0.00026639175,0.00007305961,0.000042410044,0.0017418225],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993086,0.0000068846366,0.0001619435,0.00015711674,0.00009572073,0.00026975237],"domain_scores_gemma":[0.9996763,0.000015186949,0.000013976515,0.00019867739,0.000020654648,0.000075203745],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016612394,0.0001284763,0.00011652461,0.0000463743,0.000051683077,0.00005038162,0.00010830016,0.00007219713,0.00012050913],"category_scores_gemma":[0.000004364249,0.000120200886,0.000044264438,0.00006298474,0.0000051608667,0.00016228741,0.000007562355,0.000073641495,0.000007973415],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025682159,0.0001224546,0.000019793419,0.000029604444,0.00003447295,0.000005062273,0.00016176196,0.00048509557,0.025622431,0.0007224556,0.051596444,0.92117476],"study_design_scores_gemma":[0.00069885625,0.0018528958,0.000016680764,0.000021640637,0.000018281822,0.000009302772,0.00015958388,0.37051976,0.59670866,0.0016818749,0.027921436,0.00039103575],"about_ca_topic_score_codex":0.000011102827,"about_ca_topic_score_gemma":0.0000058331902,"teacher_disagreement_score":0.9207837,"about_ca_system_score_codex":0.000044422326,"about_ca_system_score_gemma":0.000006113769,"threshold_uncertainty_score":0.490165},"labels":[],"label_agreement":null},{"id":"W2059674565","doi":"10.1109/fpt.2007.4439225","title":"Memory Footprint Reduction for FPGA Routing Algorithms","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Memory footprint; Reduction (mathematics); Parallel computing; Footprint; Compiler; Memory management; Algorithm; Embedded system; Computer hardware; Operating system; Semiconductor memory","score_opus":0.017711144902460382,"score_gpt":0.2491728526171012,"score_spread":0.2314617077146408,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2059674565","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00894049,0.00005674898,0.9569676,0.000019516103,0.0003378627,0.0002324594,7.739621e-7,0.0014459277,0.03199861],"genre_scores_gemma":[0.9061183,0.000010116338,0.09285035,0.000010226947,0.00031001488,0.000023377246,0.000002951556,0.000027081858,0.0006475805],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999468,0.000002621915,0.00015682133,0.000100551726,0.000060562044,0.00021138717],"domain_scores_gemma":[0.9997813,0.0000243758,0.000012302916,0.00011285517,0.000027573224,0.000041595707],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00035418247,0.00008234544,0.00008050311,0.0000649284,0.000039820963,0.000015248658,0.00006043509,0.00007088955,0.000017202117],"category_scores_gemma":[0.0000110239225,0.000080216196,0.000048011454,0.000071955226,0.00000909616,0.000046319237,0.000009227831,0.00006992866,0.000006724322],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050851477,0.000011710665,0.00000798624,0.00003396795,0.000019423436,0.0000016915808,0.0001859089,0.0004223073,0.12540168,0.0014933622,0.001972058,0.87044483],"study_design_scores_gemma":[0.00012161176,0.000034233643,0.00012459402,0.000010032724,0.000006244052,0.000014170166,0.00020491317,0.008561115,0.9864466,0.0011733031,0.003157936,0.00014523354],"about_ca_topic_score_codex":0.00001317448,"about_ca_topic_score_gemma":0.0000025648203,"teacher_disagreement_score":0.8971778,"about_ca_system_score_codex":0.000056270368,"about_ca_system_score_gemma":0.0000034944044,"threshold_uncertainty_score":0.32711217},"labels":[],"label_agreement":null},{"id":"W2062282643","doi":"10.1145/968280.968327","title":"Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Tile; Computer science; Layer (electronics); Virtex; Process (computing); Place and route; Very-large-scale integration; Computer architecture; Reconfigurable computing; Key (lock); Embedded system; Integrated circuit layout; Computer hardware; Integrated circuit; Operating system; Materials science","score_opus":0.012080458068272987,"score_gpt":0.20786616935939403,"score_spread":0.19578571129112105,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2062282643","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.95301074,0.0005675069,0.039098855,0.000059892645,0.000044102824,0.00018447277,0.0000035402907,0.00057146786,0.006459433],"genre_scores_gemma":[0.99149483,0.00002401369,0.008399298,0.000022171756,0.000010090153,0.000011410218,0.000001223781,0.000017825121,0.00001914142],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99951464,0.0000080175005,0.00019441417,0.000084318985,0.00007103669,0.00012758066],"domain_scores_gemma":[0.99985033,0.000015820915,0.000011079664,0.000087472734,0.0000032919795,0.000032007298],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008798505,0.00009429455,0.00018450993,0.00010160684,0.000009823178,0.000006829493,0.000054041044,0.00006171512,0.00004144852],"category_scores_gemma":[0.0000037962957,0.00008702928,0.00003654014,0.00010437896,0.000020233658,0.000105147454,0.000004700544,0.00007801656,0.0000024747499],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017443865,0.00037374487,0.0017647947,0.0021081155,0.00026231134,0.00009364875,0.015224137,0.019137917,0.84814066,0.016455164,0.00084943086,0.09557263],"study_design_scores_gemma":[0.0030386003,0.00033764172,0.025197297,0.00052874704,0.00012126922,0.00008575106,0.0006572734,0.13397364,0.82720155,0.0066938372,0.001081207,0.0010831732],"about_ca_topic_score_codex":0.000057670015,"about_ca_topic_score_gemma":0.000063434105,"teacher_disagreement_score":0.114835724,"about_ca_system_score_codex":0.00003349891,"about_ca_system_score_gemma":0.000006678622,"threshold_uncertainty_score":0.3548951},"labels":[],"label_agreement":null},{"id":"W2062553629","doi":"10.1109/tcad.2010.2061670","title":"Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling","year":2010,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Simulated annealing; Computer science; Field-programmable gate array; Benchmark (surveying); Routing (electronic design automation); Adaptive simulated annealing; Parallel computing; Computer engineering; Algorithm; Embedded system","score_opus":0.015143929766656102,"score_gpt":0.1964224691009992,"score_spread":0.1812785393343431,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2062553629","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021165852,0.00006932933,0.9764448,0.0000030989563,0.0008481058,0.00079264,0.000044449676,0.0005651373,0.000066601875],"genre_scores_gemma":[0.9894301,0.0000130745775,0.010280688,0.00001008885,0.00005734705,0.00011555876,0.000003561778,0.00006348993,0.00002605861],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.998474,0.00007879673,0.0005205341,0.000346709,0.00025934138,0.00032059196],"domain_scores_gemma":[0.99899656,0.00023120039,0.00010874533,0.0002957694,0.00021933354,0.00014837747],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003199404,0.00036412672,0.0004652668,0.0003196986,0.00012398783,0.000106172374,0.00018852686,0.00021180674,0.000011327461],"category_scores_gemma":[0.0000032400787,0.00029413422,0.00006680372,0.00027016248,0.00008337767,0.0001581225,0.0000011701792,0.00064051105,0.000004044899],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000052203533,0.00008162792,0.0000010133539,0.00010641837,0.0001760125,0.000010694271,0.00024516977,0.77882177,0.16084774,0.00012501783,0.00003310326,0.059499227],"study_design_scores_gemma":[0.0005479557,0.0009896804,0.000004703512,0.00041402236,0.00006381413,0.00010467512,0.00021937942,0.97080785,0.02647764,0.000021376416,0.00000542751,0.00034347162],"about_ca_topic_score_codex":0.00015585117,"about_ca_topic_score_gemma":0.000023046627,"teacher_disagreement_score":0.9682643,"about_ca_system_score_codex":0.00008484396,"about_ca_system_score_gemma":0.00007215962,"threshold_uncertainty_score":0.99995106},"labels":[],"label_agreement":null},{"id":"W2064570018","doi":"10.1007/s10586-012-0229-4","title":"The impact of heterogeneous multi-core clusters on graph partitioning: an empirical study","year":2012,"lang":"en","type":"article","venue":"Cluster Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Computer science; Graph partition; Graph; Core (optical fiber); Empirical research; Theoretical computer science; Statistics; Telecommunications","score_opus":0.06011409574486494,"score_gpt":0.34687051547067943,"score_spread":0.2867564197258145,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2064570018","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9509177,0.0001351446,0.047892258,0.0000057686125,0.00021065466,0.00033763575,0.0000020412276,0.00036197447,0.00013682067],"genre_scores_gemma":[0.9988911,0.0000030420742,0.0008597025,0.000033469194,0.00015687164,0.000009459426,0.0000034337081,0.000038075897,0.000004811392],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989232,0.000098291355,0.0003012693,0.00013829314,0.00013908325,0.00039989446],"domain_scores_gemma":[0.9993031,0.00014896263,0.000059304533,0.0003358368,0.000033588152,0.00011921858],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00041668362,0.00018444663,0.00018921467,0.00007574465,0.00018388832,0.000045547604,0.00019300733,0.00006458216,0.0000039876068],"category_scores_gemma":[0.000018935893,0.00012764,0.0001322139,0.0001435302,0.000046293597,0.00009765024,0.00006501603,0.00019189162,0.0000072183007],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006686934,0.001167036,0.40957272,0.000045451834,0.00033799975,0.000010446794,0.014839202,0.54748034,0.0011147414,0.0000109085695,0.0019819736,0.023372283],"study_design_scores_gemma":[0.00071250746,0.0009228143,0.104231745,0.000053987933,0.000030395991,0.00003181934,0.0005191574,0.8913107,0.0017583959,0.0000507337,0.000044957807,0.0003327756],"about_ca_topic_score_codex":0.000017157048,"about_ca_topic_score_gemma":0.0000065322597,"teacher_disagreement_score":0.34383035,"about_ca_system_score_codex":0.00006680631,"about_ca_system_score_gemma":0.0000064781284,"threshold_uncertainty_score":0.52050084},"labels":[],"label_agreement":null},{"id":"W2064997970","doi":"10.1109/reconfig.2011.27","title":"Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Speedup; Parallel computing; Computer science; Simulated annealing; Thread (computing); Scalability; Algorithm","score_opus":0.04431845667615471,"score_gpt":0.2711952791164864,"score_spread":0.2268768224403317,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2064997970","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2156391,0.000083607316,0.7776832,0.0000038869875,0.00010297856,0.00027479124,0.0000065870454,0.0011206707,0.005085199],"genre_scores_gemma":[0.93634486,0.0000145067,0.063438654,0.000045167948,0.000028414317,0.000008407521,0.000027050217,0.000042901895,0.000050055805],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99915236,0.000020752044,0.0002611515,0.00017471131,0.00010791748,0.00028312835],"domain_scores_gemma":[0.9996469,0.000027447048,0.000034908877,0.00017565064,0.00002827228,0.00008683471],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000073719006,0.00018930649,0.00017382143,0.000085643886,0.00007970204,0.000033121818,0.000120754106,0.00011043719,0.00021194557],"category_scores_gemma":[0.000004202684,0.00019303302,0.000049705468,0.000084816595,0.000020013907,0.00013868696,0.000024281058,0.00010552575,0.000028466775],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007453827,0.00015348595,0.0013592754,0.00016113213,0.00020008616,0.000087553846,0.0014914924,0.5242094,0.46434394,0.00022002628,0.0029163533,0.004782746],"study_design_scores_gemma":[0.00029687118,0.00008799265,0.00007168738,0.000054428372,0.000038388152,0.000013699478,0.000034043438,0.8957489,0.10307822,0.00011530036,0.00016319413,0.0002972952],"about_ca_topic_score_codex":0.00006823267,"about_ca_topic_score_gemma":0.0000036449512,"teacher_disagreement_score":0.72070575,"about_ca_system_score_codex":0.00008299339,"about_ca_system_score_gemma":0.000007458934,"threshold_uncertainty_score":0.7871658},"labels":[],"label_agreement":null},{"id":"W2068598660","doi":"10.1016/j.comgeo.2013.10.001","title":"An optimal algorithm for the Euclidean bottleneck full Steiner tree problem","year":2013,"lang":"en","type":"article","venue":"Computational Geometry","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Steiner tree problem; Combinatorics; k-minimum spanning tree; Mathematics; Disjoint sets; Logarithm; K-ary tree; Gomory–Hu tree; Matching (statistics); Tree (set theory); Discrete mathematics; Euclidean minimum spanning tree; Upper and lower bounds; Spanning tree; Tree structure; Minimum degree spanning tree; Binary tree","score_opus":0.01036784220015194,"score_gpt":0.23104368802641279,"score_spread":0.22067584582626085,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2068598660","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0118631255,0.00038965567,0.985803,0.00011154152,0.0001242412,0.00053915003,0.000032347205,0.0004930445,0.00064389256],"genre_scores_gemma":[0.4609056,0.000010793813,0.5380896,0.00012518305,0.0002936437,0.00026854125,0.00010395359,0.00004695188,0.00015573826],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99922633,0.000013604987,0.00020409084,0.00016044642,0.00017270075,0.00022281475],"domain_scores_gemma":[0.99936557,0.00023831322,0.000028538076,0.00016302438,0.00013183594,0.00007272774],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014853588,0.00014434385,0.00012445281,0.00012354301,0.00009896351,0.00010491596,0.00023911645,0.0000691288,0.00015828702],"category_scores_gemma":[0.000008664744,0.000111461544,0.00006929616,0.00022303485,0.000034001554,0.00022796848,0.0000206542,0.000110854315,0.00007713789],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000002906207,0.00003899218,0.00004570784,0.000028744744,0.00006269783,8.823445e-7,0.00006987864,0.27996778,0.0007301494,0.00056407665,0.019598186,0.69889],"study_design_scores_gemma":[0.00022109589,0.00013018124,0.0022889317,0.000008739801,0.000013175104,0.000009645112,0.00004195236,0.9886578,0.00054639706,0.0046782102,0.0032260928,0.00017779377],"about_ca_topic_score_codex":0.000006332267,"about_ca_topic_score_gemma":6.740404e-7,"teacher_disagreement_score":0.70869,"about_ca_system_score_codex":0.000031442778,"about_ca_system_score_gemma":0.000014999072,"threshold_uncertainty_score":0.454527},"labels":[],"label_agreement":null},{"id":"W2069460396","doi":"10.1109/fpl.2009.5272538","title":"Clock gating architectures for FPGA power reduction","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":67,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Clock gating; Digital clock manager; Clock network; Clock domain crossing; CPU multiplier; Field-programmable gate array; Computer science; Gating; Clock skew; Clock signal; Power gating; Reduction (mathematics); Computer hardware; Application-specific integrated circuit; Synchronous circuit; Electronic engineering; Embedded system; Engineering; Jitter; Electrical engineering; Transistor; Voltage; Telecommunications","score_opus":0.007858428311754624,"score_gpt":0.22772239036706296,"score_spread":0.21986396205530834,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2069460396","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20612355,0.00032376597,0.70035464,0.00034255077,0.00028957895,0.0005499884,0.000003864532,0.0037912244,0.088220835],"genre_scores_gemma":[0.96725935,0.0000032795806,0.03228058,0.0000628352,0.00010372273,0.000014548312,0.0000019328745,0.000012336153,0.00026142327],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996478,0.0000036377542,0.00009369831,0.00007728127,0.000044039785,0.00013354828],"domain_scores_gemma":[0.99985033,0.000012057828,0.000008160212,0.00009014416,0.000013885102,0.000025417809],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000055840574,0.000072818235,0.000067202964,0.000047989473,0.000031748918,0.000015787915,0.000048638227,0.000046466987,0.000036181103],"category_scores_gemma":[0.000010401477,0.000064421496,0.000040100498,0.00005121813,0.000005901316,0.000018915745,0.0000023690593,0.00006125128,0.0000043683476],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016674032,0.00003129684,0.00001874605,0.000043019427,0.000026900396,0.0000014381054,0.0006861968,0.010427507,0.45558885,0.007194174,0.051599268,0.47436592],"study_design_scores_gemma":[0.00020523176,0.0002574976,0.00063713396,0.000027519078,0.000009235138,0.000029766537,0.00006982625,0.012822928,0.94628054,0.030519824,0.008835716,0.0003047644],"about_ca_topic_score_codex":0.0000015167685,"about_ca_topic_score_gemma":4.200509e-7,"teacher_disagreement_score":0.7611358,"about_ca_system_score_codex":0.00001545845,"about_ca_system_score_gemma":0.000002289237,"threshold_uncertainty_score":0.26270324},"labels":[],"label_agreement":null},{"id":"W2070101640","doi":"10.1109/fpt.2013.6718328","title":"A case for hardened multiplexers in FPGAs","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Multiplexer; Computer science; Benchmark (surveying); Logic block; Block (permutation group theory); Parallel computing; Lookup table; Logic synthesis; Field-programmable gate array; Routing (electronic design automation); Reduction (mathematics); Logic optimization; Logic gate; Programmable logic device; Computer architecture; Embedded system; Algorithm; Multiplexing; Mathematics; Operating system; Telecommunications","score_opus":0.01650390308304619,"score_gpt":0.21447856431501836,"score_spread":0.19797466123197216,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2070101640","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6876345,0.00012375657,0.28392407,0.00013568292,0.00016735296,0.0017840774,0.000008697601,0.0022024065,0.02401943],"genre_scores_gemma":[0.96950084,0.000005870995,0.029652663,0.00004531582,0.000018030714,0.00031433662,0.0000016807527,0.000016874506,0.00044440536],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99967194,0.0000032221515,0.000094777235,0.00006575204,0.00002394535,0.00014036319],"domain_scores_gemma":[0.9998316,0.000031047923,0.0000040257623,0.00008785715,0.000013474209,0.000031994376],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004335903,0.000063143176,0.00007446184,0.000060339156,0.000011064872,0.000018652581,0.000042168293,0.000046712736,0.00017184319],"category_scores_gemma":[0.000011432878,0.000057141795,0.000026495896,0.000048604787,0.0000057146312,0.00008619809,0.0000056380873,0.000038017984,0.000047209494],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002257169,0.00015964358,0.002385119,0.00054263626,0.00010431414,0.00097293576,0.0022884742,0.0131065305,0.28901654,0.002770549,0.41802362,0.27060705],"study_design_scores_gemma":[0.0015115204,0.00011114299,0.0005694169,0.000033986067,0.000010013727,0.00040350022,0.0004477629,0.706191,0.27427313,0.0037318207,0.012074889,0.00064183044],"about_ca_topic_score_codex":0.00018872657,"about_ca_topic_score_gemma":0.00010026664,"teacher_disagreement_score":0.6930845,"about_ca_system_score_codex":0.000022543114,"about_ca_system_score_gemma":0.0000022073857,"threshold_uncertainty_score":0.23301747},"labels":[],"label_agreement":null},{"id":"W2071575532","doi":"10.1007/s11590-006-0027-0","title":"An ILP based hierarchical global routing approach for VLSI ASIC design","year":2006,"lang":"en","type":"article","venue":"Optimization Letters","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Waterloo","funders":"","keywords":"Routing (electronic design automation); Computer science; Very-large-scale integration; Integer programming; Rounding; Heuristic; Physical design; Parallel computing; Application-specific integrated circuit; Circuit design; Embedded system; Algorithm","score_opus":0.010559122700771837,"score_gpt":0.21219346988723609,"score_spread":0.20163434718646425,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2071575532","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0006359447,0.00001347574,0.99678767,0.00017072323,0.000056669563,0.0004172149,0.000015188693,0.0009509785,0.00095216295],"genre_scores_gemma":[0.34938383,7.751414e-7,0.64978004,0.00041785388,0.000120898236,0.00007681213,0.00018470206,0.000030426028,0.0000046871287],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991796,0.000048718117,0.00019654841,0.00020171006,0.00011638913,0.0002570339],"domain_scores_gemma":[0.99967235,0.00004667157,0.000029370285,0.00017384876,0.000026578922,0.000051157283],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017395774,0.00015300445,0.00012841061,0.00006164554,0.000086149405,0.00008576271,0.00013835204,0.00009287765,0.0000133931135],"category_scores_gemma":[0.000013611849,0.00016496252,0.00005451816,0.00019153144,0.000027072643,0.00017848519,0.0000049055066,0.00007589785,0.000001350472],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008630382,0.00002810539,0.00015710307,0.000017533635,0.0000060284106,0.0000010215138,0.000009990979,0.9894998,0.0042528627,0.00034431615,0.0044701206,0.001204487],"study_design_scores_gemma":[0.00030991886,0.000032329473,0.00008414179,0.000006723505,0.000013604,0.0000020983166,0.0000036456345,0.9958299,0.0033412213,0.000054166147,0.00012348106,0.00019880716],"about_ca_topic_score_codex":0.0000072768526,"about_ca_topic_score_gemma":2.824707e-7,"teacher_disagreement_score":0.34874788,"about_ca_system_score_codex":0.000098487384,"about_ca_system_score_gemma":0.000011877737,"threshold_uncertainty_score":0.67269766},"labels":[],"label_agreement":null},{"id":"W2072249022","doi":"10.1145/360276.360299","title":"Using sparse crossbars within LUT","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":72,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Crossbar switch; Lookup table; Computer science; Parallel computing; Spare part; Overhead (engineering); Path (computing); Routing (electronic design automation); Field-programmable gate array; Cluster (spacecraft); Sparse matrix; Block (permutation group theory); Embedded system; Computer network; Engineering; Mathematics; Telecommunications; Operating system","score_opus":0.05195777177682509,"score_gpt":0.26672345532088737,"score_spread":0.21476568354406228,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2072249022","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.49100685,0.00013914517,0.4134709,0.000011931214,0.00020319854,0.00010148923,0.0000012196671,0.0020274448,0.09303781],"genre_scores_gemma":[0.96539193,0.00002775815,0.033605013,0.000061323684,0.000055709042,0.0000032086118,8.3058563e-7,0.000024256558,0.0008299476],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995963,0.0000044880644,0.00010978008,0.00007470223,0.000062560706,0.00015219123],"domain_scores_gemma":[0.9998003,0.0000061810074,0.0000075220337,0.00013218529,0.000011181846,0.000042622214],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006586244,0.000081361824,0.00007767166,0.00004646648,0.000030897347,0.000032120548,0.00007032834,0.000054496548,0.00023415401],"category_scores_gemma":[0.000004171503,0.00007528416,0.000025768077,0.00010846579,0.000015865568,0.00010546803,0.000010556605,0.00007185688,0.000055804492],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022328344,0.00009078259,0.016753903,0.00010770693,0.00012225492,0.0003443298,0.0013808261,0.099502034,0.7965476,0.0126863485,0.035545085,0.036896795],"study_design_scores_gemma":[0.00036612258,0.00004582569,0.0010206942,0.000054280925,0.000023053952,0.00022984984,0.000119921504,0.63371843,0.3345381,0.0038434549,0.025330406,0.00070982665],"about_ca_topic_score_codex":0.000034274723,"about_ca_topic_score_gemma":0.00001092523,"teacher_disagreement_score":0.5342164,"about_ca_system_score_codex":0.000029184597,"about_ca_system_score_gemma":0.0000053010262,"threshold_uncertainty_score":0.3069999},"labels":[],"label_agreement":null},{"id":"W2072442523","doi":"10.1109/cjece.2003.1425097","title":"Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points","year":2003,"lang":"en","type":"article","venue":"Canadian Journal of Electrical and Computer Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Maxima and minima; Sizing; Heuristics; Heuristic; Mathematical optimization; Point (geometry); Process (computing); Function (biology); Computer science; Algorithm; Mathematics","score_opus":0.010361521872989868,"score_gpt":0.18363426442626268,"score_spread":0.17327274255327282,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2072442523","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021202069,0.00033134015,0.97814125,0.000007436945,0.00014598167,0.00008301136,0.0000054105044,0.000046267298,0.000037244943],"genre_scores_gemma":[0.81837606,0.000012617825,0.18139206,0.000032922337,0.00014926407,0.0000014306248,0.0000037405796,0.00003085213,0.000001067049],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99927145,0.000014682907,0.00024970146,0.0000860226,0.00006636398,0.00031178017],"domain_scores_gemma":[0.9994331,0.00007810941,0.000043734042,0.000047071688,0.00011702763,0.00028094693],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013528661,0.00014746757,0.00020390852,0.00030739882,0.00006893032,0.0000841407,0.00007298266,0.00007434849,0.00000279743],"category_scores_gemma":[0.000053945834,0.00013858358,0.000041206862,0.00026669688,0.000011500253,0.0001510203,0.0000022318034,0.0002448644,6.991903e-8],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000036639485,0.0000036811716,0.00027055744,0.00003743146,0.000063579115,0.000076192046,0.00008232445,0.9943077,0.00030555337,0.0012469362,0.00007184709,0.0035305393],"study_design_scores_gemma":[0.00027823352,0.00015812056,0.000084005405,0.00010435965,0.000030430261,0.0005512199,0.0000046730734,0.99713904,0.00069050025,0.000089538786,0.00068117096,0.00018873031],"about_ca_topic_score_codex":0.00003679837,"about_ca_topic_score_gemma":0.000027818078,"teacher_disagreement_score":0.797174,"about_ca_system_score_codex":0.00014214724,"about_ca_system_score_gemma":0.00016427624,"threshold_uncertainty_score":0.56512743},"labels":[],"label_agreement":null},{"id":"W2075137913","doi":"10.1109/fpl.2012.6339278","title":"Analytical placement for heterogeneous FPGAs","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":90,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Speedup; Computer science; Lookup table; Placement; Logic block; Parallel computing; Simulated annealing; Placer mining; Application-specific integrated circuit; Multiplier (economics); Computer hardware; Algorithm; Embedded system; Physical design; Circuit design","score_opus":0.02502333018816553,"score_gpt":0.2584584849067553,"score_spread":0.2334351547185898,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2075137913","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.035906624,0.0003521984,0.9279589,0.000032830805,0.00021590921,0.00031650413,0.000006064882,0.0011752405,0.034035694],"genre_scores_gemma":[0.9906472,0.000010132194,0.008606801,0.00006571721,0.00012128007,0.00004976864,0.0000036013046,0.000016702625,0.00047879523],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99960935,0.0000026655146,0.00008099666,0.0000451263,0.000046406007,0.00021543915],"domain_scores_gemma":[0.99980825,0.000020345897,0.0000035043104,0.00008954179,0.0000078622115,0.00007051348],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007245281,0.00006450522,0.000068901645,0.000027640883,0.000014876684,0.000008785616,0.00004377238,0.000038980284,0.0001822323],"category_scores_gemma":[0.0000042806737,0.00005529788,0.000041252646,0.000027339347,0.0000058155206,0.00004685477,0.0000076075767,0.000027141388,0.00004312249],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008508344,0.000548431,0.007652237,0.0005460884,0.00074020145,0.000010103934,0.00097272056,0.02416912,0.037454356,0.086180024,0.7021414,0.13950023],"study_design_scores_gemma":[0.0004857619,0.00019225485,0.00018785267,0.00001220277,0.00006109264,0.000031040687,0.00003996427,0.28708822,0.4463539,0.00071257364,0.2642909,0.0005442137],"about_ca_topic_score_codex":7.8143546e-7,"about_ca_topic_score_gemma":4.892105e-7,"teacher_disagreement_score":0.9547406,"about_ca_system_score_codex":0.00002657009,"about_ca_system_score_gemma":0.0000014679625,"threshold_uncertainty_score":0.22549821},"labels":[],"label_agreement":null},{"id":"W2075329791","doi":"10.1109/fpl.2014.6927456","title":"Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Tile; Overlay; Computer science; Field-programmable gate array; Computer architecture; Parallel computing; Embedded system; Operating system; Materials science","score_opus":0.020799726422106934,"score_gpt":0.2053828113265248,"score_spread":0.18458308490441788,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2075329791","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.029327655,0.00003438284,0.9301788,0.00001739031,0.00023797851,0.00014218397,0.000020880507,0.00055306975,0.039487638],"genre_scores_gemma":[0.99553955,0.000005780381,0.0039265994,0.000036675217,0.000047359605,0.000009195443,0.000040097333,0.00002084918,0.00037392537],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993795,0.000022265762,0.00023553701,0.00008847439,0.00016598687,0.00010822946],"domain_scores_gemma":[0.9994944,0.000106031075,0.000046878817,0.00019629052,0.00012057652,0.000035825822],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015630048,0.000104390354,0.0001750967,0.00012884078,0.000018608729,0.0000058523137,0.000080245394,0.00008915041,0.00035533597],"category_scores_gemma":[0.000029337769,0.000098836375,0.000046511937,0.00021314075,0.000027520484,0.00008024779,0.0000090268895,0.00008575416,0.000019193072],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008197343,0.00014624964,0.004754232,0.00084185967,0.00013411493,0.0000010235582,0.0002553228,0.09033145,0.7060945,0.054853242,0.10289923,0.039606776],"study_design_scores_gemma":[0.0004870512,0.00010289963,0.0058004037,0.00005878158,0.000021660775,0.0000011128471,0.000014567434,0.3628611,0.62080455,0.0007969774,0.008846221,0.00020470592],"about_ca_topic_score_codex":0.000016933158,"about_ca_topic_score_gemma":0.0000035572587,"teacher_disagreement_score":0.96621186,"about_ca_system_score_codex":0.00002163994,"about_ca_system_score_gemma":0.000018597326,"threshold_uncertainty_score":0.40304303},"labels":[],"label_agreement":null},{"id":"W2076906193","doi":"10.1142/s1469026805001611","title":"A GENETIC ALGORITHM FOR THE DESIGN OF MINIMUM-COST TWO-CONNECTED NETWORKS WITH BOUNDED RINGS","year":2005,"lang":"en","type":"article","venue":"International Journal of Computational Intelligence and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Brock University; University of Guelph","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Tabu search; Computer science; Bounded function; Genetic algorithm; Algorithm; Mathematical optimization; Network planning and design; Constraint (computer-aided design); Ring (chemistry); Enhanced Data Rates for GSM Evolution; Mathematics; Artificial intelligence; Machine learning; Computer network","score_opus":0.01981469221337038,"score_gpt":0.28029369089475836,"score_spread":0.26047899868138796,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2076906193","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00078458106,0.0007221306,0.99772453,0.00023054013,0.000053332526,0.00040186796,0.0000157124,0.000027062983,0.0000402311],"genre_scores_gemma":[0.6695532,0.00028544586,0.32963264,0.000076863,0.0003192764,0.000106730324,0.000005762072,0.000012206894,0.000007842713],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991878,0.000012517319,0.0004069629,0.00008117067,0.00021905899,0.000092492126],"domain_scores_gemma":[0.9984161,0.0006395021,0.00017361913,0.00006579153,0.0006623922,0.000042558884],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017048598,0.000098887125,0.00012290056,0.00011506641,0.00005963759,0.000054060434,0.0003095524,0.00003204492,0.000012619855],"category_scores_gemma":[0.00001012414,0.00007290301,0.000051938838,0.00012267996,0.000091588256,0.00012035452,0.000013249106,0.00010919543,0.0000013327331],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015711015,0.000025864683,0.000018742856,0.0000024932087,0.0001090668,5.4589185e-7,0.00006048413,0.69899005,0.000072701645,0.0022810595,0.00013359921,0.2982897],"study_design_scores_gemma":[0.00020834892,0.0000749222,0.00024665226,0.00003558572,0.00003703747,0.00013946427,0.000052298703,0.98225725,0.0021066992,0.011959791,0.0027948127,0.000087127395],"about_ca_topic_score_codex":0.0000033381634,"about_ca_topic_score_gemma":0.0000019746694,"teacher_disagreement_score":0.66876864,"about_ca_system_score_codex":0.000037153968,"about_ca_system_score_gemma":0.000043469354,"threshold_uncertainty_score":0.29728982},"labels":[],"label_agreement":null},{"id":"W2077651334","doi":"10.1007/s10470-006-1271-z","title":"Aladin: A Layout Synthesys Tool for Analog Integrated Circuits","year":2006,"lang":"en","type":"article","venue":"Analog Integrated Circuits and Signal Processing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"KU Leuven; Carnegie Mellon University","keywords":"Placement; Simulated annealing; Routing (electronic design automation); Computer science; IC layout editor; Physical design; Integrated circuit layout; Electronic circuit; Generator (circuit theory); Floorplan; Integrated circuit; Computer engineering; Analogue electronics; Electronic engineering; Computer architecture; Circuit design; Circuit extraction; Engineering; Embedded system; Algorithm; Electrical engineering; Voltage; Equivalent circuit","score_opus":0.011801358726977844,"score_gpt":0.21467774635943015,"score_spread":0.2028763876324523,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2077651334","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.108178645,0.0056401957,0.87073535,0.00007340191,0.000165521,0.00093821395,0.00022390626,0.0021861366,0.011858661],"genre_scores_gemma":[0.9980888,0.00007877046,0.0005980784,0.00015934971,0.0002295628,0.00015481436,0.00024163947,0.00011935641,0.00032967707],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99761724,0.000057139874,0.00071762566,0.00058408774,0.00026015632,0.0007637357],"domain_scores_gemma":[0.9989619,0.00014811782,0.00013439474,0.00022117107,0.00038723016,0.00014717616],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00043690318,0.0005761676,0.0006416522,0.00042971986,0.00033885444,0.00043404076,0.00030679416,0.00040085215,0.00008011497],"category_scores_gemma":[0.00005599094,0.00049612945,0.00016579311,0.0007977213,0.00014851519,0.00051074324,0.000019015184,0.0005091713,0.000010971182],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023860304,0.00013124481,0.0016893505,0.00067274115,0.00020237544,0.000070147515,0.00035686258,0.0013241953,0.16338891,0.002862227,0.008172323,0.8211058],"study_design_scores_gemma":[0.0032309652,0.0013139177,0.0038731738,0.0039201234,0.00090183126,0.0005212755,0.0015930218,0.68653256,0.21800822,0.03534404,0.039317552,0.005443345],"about_ca_topic_score_codex":0.00019966594,"about_ca_topic_score_gemma":0.00008138363,"teacher_disagreement_score":0.8899101,"about_ca_system_score_codex":0.00014435014,"about_ca_system_score_gemma":0.00014851909,"threshold_uncertainty_score":0.999749},"labels":[],"label_agreement":null},{"id":"W2078041678","doi":"10.1145/1952522.1952530","title":"Evaluating address register assignment and offset assignment algorithms","year":2011,"lang":"en","type":"article","venue":"ACM Transactions on Embedded Computing Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Computer science; Heuristics; Offset (computer science); Parallel computing; Partition (number theory); Algorithm; Computation; Overhead (engineering); Heuristic; Optimization problem; Register allocation; Assignment problem; Mathematical optimization; Mathematics","score_opus":0.10640099779316,"score_gpt":0.3076893389529483,"score_spread":0.20128834115978833,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2078041678","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016459225,0.00034427724,0.97728634,0.000016109761,0.00095754344,0.0006406237,0.000017334152,0.0011504797,0.0031280925],"genre_scores_gemma":[0.97257453,0.00003485389,0.026911441,0.000034718774,0.00010228774,0.00010093627,0.0000049005694,0.000064556465,0.00017180259],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99817646,0.00014842607,0.0005183886,0.00038868104,0.0003814119,0.00038665946],"domain_scores_gemma":[0.99888366,0.00015283686,0.000095796575,0.0006769948,0.00005523925,0.00013548703],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006506126,0.0003064959,0.00033633006,0.00017618804,0.00022613678,0.0000946473,0.0003014699,0.00016235551,0.000037771257],"category_scores_gemma":[0.000012983903,0.00029956203,0.00008394141,0.00016625806,0.000044883254,0.00012471639,0.000012786035,0.00032770753,0.000025208676],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000881059,0.000558541,0.00020324967,0.0010206536,0.000997003,0.000077591045,0.018474605,0.19653049,0.020943506,0.00055331516,0.0027040322,0.7578489],"study_design_scores_gemma":[0.0012083765,0.00072714634,0.00029471747,0.0009387408,0.00016356022,0.00016697368,0.0018713457,0.9645092,0.0279443,0.00038739707,0.0008083638,0.0009798646],"about_ca_topic_score_codex":0.00005944099,"about_ca_topic_score_gemma":0.0000016811246,"teacher_disagreement_score":0.9561153,"about_ca_system_score_codex":0.0001682377,"about_ca_system_score_gemma":0.000015402295,"threshold_uncertainty_score":0.99994564},"labels":[],"label_agreement":null},{"id":"W2078579271","doi":"10.1109/fpt.2010.5681497","title":"The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Datapath; Routing (electronic design automation); Computer science; Field-programmable gate array; Multipath routing; Place and route; Computer architecture; Parallel computing; Embedded system; Static routing; Computer network; Routing protocol","score_opus":0.01381953391687251,"score_gpt":0.22682393280409766,"score_spread":0.21300439888722514,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2078579271","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.95475423,0.00005456074,0.022214118,0.0000932166,0.0002443103,0.00030206528,0.0000056749586,0.0004238349,0.021908006],"genre_scores_gemma":[0.9994289,0.0000038553917,0.00042574416,0.000009993987,0.000026156838,0.00002704418,7.4240216e-7,0.000015137472,0.000062400155],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99934745,0.00006781116,0.00019965666,0.00009502695,0.00014524856,0.0001448349],"domain_scores_gemma":[0.99766374,0.0019671756,0.00004914264,0.00025664325,0.000041106945,0.000022174228],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0007616086,0.00010896198,0.00012467537,0.000065407236,0.00021915996,0.000018150145,0.00018085117,0.00006520772,0.00005536876],"category_scores_gemma":[0.00034740035,0.000057071367,0.000089390196,0.00020663436,0.000104782535,0.00002402893,0.000015102651,0.00025988667,0.0000023331995],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006582238,0.00011051881,0.007981585,0.000107451495,0.00012329765,0.0000013019924,0.0005774141,0.028981429,0.9252423,0.017696152,0.001406667,0.01770606],"study_design_scores_gemma":[0.00014660266,0.00013240206,0.0008693324,0.000036593698,0.000011825404,0.0000017066242,0.0000927996,0.25494155,0.74278414,0.00002654827,0.0008879299,0.00006852791],"about_ca_topic_score_codex":0.00006109007,"about_ca_topic_score_gemma":0.000065581255,"teacher_disagreement_score":0.22596014,"about_ca_system_score_codex":0.000012302621,"about_ca_system_score_gemma":0.00000802536,"threshold_uncertainty_score":0.23273028},"labels":[],"label_agreement":null},{"id":"W2079078065","doi":"10.1145/785411.785413","title":"Gravity","year":2003,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Computer science; Electronic circuit; Algorithm; Iterative method; Computer engineering; Time complexity; Electrical engineering","score_opus":0.015426394018364126,"score_gpt":0.2255704286877004,"score_spread":0.21014403466933626,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2079078065","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.002689606,0.00048636587,0.99377424,0.000010194404,0.00021657175,0.00046631962,0.000004433995,0.00093967153,0.0014125722],"genre_scores_gemma":[0.99350643,0.00010843625,0.005971024,0.0000062542863,0.000010567313,0.00014891704,0.0000021491796,0.00003198677,0.00021422628],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9988742,0.00015693228,0.0003413359,0.00014221085,0.00019747586,0.00028788345],"domain_scores_gemma":[0.9992534,0.0001507765,0.000057585563,0.00043878812,0.00005433093,0.000045116794],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00044571562,0.00015989906,0.00021615879,0.0002157078,0.00006510258,0.000022356495,0.00018039184,0.00012464085,0.00007548283],"category_scores_gemma":[0.000025674988,0.0001649161,0.00007880183,0.0003234461,0.00002066246,0.00014009773,4.7414224e-7,0.00018052918,0.000051805622],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000034614506,0.0003136939,0.000022091064,0.0004461633,0.000454679,0.0000032963558,0.0004747078,0.7823825,0.13467798,0.035855886,0.0032011159,0.042133268],"study_design_scores_gemma":[0.0008583309,0.00077478215,0.00008384243,0.00017732293,0.00010250298,0.00009812932,0.00013141429,0.20160297,0.7769831,0.011682808,0.006841012,0.0006638199],"about_ca_topic_score_codex":0.000008585549,"about_ca_topic_score_gemma":0.0000015512329,"teacher_disagreement_score":0.99081683,"about_ca_system_score_codex":0.00018923379,"about_ca_system_score_gemma":0.00005182712,"threshold_uncertainty_score":0.6725083},"labels":[],"label_agreement":null},{"id":"W2080270089","doi":"10.1145/1950413.1950443","title":"Towards scalable FPGA CAD through architecture","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Computer science; Scalability; Compiler; Scaling; CAD; Computer architecture; FPGA prototype; Architecture; Embedded system; Compile time; Parallel computing; Operating system; Engineering","score_opus":0.025525260103283196,"score_gpt":0.21630205378366474,"score_spread":0.19077679368038153,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2080270089","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003375169,0.00018720655,0.38146007,0.000019572946,0.0000978756,0.00008667239,0.0000029290372,0.0016205594,0.61314994],"genre_scores_gemma":[0.8986546,0.00007398169,0.09937791,0.00017078694,0.00007168357,0.00002466955,0.0000024885164,0.00003817849,0.0015857359],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99949867,0.0000069125595,0.00010330559,0.000104374936,0.00007738237,0.00020933677],"domain_scores_gemma":[0.99972963,0.0000053970384,0.0000065881613,0.00020182406,0.0000138132245,0.0000427403],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000046378085,0.00011633333,0.000109888286,0.000034335182,0.000024243678,0.000012107805,0.00014195906,0.00008906937,0.0010728475],"category_scores_gemma":[0.000004256736,0.00009397586,0.000044200282,0.000101211015,0.000021460455,0.00009421322,0.000021037327,0.00013378127,0.0001248312],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000032281892,0.0001878806,0.0009195931,0.0003855765,0.00026917816,0.0001126581,0.012739244,0.000730287,0.051941235,0.057656717,0.28602958,0.58899575],"study_design_scores_gemma":[0.00015808336,0.00008007647,0.00078381563,0.000023742805,0.000014791362,0.000027174356,0.00006041356,0.00082259387,0.884717,0.04250035,0.07041455,0.0003974052],"about_ca_topic_score_codex":0.00020246263,"about_ca_topic_score_gemma":0.000015664862,"teacher_disagreement_score":0.8952794,"about_ca_system_score_codex":0.000017456287,"about_ca_system_score_gemma":0.000006761817,"threshold_uncertainty_score":0.9998403},"labels":[],"label_agreement":null},{"id":"W2081801059","doi":"10.1016/j.mejo.2008.09.008","title":"Hardware accelerated FPGA placement","year":2008,"lang":"en","type":"article","venue":"Microelectronics Journal","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Scalability; Logic block; Routing (electronic design automation); Key (lock); Exploit; Realization (probability); Embedded system; Reconfigurable computing; FPGA prototype; Parallel computing; Computer architecture; Computer hardware; Mathematics","score_opus":0.02006410535247706,"score_gpt":0.22023026365916776,"score_spread":0.2001661583066907,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2081801059","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7340391,0.015173303,0.23677506,0.00020010934,0.000680698,0.00035747595,0.000013185875,0.0016749133,0.011086114],"genre_scores_gemma":[0.9926023,0.0043458263,0.0021001059,0.000107367894,0.00021310772,0.000008462026,0.000008052004,0.000055043274,0.00055976893],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9989304,0.000023805796,0.00026037937,0.00010728713,0.00016180363,0.00051634636],"domain_scores_gemma":[0.99962294,0.0000106139505,0.000038545142,0.00013789613,0.000074913565,0.00011509746],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014426452,0.00017578401,0.00017055735,0.00012706753,0.0002312117,0.000064008775,0.0002240172,0.00009032786,0.00029663823],"category_scores_gemma":[0.000006134967,0.00016914125,0.00008635692,0.00016599795,0.000023132867,0.00015244017,0.00001703986,0.0006517205,0.000068542395],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000035733567,0.000081321705,0.0003198652,0.00002814302,0.00023411956,0.00034789118,0.0006121452,0.0051731896,0.63948876,0.00013160103,0.33535886,0.018188372],"study_design_scores_gemma":[0.00082143885,0.000295058,0.00018970587,0.00003589346,0.000024990888,0.005495248,0.000031810087,0.0042361775,0.7749195,0.00043619037,0.213023,0.00049098226],"about_ca_topic_score_codex":0.0000012797643,"about_ca_topic_score_gemma":0.0000022253532,"teacher_disagreement_score":0.25856313,"about_ca_system_score_codex":0.00032094566,"about_ca_system_score_gemma":0.000098067074,"threshold_uncertainty_score":0.689738},"labels":[],"label_agreement":null},{"id":"W2083045602","doi":"10.1007/s10957-012-0036-3","title":"Gradient-Constrained Minimum Networks. III. Fixed Topology","year":2012,"lang":"en","type":"article","venue":"Journal of Optimization Theory and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Mathematics; Embedding; Topology (electrical circuits); Network topology; Theory of computation; Combinatorics; Heuristic; Discrete mathematics; Mathematical optimization; Algorithm; Computer science","score_opus":0.006527470420823994,"score_gpt":0.221985977791401,"score_spread":0.215458507370577,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2083045602","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019818887,0.001261257,0.9941438,0.000043374504,0.000096194264,0.00011701734,0.0000018081158,0.000065242944,0.0022894053],"genre_scores_gemma":[0.98017925,0.00068207725,0.018662244,0.00006519723,0.00030836058,0.00002445131,0.000005924396,0.00001276591,0.000059719532],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99951005,0.00004150278,0.00024219602,0.000040790223,0.00004210866,0.0001233365],"domain_scores_gemma":[0.99958646,0.00010432982,0.00008956999,0.00007940401,0.000051412073,0.00008883737],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00040042365,0.000072586634,0.00011866024,0.00008318984,0.00006818491,0.000014806037,0.00007271895,0.00006619911,0.00008344874],"category_scores_gemma":[0.000012992686,0.00006495093,0.000036934252,0.00011848129,0.000061008122,0.00017635834,0.000007815619,0.00010390723,0.000001284806],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000049406848,0.00013646914,0.00052715297,0.00002887825,0.00012781897,0.0000012700617,0.00055011385,0.5515896,0.00154713,0.408764,0.002475184,0.034202993],"study_design_scores_gemma":[0.0056548393,0.00068254705,0.0017661374,0.00022529319,0.0010329016,0.0017851276,0.00433145,0.7559964,0.021022297,0.11189163,0.0933197,0.0022916615],"about_ca_topic_score_codex":1.0985302e-7,"about_ca_topic_score_gemma":5.8900266e-8,"teacher_disagreement_score":0.9781974,"about_ca_system_score_codex":0.000013751838,"about_ca_system_score_gemma":0.00000618721,"threshold_uncertainty_score":0.2648622},"labels":[],"label_agreement":null},{"id":"W2083109774","doi":"10.1109/fpt.2010.5681478","title":"Technology issues facing the world's largest integrated circuits","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Stratix; Field-programmable gate array; Control reconfiguration; Computer science; Embedded system; Computer architecture; Software; Process (computing); Reconfigurable computing; Operating system","score_opus":0.0072085983648260705,"score_gpt":0.22660405367358114,"score_spread":0.21939545530875507,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2083109774","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.29445535,0.0014694494,0.15010144,0.0071062995,0.0020712696,0.0010598657,0.000020143356,0.026788658,0.51692754],"genre_scores_gemma":[0.99334055,0.000027638447,0.002351999,0.00009798046,0.00006343856,0.000032010877,0.000002830773,0.000025475792,0.004058082],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994959,0.000006699482,0.00012115195,0.000104369225,0.00006281897,0.00020901834],"domain_scores_gemma":[0.9995946,0.000027624239,0.000010503126,0.00029544692,0.000045025572,0.000026766109],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011719974,0.00011774458,0.00010790544,0.00018629839,0.000061827726,0.000040549385,0.0002597889,0.00012312678,0.00045425916],"category_scores_gemma":[0.00003698911,0.00007539803,0.000027413562,0.0004617915,0.000056676512,0.000070164984,0.000025103871,0.0005084306,0.00012879286],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[5.465541e-7,0.00001804503,0.0021047029,0.000016266475,0.00003862541,0.000010698681,0.00013368888,0.00003302306,0.7463648,0.051861968,0.051055636,0.14836203],"study_design_scores_gemma":[0.000068986956,0.000014164235,0.00022117427,0.000014669002,0.000007130002,0.000019786234,0.00012060386,0.0029034244,0.6484608,0.0035203393,0.34444433,0.00020461301],"about_ca_topic_score_codex":0.000031490807,"about_ca_topic_score_gemma":0.00047868438,"teacher_disagreement_score":0.6988852,"about_ca_system_score_codex":0.000010928772,"about_ca_system_score_gemma":0.0000058714536,"threshold_uncertainty_score":0.49738193},"labels":[],"label_agreement":null},{"id":"W2083536322","doi":"10.1109/fpt.2011.6132684","title":"Accelerated FPGA architecture design: Capabilities and limitations of analytical models","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Architecture; Computer science; Limiting; Computer architecture; Design methods; Embedded system; Computer engineering; Engineering","score_opus":0.16930945802324854,"score_gpt":0.24451128658917584,"score_spread":0.0752018285659273,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2083536322","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.030800123,0.00012531293,0.9024069,0.000012492299,0.000013747263,0.00013911247,0.0000034261177,0.00039757858,0.06610136],"genre_scores_gemma":[0.93705416,0.000089013294,0.062684484,0.000012644037,0.000006196326,0.000013592634,0.0000012787884,0.000012738505,0.00012589848],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996065,0.000017068507,0.00013764737,0.000079024125,0.000052416468,0.00010733824],"domain_scores_gemma":[0.99968034,0.00011745029,0.000008589394,0.00011206457,0.00003746825,0.000044074743],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0000657577,0.00008400432,0.0001200683,0.00008291436,0.000015577949,0.000008200314,0.000059695372,0.00006153855,0.000053393793],"category_scores_gemma":[0.000023366396,0.000070118054,0.00002351473,0.00009297178,0.000060311366,0.00009093882,0.0000106935895,0.00007325103,0.0000013904042],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018253912,0.000516005,0.00090206886,0.0009054643,0.00091007526,0.000031286174,0.059296854,0.17609356,0.06731833,0.33287337,0.01680611,0.3441643],"study_design_scores_gemma":[0.00023060014,0.00022808707,0.00093632156,0.000028667413,0.00005487827,0.000013484222,0.0005404912,0.65123767,0.20798652,0.13821006,0.00017883806,0.00035437394],"about_ca_topic_score_codex":0.00002169729,"about_ca_topic_score_gemma":0.000007166511,"teacher_disagreement_score":0.90625405,"about_ca_system_score_codex":0.000007267047,"about_ca_system_score_gemma":0.000007729168,"threshold_uncertainty_score":0.2859331},"labels":[],"label_agreement":null},{"id":"W2083862022","doi":"10.1109/cjece.2009.5443860","title":"Near-linear wirelength estimation for FPGA placement","year":2009,"lang":"en","type":"article","venue":"Canadian Journal of Electrical and Computer Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Very-large-scale integration; Routing (electronic design automation); Placement; Reduction (mathematics); Path (computing); Critical path method; Parallel computing; Electronic design automation; Physical design; Static timing analysis; Circuit design; Algorithm; Computer engineering; Embedded system; Mathematics; Engineering","score_opus":0.005705714384969595,"score_gpt":0.18362591248853244,"score_spread":0.17792019810356285,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2083862022","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.042309463,0.0010706397,0.95623463,0.000078007404,0.0001358173,0.00008513036,0.0000016038082,0.00005894338,0.000025734922],"genre_scores_gemma":[0.9361261,0.000033351826,0.06351984,0.000064760716,0.00023571766,0.0000013055746,0.0000015054064,0.000012633473,0.000004751971],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99945605,0.0000033824713,0.00019761604,0.000058180347,0.000056303637,0.00022844372],"domain_scores_gemma":[0.9995775,0.00004209475,0.00002211132,0.000045351688,0.00004190046,0.00027104575],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000084529,0.000101356156,0.00014880965,0.00015127216,0.000042597967,0.00005289673,0.00007932523,0.000053051233,0.0000025257239],"category_scores_gemma":[0.000016052643,0.000098296885,0.000058375943,0.00011667905,0.000005894758,0.000091407805,0.0000015888833,0.0001475353,4.7214178e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000055323117,0.0000051357374,0.000040492116,0.000029852672,0.000043087,0.000026596204,0.00010154758,0.7228489,0.00041501084,0.0009944263,0.0028067764,0.27268267],"study_design_scores_gemma":[0.00018612522,0.00035308045,0.00054051564,0.00003590624,0.0000130260705,0.000082372,5.5998026e-7,0.99272317,0.000992195,0.00019395704,0.0047626435,0.00011642861],"about_ca_topic_score_codex":0.000009354465,"about_ca_topic_score_gemma":0.000005840641,"teacher_disagreement_score":0.89381665,"about_ca_system_score_codex":0.00007639961,"about_ca_system_score_gemma":0.000057118323,"threshold_uncertainty_score":0.40084308},"labels":[],"label_agreement":null},{"id":"W2085192605","doi":"10.1109/ccece.2010.5575207","title":"An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Benchmark (surveying); Computer science; Memetic algorithm; Parallel computing; Very-large-scale integration; Suite; Algorithm; Local search (optimization); Embedded system","score_opus":0.05853442763360185,"score_gpt":0.27395896865226366,"score_spread":0.21542454101866182,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2085192605","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.19449313,0.000005873406,0.804319,0.000014840971,0.00017851104,0.00025893401,0.000006960568,0.0004984926,0.00022422509],"genre_scores_gemma":[0.7713025,0.0000026062207,0.2284687,0.00005445523,0.00005305234,0.000054512468,0.000030010537,0.000019059551,0.000015094134],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994816,0.000007305211,0.00017904415,0.000120220684,0.00007812825,0.00013371241],"domain_scores_gemma":[0.9996319,0.000049487247,0.000028144565,0.00017742591,0.00004579409,0.00006727395],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013635629,0.00009839323,0.00011902629,0.00007925904,0.00003642451,0.000018910181,0.00009524984,0.00008526188,0.000021217797],"category_scores_gemma":[0.000010847872,0.000095690186,0.000040756415,0.0000696987,0.000034732,0.00011686727,0.000004541459,0.000106721745,0.000004024738],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007283972,0.00010099266,0.0033151389,0.00020726564,0.000059885486,0.0000020412197,0.0012655625,0.020563077,0.8937386,0.024169056,0.0025687583,0.054002307],"study_design_scores_gemma":[0.00038885436,0.00017862704,0.0038761406,0.00003249378,0.000012208151,0.0000021060403,0.000033024025,0.7946817,0.19610555,0.004377402,0.000124816,0.00018704792],"about_ca_topic_score_codex":0.000015784435,"about_ca_topic_score_gemma":0.00001874818,"teacher_disagreement_score":0.77411866,"about_ca_system_score_codex":0.0000113002825,"about_ca_system_score_gemma":0.0000069780504,"threshold_uncertainty_score":0.39021325},"labels":[],"label_agreement":null},{"id":"W2087803527","doi":"10.1145/2591513.2591543","title":"Forward-scaling, serially equivalent parallelism for FPGA placement","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Parallel computing; Computer science; Thread (computing); Field-programmable gate array; Critical path method; Scaling; Parallelism (grammar); Embedded system; Mathematics","score_opus":0.014784273811161121,"score_gpt":0.2369868628952145,"score_spread":0.22220258908405338,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2087803527","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0035680002,0.000060488586,0.9633141,0.000088524626,0.00032842206,0.00043139252,0.0000060874804,0.0012100799,0.030992886],"genre_scores_gemma":[0.92833483,0.00007267725,0.068113685,0.00030505107,0.00043720775,0.00031682593,0.000025816697,0.000068928945,0.0023249912],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9992464,0.000010664375,0.00020953006,0.00014644867,0.000107839776,0.00027906895],"domain_scores_gemma":[0.999621,0.000044706136,0.000017714157,0.00021231748,0.000029273437,0.00007499614],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00025809353,0.0001450284,0.0001646241,0.00004622879,0.000040882293,0.000036772093,0.00014339192,0.00008531133,0.00019783867],"category_scores_gemma":[0.000017695022,0.00012901137,0.00008547156,0.000035306985,0.00001023115,0.00006455042,0.000023626992,0.000054177286,0.00003928367],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000115291514,0.0001491135,0.00010013255,0.0008203029,0.00030267666,0.0000030983172,0.0007493909,0.039258186,0.080586046,0.09298268,0.57352567,0.21140741],"study_design_scores_gemma":[0.0012519712,0.000358875,0.00007288846,0.000046515088,0.000042715146,0.0000038186654,0.000045465214,0.17894487,0.19979729,0.009843693,0.6089651,0.0006268207],"about_ca_topic_score_codex":0.000004621024,"about_ca_topic_score_gemma":0.000005400641,"teacher_disagreement_score":0.92476684,"about_ca_system_score_codex":0.000038106664,"about_ca_system_score_gemma":0.000006053102,"threshold_uncertainty_score":0.5260931},"labels":[],"label_agreement":null},{"id":"W2089047137","doi":"10.1145/1785481.1785581","title":"Performance-constrained template-driven retargeting for analog and RF layouts","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Parasitic extraction; Retargeting; Computer science; Integrated circuit layout; Netlist; Radio frequency; RLC circuit; Electronic engineering; IC layout editor; Page layout; Integer programming; Circuit extraction; Computer engineering; Algorithm; Integrated circuit; Engineering; Equivalent circuit; Computer hardware; Capacitor; Artificial intelligence; Electrical engineering","score_opus":0.009048149737708785,"score_gpt":0.2054912267173273,"score_spread":0.19644307697961852,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2089047137","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9382683,0.000022331002,0.024985477,0.000029345938,0.0001482531,0.00024724167,0.0000091366865,0.0008979069,0.035392016],"genre_scores_gemma":[0.97195333,0.000022525195,0.027736237,0.00002446403,0.000073258816,0.000026069045,0.000007834232,0.000019873822,0.00013641191],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999556,0.000002152391,0.00012186592,0.000101961574,0.000040953357,0.00017706824],"domain_scores_gemma":[0.9997788,0.000036768495,0.000012112142,0.00009914576,0.000021541851,0.000051644576],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011579837,0.00009614262,0.0001093177,0.0000549444,0.000057079655,0.000024526216,0.00006334721,0.00009203841,0.0000665714],"category_scores_gemma":[0.000010955061,0.000084698266,0.000026499181,0.000044973945,0.000029588276,0.000101642174,0.000011212208,0.00012824267,0.0000051047114],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013890673,0.000015613809,0.04211517,0.00029599082,0.000066852364,0.00000404391,0.00041571254,0.00033780627,0.86662537,0.0027360246,0.0067047933,0.08066873],"study_design_scores_gemma":[0.0009051385,0.00021865145,0.011999196,0.000054531807,0.000042909604,0.000062239254,0.00009128647,0.6044683,0.36334443,0.00076967914,0.01726207,0.0007815647],"about_ca_topic_score_codex":0.0000038847047,"about_ca_topic_score_gemma":0.000014598443,"teacher_disagreement_score":0.6041305,"about_ca_system_score_codex":0.000004834639,"about_ca_system_score_gemma":0.0000051628926,"threshold_uncertainty_score":0.3453895},"labels":[],"label_agreement":null},{"id":"W2089448319","doi":"10.4028/www.scientific.net/amr.706-708.1890","title":"Implementing Sparse Matrix Ordering Using Hypergraph Partitioning","year":2013,"lang":"en","type":"article","venue":"Advanced materials research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Division of Electrical, Communications and Cyber Systems","keywords":"Hypergraph; Cholesky decomposition; Sparse matrix; Computer science; Scheme (mathematics); Vertex (graph theory); Matrix (chemical analysis); Algorithm; Heuristic; Theoretical computer science; Combinatorics; Mathematics; Mathematical optimization; Graph; Eigenvalues and eigenvectors; Materials science; Computational chemistry","score_opus":0.060075169194913985,"score_gpt":0.3705282381566178,"score_spread":0.31045306896170377,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2089448319","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9834484,0.0002828545,0.012959432,0.000021418979,0.00020194681,0.0005595054,0.000011109543,0.00068261457,0.0018327279],"genre_scores_gemma":[0.96750164,0.00022232675,0.03168601,0.00000729736,0.00013865909,0.00025535643,0.000013050499,0.00007183398,0.00010384641],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9980173,0.00009130907,0.00034840408,0.00022976658,0.00030556272,0.0010076214],"domain_scores_gemma":[0.99935216,0.000071805225,0.000029705225,0.0002874609,0.0001599813,0.00009888332],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0008288883,0.00016099254,0.00021346274,0.0002640068,0.00031447312,0.00027203793,0.0002071169,0.000074981675,0.0016130212],"category_scores_gemma":[0.000059223374,0.0001662602,0.00003230287,0.00036343336,0.000053070562,0.00059111457,0.0001544755,0.0001817449,0.0001969186],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000003165664,0.0000068054865,0.00008983431,0.0000977519,0.000012422358,0.0000054094603,0.000052376912,0.0014121318,0.99064356,0.00044817172,0.0002485744,0.00697981],"study_design_scores_gemma":[0.00017804143,0.000030873394,0.00015380683,0.00009837315,0.0000037720606,0.000010114685,0.00017535925,0.0032852986,0.9883966,0.003679008,0.0037646831,0.00022409562],"about_ca_topic_score_codex":0.00020322276,"about_ca_topic_score_gemma":0.000008917728,"teacher_disagreement_score":0.01872658,"about_ca_system_score_codex":0.00008796259,"about_ca_system_score_gemma":0.000015566397,"threshold_uncertainty_score":0.99929965},"labels":[],"label_agreement":null},{"id":"W2089561452","doi":"10.1145/378239.378464","title":"On optimum switch box designs for 2-D FPGAs","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"Field-programmable gate array; Computer science; Parallel computing; S-box; Embedded system; Computer architecture; Cryptography; Algorithm","score_opus":0.030355443947766562,"score_gpt":0.25191157192334973,"score_spread":0.22155612797558316,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2089561452","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0069608483,0.00004767114,0.9018083,0.00006814971,0.00009384346,0.0002766111,0.0000022677818,0.0013583037,0.08938396],"genre_scores_gemma":[0.94603115,0.000077128214,0.049617544,0.00024769752,0.00010241041,0.00013009769,0.000005582371,0.00005128588,0.0037370936],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999495,0.0000045004995,0.00010754733,0.00010957827,0.00006569495,0.00021766362],"domain_scores_gemma":[0.9996887,0.0000682654,0.000007036853,0.00016390248,0.000019852801,0.000052276944],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008643514,0.00011121909,0.00010312254,0.00006186616,0.00003307997,0.00002283202,0.000099904355,0.000074988195,0.00022322638],"category_scores_gemma":[0.000012732317,0.00009817794,0.00005368586,0.000079262616,0.00000664475,0.000060397426,0.000005994965,0.000063470565,0.00007772794],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009890443,0.00018345239,0.00020034061,0.00014539705,0.00012928495,0.000043164127,0.0002864837,0.022721304,0.12783587,0.06339442,0.65444374,0.13051765],"study_design_scores_gemma":[0.0011990124,0.0007651076,0.00014826741,0.00008346425,0.00003916451,0.000038569586,0.000059518836,0.17830913,0.63713807,0.04411599,0.13707125,0.0010324803],"about_ca_topic_score_codex":0.00000470514,"about_ca_topic_score_gemma":0.000002964329,"teacher_disagreement_score":0.9390703,"about_ca_system_score_codex":0.000031547745,"about_ca_system_score_gemma":0.000004258203,"threshold_uncertainty_score":0.40035802},"labels":[],"label_agreement":null},{"id":"W2089966668","doi":"10.1145/1950413.1950484","title":"Regular fabric for regular FPGA (abstract only)","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Tile; Design for manufacturability; Computer science; Overhead (engineering); Routing (electronic design automation); Block (permutation group theory); Reduction (mathematics); Process (computing); Embedded system; Process variation; Computer hardware; Engineering; Electrical engineering; Mathematics; Materials science","score_opus":0.03177274203603166,"score_gpt":0.20736196025286913,"score_spread":0.17558921821683746,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2089966668","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04514934,0.0005998382,0.70390636,0.000043462125,0.00036310856,0.00089158706,0.000016516162,0.0047368933,0.24429287],"genre_scores_gemma":[0.94831175,0.000043362812,0.048542183,0.000045917892,0.00009234604,0.00006522914,0.000008652791,0.000059508096,0.0028310486],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99932736,0.0000044174526,0.00018080459,0.0001494432,0.00008255768,0.00025540212],"domain_scores_gemma":[0.99955773,0.00001924054,0.000017304057,0.00030447674,0.000032636883,0.000068620924],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001339958,0.00014377064,0.0001486896,0.00008353551,0.000034493543,0.000016474261,0.00017075705,0.00011997632,0.0003722034],"category_scores_gemma":[0.000011544446,0.00013234226,0.00009339898,0.00008936709,0.00001969766,0.00013166005,0.000013016128,0.00007887476,0.00005693981],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006352108,0.00025100596,0.00096445566,0.0006691967,0.0003472653,0.000048546222,0.00123156,0.0001190795,0.15592028,0.07495885,0.34879848,0.41662773],"study_design_scores_gemma":[0.0003891761,0.00016347764,0.005072801,0.000041121726,0.00004063577,0.000027691689,0.00007626115,0.0025997588,0.8861402,0.023934588,0.080907695,0.00060656614],"about_ca_topic_score_codex":0.000019796576,"about_ca_topic_score_gemma":0.0000053776002,"teacher_disagreement_score":0.9031624,"about_ca_system_score_codex":0.00002765624,"about_ca_system_score_gemma":0.000009814511,"threshold_uncertainty_score":0.53967613},"labels":[],"label_agreement":null},{"id":"W2090857935","doi":"10.5555/2840819.2840891","title":"High Performance Global Placement and Legalization Accounting for Fence Regions","year":2015,"lang":"en","type":"article","venue":"International Conference on Computer Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Calgary","funders":"","keywords":"Legalization; Fence (mathematics); Heuristic; Computer science; Routing (electronic design automation); CONTEST; Process (computing); Placement; Engineering; Artificial intelligence; Physical design; Embedded system; Circuit design; Structural engineering","score_opus":0.08343816140693223,"score_gpt":0.2823405100214152,"score_spread":0.19890234861448297,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2090857935","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011514889,0.00001729064,0.9855385,0.00022904556,0.00063555216,0.00027834572,0.0000129514465,0.000310815,0.0014626241],"genre_scores_gemma":[0.90752834,0.000037458747,0.09194172,0.00015197328,0.00018533587,0.00006560727,0.000023088762,0.000012111665,0.000054335294],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992511,0.000019556397,0.00018699502,0.00018817847,0.00020763293,0.00014649714],"domain_scores_gemma":[0.99951386,0.00003851256,0.000043671476,0.0001067885,0.00023388854,0.000063269465],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020090326,0.00013872853,0.00011367644,0.00006932074,0.00004563019,0.00016103132,0.0002059617,0.000056431316,0.000009966756],"category_scores_gemma":[0.000017326809,0.00014046319,0.000016433336,0.000066358465,0.00002393847,0.0002912535,0.000033318305,0.00006530283,0.0000105629615],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003173534,0.0001134754,0.0010457959,0.000104220024,0.00020390727,0.0000121159455,0.000676496,0.35740513,0.0025140143,0.4421077,0.081293225,0.11420657],"study_design_scores_gemma":[0.00046868902,0.00025531306,0.00034637758,0.00009992573,0.0000066366338,0.000012783706,0.000016045647,0.98720175,0.00285041,0.0076798014,0.0008779014,0.0001843889],"about_ca_topic_score_codex":0.0000073776346,"about_ca_topic_score_gemma":0.0000011759961,"teacher_disagreement_score":0.8960135,"about_ca_system_score_codex":0.00013684468,"about_ca_system_score_gemma":0.000040954787,"threshold_uncertainty_score":0.5727923},"labels":[],"label_agreement":null},{"id":"W2091956800","doi":"10.1109/fpt.2011.6132691","title":"Exploring FPGA technology mapping for fracturable LUT minimization","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University","funders":"","keywords":"Lookup table; Field-programmable gate array; Computer science; Enhanced Data Rates for GSM Evolution; Minification; Reduction (mathematics); Computer architecture; Computer hardware; Embedded system; Parallel computing; Computer engineering; Telecommunications; Mathematics; Operating system","score_opus":0.14925025844105103,"score_gpt":0.21918307299999418,"score_spread":0.06993281455894315,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2091956800","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01709266,0.000100299614,0.95319945,0.000029283066,0.00016574367,0.0002515601,0.000001426025,0.0026610263,0.026498564],"genre_scores_gemma":[0.8576562,0.000103418155,0.1416355,0.000024071483,0.00003940347,0.00030124586,0.0000035471614,0.000031664895,0.00020496672],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995305,0.0000024754509,0.00013511605,0.00010592786,0.00003598431,0.0001900174],"domain_scores_gemma":[0.9997726,0.000015315494,0.000014124774,0.00014378423,0.000029897772,0.000024274148],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000052309337,0.00009238212,0.00010193062,0.00020713874,0.000040229614,0.000009625165,0.00010154004,0.00008508764,0.00009870886],"category_scores_gemma":[0.000017258948,0.00008967854,0.000029166595,0.00017249267,0.000011388566,0.00025293557,0.000012590762,0.00006469162,0.000018445215],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000031388234,0.00011675955,0.0020986807,0.00063243165,0.00023713234,0.000015531825,0.0053757844,0.0016301468,0.16878927,0.038575653,0.02585996,0.7566373],"study_design_scores_gemma":[0.00017838801,0.00005334582,0.00026247694,0.00003663038,0.000009482892,0.0000053331933,0.0004140536,0.016998544,0.9491283,0.006801365,0.025839576,0.00027250187],"about_ca_topic_score_codex":0.000006172113,"about_ca_topic_score_gemma":0.0000015301152,"teacher_disagreement_score":0.84056354,"about_ca_system_score_codex":0.000023756644,"about_ca_system_score_gemma":0.000003504212,"threshold_uncertainty_score":0.3656985},"labels":[],"label_agreement":null},{"id":"W2093426958","doi":"10.1587/transinf.e96.d.1602","title":"FPGA Design Framework Combined with Commercial VLSI CAD","year":2013,"lang":"en","type":"article","venue":"IEICE Transactions on Information and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"University of Tokyo; Synopsys","keywords":"Field-programmable gate array; Computer science; Routing (electronic design automation); Bitstream; Embedded system; FPGA prototype; Very-large-scale integration; Code (set theory); Computer hardware; Computer architecture; Decoding methods; Set (abstract data type); Algorithm; Programming language","score_opus":0.012897559675903817,"score_gpt":0.2032000263192102,"score_spread":0.19030246664330638,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2093426958","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0041440665,0.000037120913,0.99056935,0.00008101893,0.00024460605,0.00068958866,0.000012286532,0.00066280237,0.0035591708],"genre_scores_gemma":[0.99664825,0.000062741616,0.0027345524,0.00013314837,0.00002228751,0.0003104259,0.000007032497,0.000014509477,0.00006703968],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999309,0.000032857155,0.00028842335,0.000059272534,0.00015319756,0.0001572178],"domain_scores_gemma":[0.99956506,0.00008241346,0.000040169045,0.00015459684,0.00007222253,0.000085555235],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011659506,0.00014636545,0.00016020346,0.00015663452,0.00014386009,0.00020883455,0.00007268229,0.00013725038,0.00006856994],"category_scores_gemma":[0.000002762509,0.0001205211,0.000024918654,0.00016537108,0.000026361666,0.00094919436,6.821451e-7,0.00022265904,0.00017449383],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00036110423,0.00023686638,0.0002152695,0.0017625649,0.00056644424,0.000004989544,0.01899144,0.43583724,0.0008524797,0.010071057,0.033809725,0.49729082],"study_design_scores_gemma":[0.0033378156,0.00223789,0.003045477,0.0011090417,0.00014773833,0.00017691696,0.0062228767,0.92515,0.012181706,0.00078027847,0.043647308,0.0019629903],"about_ca_topic_score_codex":0.00010868964,"about_ca_topic_score_gemma":0.000004563633,"teacher_disagreement_score":0.9925042,"about_ca_system_score_codex":0.000038664726,"about_ca_system_score_gemma":0.000010912092,"threshold_uncertainty_score":0.49147078},"labels":[],"label_agreement":null},{"id":"W2094806828","doi":"10.1145/329166.329208","title":"Timing-driven placement for FPGAs","year":2000,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":284,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Simulated annealing; Static timing analysis; Path (computing); Field-programmable gate array; Placement; Critical path method; Algorithm; Connection (principal bundle); Embedded system; Physical design; Mathematics; Engineering; Circuit design","score_opus":0.018045668936119946,"score_gpt":0.23193278232559508,"score_spread":0.21388711338947514,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2094806828","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024248833,0.00009637981,0.6233036,0.00008855998,0.00008710975,0.0005482415,0.000009476274,0.0023709424,0.34924683],"genre_scores_gemma":[0.9299089,0.000080783204,0.055180695,0.00016297745,0.000102977516,0.00016800412,0.000011777518,0.00003739137,0.014346544],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99970144,0.0000019018054,0.00007394951,0.00006180069,0.000038561247,0.00012231719],"domain_scores_gemma":[0.99986005,0.000016291177,0.0000027258393,0.000086712826,0.000006803182,0.000027389695],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000031495376,0.000060530987,0.00005931261,0.000020675576,0.00001908726,0.0000112510525,0.00005547351,0.000032714786,0.0018594434],"category_scores_gemma":[0.0000014760645,0.000055262426,0.000029491981,0.000027333623,0.00000461493,0.000036354635,0.000002764466,0.00002644637,0.000105536885],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022448785,0.00005124892,0.00006876425,0.00012848957,0.000078682584,0.0000039926067,0.00044078424,0.04939502,0.017399538,0.0029921771,0.5083338,0.42108503],"study_design_scores_gemma":[0.00047406464,0.0001335625,0.00005766222,0.000026848138,0.00001796781,0.000004574836,0.00003097516,0.30633435,0.15402374,0.0010225116,0.5375215,0.00035225577],"about_ca_topic_score_codex":0.0000020384716,"about_ca_topic_score_gemma":0.0000015717154,"teacher_disagreement_score":0.90566003,"about_ca_system_score_codex":0.000018591843,"about_ca_system_score_gemma":0.000002079999,"threshold_uncertainty_score":0.999053},"labels":[],"label_agreement":null},{"id":"W2095258817","doi":"10.1109/fpt.2013.6718327","title":"COFFE: Fully-automated transistor sizing for FPGAs","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":92,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Transistor; Computer science; Sizing; Process (computing); Routing (electronic design automation); Electronic engineering; Embedded system; Engineering; Electrical engineering; Voltage","score_opus":0.007361591502590679,"score_gpt":0.19508584108261845,"score_spread":0.18772424958002776,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2095258817","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.056900643,0.00048564383,0.87771976,0.00024965697,0.0003257332,0.0013799428,0.000013743336,0.021122452,0.04180241],"genre_scores_gemma":[0.9645441,0.000016953361,0.034299564,0.00010706913,0.00005356684,0.0002603321,0.000008220495,0.000042534062,0.00066766463],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994933,0.0000052845344,0.000141737,0.0000968664,0.000055663102,0.00020717154],"domain_scores_gemma":[0.99972945,0.00004345055,0.000008201307,0.0001247282,0.000038738817,0.00005539993],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005440372,0.000109913104,0.00012511524,0.00005186167,0.000033727618,0.000035035297,0.000089762616,0.000076826014,0.00032812727],"category_scores_gemma":[0.000007872486,0.00009911249,0.000058730315,0.0000698317,0.000010942518,0.0001297765,0.000003850301,0.00005018907,0.000108092674],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000045687793,0.000031695305,0.000036844045,0.00028693452,0.000076732234,0.000002072251,0.00029976634,0.00059138966,0.525927,0.0015988954,0.39899987,0.07214422],"study_design_scores_gemma":[0.00042803056,0.00007744328,0.0003156831,0.000033987202,0.000022182627,0.0000063970524,0.000054785567,0.585524,0.37014925,0.0011025856,0.041865304,0.0004202932],"about_ca_topic_score_codex":0.000025325728,"about_ca_topic_score_gemma":0.000005409434,"teacher_disagreement_score":0.90764344,"about_ca_system_score_codex":0.000029476445,"about_ca_system_score_gemma":0.00000447012,"threshold_uncertainty_score":0.40416902},"labels":[],"label_agreement":null},{"id":"W2095574503","doi":"10.1109/tvlsi.2005.848817","title":"A novel FPGA architecture supporting wide, shallow memories","year":2005,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Benchmark (surveying); Computer science; Architecture; Embedded system; Gate array; Computer architecture; Computer hardware; Parallel computing; Memory architecture","score_opus":0.01038495027989584,"score_gpt":0.22683062754143285,"score_spread":0.21644567726153702,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2095574503","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016793149,0.00017543425,0.97576815,0.00016062795,0.0015645868,0.00064528745,0.0002356498,0.001823633,0.0028335026],"genre_scores_gemma":[0.992483,0.000047419897,0.004894864,0.00012138944,0.00035203306,0.00031396182,0.000034393084,0.00009950063,0.0016534476],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99777955,0.00006891848,0.00076845905,0.00040213647,0.0004299695,0.000550971],"domain_scores_gemma":[0.99900097,0.00012976785,0.00010925862,0.00046134825,0.0001347529,0.00016393306],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004260132,0.0004340347,0.00043783133,0.00039193995,0.00028012105,0.00020021193,0.0002586871,0.00032442002,0.00016726197],"category_scores_gemma":[0.000013770134,0.00040311588,0.00025798095,0.0004084019,0.00004875072,0.0005338564,0.0000015583969,0.00069614087,0.00013469443],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012862011,0.000839007,0.000093878196,0.00056022755,0.0004229884,0.000024451976,0.0078306785,0.62687683,0.23652379,0.00040219672,0.009043363,0.117253944],"study_design_scores_gemma":[0.0012396335,0.0002680676,0.00009845039,0.0007332785,0.00013666776,0.00023122506,0.002304846,0.38059932,0.57793725,0.00009129186,0.035084672,0.0012752736],"about_ca_topic_score_codex":0.000057141802,"about_ca_topic_score_gemma":0.0009881116,"teacher_disagreement_score":0.9756898,"about_ca_system_score_codex":0.0002666743,"about_ca_system_score_gemma":0.000042571635,"threshold_uncertainty_score":0.99984205},"labels":[],"label_agreement":null},{"id":"W2095954771","doi":"10.1109/fpl.2010.17","title":"Parallelizing Simulated Annealing-Based Placement Using GPGPU","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":36,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Speedup; Computer science; General-purpose computing on graphics processing units; Simulated annealing; Parallel computing; Graphics; Field-programmable gate array; Graphics processing unit; Computer architecture; Embedded system; Algorithm; Computer graphics (images)","score_opus":0.016375412988447066,"score_gpt":0.24595474976537712,"score_spread":0.22957933677693004,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2095954771","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5887993,0.000050926083,0.40183055,0.000022639375,0.0002903259,0.00020109481,0.0000024843862,0.0022104639,0.0065922337],"genre_scores_gemma":[0.96726197,0.0000027746983,0.03248834,0.0000917619,0.000063516796,0.0000035949786,0.000006217743,0.000032884873,0.000048950613],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99938726,0.0000073829096,0.0001650764,0.00011596977,0.00009895885,0.00022536721],"domain_scores_gemma":[0.99966425,0.000030100227,0.000014668922,0.00019767457,0.000027210705,0.00006607494],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011664157,0.00012894136,0.00011295754,0.000081272905,0.00005098923,0.000036952075,0.000098911456,0.00010614275,0.00031859908],"category_scores_gemma":[0.000010087847,0.00012213389,0.00004172872,0.00010537406,0.000014901421,0.00006850011,0.000011563444,0.00019313136,0.000021143527],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000047634007,0.00001396806,0.00039783982,0.000026740125,0.000016443772,0.0000075626863,0.000040571515,0.5896692,0.40727672,0.00019552882,0.0008541465,0.0014964624],"study_design_scores_gemma":[0.00018264224,0.000014907258,0.000033044344,0.00001150845,0.0000069082835,0.0000017232048,0.000008967893,0.8413532,0.15534557,0.00006691261,0.0028129092,0.0001617134],"about_ca_topic_score_codex":0.00003412178,"about_ca_topic_score_gemma":0.000014090496,"teacher_disagreement_score":0.37846267,"about_ca_system_score_codex":0.000025188669,"about_ca_system_score_gemma":0.000012164184,"threshold_uncertainty_score":0.4980476},"labels":[],"label_agreement":null},{"id":"W2096185144","doi":"10.1145/774572.774683","title":"Incremental placement for layout driven optimizations on FPGAs","year":2002,"lang":"en","type":"article","venue":"Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":31,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Field-programmable gate array; Parallel computing; Computer architecture; Embedded system","score_opus":0.06623920370334359,"score_gpt":0.28090486888024707,"score_spread":0.2146656651769035,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2096185144","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014318817,0.00025165302,0.29083475,0.00424105,0.0031585672,0.00937621,0.0011912554,0.00685747,0.66977024],"genre_scores_gemma":[0.9468503,0.00040525946,0.05142388,0.00031182021,0.00020247875,0.0004214893,0.00009667872,0.000112606176,0.0001754791],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9958125,0.00011314,0.001450764,0.00086092897,0.0011160902,0.00064657565],"domain_scores_gemma":[0.996768,0.0010561333,0.00040703453,0.0011165742,0.00037482972,0.0002774451],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004587111,0.00074898044,0.00096532085,0.0005441511,0.00015336482,0.00009409167,0.002135715,0.000555598,0.0005244619],"category_scores_gemma":[0.00034719627,0.000719349,0.000511513,0.0003867093,0.00039471584,0.00022826155,0.00024191645,0.00070344255,0.000038236307],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00042503892,0.0018404794,0.00013439219,0.00014612445,0.0003619305,0.000025262781,0.00007466313,0.117423095,0.8233004,0.036431834,0.014353674,0.0054831086],"study_design_scores_gemma":[0.014455651,0.028353726,0.007362762,0.0073629506,0.0007614689,0.00024273405,0.00025754343,0.25971696,0.6473716,0.0060783788,0.020334521,0.0077017094],"about_ca_topic_score_codex":0.000011567663,"about_ca_topic_score_gemma":0.000009944303,"teacher_disagreement_score":0.9325315,"about_ca_system_score_codex":0.00053505634,"about_ca_system_score_gemma":0.00006449631,"threshold_uncertainty_score":0.9995258},"labels":[],"label_agreement":null},{"id":"W2097448746","doi":"10.1109/ccece.1997.614778","title":"Circuit clustering and its effects on a multi-way circuit partitioning heuristic","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Heuristic; Cluster analysis; Computer science; Phase (matter); Algorithm; Artificial intelligence; Physics","score_opus":0.03627549572137415,"score_gpt":0.21638120732653668,"score_spread":0.18010571160516253,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2097448746","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20540844,0.0027073964,0.71288896,0.000045184566,0.00048606188,0.0009076676,0.000008276128,0.0050545637,0.07249345],"genre_scores_gemma":[0.9986309,0.00012864693,0.0004597947,0.00010318767,0.000073267045,0.000056895915,0.0000014678498,0.00003878516,0.0005070872],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993069,0.00001877679,0.00014424173,0.00017762289,0.00009967324,0.0002527531],"domain_scores_gemma":[0.999652,0.00009398961,0.000013882065,0.00013590482,0.000014115817,0.00009008389],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007182836,0.00015869125,0.00015350817,0.00009089288,0.00007399736,0.00005596577,0.00006826734,0.000080437036,0.00016135722],"category_scores_gemma":[0.000040090083,0.00015925648,0.000031633168,0.00009200489,0.000009642625,0.00010558434,0.000017863958,0.00014423027,0.00015419112],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011983551,0.00037952198,0.0027855823,0.0041883597,0.0003542519,0.000632893,0.004165121,0.009548851,0.41371655,0.01999575,0.012270524,0.5319506],"study_design_scores_gemma":[0.0009580691,0.00023943381,0.0036773568,0.00046505427,0.00003899618,0.000072146504,0.000019021958,0.87602746,0.11562878,0.0007712237,0.0013351493,0.0007673369],"about_ca_topic_score_codex":0.0000028440734,"about_ca_topic_score_gemma":0.000003762913,"teacher_disagreement_score":0.86647856,"about_ca_system_score_codex":0.000038222704,"about_ca_system_score_gemma":9.361516e-7,"threshold_uncertainty_score":0.6494291},"labels":[],"label_agreement":null},{"id":"W2097646901","doi":"10.1080/00207540500031980","title":"A practical exact algorithm for the shortest loop design problem in a block layout","year":2005,"lang":"en","type":"article","venue":"International Journal of Production Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"HEC Montréal","funders":"","keywords":"Solver; Block (permutation group theory); Integer programming; Scheme (mathematics); Loop (graph theory); Mathematical optimization; Linear programming; Computer science; Simple (philosophy); Algorithm; Mathematics; Combinatorics","score_opus":0.14603698237724172,"score_gpt":0.42884330365835266,"score_spread":0.28280632128111094,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2097646901","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0046391254,0.0006578489,0.96823627,0.024055714,0.0008901486,0.0010163323,0.000005952779,0.00007929321,0.00041933949],"genre_scores_gemma":[0.6946818,0.0007251685,0.30008253,0.000045369754,0.0035969855,0.00014884991,0.0000018958222,0.00004034292,0.0006770088],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983822,0.00011796693,0.0003904346,0.00012067289,0.0007681345,0.00022059966],"domain_scores_gemma":[0.9982255,0.00046719346,0.00006331985,0.000114257586,0.0010786571,0.00005103496],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0037117503,0.00008207817,0.000109554465,0.00043804673,0.000053233845,0.000103161176,0.00035216863,0.000059155194,0.000037799808],"category_scores_gemma":[0.00058297126,0.000059629074,0.00006177672,0.00022801221,0.000059661128,0.00038959956,0.000029360923,0.0006398927,0.000011397865],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00023983205,0.00047919777,0.00020832541,0.000021865917,0.00034745643,0.0000855717,0.00073866436,0.07290403,0.019844726,0.00054490665,0.1477567,0.7568287],"study_design_scores_gemma":[0.0015536821,0.00080763217,0.00077935064,0.00032894468,0.000040468174,0.0029299113,0.0006789212,0.66115266,0.15945642,0.0044469573,0.16744074,0.00038433005],"about_ca_topic_score_codex":0.0000080785285,"about_ca_topic_score_gemma":0.000007806692,"teacher_disagreement_score":0.7564444,"about_ca_system_score_codex":0.00028378435,"about_ca_system_score_gemma":0.00012880086,"threshold_uncertainty_score":0.2780051},"labels":[],"label_agreement":null},{"id":"W2097683623","doi":"10.1145/2554688.2554788","title":"Optimizing effective interconnect capacitance for FPGA power reduction","year":2014,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Capacitance; Reduction (mathematics); Interconnection; Field-programmable gate array; Power (physics); Materials science; Electronic engineering; Electrical engineering; Optoelectronics; Computer science; Embedded system; Engineering; Physics; Telecommunications; Electrode","score_opus":0.006285665850792426,"score_gpt":0.20946049749945667,"score_spread":0.20317483164866423,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2097683623","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.015906876,0.000079990125,0.9537829,0.000022902512,0.00036718565,0.0003587332,0.0000015464626,0.0010074242,0.028472444],"genre_scores_gemma":[0.96076196,0.000007868735,0.038765952,0.000024825735,0.000090808935,0.0001657861,0.0000019054386,0.000027040813,0.0001538357],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99958646,0.000014558242,0.00009544908,0.0001176543,0.000037648486,0.00014820774],"domain_scores_gemma":[0.999734,0.00007054814,0.000011368931,0.00012429629,0.000030603627,0.000029172073],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016523789,0.00009735959,0.00011202256,0.000055485238,0.000032026022,0.000020338446,0.00006208624,0.00006199385,0.000030051113],"category_scores_gemma":[0.000037029713,0.00008989932,0.000052778523,0.000053954922,0.000013766951,0.00013216463,0.0000028356928,0.000071014365,0.000013300625],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000027443723,0.000021786222,0.0000075404514,0.00012869017,0.00007545824,5.0302776e-7,0.0014462451,0.0033631397,0.8148024,0.012325189,0.016765244,0.15103634],"study_design_scores_gemma":[0.0001989104,0.00018093335,0.000020662512,0.000041878837,0.000008842981,0.0000081809285,0.00009858197,0.021888949,0.9683774,0.0031017351,0.0058736084,0.00020031435],"about_ca_topic_score_codex":0.0000036061545,"about_ca_topic_score_gemma":0.0000017152959,"teacher_disagreement_score":0.9448551,"about_ca_system_score_codex":0.000049951148,"about_ca_system_score_gemma":0.000001375901,"threshold_uncertainty_score":0.36659878},"labels":[],"label_agreement":null},{"id":"W2099587669","doi":"10.1109/glsv.1992.218354","title":"A systematic approach for designing systolic arrays","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Regina","funders":"","keywords":"Dependency (UML); Transformation (genetics); Matrix (chemical analysis); Integer (computer science); Inverse; Computer science; Algorithm; Rank (graph theory); Square matrix; Mathematics; Theoretical computer science; Mathematical optimization; Discrete mathematics; Algebra over a field; Combinatorics; Artificial intelligence; Symmetric matrix; Pure mathematics; Programming language; Eigenvalues and eigenvectors","score_opus":0.018095632150632122,"score_gpt":0.2069893053875768,"score_spread":0.18889367323694467,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2099587669","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00013652268,0.00038900366,0.9419998,9.565987e-7,0.000045865178,0.0009225645,8.110055e-7,0.0010882819,0.055416223],"genre_scores_gemma":[0.6559278,0.000006165601,0.34291777,0.000016472213,0.000017989583,0.00066592824,0.00000195203,0.00003447282,0.00041150575],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99938565,0.000030018138,0.00020418921,0.00010533271,0.00006867969,0.00020615004],"domain_scores_gemma":[0.9996683,0.00007243485,0.000017487313,0.0001751098,0.00002125234,0.000045397417],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003182382,0.000119108176,0.00022251417,0.00006968194,0.00004016755,0.000032614633,0.000085410335,0.00006634527,0.000009807433],"category_scores_gemma":[0.000054792396,0.00009912503,0.00006582897,0.000094744166,0.0000067800147,0.00006242965,0.0000025564236,0.000049818933,0.000010502189],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000009877978,0.0001963145,0.000126593,0.2627637,0.0007754385,0.000010966447,0.002312948,0.030776935,0.16955177,0.49600658,0.03666317,0.00080569857],"study_design_scores_gemma":[0.0006694731,0.00012071686,0.0000041640615,0.001879228,0.00017356341,0.00013826074,0.0008819715,0.6422974,0.34888235,0.0035116856,0.00045931622,0.0009819095],"about_ca_topic_score_codex":9.3182774e-7,"about_ca_topic_score_gemma":1.4475359e-7,"teacher_disagreement_score":0.6557912,"about_ca_system_score_codex":0.000037589805,"about_ca_system_score_gemma":0.0000069000816,"threshold_uncertainty_score":0.4042201},"labels":[],"label_agreement":null},{"id":"W2100201259","doi":"10.1109/icm.2008.5393533","title":"Placement algorithm for multiplier-based FPGA circuits","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Field-programmable gate array; Application-specific integrated circuit; Computer science; Routing (electronic design automation); Greedy algorithm; Pipeline (software); Multiplier (economics); Power consumption; Reduction (mathematics); Algorithm; Electronic circuit; Integer programming; Interconnection; Network routing; Power (physics); Embedded system; Mathematics; Telecommunications; Engineering","score_opus":0.02650386566117851,"score_gpt":0.2279425466022554,"score_spread":0.2014386809410769,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100201259","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014102513,0.00007373579,0.98919433,0.000013417062,0.000106989995,0.00037860122,0.000016030128,0.0012998389,0.007506814],"genre_scores_gemma":[0.77601945,0.00003545849,0.22194228,0.00019361041,0.00012368053,0.00034113514,0.000030022049,0.000057821235,0.0012565295],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99945945,0.0000039703095,0.00012951244,0.00011436805,0.000088600194,0.00020411077],"domain_scores_gemma":[0.99971926,0.000043087126,0.000009220091,0.00014601162,0.000026657775,0.000055776705],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000058277677,0.00011263208,0.000110875306,0.00006122129,0.00005779866,0.000007924251,0.0000851557,0.00006456166,0.00009296146],"category_scores_gemma":[0.000005156539,0.00010729694,0.000057491514,0.00006193261,0.000015304007,0.000044641954,0.0000056851923,0.000051510597,0.000029669682],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000054876023,0.00014535898,0.00015816132,0.00011286282,0.00007968354,0.000024304629,0.00023997859,0.008387797,0.029038388,0.00021833692,0.12873824,0.8328514],"study_design_scores_gemma":[0.00078967714,0.00010241082,0.000107118605,0.000010991115,0.0000076154574,0.0000069161974,0.0000146597295,0.5744041,0.3975736,0.00007876177,0.026635652,0.00026849468],"about_ca_topic_score_codex":0.0000037675868,"about_ca_topic_score_gemma":0.0000010590229,"teacher_disagreement_score":0.8325829,"about_ca_system_score_codex":0.00004550744,"about_ca_system_score_gemma":0.000012993822,"threshold_uncertainty_score":0.43754423},"labels":[],"label_agreement":null},{"id":"W2100412947","doi":"10.1145/611817.611824","title":"Hardware-assisted simulated annealing with application for fast FPGA placement","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":61,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Office of Naval Research; Defense Advanced Research Projects Agency; National Science Foundation","keywords":"Netlist; Field-programmable gate array; Simulated annealing; Computer science; Placement; Exploit; Lookup table; Routing (electronic design automation); Parallel computing; Reconfigurable computing; Computer hardware; Embedded system; Computer engineering; Physical design; Algorithm; Circuit design","score_opus":0.012069945974130214,"score_gpt":0.22692480863411527,"score_spread":0.21485486265998505,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100412947","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008558071,0.000045565706,0.97933406,0.000011187702,0.000025029307,0.0006304738,0.0000059416834,0.0010555655,0.010334093],"genre_scores_gemma":[0.97339135,0.000006271499,0.025986856,0.00003825578,0.000014572936,0.00014578046,0.000030833693,0.000034332003,0.0003517562],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994889,0.0000069841117,0.00013283899,0.00012962196,0.00007298862,0.00016864964],"domain_scores_gemma":[0.99970907,0.000026674572,0.00001751176,0.00015600915,0.00004794676,0.000042769487],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008871416,0.00011139633,0.00010438559,0.000047702113,0.000045982673,0.00002131531,0.00005350712,0.000057259884,0.00003117344],"category_scores_gemma":[0.0000059370136,0.00009369475,0.00002492586,0.0001186636,0.000007741932,0.000057163517,0.0000029438609,0.000046188827,0.000008052204],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012966483,0.00018064663,0.001078699,0.00048723817,0.000342784,0.000005402655,0.0005042634,0.668144,0.19468537,0.010827036,0.013364718,0.11025022],"study_design_scores_gemma":[0.0011700179,0.0002089657,0.0001892812,0.000041232655,0.00004272706,0.000008025143,0.00014757266,0.40281314,0.5413576,0.00031241574,0.053230926,0.00047815515],"about_ca_topic_score_codex":0.000005896202,"about_ca_topic_score_gemma":0.0000068844856,"teacher_disagreement_score":0.96483326,"about_ca_system_score_codex":0.00004853555,"about_ca_system_score_gemma":0.000008472288,"threshold_uncertainty_score":0.38207608},"labels":[],"label_agreement":null},{"id":"W2100746765","doi":"10.1109/mwscas.1992.271293","title":"A pipelined VLSI arithmetic architecture","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor; University of Waterloo","funders":"National Center for Theoretical Sciences","keywords":"Very-large-scale integration; Computer science; Arithmetic; Parallel computing; Architecture; Tree (set theory); Binary tree; Reduction (mathematics); Pyramid (geometry); Computer architecture; Theoretical computer science; Algorithm; Embedded system; Mathematics","score_opus":0.004954174108534439,"score_gpt":0.17769906845361663,"score_spread":0.1727448943450822,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100746765","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003683738,0.0002345291,0.7717764,0.000032288895,0.00008862134,0.00010342262,0.0000011024642,0.0015101113,0.22256981],"genre_scores_gemma":[0.94207203,0.000024051304,0.056198835,0.00012593193,0.00003201077,0.000016957003,0.0000014398242,0.00002636851,0.0015023829],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995885,0.000012850888,0.00009452728,0.000081870305,0.000063962114,0.00015827957],"domain_scores_gemma":[0.99976623,0.00001820511,0.000004581069,0.00015226669,0.000010944429,0.00004776048],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006826759,0.000093681185,0.00008777394,0.00006331929,0.000017321729,0.000016714876,0.000065038745,0.0000573117,0.00031382503],"category_scores_gemma":[0.000020606209,0.000078370635,0.000036338064,0.00011559286,0.000010790048,0.000025697394,0.000004079226,0.000110474844,0.000071839524],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012140198,0.00019280364,0.0009540405,0.0003656729,0.00020537889,0.00012449917,0.0011649145,0.014246726,0.28762767,0.1186107,0.16172126,0.41477418],"study_design_scores_gemma":[0.00056478847,0.00010712923,0.00025222436,0.000035620018,0.000029080604,0.00012898525,0.00006356004,0.014962882,0.55863196,0.041192047,0.38320693,0.0008247663],"about_ca_topic_score_codex":0.000002526331,"about_ca_topic_score_gemma":0.000003583031,"teacher_disagreement_score":0.9383883,"about_ca_system_score_codex":0.000013120492,"about_ca_system_score_gemma":0.0000052578685,"threshold_uncertainty_score":0.34361643},"labels":[],"label_agreement":null},{"id":"W2100873809","doi":"10.1109/ccece.2002.1013007","title":"Netlist partitioning for FPGA-based run-time reconfiguration","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Winnipeg; University of Manitoba","funders":"","keywords":"Netlist; Computer science; Control reconfiguration; Field-programmable gate array; Embedded system; Reconfigurable computing; Computer architecture; Flexibility (engineering); Graph partition; Parallel computing; Graph; Distributed computing; Theoretical computer science","score_opus":0.012510482958629133,"score_gpt":0.20796417693032182,"score_spread":0.19545369397169268,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100873809","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.002826082,0.00005031636,0.91707665,0.000041665782,0.00008654764,0.0002480072,0.0000052781634,0.0010549424,0.07861052],"genre_scores_gemma":[0.95840627,0.0000068750055,0.039515506,0.00015593036,0.000051911757,0.0001568983,0.00004582317,0.000032799155,0.0016279706],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996047,0.000010436525,0.00012389137,0.00008415097,0.000041282186,0.00013554751],"domain_scores_gemma":[0.9997839,0.000041011168,0.000011667842,0.000103142746,0.000027774198,0.00003255539],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012189054,0.00007536424,0.00007646413,0.000040227587,0.000049839808,0.00005299057,0.000037771006,0.000054243952,0.00041531379],"category_scores_gemma":[0.0000292051,0.00007611821,0.000038691906,0.00006114564,0.0000073235674,0.00017053976,8.046375e-7,0.000036710084,0.000049775557],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000030596682,0.00012353135,0.00034391484,0.00030115063,0.000100449906,0.000005854523,0.00020048929,0.04623651,0.5571278,0.1068068,0.22317517,0.06554777],"study_design_scores_gemma":[0.00025998647,0.00005722642,0.000038128437,0.000020228537,0.000009715172,0.0000018962629,0.0000087069675,0.09018458,0.82917744,0.0019612592,0.07807577,0.00020506613],"about_ca_topic_score_codex":0.000002280511,"about_ca_topic_score_gemma":0.0000040314903,"teacher_disagreement_score":0.95558023,"about_ca_system_score_codex":0.000027015278,"about_ca_system_score_gemma":0.000010402715,"threshold_uncertainty_score":0.45473945},"labels":[],"label_agreement":null},{"id":"W2100925048","doi":"10.5555/1129601.1129661","title":"Efficient analog platform characterization through analog constraint graphs","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Heuristics; Theoretical computer science; Executable; Bipartite graph; Analogue electronics; Leverage (statistics); Algorithm; Graph; Mathematical optimization; Electronic circuit; Mathematics; Artificial intelligence","score_opus":0.01363342740386932,"score_gpt":0.21743983049134,"score_spread":0.20380640308747067,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100925048","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3503433,0.000063579,0.5812013,0.000072686504,0.00011486486,0.00021529126,0.000020758747,0.0013700735,0.06659814],"genre_scores_gemma":[0.99292994,0.0000689667,0.006525584,0.00019066074,0.00006462751,0.000015361935,0.00005020515,0.000019916177,0.00013473647],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999337,0.0000048972206,0.00020627143,0.00012739057,0.00010775885,0.00021666306],"domain_scores_gemma":[0.9997391,0.000012930633,0.000020888276,0.00015513219,0.000024910694,0.00004701536],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000075581156,0.00013556438,0.00013262159,0.00009046231,0.00004301341,0.000029723406,0.00009007417,0.00008910056,0.00044316685],"category_scores_gemma":[0.000003836073,0.000121226694,0.00005653064,0.00019380699,0.000037596084,0.00010788346,0.000011481319,0.000100387784,0.000099296616],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000121870935,0.00017231073,0.0008690105,0.00009216624,0.00012900852,0.000019400137,0.0013824195,0.022159878,0.5712876,0.18782488,0.0045005446,0.21155062],"study_design_scores_gemma":[0.0007496644,0.00015439981,0.008356444,0.00007394615,0.00005106527,0.000068555615,0.0001618099,0.58345604,0.37290964,0.0027786472,0.030105669,0.0011341482],"about_ca_topic_score_codex":0.0000047881713,"about_ca_topic_score_gemma":0.0000067942633,"teacher_disagreement_score":0.64258665,"about_ca_system_score_codex":0.00004821496,"about_ca_system_score_gemma":0.000007177845,"threshold_uncertainty_score":0.4943481},"labels":[],"label_agreement":null},{"id":"W2101356024","doi":"10.5555/996070.1009965","title":"On the Interaction Between Power-Aware FPGA CAD Algorithms","year":2003,"lang":"en","type":"article","venue":"International Conference on Computer Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":108,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Computer science; CAD; Cluster analysis; Routing (electronic design automation); Power analysis; Algorithm; Design flow; Energy consumption; Electronic design automation; Power (physics); Embedded system; Power optimization; FPGA prototype; Energy (signal processing); Field (mathematics); Reconfigurable computing; Power consumption; Artificial intelligence; Engineering; Electrical engineering","score_opus":0.07563059520384806,"score_gpt":0.2878558569216994,"score_spread":0.21222526171785133,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2101356024","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0033502006,0.000007435939,0.97250277,0.00039210697,0.0011978359,0.0002755516,0.000018441262,0.00046258717,0.021793092],"genre_scores_gemma":[0.99392474,0.000019051935,0.005186769,0.00043671537,0.00018668984,0.00005296064,0.000014549036,0.0000330529,0.0001454964],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987544,0.0001308526,0.0002787629,0.00026544122,0.00035490617,0.00021565497],"domain_scores_gemma":[0.99901396,0.00044015414,0.000057598936,0.00027408422,0.0001468085,0.00006737442],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00029964084,0.00024461414,0.0001748653,0.00017757594,0.00007582938,0.00019175325,0.0004553256,0.0001045827,0.0005545891],"category_scores_gemma":[0.00003578176,0.00019224909,0.00008149338,0.00010452416,0.00003267115,0.00017060677,0.000024460072,0.00040053314,0.000296946],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011176326,0.00028144335,0.00028386535,0.000028192766,0.00083729817,0.000092369526,0.001031419,0.038305566,0.0041357484,0.5866717,0.13780132,0.23041932],"study_design_scores_gemma":[0.00093549635,0.0012266275,0.00079626066,0.0005248375,0.000033249587,0.00005993009,0.00013149272,0.776378,0.11742881,0.085822545,0.015497253,0.0011655439],"about_ca_topic_score_codex":0.0000066582256,"about_ca_topic_score_gemma":5.732785e-7,"teacher_disagreement_score":0.99057454,"about_ca_system_score_codex":0.00014441645,"about_ca_system_score_gemma":0.0000308702,"threshold_uncertainty_score":0.78396904},"labels":[],"label_agreement":null},{"id":"W2101442766","doi":"10.1109/tvlsi.2010.2076841","title":"Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)","year":2010,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Application-specific integrated circuit; Notation; Computer science; Integrated circuit; Embedded system; Mathematics; Arithmetic; Operating system","score_opus":0.008960722417650318,"score_gpt":0.21234122466449126,"score_spread":0.20338050224684096,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2101442766","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.38081563,0.00014356557,0.6128624,0.000029012352,0.0024103976,0.0010226475,0.00012635182,0.0007750267,0.0018149702],"genre_scores_gemma":[0.9975489,0.00015415183,0.0014725393,0.000024297273,0.00007525397,0.00033522435,0.00002082894,0.00005514337,0.00031367276],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985103,0.00006464894,0.0004800436,0.0003018056,0.0002649424,0.0003782725],"domain_scores_gemma":[0.99934787,0.000059939583,0.00005250113,0.00033721118,0.00008227726,0.000120185265],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00039093237,0.00030410427,0.00034116092,0.0003160043,0.00015639862,0.00014829038,0.00015826608,0.00032945856,0.0000428212],"category_scores_gemma":[0.0000056586186,0.00028278705,0.0000911361,0.00039425355,0.000057815923,0.0006121469,0.0000010120459,0.0008139834,0.000022962811],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002471973,0.00096440857,0.0013999473,0.0010191144,0.00041901905,0.00004576362,0.0067988643,0.08970217,0.45667922,0.0015849473,0.0023417298,0.4387976],"study_design_scores_gemma":[0.0013514955,0.00025308426,0.00065379875,0.00027489066,0.000088483815,0.00013550627,0.0012287447,0.72131264,0.256258,0.000060686023,0.017573768,0.00080890855],"about_ca_topic_score_codex":0.000089931455,"about_ca_topic_score_gemma":0.0010652668,"teacher_disagreement_score":0.63161045,"about_ca_system_score_codex":0.00010071387,"about_ca_system_score_gemma":0.000024431472,"threshold_uncertainty_score":0.99996245},"labels":[],"label_agreement":null},{"id":"W2101693825","doi":"10.1109/ccece.2005.1557360","title":"Novel approaches to placement","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Manitoba","funders":"","keywords":"Computer science; Planar graph; Planar; Theoretical computer science; Very-large-scale integration; Graph; Conjecture; Graph drawing; Electronic circuit; Computer engineering; Mathematics; Computer graphics (images)","score_opus":0.067253036083523,"score_gpt":0.19442043936652423,"score_spread":0.12716740328300125,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2101693825","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004317788,0.000021870284,0.77951735,0.000049257476,0.00002770588,0.00009655709,0.0000013848393,0.0007482417,0.21521987],"genre_scores_gemma":[0.9246502,8.441798e-7,0.07324117,0.000049945305,0.0000594429,0.000035348625,0.0000031403204,0.000013295943,0.0019466339],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997245,9.958947e-7,0.00006516077,0.000058735735,0.00004910295,0.00010147895],"domain_scores_gemma":[0.9998852,0.000004414765,0.000002216405,0.00008272448,0.0000027046929,0.000022714987],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000034486242,0.00005501516,0.000046162048,0.000035938465,0.000010114119,0.000012969097,0.000048647136,0.000023541266,0.000058134192],"category_scores_gemma":[6.813739e-7,0.00004895642,0.000014009635,0.000057551406,0.0000027972505,0.00002498936,0.000009362984,0.000025347565,0.000064617845],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000006216526,0.00016256813,0.0004639571,0.00007228362,0.00003381264,0.000003387184,0.00018024529,0.10133954,0.39152852,0.113746025,0.36620837,0.02625506],"study_design_scores_gemma":[0.0003196443,0.00007817236,0.002003622,0.000015943639,0.000009376274,0.0000084275325,0.000069405876,0.055272102,0.82609344,0.0014265059,0.11415388,0.0005494867],"about_ca_topic_score_codex":0.00002524296,"about_ca_topic_score_gemma":0.000011431931,"teacher_disagreement_score":0.9203324,"about_ca_system_score_codex":0.000020752674,"about_ca_system_score_gemma":0.0000013532779,"threshold_uncertainty_score":0.19963849},"labels":[],"label_agreement":null},{"id":"W2102503881","doi":"10.1145/1950413.1950449","title":"An analytical model relating FPGA architecture parameters to routability","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Router; Block (permutation group theory); Computer science; Logic block; CAD; Channel (broadcasting); Embedded system; Parallel computing; Electronic engineering; Computer hardware; Engineering; Mathematics; Engineering drawing","score_opus":0.04758543518465032,"score_gpt":0.2551578394130092,"score_spread":0.20757240422835888,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2102503881","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.276553,0.0000036038998,0.6947223,0.000012552993,0.0000178188,0.00011838881,0.0000023799755,0.0009851351,0.027584802],"genre_scores_gemma":[0.76503396,4.3107877e-7,0.2347912,0.00008386767,0.00000996249,0.00001302408,0.0000012663718,0.000019735933,0.00004656386],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99929684,0.000018451403,0.00017271155,0.00018871584,0.00009139258,0.00023188752],"domain_scores_gemma":[0.99942935,0.000022099975,0.0000073282254,0.0003528248,0.000016283824,0.00017214505],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015954969,0.00012796292,0.00013793712,0.00007476767,0.000026645295,0.000017783123,0.00015669527,0.00009367872,0.00008346452],"category_scores_gemma":[0.000027561979,0.00011017727,0.000051734438,0.0001228182,0.000019610605,0.00010108478,0.000018979239,0.0001876452,0.000022147797],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000052265044,0.00019133181,0.009769316,0.00008982047,0.000093028466,0.000017559672,0.008417015,0.79480493,0.021461258,0.009496854,0.0017716902,0.15383494],"study_design_scores_gemma":[0.000048123624,0.00009016415,0.0012481463,0.0000076149017,0.0000117219015,0.0000030927176,0.000039564115,0.9680267,0.020602265,0.009672379,0.000026642147,0.0002236093],"about_ca_topic_score_codex":0.00006154761,"about_ca_topic_score_gemma":0.000026527694,"teacher_disagreement_score":0.48848093,"about_ca_system_score_codex":0.000035176854,"about_ca_system_score_gemma":0.000006077407,"threshold_uncertainty_score":0.4492899},"labels":[],"label_agreement":null},{"id":"W2102704825","doi":"10.1109/tcad.2004.828124","title":"Area Optimization of Delay-Optimized Structures Using Intrinsic Constraint Graphs","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Sizing; Block (permutation group theory); Computer science; Mathematical optimization; Routing (electronic design automation); Similarity (geometry); Constraint (computer-aided design); Optimization problem; Relation (database); Algorithm; Mathematics; Data mining; Artificial intelligence","score_opus":0.030453359302128807,"score_gpt":0.22006195759192956,"score_spread":0.18960859828980076,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2102704825","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03060397,0.00028909728,0.9673809,0.000002158671,0.0006098362,0.00065966125,0.00007155887,0.00033408467,0.000048723017],"genre_scores_gemma":[0.94497955,0.00019978046,0.054720256,0.000008160609,0.000018415692,0.000022838252,0.0000066516636,0.000042276726,0.0000020867444],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99839014,0.00011630509,0.00077169714,0.00026463438,0.00022165407,0.0002355495],"domain_scores_gemma":[0.9990816,0.00012253459,0.00017307016,0.00025720807,0.00026483007,0.00010073686],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00022968027,0.00032925216,0.0006206048,0.0005502877,0.000086066735,0.00005951265,0.0001578217,0.00024203032,0.000014167407],"category_scores_gemma":[0.0000036171843,0.00029459162,0.00012423107,0.000465752,0.00013830367,0.0001603961,9.981858e-7,0.00026690122,4.1549953e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025255971,0.000058114856,0.0000014773166,0.00013305173,0.00019516308,0.0000082713495,0.0002170395,0.9550849,0.03145833,0.00056492514,0.000013090073,0.012240377],"study_design_scores_gemma":[0.0011296292,0.0003894069,0.0000033258484,0.00060184184,0.00009281546,0.00017304516,0.00015151489,0.8946494,0.10204773,0.0004594571,0.0000021995252,0.00029965074],"about_ca_topic_score_codex":0.00019963292,"about_ca_topic_score_gemma":0.0000018329027,"teacher_disagreement_score":0.91437554,"about_ca_system_score_codex":0.0001184316,"about_ca_system_score_gemma":0.00008993037,"threshold_uncertainty_score":0.99995065},"labels":[],"label_agreement":null},{"id":"W2102892811","doi":"10.1145/1462586.1462587","title":"Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms","year":2009,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Routing (electronic design automation); Static routing; Memory footprint; Field-programmable gate array; Policy-based routing; Multipath routing; Footprint; Distributed computing; Parallel computing; Embedded system; Routing protocol","score_opus":0.013504579150675147,"score_gpt":0.237491180714835,"score_spread":0.22398660156415984,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2102892811","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10030053,0.0020225444,0.8908755,0.0011884581,0.000619018,0.0012849885,0.000031165833,0.0026818754,0.0009958978],"genre_scores_gemma":[0.9946304,0.0005894154,0.0041824984,0.000012000309,0.000015941318,0.00021543112,0.0000036777174,0.000023511166,0.00032713017],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99910986,0.00001881966,0.0002897328,0.00026353844,0.00005560669,0.00026242188],"domain_scores_gemma":[0.99949133,0.000062236875,0.00004374026,0.000316348,0.000037978552,0.000048350936],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002205164,0.00018359553,0.00027034568,0.00044839503,0.00021349367,0.000043278353,0.000121231395,0.00030706453,0.000004543272],"category_scores_gemma":[0.000015430893,0.00018597128,0.00003746321,0.00022645725,0.00006257712,0.00008748435,0.0000010970722,0.00028223573,0.0000023237003],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001547424,0.000032398657,0.0000031610357,0.00015320683,0.00007486282,0.0000028028664,0.00015773486,0.002207776,0.032679353,0.0010271705,0.000054770295,0.9635913],"study_design_scores_gemma":[0.003101533,0.002949791,0.00034313777,0.0011319813,0.00034439267,0.0021889647,0.008378261,0.40193123,0.49514592,0.07829424,0.0041684923,0.002022067],"about_ca_topic_score_codex":0.00001217116,"about_ca_topic_score_gemma":0.0000030624913,"teacher_disagreement_score":0.96156925,"about_ca_system_score_codex":0.000059115944,"about_ca_system_score_gemma":0.000009065164,"threshold_uncertainty_score":0.7583689},"labels":[],"label_agreement":null},{"id":"W2103117726","doi":"10.1109/tvlsi.2005.859561","title":"Routing architecture optimizations for high-density embedded programmable IP cores","year":2005,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Routing (electronic design automation); Logic block; Block (permutation group theory); Programmable logic array; Programmable logic device; Parallel computing; Channel (broadcasting); Computer science; Programmable Array Logic; Gate array; Logic gate; Simple programmable logic device; Block size; Square (algebra); Field-programmable gate array; Topology (electrical circuits); Logic synthesis; Computer hardware; Logic family; Embedded system; Engineering; Algorithm; Mathematics; Electrical engineering; Telecommunications; Key (lock); Geometry","score_opus":0.009668095962273072,"score_gpt":0.22336247586649963,"score_spread":0.21369437990422654,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2103117726","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011367593,0.00009152587,0.98305106,0.00009372881,0.0011942482,0.001532869,0.00028875982,0.0019118504,0.00046839172],"genre_scores_gemma":[0.97180474,0.000036666755,0.025553778,0.000049258455,0.0003201722,0.00087410054,0.00010038033,0.00009238482,0.0011685111],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.998157,0.00008589779,0.00059748313,0.00037889564,0.0002838677,0.0004968438],"domain_scores_gemma":[0.99900997,0.00012563026,0.00009534228,0.00041292576,0.00022225203,0.00013389112],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00034117248,0.00036675192,0.00039556756,0.00030601062,0.00044918177,0.00022789676,0.00020156067,0.00030419708,0.000051212097],"category_scores_gemma":[0.000012177174,0.0003477865,0.00021526849,0.00038003165,0.000041096748,0.00039454835,0.0000013698509,0.00043547305,0.000042244224],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000066000066,0.00027153533,0.000008609233,0.00014968206,0.00013960463,0.000002113793,0.0013275772,0.9435439,0.011640689,0.0007564009,0.002986883,0.03910699],"study_design_scores_gemma":[0.00081016513,0.00018648981,0.000018242876,0.00026934227,0.00010394246,0.00003293558,0.000624188,0.80503654,0.1884876,0.00012075766,0.003770978,0.0005387985],"about_ca_topic_score_codex":0.00008235109,"about_ca_topic_score_gemma":0.0006335845,"teacher_disagreement_score":0.9604372,"about_ca_system_score_codex":0.0002512417,"about_ca_system_score_gemma":0.000037870992,"threshold_uncertainty_score":0.9998974},"labels":[],"label_agreement":null},{"id":"W2103312793","doi":"10.1109/cicc.1988.20785","title":"Constraint propagation and design interaction in an object orientated IC design environment","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Smalltalk; Constraint (computer-aided design); Local consistency; Computer science; Consistency (knowledge bases); Object (grammar); Object-oriented design; Object-oriented programming; Programming language; Theoretical computer science; Constraint satisfaction; Human–computer interaction; Artificial intelligence; Engineering","score_opus":0.025779655090000075,"score_gpt":0.22958206443403548,"score_spread":0.2038024093440354,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2103312793","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.061936762,0.000037848124,0.936035,0.0000037840227,0.000039193554,0.00047122402,3.9442955e-7,0.00025998376,0.0012158103],"genre_scores_gemma":[0.9480409,0.00006693698,0.05177126,0.000013008145,0.000005252196,0.00006254596,0.0000033516105,0.000015357007,0.000021382233],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99939406,0.00012086009,0.000156241,0.00013636853,0.00006272706,0.00012973596],"domain_scores_gemma":[0.99980897,0.000037298414,0.000015357842,0.00008828382,0.000006462821,0.000043643096],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002813505,0.000105073435,0.0000881021,0.00009204221,0.000021134423,0.000030174058,0.000027647147,0.00005791942,0.00013714844],"category_scores_gemma":[0.000011385471,0.000099105375,0.00000912316,0.00006308507,0.0000233757,0.00023340125,0.0000032260784,0.000090811285,0.000012104655],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000064798434,0.00021962672,0.0016422153,0.000064292246,0.00004065223,0.00004441567,0.0020688353,0.08977973,0.80867213,0.0023438104,0.00066753087,0.09439197],"study_design_scores_gemma":[0.0004318857,0.00034240447,0.0007433151,0.000027678445,0.000010061771,0.000040853967,0.00041960715,0.15753463,0.83899665,0.0009279221,0.00023598642,0.00028902024],"about_ca_topic_score_codex":0.000005729748,"about_ca_topic_score_gemma":0.000002332041,"teacher_disagreement_score":0.88610417,"about_ca_system_score_codex":0.00010120975,"about_ca_system_score_gemma":0.000009046158,"threshold_uncertainty_score":0.40414},"labels":[],"label_agreement":null},{"id":"W2104079056","doi":"10.1145/1950413.1950445","title":"Scalable and deterministic timing-driven parallel placement for FPGAs","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Parallel computing; Scalability; Speedup; Bounding overwatch; Metric (unit); Simulated annealing; Parallelism (grammar); Algorithm","score_opus":0.049267417948559496,"score_gpt":0.23822344027810072,"score_spread":0.18895602232954123,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2104079056","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012704221,0.00008894929,0.9356799,0.000008673542,0.00006955781,0.00041569807,0.000005327633,0.0006852784,0.0503424],"genre_scores_gemma":[0.84258753,0.00003565651,0.15623531,0.000039435505,0.00002113321,0.00012335971,0.0000026411049,0.000021714312,0.0009332109],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996167,0.0000031352931,0.00009859441,0.00009342364,0.000035136552,0.00015301864],"domain_scores_gemma":[0.99981236,0.000022341683,0.0000083637415,0.00009614214,0.000011781188,0.000049003407],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004921425,0.00008476393,0.00009170792,0.000032472864,0.00002929804,0.000013051108,0.00005579927,0.000043427437,0.0001233759],"category_scores_gemma":[0.000005191046,0.00007623388,0.00002009833,0.000020326168,0.000015390036,0.000048222395,0.000014733003,0.000030300875,0.000013491873],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005306218,0.00082133326,0.013353916,0.0045729233,0.0010768174,0.00014517008,0.013844474,0.012393888,0.094500974,0.09301435,0.4029314,0.36281413],"study_design_scores_gemma":[0.0015622725,0.00080862705,0.0016602192,0.00011284845,0.00011471552,0.000036037403,0.00019174605,0.8673704,0.096235976,0.009026108,0.021860443,0.0010205805],"about_ca_topic_score_codex":0.000005807079,"about_ca_topic_score_gemma":0.000004325945,"teacher_disagreement_score":0.85497653,"about_ca_system_score_codex":0.0000119148835,"about_ca_system_score_gemma":0.0000032474702,"threshold_uncertainty_score":0.31087273},"labels":[],"label_agreement":null},{"id":"W2104156100","doi":"10.1109/ccece.2005.1557021","title":"Generating diverse pools of Steiner trees for VLSI routing","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Steiner tree problem; Very-large-scale integration; Routing (electronic design automation); Computer science; Tree (set theory); Interconnection; Iterated function; Set (abstract data type); Spanning tree; Combinatorics; Algorithm; Mathematics; Computer network","score_opus":0.0132736315981807,"score_gpt":0.21511545986744113,"score_spread":0.20184182826926042,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2104156100","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.26804546,0.00012896027,0.70952463,0.000012175084,0.00007916673,0.00025199924,0.000015561729,0.000760328,0.021181721],"genre_scores_gemma":[0.9435922,0.0000028161564,0.055451516,0.0000126136265,0.00013209356,0.000017296432,0.000008263629,0.000018225292,0.0007649926],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995562,0.000004476008,0.00017442575,0.00007237593,0.000056135643,0.00013639848],"domain_scores_gemma":[0.9998139,0.000033886023,0.000020673631,0.00008898915,0.000028078,0.000014430922],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007775817,0.000078906196,0.00011244582,0.000041538962,0.00002970942,0.000014082691,0.000059826438,0.000044982924,0.000030201309],"category_scores_gemma":[0.000009162876,0.000070098184,0.000053354554,0.00005396787,0.000008531422,0.000071108225,0.0000115524135,0.000031492276,0.0000019408485],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000024142544,0.000017672117,0.0014537085,0.000059368278,0.000022153275,0.0000013151855,0.00007438166,0.02679936,0.925726,0.006423405,0.01437717,0.025043074],"study_design_scores_gemma":[0.00029128857,0.000050807794,0.00053862826,0.000026841264,0.000018473222,0.0000014207362,0.00010381814,0.29412356,0.7027037,0.0005075401,0.0014300063,0.000203899],"about_ca_topic_score_codex":0.00007894669,"about_ca_topic_score_gemma":0.000042226733,"teacher_disagreement_score":0.6755467,"about_ca_system_score_codex":0.000014117471,"about_ca_system_score_gemma":0.000003062343,"threshold_uncertainty_score":0.28585207},"labels":[],"label_agreement":null},{"id":"W2104559065","doi":"10.1109/icpp.2008.89","title":"A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Verilog; Computer science; Algorithm; Speedup; Hypergraph; Parallel computing; Metric (unit); Algorithm design; Field-programmable gate array; Mathematics; Embedded system","score_opus":0.07598177386968231,"score_gpt":0.26839527080925396,"score_spread":0.19241349693957166,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2104559065","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0029770327,0.000051635314,0.99379206,0.00001002537,0.000074797164,0.00024000714,0.000015285044,0.00094798766,0.0018911808],"genre_scores_gemma":[0.69617444,0.00003056554,0.30308464,0.000036377543,0.00007219128,0.00008647067,0.000022425556,0.000021634065,0.00047121063],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99952054,0.000005580279,0.0001400699,0.00010006417,0.00006385364,0.00016988492],"domain_scores_gemma":[0.9997617,0.00005521331,0.000012832127,0.00009613694,0.000035786285,0.000038309507],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000054972657,0.000093962495,0.000099835685,0.000043559674,0.0000891423,0.000011621185,0.000048138543,0.000064276515,0.000052104388],"category_scores_gemma":[0.0000109982875,0.00009263136,0.000048933834,0.000057025707,0.000015282854,0.00013568277,0.0000064097862,0.00004836589,0.000026809099],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010273262,0.000043732263,0.00022830641,0.000044581007,0.00005529673,0.000010824414,0.00048235475,0.80007976,0.00431658,0.0006340133,0.009458294,0.18463598],"study_design_scores_gemma":[0.0002859748,0.000030324603,0.0005901217,0.0000075629755,0.000004568258,0.000004251892,0.000007749211,0.98646086,0.007126578,0.0005082454,0.0048327297,0.00014103972],"about_ca_topic_score_codex":0.000010138374,"about_ca_topic_score_gemma":0.0000026952648,"teacher_disagreement_score":0.6931974,"about_ca_system_score_codex":0.000026910957,"about_ca_system_score_gemma":0.000005574276,"threshold_uncertainty_score":0.37773973},"labels":[],"label_agreement":null},{"id":"W2104606487","doi":"10.1109/tvlsi.2011.2153883","title":"Optimizing Floating Point Units in Hybrid FPGAs","year":2011,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Field-programmable gate array; Adder; Floating point; Benchmark (surveying); Throughput; Lookup table; Parallel computing; Routing (electronic design automation); Flexibility (engineering); Floating-point unit; Computer hardware; Embedded system; Computer architecture; Algorithm; Latency (audio); Mathematics","score_opus":0.025628805194764796,"score_gpt":0.21296268698502904,"score_spread":0.18733388179026425,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2104606487","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.046991047,0.00015585142,0.9433909,0.0000091535485,0.0015882702,0.000552868,0.00008405825,0.0010960065,0.0061318506],"genre_scores_gemma":[0.9957795,0.00007898681,0.0034443263,0.000031153613,0.000080808284,0.00018110388,0.000016750611,0.000079257195,0.00030812077],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9981198,0.00014004315,0.00069579104,0.0003291656,0.00026638026,0.00044886567],"domain_scores_gemma":[0.99921125,0.000069258516,0.00007606835,0.00038443058,0.00013987644,0.00011910827],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004995248,0.00033838523,0.0003700187,0.0005420534,0.00016287022,0.0000925322,0.00021431164,0.00019265225,0.00012611096],"category_scores_gemma":[0.00000967425,0.00033886355,0.00011915891,0.00058352866,0.000030140398,0.0006106331,0.0000014742849,0.0005897791,0.000101129976],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00035647422,0.0017425846,0.00029857832,0.0011853114,0.0005455468,0.00031006633,0.051207624,0.6963913,0.17148761,0.001896839,0.0065978304,0.06798023],"study_design_scores_gemma":[0.0006805389,0.00017028548,0.000039565144,0.00083887664,0.000038662867,0.00007319728,0.003754419,0.51876575,0.47425416,0.00007918622,0.00068241055,0.00062296254],"about_ca_topic_score_codex":0.00030928047,"about_ca_topic_score_gemma":0.0003931076,"teacher_disagreement_score":0.94878846,"about_ca_system_score_codex":0.00028635107,"about_ca_system_score_gemma":0.000034843233,"threshold_uncertainty_score":0.99990636},"labels":[],"label_agreement":null},{"id":"W2104812993","doi":"10.1145/329166.329199","title":"Generating highly-routable sparse crossbars for PLDs","year":2000,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":38,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Routing (electronic design automation); Network routing; Sparse matrix; Parallel computing; Algorithm; Computer network","score_opus":0.013929553493395353,"score_gpt":0.22244625556785652,"score_spread":0.20851670207446116,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2104812993","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.40358204,0.0004893906,0.45274773,0.0000730706,0.0002568622,0.000617039,0.00003217121,0.0044601643,0.13774154],"genre_scores_gemma":[0.89202464,0.00007127044,0.09330155,0.00021726711,0.00022371284,0.000118064,0.000014407828,0.000055248318,0.013973833],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994386,0.0000040952673,0.00014534513,0.000112554844,0.000056405373,0.00024301105],"domain_scores_gemma":[0.99976677,0.000020671632,0.0000060131715,0.0001454678,0.000014701356,0.000046392826],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000082102546,0.000106369545,0.00011203772,0.000029533227,0.00007063498,0.00006257815,0.00008727193,0.00007355711,0.00095730746],"category_scores_gemma":[0.000004015701,0.0000999035,0.000047948724,0.00006644278,0.000011100274,0.00012078911,0.000005060113,0.00005523464,0.00008239628],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018535025,0.000052468004,0.00024326757,0.00014650021,0.00007480622,0.000010057112,0.00042165842,0.109756686,0.235172,0.0039147916,0.2174686,0.43272063],"study_design_scores_gemma":[0.000376137,0.000072813695,0.000042325843,0.00001771226,0.000013346803,0.000008506799,0.000017694147,0.44076833,0.33308727,0.00095293333,0.22424796,0.00039499326],"about_ca_topic_score_codex":0.000019892736,"about_ca_topic_score_gemma":0.000007826195,"teacher_disagreement_score":0.4884426,"about_ca_system_score_codex":0.000024280012,"about_ca_system_score_gemma":0.000005808829,"threshold_uncertainty_score":0.99995595},"labels":[],"label_agreement":null},{"id":"W2105601985","doi":"10.1109/mwscas.2007.4488736","title":"Parasitic-aware physical design optimization of deep sub-micron analog circuits","year":2007,"lang":"en","type":"article","venue":"Conference proceedings","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Physical design; Design flow; Computer science; Schematic; Software portability; Electronic engineering; Electronic circuit; Analogue electronics; Parasitic extraction; Integrated circuit design; Electronic design automation; Reliability (semiconductor); Circuit design; Computer architecture; Computer engineering; Embedded system; Engineering; Electrical engineering","score_opus":0.02110707230612559,"score_gpt":0.23844966280508517,"score_spread":0.21734259049895957,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2105601985","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10323435,0.00004991804,0.8928217,0.000007737248,0.000037081827,0.0002080216,0.000002004665,0.00043227943,0.0032068694],"genre_scores_gemma":[0.9920209,0.000047155285,0.0078042485,0.0000131082925,0.00005489786,0.000015712249,0.000005928427,0.00002956394,0.000008470215],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99916345,0.000003448107,0.00022281455,0.00017646459,0.00014887749,0.00028496108],"domain_scores_gemma":[0.9994873,0.000033196655,0.000057148925,0.000075396725,0.00026615194,0.00008081009],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021148362,0.00016667836,0.0002190908,0.00012753136,0.000035387628,0.000039910203,0.00017927386,0.00011505085,0.000022879885],"category_scores_gemma":[0.0000310254,0.00017432508,0.000044395445,0.00025246348,0.000057308356,0.0002316905,0.0000123247355,0.00014086752,0.0000076161045],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018169478,0.000091320864,0.0016098194,0.00032880303,0.000044654855,0.0000059361428,0.0027011454,0.0072454787,0.9325323,0.0031964392,0.00054147764,0.051684454],"study_design_scores_gemma":[0.00012405882,0.000097140844,0.00071150804,0.00006387965,0.000023041372,0.0000068332406,0.00014915068,0.28098363,0.71666944,0.0009452708,0.000016228372,0.00020982491],"about_ca_topic_score_codex":0.0000019765582,"about_ca_topic_score_gemma":5.321403e-7,"teacher_disagreement_score":0.88878655,"about_ca_system_score_codex":0.000048075373,"about_ca_system_score_gemma":0.000017208482,"threshold_uncertainty_score":0.71087706},"labels":[],"label_agreement":null},{"id":"W2106448546","doi":"10.1145/1065579.1065770","title":"Logic block clustering of large designs for channel-width constrained FPGAs","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":35,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Western Canada Research Grid","keywords":"Computer science; Field-programmable gate array; Block (permutation group theory); Cluster analysis; Logic block; Parallel computing; Channel (broadcasting); Logic gate; Logic synthesis; Algorithm; Computer architecture; Computer hardware; Mathematics; Telecommunications; Artificial intelligence","score_opus":0.03243443050342985,"score_gpt":0.2615054143327757,"score_spread":0.22907098382934585,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2106448546","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019967319,0.00015131959,0.98148143,0.000083160696,0.00006448251,0.00038592351,0.000027156973,0.00080203795,0.015007737],"genre_scores_gemma":[0.91814464,0.000032314056,0.08116353,0.0001166968,0.000098305536,0.000050396095,0.0000060452285,0.00002902155,0.0003590247],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992812,0.000008048261,0.00023659349,0.000116859504,0.00006908693,0.00028816986],"domain_scores_gemma":[0.9996804,0.000055480905,0.000025644518,0.00014737826,0.00003817803,0.00005291127],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017773747,0.00013669465,0.00019914526,0.00008425727,0.00003100093,0.000010926517,0.00011840461,0.0000969955,0.00012778872],"category_scores_gemma":[0.000015718722,0.00012633514,0.00007933147,0.000078313926,0.000021466634,0.00007851107,0.000019619702,0.00006231352,0.000009478171],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000114915,0.0005391005,0.00013799484,0.001670693,0.0004989633,0.00001838329,0.0021112498,0.16588125,0.62407774,0.040028293,0.080885306,0.084036104],"study_design_scores_gemma":[0.00083558273,0.00019605846,0.000024206072,0.00004996998,0.00002617592,0.00001830402,0.00008284417,0.61026794,0.37621295,0.0018583843,0.010077837,0.00034972638],"about_ca_topic_score_codex":0.0000023225869,"about_ca_topic_score_gemma":0.000019041703,"teacher_disagreement_score":0.91614795,"about_ca_system_score_codex":0.000027416776,"about_ca_system_score_gemma":0.000008611582,"threshold_uncertainty_score":0.51517975},"labels":[],"label_agreement":null},{"id":"W2106697480","doi":"10.1145/2145694.2145754","title":"Parallel FPGA placement based on individual LUT placement (abstract only)","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Lookup table; Computer science; Parallel computing; Placement; Path (computing); CAD; Critical path method; Computer hardware; Computer architecture; Embedded system; Physical design; Circuit design; Engineering; Engineering drawing","score_opus":0.026335585204179786,"score_gpt":0.2456686059204377,"score_spread":0.21933302071625793,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2106697480","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.097126335,0.00051286654,0.35788485,0.00029781752,0.0012013029,0.0017476392,0.000086823915,0.0053559053,0.53578645],"genre_scores_gemma":[0.98906034,0.000018015107,0.009621886,0.00041798214,0.00015574186,0.00008355554,0.000043492757,0.00004306753,0.00055590464],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99875,0.00001632866,0.0002428684,0.00014819515,0.00034829683,0.0004943408],"domain_scores_gemma":[0.9994408,0.00006325833,0.000026562115,0.00028534667,0.000012548779,0.0001715099],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00032656812,0.00023632769,0.00016481848,0.00013230342,0.000050113926,0.000039273506,0.00017050508,0.00011427308,0.0016930045],"category_scores_gemma":[0.000008300265,0.00020790516,0.00006712676,0.00008539003,0.000015090695,0.0001499773,0.000025440271,0.00019537029,0.000319857],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00025034792,0.0021398768,0.014145235,0.00041297934,0.0005119938,0.000031052194,0.0014149784,0.22081542,0.008038372,0.0078074518,0.6633668,0.08106549],"study_design_scores_gemma":[0.008383934,0.002184842,0.09908527,0.00045802377,0.00031441645,0.000032160217,0.001056807,0.11091582,0.3781998,0.0003585916,0.3939372,0.0050731613],"about_ca_topic_score_codex":0.00000841363,"about_ca_topic_score_gemma":0.000003659828,"teacher_disagreement_score":0.89193404,"about_ca_system_score_codex":0.00011527594,"about_ca_system_score_gemma":0.000019267214,"threshold_uncertainty_score":0.9992196},"labels":[],"label_agreement":null},{"id":"W2106794245","doi":"10.1109/ccece.1998.682781","title":"A nonlinear programming placement approach based on target distance model and iterative construction method","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Computer science; Nonlinear system; Iterative method; Set (abstract data type); Placement; Very-large-scale integration; Mathematical optimization; Nonlinear programming; Algorithm; Feature (linguistics); Function (biology); Physical design; Mathematics; Integrated circuit; Programming language","score_opus":0.0185942786680179,"score_gpt":0.23841179964197282,"score_spread":0.2198175209739549,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2106794245","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00034025844,0.00006298242,0.98485273,0.00002401843,0.000016883068,0.00027720377,0.000009008644,0.00048994017,0.013926983],"genre_scores_gemma":[0.11808622,0.000009606455,0.8815914,0.000057092977,0.00001734055,0.00007825187,0.000008904839,0.000015854623,0.00013536392],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999472,0.00001765834,0.00012024272,0.00015797549,0.00009413312,0.00013794356],"domain_scores_gemma":[0.99979603,0.000020335474,0.00001450503,0.00010382438,0.000022112206,0.00004319912],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009683915,0.00012292106,0.000114533745,0.00005526003,0.00004262254,0.000040355015,0.000035406632,0.000051031493,0.000030259434],"category_scores_gemma":[0.000006241988,0.000106817264,0.00002201357,0.000080463025,0.000021818125,0.00007970981,0.000006004504,0.00010000292,0.0000016712494],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000030199257,0.0002346561,0.000117836236,0.00023067073,0.00005135656,0.000004283893,0.0011290063,0.8206009,0.0032985613,0.0061265817,0.0017903603,0.16638558],"study_design_scores_gemma":[0.0001922219,0.00005632012,9.611542e-7,0.000014040894,0.0000052559853,0.0000028016668,0.00005387533,0.9885657,0.009689939,0.00010826358,0.0011785663,0.00013209583],"about_ca_topic_score_codex":9.3405527e-7,"about_ca_topic_score_gemma":3.4992647e-7,"teacher_disagreement_score":0.16796474,"about_ca_system_score_codex":0.00003551554,"about_ca_system_score_gemma":0.0000023770535,"threshold_uncertainty_score":0.43558815},"labels":[],"label_agreement":null},{"id":"W2107547422","doi":"10.5555/1950815.1950972","title":"An integer programming placement approach to FPGA clock power reduction","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Clock skew; Digital clock manager; Clock network; Clock gating; CPU multiplier; Computer science; Field-programmable gate array; Integer programming; Synchronous circuit; Reduction (mathematics); Static timing analysis; Routing (electronic design automation); Dynamic demand; Clock rate; Skew; Timing failure; Parallel computing; Embedded system; Power (physics); Clock signal; Mathematics; Algorithm; Jitter; Telecommunications; Chip","score_opus":0.026024550565928735,"score_gpt":0.22797989032749408,"score_spread":0.20195533976156535,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2107547422","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022137947,0.000028164113,0.8131089,0.0000057495267,0.0001714972,0.0004617069,6.1779986e-7,0.0019250601,0.16216035],"genre_scores_gemma":[0.85421866,0.0000026292173,0.14523701,0.000021086902,0.00004196938,0.0001215068,0.000004305569,0.000027332633,0.000325505],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993934,0.000011175754,0.00013729741,0.00016363838,0.00008908153,0.00020542582],"domain_scores_gemma":[0.99963427,0.0000015882572,0.0000090461945,0.0002293311,0.000025256135,0.000100490935],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012997333,0.000117682896,0.00009009539,0.000094297786,0.000026511732,0.000026922862,0.00011681813,0.00006758968,0.00015068964],"category_scores_gemma":[0.0000024375986,0.00010391966,0.00002787245,0.00012607248,0.000009846176,0.00015131867,0.000014988486,0.00009372384,0.000047551086],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015686845,0.0020197516,0.00050797244,0.00025509737,0.00028239482,0.000011967733,0.03995875,0.004522844,0.16570863,0.037298393,0.08479188,0.66448545],"study_design_scores_gemma":[0.00046260853,0.0014837182,0.00081568497,0.000062083884,0.000045613437,0.000081878476,0.005611286,0.015844522,0.9074011,0.00070039724,0.066013224,0.0014779173],"about_ca_topic_score_codex":0.000025646548,"about_ca_topic_score_gemma":0.0000010487356,"teacher_disagreement_score":0.8320807,"about_ca_system_score_codex":0.000048649174,"about_ca_system_score_gemma":0.0000039394486,"threshold_uncertainty_score":0.42377207},"labels":[],"label_agreement":null},{"id":"W2107940981","doi":"10.5555/1351542.1351654","title":"Optimizing time warp simulation with reinforcement learning techniques","year":2007,"lang":"en","type":"article","venue":"Winter Simulation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Reinforcement learning; Computer science; Benchmark (surveying); Bellman equation; Dynamic programming; Function (biology); Bounded function; State (computer science); Optimal control; Artificial intelligence; Mathematical optimization; Algorithm; Mathematics","score_opus":0.01747016352218258,"score_gpt":0.25604442832303126,"score_spread":0.23857426480084867,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2107940981","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009935752,0.000015630489,0.969902,0.000010370532,0.000035418274,0.0002752017,4.9886944e-7,0.0017041949,0.018120958],"genre_scores_gemma":[0.98137736,0.0000045827137,0.017866598,0.00003738791,0.00007204509,0.000010602856,0.000022546055,0.000036725196,0.0005721278],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990458,0.000017803926,0.0003028787,0.00018096094,0.00019925974,0.0002533334],"domain_scores_gemma":[0.99940115,0.0001319234,0.00006361639,0.00017861938,0.00016095067,0.00006374169],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00026562327,0.00018920952,0.00015976382,0.00017296312,0.00007406136,0.00007616848,0.00011545973,0.000105109655,0.0002506616],"category_scores_gemma":[0.000022457323,0.00017679647,0.00003624635,0.00014855241,0.00002803686,0.0003519836,0.000024389688,0.00020926815,0.000050326795],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000027285643,0.0000053780777,0.00016692646,0.000016776406,0.00001595303,0.0000035323192,0.0005436584,0.9677208,0.0077564963,0.000092394985,0.000017620567,0.023633141],"study_design_scores_gemma":[0.0001452916,0.00013047656,0.00014901446,0.000116749114,0.000010641773,0.0000014513068,0.00003402839,0.9462466,0.049271595,0.000059479073,0.0035970635,0.00023758881],"about_ca_topic_score_codex":0.0000034775633,"about_ca_topic_score_gemma":0.0000023681484,"teacher_disagreement_score":0.9714416,"about_ca_system_score_codex":0.00008771767,"about_ca_system_score_gemma":0.0000113305805,"threshold_uncertainty_score":0.7209551},"labels":[],"label_agreement":null},{"id":"W2108099581","doi":"10.1109/ipdps.2008.4536237","title":"A new diffusion-based multilevel algorithm for computing graph partitions of very high quality","year":2008,"lang":"en","type":"article","venue":"Proceedings - IEEE International Parallel and Distributed Processing Symposium","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":47,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Computer science; Partition (number theory); Graph; Heuristic; Algorithm; Vertex (graph theory); Theoretical computer science; Parallel computing; Mathematics; Combinatorics; Artificial intelligence","score_opus":0.027036500708916063,"score_gpt":0.27406991313517715,"score_spread":0.2470334124262611,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2108099581","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.091218375,0.00013859561,0.90693593,0.00020370043,0.00021619909,0.00025414972,0.00036652866,0.0004250623,0.00024143909],"genre_scores_gemma":[0.91502464,0.00006788603,0.08428211,0.000047663798,0.00019607518,0.00006239552,0.00024372808,0.000028664186,0.000046847348],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99865454,0.000005116042,0.00050917425,0.0002854197,0.0002795751,0.00026617307],"domain_scores_gemma":[0.9991144,0.0000903145,0.0001796057,0.00006087376,0.00042471325,0.00013011236],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014529185,0.00023745158,0.00030507773,0.00015249166,0.00021418219,0.00007674744,0.00021502255,0.00013212023,0.0000073912674],"category_scores_gemma":[0.0000388481,0.00023888468,0.000102106766,0.00017742426,0.00009598116,0.00029148685,0.0000255654,0.00014255349,9.3603404e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00094109675,0.0021951215,0.04701219,0.0056404187,0.0011855582,0.000030527935,0.0055061863,0.075074,0.5504491,0.008731439,0.07882733,0.22440703],"study_design_scores_gemma":[0.0027908923,0.00014618991,0.009007657,0.0004930208,0.00007344143,0.000043316955,0.00010857455,0.9282164,0.050427202,0.0068941643,0.0010582405,0.0007409182],"about_ca_topic_score_codex":0.000060347287,"about_ca_topic_score_gemma":9.1639845e-7,"teacher_disagreement_score":0.8531424,"about_ca_system_score_codex":0.000057964986,"about_ca_system_score_gemma":0.00006718477,"threshold_uncertainty_score":0.97414345},"labels":[],"label_agreement":null},{"id":"W2108349468","doi":"10.1145/1120725.1120786","title":"A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Tsinghua University; University of Toronto","keywords":"RLC circuit; Crosstalk; Computer science; Routing (electronic design automation); Network routing; Electronic engineering; Voltage; Computer network; Electrical engineering; Engineering; Capacitor","score_opus":0.00848239604748847,"score_gpt":0.21167072350418972,"score_spread":0.20318832745670126,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2108349468","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7466647,0.00010052714,0.18717544,0.0002065816,0.00003970411,0.0003216968,0.000006636231,0.0013633611,0.064121366],"genre_scores_gemma":[0.96066946,0.000023045744,0.038887035,0.000058726935,0.000051511106,0.000019813955,0.0000019113431,0.000010441051,0.0002780642],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99945956,0.0000035519058,0.00012725264,0.00011660066,0.00007193669,0.00022110777],"domain_scores_gemma":[0.9998103,0.000004861624,0.000009568865,0.00008958108,0.0000181441,0.00006758881],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006752947,0.00010017319,0.000088509594,0.000026137188,0.00006096889,0.000049088794,0.000061567545,0.00005435525,0.00002537396],"category_scores_gemma":[0.0000036270496,0.000094660936,0.000017030661,0.00010145821,0.000012647715,0.00018838674,0.000034136017,0.000052354288,0.000030362933],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000024258234,0.000073157455,0.04202601,0.00022555824,0.000057114426,0.000006767053,0.0017455332,0.017676923,0.066430695,0.0027668471,0.037785437,0.8311817],"study_design_scores_gemma":[0.00046462702,0.00025178056,0.014895405,0.0001600178,0.000018882027,0.000056404646,0.00006466173,0.90944356,0.04873652,0.00024555114,0.024979781,0.00068280014],"about_ca_topic_score_codex":0.000019346147,"about_ca_topic_score_gemma":0.000056381174,"teacher_disagreement_score":0.89176667,"about_ca_system_score_codex":0.000096223215,"about_ca_system_score_gemma":0.000006057814,"threshold_uncertainty_score":0.3860161},"labels":[],"label_agreement":null},{"id":"W2110405757","doi":"10.1109/tcad.2005.860957","title":"Placement Algorithm in Analog-Layout Designs","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University; Dalhousie University","funders":"","keywords":"Computer science; Algorithm","score_opus":0.026449712335902133,"score_gpt":0.21781510018232786,"score_spread":0.19136538784642573,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2110405757","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0057917675,0.00045062546,0.99152994,0.000003931649,0.0006349033,0.00073273253,0.00006665006,0.00044257953,0.00034683922],"genre_scores_gemma":[0.99304473,0.000108226806,0.0065045822,0.00001294828,0.00006203153,0.000120784585,0.000010004322,0.000049792496,0.00008691821],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9981187,0.00018829863,0.00076480856,0.0003308354,0.00024497384,0.00035236403],"domain_scores_gemma":[0.9992782,0.00017580572,0.00008417449,0.00026755958,0.000108196284,0.00008605384],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00042221215,0.00035201295,0.0005398063,0.0006090558,0.00007174122,0.00008627028,0.00018022381,0.00022638326,0.000014686853],"category_scores_gemma":[0.0000011297484,0.0003250045,0.000086392225,0.0005022311,0.000055650788,0.00014556963,6.9222443e-7,0.00033008272,0.0000071465993],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000150875085,0.00020985084,0.00001731032,0.000120409124,0.000102919344,0.000037699927,0.00017797071,0.8731887,0.032595344,0.00015351495,0.0009869413,0.09239429],"study_design_scores_gemma":[0.000747844,0.00050972804,0.00005809241,0.00043441931,0.00003400023,0.00005982307,0.00012092947,0.9405707,0.056839276,0.00011273598,0.00012057995,0.00039188316],"about_ca_topic_score_codex":0.00061218766,"about_ca_topic_score_gemma":0.000022506341,"teacher_disagreement_score":0.98725295,"about_ca_system_score_codex":0.00017963054,"about_ca_system_score_gemma":0.000046367117,"threshold_uncertainty_score":0.9999202},"labels":[],"label_agreement":null},{"id":"W2110659707","doi":"10.1109/pcee.2000.873615","title":"Parallel efficient implementation of hierarchical algorithms for module placement of large chips","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"St. Francis Xavier University","funders":"","keywords":"Computer science; Algorithm; Benchmark (surveying); Simulated annealing; Parallel computing; Convergence (economics); Electronic circuit; Placement; Multiprocessing; Integrated circuit; Physical design","score_opus":0.0253424165269703,"score_gpt":0.2836081885869562,"score_spread":0.2582657720599859,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2110659707","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.069715634,0.00009681256,0.9279707,0.000029349138,0.000042991745,0.00045205778,0.00006552078,0.00013674013,0.001490189],"genre_scores_gemma":[0.94561774,0.000029305298,0.054163516,0.000011478046,0.000018224575,0.00006743944,0.000014585421,0.00001270106,0.00006503594],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994021,0.000007952861,0.00024430576,0.00007928621,0.000110885245,0.00015546686],"domain_scores_gemma":[0.9997881,0.000025681702,0.000027279435,0.00010529339,0.000025111935,0.000028498853],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012394274,0.00007178791,0.00012853541,0.00006325234,0.000016224547,0.0000030060135,0.00006464938,0.00003516453,0.0003432577],"category_scores_gemma":[0.0000030342896,0.00006641823,0.000055099095,0.00006098118,0.000010925254,0.000021027936,0.000012897481,0.000036777747,0.000002281323],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012394469,0.002516856,0.0026461398,0.0024745795,0.0007864426,0.0000046284126,0.009000072,0.18035309,0.22751339,0.12662357,0.10364635,0.34431094],"study_design_scores_gemma":[0.0009980028,0.00022082128,0.0004657091,0.000011757313,0.000013939647,7.432176e-7,0.00017829018,0.7576238,0.2390745,0.0003193238,0.00097395916,0.00011916735],"about_ca_topic_score_codex":0.000006563678,"about_ca_topic_score_gemma":0.0000037304244,"teacher_disagreement_score":0.87590206,"about_ca_system_score_codex":0.000018281024,"about_ca_system_score_gemma":0.0000023244272,"threshold_uncertainty_score":0.3758431},"labels":[],"label_agreement":null},{"id":"W2110681214","doi":"10.1109/tvlsi.2009.2029232","title":"The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Datapath; Computer science; Routing (electronic design automation); Field-programmable gate array; Logic block; Block (permutation group theory); Electronic circuit; Computer hardware; Parallel computing; Embedded system; Engineering; Electrical engineering; Mathematics","score_opus":0.011492852009050107,"score_gpt":0.22445098763695798,"score_spread":0.21295813562790786,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2110681214","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.028101366,0.00016220882,0.96913314,0.00007104418,0.0006383796,0.0010544915,0.000018352432,0.00029850515,0.00052253023],"genre_scores_gemma":[0.9989475,0.00006216456,0.0004736869,0.000016619762,0.000045985413,0.00014899985,0.000003297067,0.000025718542,0.00027602987],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9982784,0.00040976852,0.0005649064,0.00018302331,0.00030804152,0.0002559031],"domain_scores_gemma":[0.9981691,0.0010418232,0.00016365046,0.0004904488,0.00009425789,0.000040697698],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0012116295,0.00023709227,0.00029920827,0.00013234453,0.00031160068,0.00008215017,0.00027799566,0.00018890358,0.000010794537],"category_scores_gemma":[0.000049596194,0.00014217163,0.00017671075,0.0003158662,0.000039325307,0.00015221354,7.303786e-7,0.0004064812,0.000012540276],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00040928886,0.0001881082,0.00006792108,0.0001326509,0.00016877794,0.0000018180593,0.002685541,0.8157995,0.13237788,0.0003523738,0.0010744344,0.046741735],"study_design_scores_gemma":[0.00032157765,0.00086561334,0.000029696794,0.00038566894,0.00004370707,0.0000039693336,0.00044447693,0.45414436,0.54335755,0.000027787126,0.00024045508,0.0001351318],"about_ca_topic_score_codex":0.0000518858,"about_ca_topic_score_gemma":0.000036561396,"teacher_disagreement_score":0.9708461,"about_ca_system_score_codex":0.00007584407,"about_ca_system_score_gemma":0.000010421932,"threshold_uncertainty_score":0.5797591},"labels":[],"label_agreement":null},{"id":"W2111337158","doi":"10.1145/1228784.1228915","title":"Floorplan repair using dynamic whitespace management","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary; University of Waterloo","funders":"","keywords":"Floorplan; Computer science; Range (aeronautics); Design flow; Integrated circuit layout; Parallel computing; Algorithm; Embedded system; Integrated circuit; Engineering","score_opus":0.007260622656705033,"score_gpt":0.23185367201022636,"score_spread":0.2245930493535213,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2111337158","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.055033416,0.00013542255,0.8112821,0.000007862034,0.000120913835,0.00014313977,7.9459784e-7,0.0035482438,0.12972811],"genre_scores_gemma":[0.84463406,0.00003598129,0.1534839,0.000049205257,0.00002391659,0.0000026259881,0.0000024253006,0.000028527138,0.001739349],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994792,0.0000035248427,0.00011855837,0.00010001185,0.00008268545,0.00021606774],"domain_scores_gemma":[0.99974954,0.0000090397525,0.0000075187854,0.00018075769,0.000008334732,0.000044836135],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017932263,0.00009356208,0.000074118514,0.00011461444,0.000026230658,0.000012717711,0.00006962491,0.000048394817,0.000076317236],"category_scores_gemma":[0.0000012226834,0.00009133981,0.00004219714,0.00013917618,0.000008173526,0.000059283455,0.00001970396,0.00006280825,0.000034422053],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000840144,0.00032980874,0.022464124,0.0022170418,0.0014141576,0.0022631157,0.0017479031,0.03850785,0.40480906,0.037256002,0.119116634,0.3697903],"study_design_scores_gemma":[0.00068654557,0.00010523013,0.016062101,0.00019117777,0.00009680453,0.00012520762,0.0008034413,0.84714663,0.07712781,0.0021430752,0.054000434,0.0015115655],"about_ca_topic_score_codex":0.000008304282,"about_ca_topic_score_gemma":0.00002316385,"teacher_disagreement_score":0.80863875,"about_ca_system_score_codex":0.00007718714,"about_ca_system_score_gemma":0.0000013064985,"threshold_uncertainty_score":0.3724729},"labels":[],"label_agreement":null},{"id":"W2111427553","doi":"10.1145/1046192.1046220","title":"Design, layout and verification of an FPGA using automated tools","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":51,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Field-programmable gate array; Computer science; Process (computing); Embedded system; Electronic design automation; Architecture; Design layout record; FPGA prototype; Design flow; Automation; Computer architecture; Set (abstract data type); Integrated circuit layout; Reconfigurable computing; Computer hardware; Integrated circuit; Engineering; Operating system; Circuit extraction","score_opus":0.04524113431800826,"score_gpt":0.2662992822355516,"score_spread":0.22105814791754336,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2111427553","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.48166484,0.00009025124,0.5151646,0.000006425385,0.00001392748,0.00012819639,0.0000018590796,0.0016999361,0.0012299555],"genre_scores_gemma":[0.8443482,0.0000130991475,0.15558304,0.000010163921,0.000015417178,0.0000031586337,0.0000028377387,0.00001111086,0.000012958378],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996854,0.000013394361,0.00011628687,0.00006486419,0.0000444813,0.00007555226],"domain_scores_gemma":[0.99981904,0.000013427266,0.0000135802275,0.00010876097,0.00001811601,0.00002710086],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009395096,0.000058758385,0.00007644989,0.000047528876,0.000014836109,0.000018735142,0.000042466752,0.000051205516,0.000025229645],"category_scores_gemma":[0.000004990072,0.00005638077,0.000008331994,0.000061953506,0.000011995959,0.0002515552,0.0000047027556,0.000028750692,0.000002738309],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000036740128,0.000017638718,0.000043688546,0.00002511711,0.000010858143,5.9133856e-7,0.00021813464,0.023753706,0.90167856,0.00016172799,0.00031013193,0.07377615],"study_design_scores_gemma":[0.00004608331,0.000016386675,0.0004280573,0.000005734852,0.0000040656623,0.0000029893988,0.000010174258,0.5954747,0.40383497,0.000026637696,0.00009903185,0.000051185256],"about_ca_topic_score_codex":0.000008958178,"about_ca_topic_score_gemma":0.0000012938324,"teacher_disagreement_score":0.57172096,"about_ca_system_score_codex":0.00001793852,"about_ca_system_score_gemma":0.0000048626152,"threshold_uncertainty_score":0.22991411},"labels":[],"label_agreement":null},{"id":"W2111524252","doi":"10.1109/cicc.1993.590685","title":"A combined eigenvector tabu search approach for circuit partitioning","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Tabu search; Guided Local Search; Eigenvalues and eigenvectors; Partition (number theory); Mathematical optimization; Computer science; Algorithm; Iterative method; Search algorithm; Mathematics","score_opus":0.06031010982164158,"score_gpt":0.2190760474328658,"score_spread":0.1587659376112242,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2111524252","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00446041,0.00013465626,0.92426133,0.000017842003,0.00004390533,0.00039631053,0.0000073413535,0.001321541,0.069356665],"genre_scores_gemma":[0.9780801,0.000028427245,0.020161677,0.00004314401,0.000072841205,0.00021718741,0.000017990269,0.000033457723,0.0013451555],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99940574,0.000008746789,0.00012329897,0.00012161766,0.00008887763,0.00025170017],"domain_scores_gemma":[0.999731,0.00003019918,0.000006108863,0.00014620964,0.00002652986,0.000059975147],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000100450314,0.00009514925,0.00011298801,0.00006065187,0.000063379724,0.000038324302,0.0000955559,0.00006397066,0.00048871286],"category_scores_gemma":[0.000007686729,0.00009304939,0.00005410029,0.00011549633,0.000015329695,0.00008327763,0.000008714541,0.00008254798,0.000041679523],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000032186275,0.0008774232,0.0043481966,0.0017710474,0.0005440029,0.00001792104,0.0044027986,0.026685463,0.24052262,0.13386886,0.4516558,0.13527367],"study_design_scores_gemma":[0.00041919673,0.000109454915,0.00015943772,0.000010411533,0.000012000088,0.0000041618187,0.00006338224,0.9235094,0.07178688,0.00085791154,0.0027893367,0.0002783933],"about_ca_topic_score_codex":0.000005520899,"about_ca_topic_score_gemma":4.5552935e-7,"teacher_disagreement_score":0.9736197,"about_ca_system_score_codex":0.000031422383,"about_ca_system_score_gemma":0.0000021503233,"threshold_uncertainty_score":0.5351063},"labels":[],"label_agreement":null},{"id":"W2112003649","doi":"10.1145/370155.370571","title":"Combinatorial routing analysis and design of universal switch blocks","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"Routing (electronic design automation); Block (permutation group theory); Computer science; Set (abstract data type); USB; Decomposition; Dimension (graph theory); Constraint (computer-aided design); Parallel computing; Mathematics; Topology (electrical circuits); Discrete mathematics; Combinatorics; Embedded system; Operating system; Programming language; Software","score_opus":0.01005446106605642,"score_gpt":0.20406582588712713,"score_spread":0.1940113648210707,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2112003649","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10696795,0.000044120246,0.88202864,0.000005569634,0.000049067265,0.000070247304,7.0137196e-7,0.00031248954,0.010521229],"genre_scores_gemma":[0.995028,0.00006625471,0.0047855214,0.000003391026,0.000021513959,0.0000013023051,0.0000010529053,0.00000799733,0.00008491988],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996249,0.0000127201165,0.00011411201,0.000075494994,0.00006728911,0.00010550407],"domain_scores_gemma":[0.9997893,0.000045570116,0.000015248305,0.000094060466,0.000022405804,0.00003339562],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011831124,0.00007017711,0.0001526247,0.00014104009,0.00001952928,0.00001005666,0.000057138222,0.000057457524,0.00010348718],"category_scores_gemma":[0.0000068141917,0.00006761728,0.000035662335,0.0003907361,0.000015104779,0.000055177774,0.000013456749,0.000052653635,8.0692405e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002318832,0.0003597415,0.25102177,0.00016795643,0.006584687,0.00021085028,0.0035579347,0.089895025,0.43531284,0.08542021,0.0054724663,0.12176464],"study_design_scores_gemma":[0.0011230815,0.00021228868,0.005046856,0.00002450413,0.0008318901,0.000013563897,0.00033454405,0.8049332,0.1824514,0.0038928937,0.00057900307,0.00055677455],"about_ca_topic_score_codex":0.000080183636,"about_ca_topic_score_gemma":0.0000039516704,"teacher_disagreement_score":0.8880601,"about_ca_system_score_codex":0.000015726977,"about_ca_system_score_gemma":0.000004343529,"threshold_uncertainty_score":0.27573526},"labels":[],"label_agreement":null},{"id":"W2112357703","doi":"10.1109/cicc.2005.1568636","title":"An improved \"soft\" eFPGA design and implementation strategy","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":30,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Application-specific integrated circuit; Field-programmable gate array; Overhead (engineering); Computer science; Design flow; Standard cell; Logic synthesis; Embedded system; Computer architecture; Physical design; Programmable logic device; Integrated circuit design; Quality (philosophy); Electronic design automation; Logic gate; Computer hardware; Circuit design; Integrated circuit; Algorithm; Operating system","score_opus":0.010583452235490438,"score_gpt":0.25233526301391923,"score_spread":0.2417518107784288,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2112357703","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.059233807,0.000088677996,0.9371498,0.0000062809845,0.000019534813,0.00022969901,0.0000023445887,0.0008948386,0.0023750092],"genre_scores_gemma":[0.97273207,0.000014671961,0.027092112,0.000015851627,0.000037974885,0.000026493968,0.00001497617,0.000017138937,0.00004872265],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99961627,0.000012538974,0.00011086382,0.00009144886,0.00003897417,0.0001299321],"domain_scores_gemma":[0.99985135,0.00001106773,0.0000090480335,0.00008515443,0.000012191753,0.000031184692],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008604499,0.00008199118,0.00006243685,0.000040968902,0.00002662438,0.000052286185,0.000040661333,0.00004143936,0.000094093855],"category_scores_gemma":[4.2596744e-7,0.00007669169,0.000009926834,0.000047240253,0.000008453514,0.00018564568,0.0000035077344,0.000037136484,0.0000033787942],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000035593018,0.000015409205,0.00030682192,0.000019437526,0.000008844885,0.0000021814485,0.000040403007,0.0022936019,0.8490734,0.0018943152,0.003979189,0.14236285],"study_design_scores_gemma":[0.00047131372,0.00031658274,0.007157997,0.0000036961374,0.000015684343,0.000008699478,0.0001537762,0.31543782,0.6679999,0.0075842487,0.00051213405,0.00033809798],"about_ca_topic_score_codex":0.00017035953,"about_ca_topic_score_gemma":0.00003695638,"teacher_disagreement_score":0.9134982,"about_ca_system_score_codex":0.000015270361,"about_ca_system_score_gemma":0.000005224309,"threshold_uncertainty_score":0.31273964},"labels":[],"label_agreement":null},{"id":"W2112586548","doi":"10.1109/cicc.1994.379741","title":"Minimizing interconnection delays in array-based FPGAs","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Interconnection; Field-programmable gate array; Computer science; CAD; Limit (mathematics); Focus (optics); Perspective (graphical); Computer architecture; Embedded system; Electronic circuit; Computer engineering; Engineering; Telecommunications; Artificial intelligence; Electrical engineering; Engineering drawing; Mathematics","score_opus":0.019054710568053,"score_gpt":0.1859508983327029,"score_spread":0.1668961877646499,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2112586548","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1309449,0.00019768722,0.7312033,0.00011237702,0.00020258615,0.00015821574,0.0000010264172,0.0018249684,0.13535492],"genre_scores_gemma":[0.9892713,0.00002160221,0.010423797,0.00009256986,0.00002939876,0.000020611467,0.0000012259287,0.00001797795,0.00012151568],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99958324,0.000009768262,0.0001316471,0.00008759966,0.00004671711,0.00014102024],"domain_scores_gemma":[0.99982977,0.000025523426,0.000007014796,0.00010306716,0.000007726492,0.000026923128],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000060520262,0.00008177365,0.00008411737,0.00014486213,0.000012744766,0.00001651787,0.000059237373,0.00006293932,0.00048367336],"category_scores_gemma":[0.0000089136265,0.000081989376,0.000030205932,0.0001378526,0.0000070171263,0.000091730646,0.0000033065694,0.00010010106,0.000080668164],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020278052,0.0002963937,0.0056815967,0.00028161678,0.000051804614,0.00008849574,0.0024224822,0.053673953,0.6392146,0.0017840442,0.066005394,0.23047939],"study_design_scores_gemma":[0.00036388446,0.00006244112,0.00021697099,0.00006705704,0.0000047938024,0.000007781855,0.00009872708,0.5799182,0.41360715,0.0003809385,0.0049820715,0.0002899474],"about_ca_topic_score_codex":0.000020258907,"about_ca_topic_score_gemma":0.00004638571,"teacher_disagreement_score":0.8583264,"about_ca_system_score_codex":0.000053333046,"about_ca_system_score_gemma":0.0000011696296,"threshold_uncertainty_score":0.5295884},"labels":[],"label_agreement":null},{"id":"W2112868953","doi":"10.1109/iscas.2008.4542032","title":"Binning algorithm for accurate computer aided device modeling","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Algorithm; Black box; Set (abstract data type); Context (archaeology); Artificial neural network; Generality; Artificial intelligence","score_opus":0.04933811692239483,"score_gpt":0.2505110461761093,"score_spread":0.2011729292537145,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2112868953","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008462552,0.00010151227,0.9881565,0.000012307463,0.000114308816,0.00017295445,0.0000032165178,0.0014222325,0.0015543912],"genre_scores_gemma":[0.26619062,0.000048728445,0.73335767,0.00012748096,0.00012424118,0.000035803947,0.0000072528296,0.000031819753,0.000076374905],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994558,0.0000044610806,0.00015970289,0.000116538205,0.00006145773,0.00020204349],"domain_scores_gemma":[0.999761,0.000031300853,0.000009539705,0.00011165449,0.00004348549,0.000043029042],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006672558,0.00011275979,0.00012727304,0.000062899584,0.000074262076,0.000018206127,0.00009583975,0.000062946114,0.000014273782],"category_scores_gemma":[0.000002475043,0.000105696025,0.000050392897,0.00008195728,0.0000073506326,0.00014969283,0.000015917345,0.00007204061,0.000016209364],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000058312703,0.00003792843,0.00005351943,0.00010787056,0.00012990773,0.000036336693,0.0007691666,0.44247967,0.010631868,0.00089844264,0.026307777,0.5185417],"study_design_scores_gemma":[0.00015370263,0.000021608419,0.000005080248,0.000013629019,0.0000043190726,0.000016473925,0.000008134357,0.9909369,0.0073901443,0.0002649511,0.0010287963,0.0001562794],"about_ca_topic_score_codex":0.000010473611,"about_ca_topic_score_gemma":7.641297e-7,"teacher_disagreement_score":0.5484572,"about_ca_system_score_codex":0.000021353464,"about_ca_system_score_gemma":0.0000070445203,"threshold_uncertainty_score":0.43101588},"labels":[],"label_agreement":null},{"id":"W2113267287","doi":"10.1109/date.2005.59","title":"An Improved Multi-Level Framework for Force-Directed Placement","year":2005,"lang":"en","type":"article","venue":"Design, Automation, and Test in Europe","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":22,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Cluster analysis; Computer science; Heuristic; Quality (philosophy); Unification; Mathematical optimization; Algorithm; Mathematics; Artificial intelligence","score_opus":0.031681822945312396,"score_gpt":0.2679957733737577,"score_spread":0.23631395042844527,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2113267287","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01170152,0.00019992985,0.9851505,0.000031414467,0.000070186376,0.0007511345,0.000026623753,0.0019365345,0.00013216265],"genre_scores_gemma":[0.49719256,0.0001019287,0.50221,0.0000746704,0.0000846875,0.0001382244,0.000027633396,0.000051438557,0.000118809774],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991235,0.00004441293,0.00030107304,0.00020904228,0.000075842945,0.00024609326],"domain_scores_gemma":[0.9992402,0.00033903442,0.000043128442,0.0002014766,0.00010112746,0.00007499339],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002974616,0.00018442556,0.00016694488,0.00013860757,0.00007750874,0.000072775954,0.00012441381,0.0001100943,0.000017471948],"category_scores_gemma":[0.00029420707,0.00018438845,0.000019828232,0.0002560304,0.00002046931,0.00026216594,0.000009270335,0.000109976296,0.000008253769],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001313385,0.0015909536,0.0072868345,0.0007939192,0.0001602394,0.000018013072,0.008713171,0.049688194,0.38559312,0.007845471,0.010810526,0.5273682],"study_design_scores_gemma":[0.00060741254,0.00019352075,0.012140878,0.0000572164,0.000011656408,0.000004371085,0.000017509707,0.96173495,0.022793002,0.0005212371,0.0016373987,0.00028083994],"about_ca_topic_score_codex":0.0000043123823,"about_ca_topic_score_gemma":0.00001337753,"teacher_disagreement_score":0.9120468,"about_ca_system_score_codex":0.000044858552,"about_ca_system_score_gemma":0.00001976955,"threshold_uncertainty_score":0.75191426},"labels":[],"label_agreement":null},{"id":"W2113502461","doi":"10.1109/edac.1993.386479","title":"ML-Germinal: A new heuristic standard cell placement algorithm","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Heuristic; Convergence (economics); Algorithm; Computer science; Point (geometry); Mathematical optimization; Mathematics; Artificial intelligence","score_opus":0.011626576245762403,"score_gpt":0.19515569763697455,"score_spread":0.18352912139121214,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2113502461","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0004012776,0.0008886005,0.87521434,0.000058269612,0.0001400695,0.0001825526,0.0000125661345,0.0016011113,0.1215012],"genre_scores_gemma":[0.6049311,0.0013093029,0.3213305,0.0003385692,0.00051641115,0.000063836786,0.000014391096,0.00017651761,0.07131935],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99931586,0.0000074303457,0.00015842743,0.00012682284,0.00015668155,0.00023479541],"domain_scores_gemma":[0.9996476,0.000020376816,0.000011678238,0.0001869218,0.0000145571785,0.00011885392],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000054752458,0.00014029152,0.00013791144,0.00006319912,0.000027012475,0.000034403736,0.000104523606,0.000059425576,0.0028592665],"category_scores_gemma":[0.0000035729101,0.0001311018,0.000042868873,0.0000975696,0.000009741527,0.00006200348,0.000016794917,0.00010488555,0.00030040744],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000024541785,0.000028768387,0.0000128617385,0.00004752926,0.00001569315,0.00004466845,0.00021901041,0.0002705772,0.0019176971,0.00011668559,0.79634005,0.20098402],"study_design_scores_gemma":[0.000993997,0.00042773312,0.00002679893,0.00004787948,0.00004669244,0.000032117467,0.00009029505,0.25458482,0.14063041,0.00095857715,0.601387,0.00077365915],"about_ca_topic_score_codex":0.000014035681,"about_ca_topic_score_gemma":0.0000018970512,"teacher_disagreement_score":0.60452986,"about_ca_system_score_codex":0.000066235996,"about_ca_system_score_gemma":0.000005851496,"threshold_uncertainty_score":0.99805224},"labels":[],"label_agreement":null},{"id":"W2113645429","doi":"10.1109/tvlsi.2004.824300","title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":416,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Lookup table; Field-programmable gate array; Computer science; Parallel computing; Benchmark (surveying); Cluster (spacecraft); Cluster analysis; Context (archaeology); Logic block; Logic synthesis; Logic gate; Algorithm; Computer hardware; Artificial intelligence","score_opus":0.00342918692884033,"score_gpt":0.18936024284456082,"score_spread":0.18593105591572048,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2113645429","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.616466,0.00017806696,0.38194332,0.000025490954,0.00048238246,0.0004678368,0.00001791062,0.00017377717,0.0002452389],"genre_scores_gemma":[0.9991997,0.000339894,0.00011724561,0.000019930332,0.000041748262,0.00010412101,0.0000021144851,0.000029354582,0.00014590418],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99897355,0.00010123926,0.00032092934,0.00019975484,0.0001880616,0.00021644714],"domain_scores_gemma":[0.99930835,0.0002723569,0.00005392138,0.00025192735,0.00004940851,0.00006403861],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004436456,0.00022837796,0.00026653687,0.00009492645,0.0002649678,0.000079272875,0.00008768544,0.00016533001,0.0000036925976],"category_scores_gemma":[0.000008536133,0.00016027565,0.00007365141,0.00013108687,0.000071009774,0.0002062305,0.0000012689158,0.0003049282,0.000010710941],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.002809599,0.00068520283,0.0026990047,0.004624898,0.00097596715,0.00002393651,0.009603751,0.2574735,0.40402797,0.00064781617,0.0023807588,0.3140476],"study_design_scores_gemma":[0.0014688773,0.0010978203,0.0012360855,0.00062314695,0.00008238578,0.00007234038,0.0002705002,0.07715348,0.91720116,0.000028668543,0.0004184428,0.00034708675],"about_ca_topic_score_codex":0.000041849165,"about_ca_topic_score_gemma":0.00020109597,"teacher_disagreement_score":0.51317316,"about_ca_system_score_codex":0.000116960255,"about_ca_system_score_gemma":0.000009163139,"threshold_uncertainty_score":0.65358514},"labels":[],"label_agreement":null},{"id":"W2113702211","doi":"10.1109/icvd.2003.1183116","title":"An efficient practical heuristic for good ratio-cut partitioning","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Ministry of Economy, Trade and Industry","keywords":"Submodular set function; Heuristics; Algorithm; Mathematics; Heuristic; Computer science; Benchmark (surveying); Simulated annealing; Mathematical optimization","score_opus":0.01947762997045741,"score_gpt":0.28296894747007856,"score_spread":0.2634913174996211,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2113702211","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008804522,0.000022685474,0.9718453,0.00002924436,0.0000932888,0.00021427112,0.000002738909,0.0007033396,0.018284569],"genre_scores_gemma":[0.9371971,0.0000035435214,0.06250668,0.00004320416,0.000036632315,0.0000845387,0.0000069051007,0.000019150251,0.00010225764],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995398,0.000019590925,0.000120697565,0.00010080239,0.000053936616,0.00016518195],"domain_scores_gemma":[0.99969524,0.00007741904,0.000009792081,0.0001280036,0.000027724263,0.000061847146],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016248792,0.00007559565,0.00007655653,0.000029244635,0.00006031789,0.00004554448,0.000032411455,0.00004759522,0.00012155464],"category_scores_gemma":[0.00008347312,0.000071170245,0.00002727616,0.000055023425,0.000010578611,0.000076023745,0.0000019472702,0.00006010171,0.000023509549],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010316262,0.00025330464,0.00019438518,0.0001024132,0.000040898874,0.000011796305,0.00030817234,0.05088813,0.026326625,0.9030502,0.016842293,0.0019714667],"study_design_scores_gemma":[0.0003449681,0.00023933194,0.00007755733,0.000015970427,0.00003235185,0.000031693507,0.00013131711,0.70448506,0.2724387,0.005231921,0.016632993,0.00033815237],"about_ca_topic_score_codex":0.0000012222013,"about_ca_topic_score_gemma":0.0000030906708,"teacher_disagreement_score":0.9283926,"about_ca_system_score_codex":0.00002487926,"about_ca_system_score_gemma":0.000012594162,"threshold_uncertainty_score":0.29022384},"labels":[],"label_agreement":null},{"id":"W2114452736","doi":"10.1109/fpl.2008.4629975","title":"The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Computer science; Field-programmable gate array; Routing (electronic design automation); Block (permutation group theory); Exploit; Flexibility (engineering); Computer hardware; Logic block; Parallel computing; Embedded system","score_opus":0.017970199267990306,"score_gpt":0.21835694936224073,"score_spread":0.20038675009425042,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2114452736","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.97629255,0.00009989004,0.019702848,0.000039161216,0.00003697857,0.00034618666,0.0000013386741,0.00015138047,0.0033296468],"genre_scores_gemma":[0.99955016,0.000080683625,0.0002103584,0.000014217128,0.000012490862,0.00003606336,4.7531162e-7,0.000015531426,0.00008004019],"study_design_codex":"observational","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99916774,0.00006520696,0.00027011544,0.00011098244,0.00014869952,0.00023727451],"domain_scores_gemma":[0.99890435,0.0006975459,0.00005164757,0.00030974267,0.000015976477,0.000020751619],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005306544,0.00013129273,0.00019096099,0.00005253751,0.00007792942,0.000011849222,0.00025875005,0.00006436122,0.000018674158],"category_scores_gemma":[0.0001012177,0.00006754571,0.00007423445,0.00017535378,0.00003953921,0.000027798424,0.00002887332,0.0001891141,0.0000034414086],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00032887916,0.00044064238,0.65123296,0.00080027746,0.00024983566,0.00010346319,0.015447611,0.072176486,0.12960915,0.00112675,0.0021584346,0.12632552],"study_design_scores_gemma":[0.0003825068,0.00050922215,0.0048723295,0.00019055403,0.000009008432,0.000004922723,0.00022912766,0.10772708,0.88573307,0.000028491513,0.00016094549,0.00015276847],"about_ca_topic_score_codex":0.00029245843,"about_ca_topic_score_gemma":0.00008750174,"teacher_disagreement_score":0.7561239,"about_ca_system_score_codex":0.00001466639,"about_ca_system_score_gemma":0.0000035939324,"threshold_uncertainty_score":0.2754434},"labels":[],"label_agreement":null},{"id":"W2114971758","doi":"10.1109/iscas.2011.5938203","title":"Machine-learning framework for automatic netlist creation","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université du Québec à Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; Mitacs; CMC Microsystems","keywords":"Netlist; Computer science; Set (abstract data type); Electronic circuit; Design flow; Computer architecture; Electronic design automation; Computer engineering; Embedded system; Programming language; Engineering; Electrical engineering","score_opus":0.022093692119366688,"score_gpt":0.23854532081088975,"score_spread":0.21645162869152307,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2114971758","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0017323978,0.00008826726,0.92881876,0.0000064795054,0.00006725464,0.00016230786,0.0000013709239,0.0022551215,0.06686803],"genre_scores_gemma":[0.6953287,0.000019194222,0.30417106,0.00002641683,0.000034765624,0.000055921824,0.0000066709244,0.000024879346,0.00033237625],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996604,0.0000072361677,0.000105853724,0.000066540175,0.000040482446,0.00011950149],"domain_scores_gemma":[0.99979955,0.000050892802,0.000013142748,0.00009308298,0.00001374645,0.000029605259],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007530272,0.00007605762,0.00008084147,0.000043529493,0.00003872569,0.000016966445,0.00006546503,0.00007659564,0.00043710484],"category_scores_gemma":[0.000040197512,0.00006890685,0.000035238936,0.00005706115,0.0000077739605,0.000070567236,0.000006103897,0.000092728165,0.000030785042],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001764907,0.000089012654,0.007402519,0.00060134946,0.00015051493,0.0000059883782,0.0039735218,0.0009525404,0.0045169336,0.5482186,0.00927028,0.42480108],"study_design_scores_gemma":[0.00013637652,0.0001228709,0.001806286,0.000060695278,0.000025650417,0.0000038909707,0.000058147827,0.88856775,0.026584161,0.074628286,0.0077195973,0.00028632325],"about_ca_topic_score_codex":0.000022216684,"about_ca_topic_score_gemma":0.0000025333973,"teacher_disagreement_score":0.8876152,"about_ca_system_score_codex":0.000015736681,"about_ca_system_score_gemma":0.0000023008513,"threshold_uncertainty_score":0.47859913},"labels":[],"label_agreement":null},{"id":"W2115546910","doi":"10.1109/92.920838","title":"Structural analysis and generation of synthetic digital circuits with memory","year":2001,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto; University of British Columbia","funders":"","keywords":"Computer science; Electronic circuit; Digital electronics; Combinational logic; Benchmark (surveying); Electronic engineering; Sequential logic; Generator (circuit theory); Logic gate; Computer architecture; Computer engineering; Engineering; Algorithm; Electrical engineering; Power (physics)","score_opus":0.01293733158551884,"score_gpt":0.2052804723198291,"score_spread":0.19234314073431025,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2115546910","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.39371774,0.00007481692,0.60508406,0.0000056790323,0.00020434389,0.00020445445,0.000089255096,0.00019700975,0.00042261515],"genre_scores_gemma":[0.999323,0.00005891173,0.00014969548,0.000005966013,0.00005619817,0.00006737498,0.000035758996,0.000030159388,0.0002729411],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988825,0.000047097754,0.0003840935,0.00023977393,0.0002571162,0.00018947147],"domain_scores_gemma":[0.99943477,0.00004093064,0.00006883555,0.00026480167,0.00011517825,0.000075509466],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012117645,0.00021808494,0.0003326496,0.00044495123,0.00011234708,0.0001275597,0.00008153054,0.00013362453,0.000041254003],"category_scores_gemma":[0.0000024281885,0.0001814288,0.00011503073,0.00059577724,0.000046362347,0.00048596767,5.219866e-7,0.00017091236,0.000005943053],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00013254605,0.00035218772,0.0030550451,0.0004284438,0.0025528788,0.000035509514,0.004286522,0.6939418,0.16845626,0.0002487892,0.00035559465,0.12615448],"study_design_scores_gemma":[0.00048403628,0.00022976664,0.0005875283,0.0001517917,0.00045291695,0.00010941417,0.000902733,0.82869995,0.16784766,0.000016589933,0.00008594789,0.00043166798],"about_ca_topic_score_codex":0.000044513406,"about_ca_topic_score_gemma":0.00031029808,"teacher_disagreement_score":0.60560524,"about_ca_system_score_codex":0.00008205809,"about_ca_system_score_gemma":0.000013988775,"threshold_uncertainty_score":0.7398452},"labels":[],"label_agreement":null},{"id":"W2115579119","doi":"10.1109/socdc.2009.5423783","title":"Chip package-system co-design","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Apache (Canada)","funders":"","keywords":"Chip; System on a chip; Computer science; Integrated circuit design; Embedded system; Dissipation; Power (physics); System in package; Chip-scale package; Telecommunications","score_opus":0.01631723666921509,"score_gpt":0.22064886285696708,"score_spread":0.204331626187752,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2115579119","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0008740003,0.00009524716,0.727489,0.000023649965,0.000048340433,0.00014088144,0.0000012336624,0.0036682934,0.26765937],"genre_scores_gemma":[0.98614365,0.000015616642,0.013159683,0.00008593226,0.00007254312,0.000008101143,0.0000021746575,0.000016229162,0.0004960472],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995288,0.0000150171845,0.00011769866,0.000085712345,0.00008040769,0.00017235974],"domain_scores_gemma":[0.999731,0.000017039876,0.0000076703955,0.00018185927,0.000009351232,0.000053071995],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011350496,0.00010284242,0.00011091347,0.000053148084,0.000025632185,0.000026997315,0.00010180871,0.000067821355,0.00007611987],"category_scores_gemma":[0.0000029767732,0.00008895338,0.00003467124,0.000078526515,0.000005802172,0.00007029384,0.0000023331286,0.000074930904,0.0002392919],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012587746,0.000052481504,0.00009468235,0.000116366544,0.00005140415,0.00008985277,0.0003463989,0.0014076057,0.3145701,0.040125642,0.50928444,0.13384843],"study_design_scores_gemma":[0.0002659145,0.0002064246,0.0011135216,0.000052410407,0.000012571914,0.000041180065,0.000069115216,0.029723259,0.9534458,0.001707351,0.012878884,0.00048354996],"about_ca_topic_score_codex":0.0000015618215,"about_ca_topic_score_gemma":1.5775053e-7,"teacher_disagreement_score":0.98526967,"about_ca_system_score_codex":0.000036907957,"about_ca_system_score_gemma":0.0000037676637,"threshold_uncertainty_score":0.36274132},"labels":[],"label_agreement":null},{"id":"W2115663817","doi":"10.1109/iccd.1992.276198","title":"Improving FPGA routing architectures using architecture and CAD interactions","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Router; Flexibility (engineering); Computer science; Block (permutation group theory); Logic block; Architecture; Computer architecture; Embedded system; Programmable Array Logic; Gate array; Logic synthesis; Logic gate; Computer network; Logic family; Algorithm; Mathematics","score_opus":0.011274832272166803,"score_gpt":0.23054443388401005,"score_spread":0.21926960161184325,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2115663817","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.30039752,0.00022274085,0.68387574,0.000012066032,0.00012360341,0.00012294587,0.0000023469124,0.00076655357,0.014476523],"genre_scores_gemma":[0.9453335,0.00000532084,0.054439753,0.000044398832,0.000049453298,0.000006133981,7.0502324e-7,0.000030842777,0.00008992842],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994029,0.000024923185,0.00014196459,0.00014290205,0.000062066116,0.00022527139],"domain_scores_gemma":[0.99972093,0.000053831285,0.000019226369,0.00013110419,0.000012207121,0.0000627207],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000091061265,0.00014497808,0.000117994816,0.00012305033,0.000096687225,0.000057265563,0.000052864245,0.000052910877,0.000046672412],"category_scores_gemma":[0.000048081085,0.00012852691,0.000036156296,0.000102025406,0.000023381908,0.00005322249,0.000017633625,0.00026724173,0.00000177125],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004969508,0.000020989499,0.0014561438,0.00015028643,0.000076017386,0.000018020113,0.0015389516,0.031597633,0.7086757,0.0029926815,0.0002534681,0.25321513],"study_design_scores_gemma":[0.0004490913,0.00007098982,0.0007942588,0.00014754261,0.000072998046,0.00090260647,0.0005270564,0.24180934,0.7404604,0.0066820597,0.0069805,0.0011031434],"about_ca_topic_score_codex":0.0000775989,"about_ca_topic_score_gemma":0.00004583576,"teacher_disagreement_score":0.64493597,"about_ca_system_score_codex":0.00003305802,"about_ca_system_score_gemma":0.000008927981,"threshold_uncertainty_score":0.5241175},"labels":[],"label_agreement":null},{"id":"W2116417357","doi":"10.1109/fpt.2004.1393307","title":"Retiming aware clustering for sequential circuits","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Retiming; Benchmark (surveying); Computer science; Cluster analysis; Parallel computing; Field-programmable gate array; Sequential logic; Minification; Node (physics); Electronic circuit; Algorithm; Logic synthesis; Logic gate; Computer hardware; Artificial intelligence; Engineering","score_opus":0.027402562084977388,"score_gpt":0.2507252586549246,"score_spread":0.22332269656994724,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2116417357","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0032539093,0.000067859844,0.9769389,0.000053177024,0.00012159008,0.00018531397,0.0000045987226,0.001420762,0.017953858],"genre_scores_gemma":[0.9767506,0.000015191607,0.02219277,0.00008028396,0.00030750575,0.00004653869,0.0000060276047,0.000033751883,0.00056732254],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995404,0.0000031130048,0.000122192,0.000093728915,0.000052682135,0.0001879113],"domain_scores_gemma":[0.999812,0.000016733433,0.000007887357,0.00010863886,0.000017011764,0.00003774559],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000070761,0.00008655356,0.00008553756,0.00004724323,0.000038395072,0.000027648108,0.00008190534,0.00006371811,0.000119149256],"category_scores_gemma":[0.0000048856973,0.00008872705,0.000047258138,0.000041030886,0.000006336553,0.00012372505,0.0000136029,0.000054789838,0.000020254782],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000053144445,0.00002097236,0.00006992821,0.00031069477,0.00006598116,0.0000055829096,0.00054457935,0.029767673,0.19302154,0.0013993692,0.045769542,0.7290188],"study_design_scores_gemma":[0.0002651278,0.000033703123,0.00002720474,0.00003915296,0.000013624837,0.000015217182,0.0000342324,0.6719804,0.27356192,0.00022414216,0.05349434,0.0003109592],"about_ca_topic_score_codex":0.0000027629355,"about_ca_topic_score_gemma":0.0000148770805,"teacher_disagreement_score":0.9734967,"about_ca_system_score_codex":0.000049240854,"about_ca_system_score_gemma":0.0000043325203,"threshold_uncertainty_score":0.3618184},"labels":[],"label_agreement":null},{"id":"W2116518941","doi":"10.1109/tcad.2005.862748","title":"Force-Directed Methods for Generic Placement","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Computation; Computer science; Placement; Cluster analysis; Minification; Mathematical optimization; Algorithm; Mathematics; Physical design; Artificial intelligence; Embedded system","score_opus":0.03467480259999626,"score_gpt":0.2627210986315455,"score_spread":0.22804629603154927,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2116518941","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0012072691,0.00072849594,0.994521,0.000003893153,0.0010374236,0.001196129,0.000082734725,0.0010287632,0.0001942784],"genre_scores_gemma":[0.8735674,0.00012415393,0.12530012,0.000017151002,0.000113368056,0.00047085586,0.000021188513,0.00008320248,0.0003025436],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983943,0.00019940488,0.000651371,0.00030493992,0.00014032482,0.00030964674],"domain_scores_gemma":[0.99899393,0.00037817852,0.00009680395,0.00025429123,0.00019634215,0.00008042557],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004895951,0.00032750002,0.00052639376,0.00034759555,0.000114155366,0.000081939266,0.00015623945,0.00020394911,0.000009216138],"category_scores_gemma":[0.0000024954772,0.00029129087,0.00012830725,0.00028849748,0.000041149106,0.00010032817,6.542418e-7,0.00017769822,0.0000023966245],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003027113,0.00011172138,0.0000013695296,0.00026179512,0.0002046773,0.0000025363715,0.00010419532,0.61574584,0.22809854,0.000195895,0.0028327669,0.1524104],"study_design_scores_gemma":[0.0005231153,0.00046680772,0.0000045909637,0.00017365643,0.000059508435,0.000029054927,0.00003501829,0.8203485,0.17719254,0.0001328068,0.00075511244,0.00027926167],"about_ca_topic_score_codex":0.00013309423,"about_ca_topic_score_gemma":0.0000040700006,"teacher_disagreement_score":0.87236017,"about_ca_system_score_codex":0.0001165468,"about_ca_system_score_gemma":0.00003690923,"threshold_uncertainty_score":0.9999539},"labels":[],"label_agreement":null},{"id":"W2118653269","doi":"10.1145/1065579.1065694","title":"Incremental retiming for FPGA physical synthesis","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":21,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Alterra Power (Canada)","funders":"","keywords":"Retiming; Field-programmable gate array; Computer science; Parallel computing; Computer architecture; Embedded system","score_opus":0.013365233755510304,"score_gpt":0.23179216931382068,"score_spread":0.2184269355583104,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2118653269","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.26942384,0.000116447634,0.6072934,0.00033285737,0.0001096421,0.00061253645,0.000021451062,0.003969523,0.118120246],"genre_scores_gemma":[0.9642301,0.000006898475,0.035236612,0.00004858656,0.00023690781,0.00008945076,0.0000012688982,0.000021370846,0.00012879139],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996618,0.0000032619391,0.00007306919,0.00007328788,0.000052948013,0.00013560323],"domain_scores_gemma":[0.99981123,0.00006168627,0.0000052339506,0.00008530609,0.00000762069,0.00002889761],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000052274572,0.00007294348,0.000085692525,0.000029000306,0.000026241672,0.000013679199,0.00006605041,0.000030947074,0.000084986845],"category_scores_gemma":[0.000011700172,0.00006691808,0.000050739545,0.000031990166,0.00000834194,0.00008659016,0.0000091359925,0.00003755327,0.000033007662],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008490824,0.0000639501,0.000039324954,0.00006793552,0.000050723644,0.0000010316664,0.00028562133,0.00063710014,0.2952008,0.003080721,0.053683966,0.6468803],"study_design_scores_gemma":[0.00005710842,0.000017108772,0.000024399485,0.000009904726,0.000010628362,0.0000013543078,0.00002356553,0.078375965,0.90811956,0.00022909965,0.013015269,0.000116055475],"about_ca_topic_score_codex":0.0000022671397,"about_ca_topic_score_gemma":0.0000019842744,"teacher_disagreement_score":0.6948063,"about_ca_system_score_codex":0.000038891718,"about_ca_system_score_gemma":0.0000019614804,"threshold_uncertainty_score":0.272884},"labels":[],"label_agreement":null},{"id":"W2118867008","doi":"10.1109/iwsoc.2005.69","title":"Global lower bounds for the VLSI macrocell floorplanning problem using semidefinite optimization","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Macrocell; Floorplan; Semidefinite programming; Benchmark (surveying); Very-large-scale integration; Computer science; Integer programming; Mathematical optimization; Upper and lower bounds; Integer (computer science); Parallel computing; Algorithm; Mathematics; Telecommunications; Embedded system","score_opus":0.015310811595894465,"score_gpt":0.24136071035656403,"score_spread":0.22604989876066958,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2118867008","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019195058,0.00046957014,0.98040605,0.000072817085,0.00010628886,0.0003161128,0.000012449876,0.0007747236,0.015922483],"genre_scores_gemma":[0.47819182,0.00007014896,0.5207929,0.00023029615,0.00024233123,0.000046987232,0.000013788298,0.000040699648,0.0003710028],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993653,0.0000058343,0.00017902443,0.00012006625,0.000087909415,0.0002418533],"domain_scores_gemma":[0.9997194,0.00003909821,0.000022141478,0.00014264045,0.00004215171,0.000034580673],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014014452,0.00013347743,0.00009885625,0.000029718809,0.00012200114,0.00010027763,0.00012664778,0.00008412094,0.00007858142],"category_scores_gemma":[0.0000067252,0.0001016507,0.00005637364,0.00015865208,0.000016894823,0.00017420443,0.000018716768,0.000059811515,0.000007733003],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005043103,0.000008118112,0.00009954534,0.000023461018,0.000020227892,5.65601e-7,0.000045950826,0.9859316,0.0008226931,0.0004784781,0.0064908867,0.0060734623],"study_design_scores_gemma":[0.00014846968,0.000019171204,0.000010465855,0.000022152559,0.000024769048,0.000012368577,0.000020130088,0.978033,0.0026565013,0.00024334781,0.01865496,0.00015467417],"about_ca_topic_score_codex":0.000013229537,"about_ca_topic_score_gemma":0.000010116207,"teacher_disagreement_score":0.47627234,"about_ca_system_score_codex":0.000105358566,"about_ca_system_score_gemma":0.000012866789,"threshold_uncertainty_score":0.41451952},"labels":[],"label_agreement":null},{"id":"W2118882683","doi":"10.1109/ccece.1998.682778","title":"On the FPGA board level routing problem","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University; Université de Montréal","funders":"","keywords":"Emulation; Routing (electronic design automation); Field-programmable gate array; Simple (philosophy); Computer science; Constraint (computer-aided design); Logic synthesis; Logic gate; Parallel computing; Embedded system; Algorithm; Mathematics","score_opus":0.046674579398864324,"score_gpt":0.20446758714914792,"score_spread":0.1577930077502836,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2118882683","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010037588,0.00008742575,0.117203906,0.00066107855,0.0000759942,0.0002627507,0.000002494443,0.0021074577,0.8695613],"genre_scores_gemma":[0.992635,0.000019524785,0.0033934172,0.0002647803,0.000039089864,0.000022721439,3.0068946e-7,0.000019628143,0.0036055339],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959683,0.000008926504,0.00009058782,0.00007100774,0.0000798868,0.00015276067],"domain_scores_gemma":[0.9997508,0.000056093686,0.0000073268698,0.00015599973,0.0000080861655,0.000021702634],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000086196465,0.00008105714,0.00006028709,0.000023512383,0.00004720091,0.00002925432,0.00011134895,0.000040622417,0.00078797824],"category_scores_gemma":[0.000010586197,0.00005058307,0.000030784464,0.00007221387,0.000009389841,0.000040556766,0.000011328603,0.000118228025,0.00030034475],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000015476584,0.00004651526,0.00012676342,0.00003596207,0.00004989808,0.000009358092,0.0008775368,0.0015588506,0.011651965,0.13557884,0.71341014,0.13665259],"study_design_scores_gemma":[0.0005551518,0.0002870073,0.0009673457,0.00022588877,0.000031866177,0.000023997643,0.00028351235,0.4773776,0.41079107,0.03351034,0.07461639,0.0013298495],"about_ca_topic_score_codex":0.000009318894,"about_ca_topic_score_gemma":0.000003174335,"teacher_disagreement_score":0.9825974,"about_ca_system_score_codex":0.000020178348,"about_ca_system_score_gemma":7.7998294e-7,"threshold_uncertainty_score":0.8627809},"labels":[],"label_agreement":null},{"id":"W2118988958","doi":"10.1145/1344671.1344680","title":"WireMap","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":30,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Xilinx (Canada)","funders":"","keywords":"Lookup table; Reduction (mathematics); Computer science; Heuristic; Enhanced Data Rates for GSM Evolution; Routing (electronic design automation); Path (computing); Algorithm; Mathematics; Embedded system; Telecommunications; Computer network; Artificial intelligence","score_opus":0.013113374030621133,"score_gpt":0.16532515317880578,"score_spread":0.15221177914818465,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2118988958","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.083801955,0.00017831996,0.19684412,0.00002240339,0.00008748397,0.000055240336,4.3874272e-7,0.00358769,0.71542233],"genre_scores_gemma":[0.99342686,0.00006618087,0.004972205,0.00003777051,0.000024869123,0.0000032492283,3.81436e-7,0.0000072003704,0.0014613051],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9998554,0.00000107798,0.000033601635,0.000025784762,0.00002758178,0.000056529654],"domain_scores_gemma":[0.99991596,0.0000033237804,0.0000011308313,0.000059374073,0.0000036734525,0.00001656126],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000010528453,0.000029134715,0.000030877603,0.000016129312,0.000013186348,0.0000016802861,0.000030538202,0.000018632005,0.00016632814],"category_scores_gemma":[9.787445e-7,0.000025358035,0.000011936449,0.000031950338,0.000007074614,0.000030764648,0.0000027663543,0.000024629835,0.00013550057],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000014011339,0.00002349143,0.0031728174,0.00003292015,0.000027386099,0.00009281651,0.00040117855,0.00034426656,0.097543396,0.00906962,0.85161966,0.037671022],"study_design_scores_gemma":[0.00020706812,0.000050221544,0.00635734,0.000010737037,0.000004308593,0.00018603161,0.000018997966,0.020290148,0.7597368,0.0022491687,0.21043219,0.00045703433],"about_ca_topic_score_codex":0.0000021594806,"about_ca_topic_score_gemma":4.5316597e-7,"teacher_disagreement_score":0.9096249,"about_ca_system_score_codex":0.0000052721502,"about_ca_system_score_gemma":0.0000012959451,"threshold_uncertainty_score":0.18211766},"labels":[],"label_agreement":null},{"id":"W2120569261","doi":"10.5555/1950815.1950894","title":"Area-efficient FPGA logic elements: architecture and synthesis","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Logic optimization; Computer science; Logic synthesis; Programmable logic array; Functional decomposition; Lookup table; Logic family; Logic block; Logic gate; Field-programmable gate array; Sequential logic; Trimming; Programmable logic device; Parallel computing; Combinational logic; Algorithm; Computer hardware","score_opus":0.02449781595460505,"score_gpt":0.1957363852504816,"score_spread":0.17123856929587655,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2120569261","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1258838,0.00053937826,0.643262,0.00003921462,0.00010661804,0.0003600772,0.000010905247,0.002364976,0.22743303],"genre_scores_gemma":[0.97866493,0.00004960404,0.021062704,0.00006301644,0.000013732907,0.000035115987,6.566851e-7,0.000016002205,0.000094212715],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99954957,0.000008591144,0.00011014051,0.000108901375,0.00006137122,0.00016142236],"domain_scores_gemma":[0.9997709,0.000023442457,0.000009347749,0.00013661988,0.000009090033,0.00005060506],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000074489035,0.0001064714,0.000097421915,0.00006700041,0.000024399345,0.000011451481,0.000078142264,0.000050762013,0.0005238339],"category_scores_gemma":[0.00001276763,0.00008145691,0.000024064328,0.00005769482,0.00002150859,0.000019537025,0.00002174032,0.00007038337,0.000018420991],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003601718,0.0004488225,0.0026810113,0.00036502432,0.00030664992,0.000094699746,0.0036067246,0.0014768034,0.06153867,0.012676348,0.017830739,0.8989385],"study_design_scores_gemma":[0.00039431345,0.0002194312,0.005741203,0.0001178292,0.00008703089,0.00006837959,0.00033139612,0.019729743,0.9506862,0.0121609,0.009398729,0.0010648217],"about_ca_topic_score_codex":0.000010249819,"about_ca_topic_score_gemma":0.000004287621,"teacher_disagreement_score":0.89787364,"about_ca_system_score_codex":0.000012726853,"about_ca_system_score_gemma":0.0000019562535,"threshold_uncertainty_score":0.5735614},"labels":[],"label_agreement":null},{"id":"W2121764243","doi":"10.1109/iwsoc.2005.15","title":"A low-power partitioning methodology by maximizing sleep time and minimizing cut nets","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Mathematical optimization; Computer science; Maximization; Minification; Very-large-scale integration; Heuristic; Power (physics); Dual (grammatical number); Genetic algorithm; Idle; Algorithm; Mathematics; Embedded system","score_opus":0.017046975054928432,"score_gpt":0.2349584021968112,"score_spread":0.21791142714188275,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2121764243","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14434068,0.0022397593,0.7940437,0.000569071,0.00014842524,0.00029610647,0.000010245141,0.0029551785,0.05539681],"genre_scores_gemma":[0.7492005,0.0001248315,0.24924862,0.00053444045,0.0000755554,0.000029933242,0.000011077252,0.000054682987,0.0007203123],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99919415,0.000049790746,0.00020842365,0.00017991544,0.0000713885,0.00029634856],"domain_scores_gemma":[0.99961066,0.00013259752,0.00002094885,0.00013759942,0.000016228729,0.00008198693],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000268981,0.00015369564,0.00020296103,0.000077638586,0.00006178853,0.000045620487,0.00007850447,0.00012139396,0.00052389107],"category_scores_gemma":[0.000026373878,0.00015411129,0.00003635291,0.000080417885,0.000031280335,0.00020696329,0.000031960688,0.00013892593,0.000092272996],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001138449,0.000044511602,0.00016635738,0.00004713548,0.00011216531,0.000014721415,0.0010691262,0.0028285717,0.7802986,0.0008920874,0.085064635,0.12945068],"study_design_scores_gemma":[0.00045660892,0.00008836005,0.000114949304,0.000063448475,0.000034048713,0.00007492234,0.00008905394,0.16524014,0.77602637,0.0006907607,0.056483246,0.0006380721],"about_ca_topic_score_codex":0.0000076037813,"about_ca_topic_score_gemma":0.0000055935275,"teacher_disagreement_score":0.6048599,"about_ca_system_score_codex":0.000031027565,"about_ca_system_score_gemma":0.0000031704728,"threshold_uncertainty_score":0.6284476},"labels":[],"label_agreement":null},{"id":"W2121969545","doi":"","title":"Via-programmable logic array VPEX2 with configurable DFF using 2 logic elements","year":2009,"lang":"en","type":"article","venue":"Proceedings of the 2009 12th International Symposium on Integrated Circuits","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Programmable logic array; Programmable logic device; Programmable Array Logic; Logic gate; Logic family; Pass transistor logic; Simple programmable logic device; AND-OR-Invert; Computer science; Logic synthesis; Macrocell array; Logic optimization; Sequential logic; Electronic circuit; Computer hardware; Electronic engineering; Arithmetic; Digital electronics; Algorithm; Engineering; Mathematics; Electrical engineering","score_opus":0.015432732048414001,"score_gpt":0.2319377623383298,"score_spread":0.2165050302899158,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2121969545","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.44065598,0.00039364083,0.0374426,0.0023323724,0.0018044141,0.0027848664,0.00016589292,0.0025874951,0.5118327],"genre_scores_gemma":[0.99708736,0.00005055524,0.0017015417,0.00044221044,0.00011030753,0.00003795755,0.00001527008,0.000044852215,0.00050995813],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99808544,0.000007983506,0.0005208818,0.00034799488,0.00059304625,0.00044465208],"domain_scores_gemma":[0.99884546,0.00001930527,0.00026374002,0.0001601592,0.000618167,0.00009316193],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002560865,0.00037701763,0.00032087354,0.00018865647,0.00011511417,0.000148684,0.00086613983,0.0001695522,0.0001441938],"category_scores_gemma":[0.00003621385,0.00025943416,0.00012320669,0.00051388657,0.000077602,0.00034763932,0.000018310371,0.0004284754,0.000017961442],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000050713406,0.00018109984,0.00081927044,0.000041683565,0.00016948931,0.0000027578972,0.00010539046,0.0022199028,0.9821371,0.00815427,0.0017287547,0.004389568],"study_design_scores_gemma":[0.00064919505,0.000593807,0.00035058515,0.0005761151,0.000069296446,0.00008585189,0.00009502419,0.010600943,0.97429913,0.008743316,0.0034526312,0.00048407365],"about_ca_topic_score_codex":0.000037744197,"about_ca_topic_score_gemma":0.0000016170967,"teacher_disagreement_score":0.55643135,"about_ca_system_score_codex":0.00030889243,"about_ca_system_score_gemma":0.000028058259,"threshold_uncertainty_score":0.9999858},"labels":[],"label_agreement":null},{"id":"W2122110986","doi":"10.1177/0037549709102760","title":"A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation","year":2009,"lang":"en","type":"article","venue":"SIMULATION","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Netlist; Computer science; Verilog; Algorithm; Very-large-scale integration; Hypergraph; Parallel computing; Speedup; Theoretical computer science; Mathematics; Field-programmable gate array; Computer hardware; Embedded system","score_opus":0.02922559888970879,"score_gpt":0.2835362861571888,"score_spread":0.25431068726748,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2122110986","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0027603942,0.000039598166,0.99539685,0.000015480222,0.00009158088,0.00058486493,0.000041325526,0.0009867802,0.000083145984],"genre_scores_gemma":[0.908032,0.0000037654022,0.09146828,0.000027070268,0.00013218481,0.000036070356,0.00026996929,0.000020341091,0.000010303971],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993158,0.000022947292,0.00021653113,0.00014454436,0.00010263044,0.00019752955],"domain_scores_gemma":[0.9995083,0.00019668117,0.000037863145,0.0001266537,0.00008597066,0.000044537028],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011425813,0.00013129102,0.00012881063,0.00007431584,0.000100637255,0.000043462165,0.00005608144,0.000112858674,0.000016186388],"category_scores_gemma":[0.000051522828,0.00014465862,0.000056656354,0.00014525076,0.000008906943,0.00025977686,0.0000037918173,0.00006490955,0.00001015233],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007957172,0.000012813544,0.00002028575,0.000005690936,0.0000073056112,5.085249e-7,0.00006347987,0.86830527,0.0021341091,0.000043703578,0.00011564593,0.1292832],"study_design_scores_gemma":[0.00040321492,0.000106256586,0.0010433429,0.000021445432,0.000017333721,2.926711e-7,0.000005186388,0.9890216,0.0054441867,0.0026252484,0.0011382177,0.00017365553],"about_ca_topic_score_codex":0.0000011551838,"about_ca_topic_score_gemma":3.757114e-7,"teacher_disagreement_score":0.9052716,"about_ca_system_score_codex":0.00009079902,"about_ca_system_score_gemma":0.00000681185,"threshold_uncertainty_score":0.58990073},"labels":[],"label_agreement":null},{"id":"W2123201137","doi":"10.1109/saahpc.2011.16","title":"GPU-Accelerated Wire-Length Estimation for FPGA Placement","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Parallel computing; Field-programmable gate array; Thread (computing); Exploit; Cardinality (data modeling); CUDA; Massively parallel; Algorithm; Embedded system","score_opus":0.05265519832774968,"score_gpt":0.2457630288427234,"score_spread":0.19310783051497374,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2123201137","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009656754,0.000038821752,0.9442624,0.000008173564,0.00010770361,0.0003878714,0.000004665624,0.0014817738,0.04405186],"genre_scores_gemma":[0.8994702,0.000019030082,0.09983169,0.000036483973,0.00002375607,0.000144366,0.000017327133,0.000024492012,0.0004326132],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995821,0.0000040820373,0.00013283922,0.000086074135,0.000051167677,0.00014373896],"domain_scores_gemma":[0.9997994,0.000013024557,0.000012100533,0.000112675116,0.000027440892,0.00003537539],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007575212,0.000092806105,0.00008407556,0.000048137827,0.000028519145,0.000015046316,0.00006804785,0.000055398737,0.00035666925],"category_scores_gemma":[0.000006535762,0.00008456846,0.00002697085,0.00005934692,0.0000074237737,0.000115037175,0.000007059766,0.000038355774,0.00003681762],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014797255,0.00032490122,0.00035423966,0.0005822647,0.00032833233,0.000009376339,0.00322593,0.008898697,0.09616213,0.030489609,0.21256399,0.6469126],"study_design_scores_gemma":[0.0003217169,0.00014519224,0.0002267494,0.000016592534,0.000015466307,0.0000020231064,0.000043627973,0.36983597,0.62366474,0.001691934,0.0038009782,0.00023501112],"about_ca_topic_score_codex":0.00001115458,"about_ca_topic_score_gemma":0.000003159834,"teacher_disagreement_score":0.8898135,"about_ca_system_score_codex":0.000030503987,"about_ca_system_score_gemma":0.0000051110715,"threshold_uncertainty_score":0.39052778},"labels":[],"label_agreement":null},{"id":"W2123802188","doi":"10.1145/360276.360300","title":"Detailed routing architectures for embedded programmable logic IP cores","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Application-specific integrated circuit; Routing (electronic design automation); Logic block; Programmable logic device; Block (permutation group theory); Computer science; Field-programmable gate array; Programmable logic array; Channel (broadcasting); Programmable Array Logic; Chip; Logic synthesis; Parallel computing; Simple programmable logic device; Logic gate; Computer hardware; Logic family; Embedded system; Algorithm; Mathematics; Telecommunications","score_opus":0.021818477297364424,"score_gpt":0.2526746141540688,"score_spread":0.23085613685670436,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2123802188","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15157966,0.00020634076,0.8129085,0.00007109539,0.000076937904,0.0007716781,0.000002762663,0.003483099,0.030899957],"genre_scores_gemma":[0.93659735,0.000015444846,0.062326208,0.00012902962,0.000060187776,0.00018124122,0.000006476328,0.00003375158,0.0006503119],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993207,0.0000118094285,0.00015305226,0.00013125334,0.00006998934,0.0003132349],"domain_scores_gemma":[0.99969685,0.00006793574,0.000016302482,0.00014482127,0.000025400519,0.000048690275],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015092386,0.00013582216,0.0001438847,0.00006203697,0.00004973022,0.000052621315,0.000115889954,0.00006819457,0.00006962578],"category_scores_gemma":[0.00003426474,0.00010880267,0.00007166693,0.00010426159,0.000016099884,0.000028217883,0.000014848117,0.00009271154,0.000010100305],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020902428,0.00027288115,0.023209484,0.0005889627,0.00040860617,0.000086720094,0.0020171944,0.061954923,0.10986798,0.051584434,0.024572814,0.725227],"study_design_scores_gemma":[0.0019079344,0.00070288766,0.004108517,0.00013341852,0.00008857565,0.00013602286,0.00034019386,0.62280065,0.24965478,0.09212851,0.026421694,0.0015767924],"about_ca_topic_score_codex":0.000007797099,"about_ca_topic_score_gemma":0.0000586748,"teacher_disagreement_score":0.78501767,"about_ca_system_score_codex":0.000018131188,"about_ca_system_score_gemma":0.0000068221166,"threshold_uncertainty_score":0.4436844},"labels":[],"label_agreement":null},{"id":"W2124402195","doi":"10.1109/fccm.2013.40","title":"Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Netlist; Field-programmable gate array; Computer science; Bitstream; Routing (electronic design automation); Sandbox (software development); Verilog; Embedded system; Suite; Computer architecture; CAD; State (computer science); Virtex; Computer hardware; Operating system; Engineering; Telecommunications","score_opus":0.023327690126324872,"score_gpt":0.23527031926127703,"score_spread":0.21194262913495215,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2124402195","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.43556345,0.003703388,0.0876439,0.00092384586,0.00043963,0.0013161399,0.0000041744306,0.00647416,0.4639313],"genre_scores_gemma":[0.9981957,0.0004507809,0.00030279616,0.0005980668,0.00015420408,0.00006636877,0.000001887842,0.00003233107,0.00019784283],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992514,0.000024023635,0.00019406996,0.00013452742,0.00013376721,0.00026220604],"domain_scores_gemma":[0.99954605,0.00012179823,0.00002164085,0.0002355717,0.000022059981,0.000052865158],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018096386,0.00014366441,0.00012036056,0.00006439335,0.00008328466,0.00005727171,0.00026055693,0.0001286713,0.0002432241],"category_scores_gemma":[0.000019715211,0.00009443709,0.000043803364,0.00012749738,0.000022494038,0.00018784354,0.000023614688,0.00034464014,0.00036819134],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000022840054,0.000022695831,0.0029324822,0.00021390324,0.00012334438,0.0000062912122,0.0015722077,0.0017667053,0.22253966,0.024930606,0.15839104,0.5874988],"study_design_scores_gemma":[0.0008822431,0.00026051243,0.034724683,0.0013162936,0.00010532158,0.00007724256,0.0026819091,0.19937928,0.6553307,0.032338396,0.0703601,0.0025432685],"about_ca_topic_score_codex":0.00008177389,"about_ca_topic_score_gemma":0.0000074620825,"teacher_disagreement_score":0.5849555,"about_ca_system_score_codex":0.000034234963,"about_ca_system_score_gemma":0.000005605649,"threshold_uncertainty_score":0.47324774},"labels":[],"label_agreement":null},{"id":"W2124752818","doi":"10.1109/tc.2003.1159751","title":"General models and a reduction design technique for FPGA switch box designs","year":2003,"lang":"en","type":"article","venue":"IEEE Transactions on Computers","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Routing (electronic design automation); Reduction (mathematics); Field-programmable gate array; Set (abstract data type); Topology (electrical circuits); Embedded system; Mathematics; Combinatorics","score_opus":0.04322566978115681,"score_gpt":0.24254347381377225,"score_spread":0.19931780403261545,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2124752818","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00062147266,0.000059985516,0.9968259,0.000020327692,0.00048235717,0.0010182144,0.00000882249,0.0007984095,0.00016456532],"genre_scores_gemma":[0.5955901,0.00009187353,0.40372235,0.000028499822,0.000029508414,0.00045031382,9.475912e-7,0.000043388274,0.000042980468],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991543,0.00005421,0.00019868443,0.00024721533,0.000091423,0.00025414856],"domain_scores_gemma":[0.9995928,0.000069618836,0.000020611958,0.00019169445,0.000037353035,0.00008795088],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020395467,0.00021185545,0.00018057867,0.00020860488,0.00014045453,0.000046357214,0.00008630566,0.00014664908,0.0000055102055],"category_scores_gemma":[9.083511e-7,0.00022977647,0.00008443723,0.00016305558,0.000031945747,0.00020678135,3.5296068e-7,0.0001742342,0.0000019311462],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025315181,0.000053333704,1.0008504e-7,0.000033580363,0.00005703897,0.0000019492422,0.00018150064,0.8357038,0.12998451,0.00033559318,0.0020795113,0.031543773],"study_design_scores_gemma":[0.00027026076,0.00018924089,3.515603e-7,0.000034509067,0.000027412701,0.000068776186,0.00001102993,0.3072862,0.6887971,0.0028482755,0.000226985,0.00023983723],"about_ca_topic_score_codex":0.0000058899977,"about_ca_topic_score_gemma":7.349277e-7,"teacher_disagreement_score":0.5949687,"about_ca_system_score_codex":0.000087844805,"about_ca_system_score_gemma":0.000021246788,"threshold_uncertainty_score":0.9370013},"labels":[],"label_agreement":null},{"id":"W2125290282","doi":"10.1109/ccece.2009.5090315","title":"Near-linear wirelength estimation for FPGA placement","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Routing (electronic design automation); Reduction (mathematics); Path (computing); Algorithm; Parallel computing; Static timing analysis; Star (game theory); Critical path method; Differentiable function; Placement; Computer engineering; Circuit design; Embedded system; Mathematics; Physical design","score_opus":0.012375305794748607,"score_gpt":0.24766384199299607,"score_spread":0.23528853619824747,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2125290282","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009819183,0.00004147172,0.9794631,0.00010805492,0.000050823965,0.00028750792,0.0000026178845,0.0011741862,0.00905307],"genre_scores_gemma":[0.8131332,0.000014756246,0.1862939,0.00012499378,0.00004249119,0.00002916572,0.000014189742,0.000012080147,0.00033521812],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996342,0.0000025712757,0.00010760663,0.0000707328,0.0000581952,0.00012671515],"domain_scores_gemma":[0.9998311,0.000016726854,0.000008079458,0.00009795124,0.000015940308,0.000030219415],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0000683458,0.00007517432,0.00007229179,0.000024308049,0.00003475919,0.00002119444,0.00005062878,0.000044721746,0.00004800604],"category_scores_gemma":[0.0000083403875,0.000069380454,0.000028888864,0.000045596702,0.0000050117933,0.00007795184,0.0000025862992,0.0000380068,0.000024994279],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000263333,0.000076930744,0.000020294301,0.00008669007,0.00003306888,0.0000019213562,0.00028407428,0.17872004,0.016843282,0.008038815,0.10040203,0.6954665],"study_design_scores_gemma":[0.00017305026,0.00013091187,0.00006879514,0.000008597121,0.0000057250795,0.0000011361162,0.000006180498,0.9182057,0.07191886,0.0012664138,0.008106549,0.00010808914],"about_ca_topic_score_codex":0.0000014123988,"about_ca_topic_score_gemma":5.4107807e-7,"teacher_disagreement_score":0.80331403,"about_ca_system_score_codex":0.00002790314,"about_ca_system_score_gemma":0.0000050081526,"threshold_uncertainty_score":0.28292528},"labels":[],"label_agreement":null},{"id":"W2126743471","doi":"10.1109/iwsoc.2005.17","title":"A multilevel eigenvalue based circuit partitioning technique","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Very-large-scale integration; Partition (number theory); Computer science; Electronic circuit; Eigenvalues and eigenvectors; Matrix (chemical analysis); Algorithm; Physical design; Eigendecomposition of a matrix; Parallel computing; Circuit design; Mathematics; Engineering; Embedded system","score_opus":0.020216498490102118,"score_gpt":0.21608332661219026,"score_spread":0.19586682812208814,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2126743471","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0017588875,0.000059564834,0.942461,0.00004418506,0.000030652573,0.00024871892,0.0000045670995,0.0028681317,0.05252428],"genre_scores_gemma":[0.90888137,0.000008242042,0.090231,0.000188393,0.00008723565,0.00023385542,0.0000060331427,0.000033664106,0.0003301851],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99938047,0.000012041452,0.00016827876,0.00012306252,0.00009729485,0.00021887127],"domain_scores_gemma":[0.9996811,0.000026524162,0.000011593427,0.00019557716,0.000023070452,0.00006213233],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013758757,0.00012373955,0.00010636532,0.000095915726,0.000046565176,0.000026973412,0.0001064019,0.000098272845,0.0007698208],"category_scores_gemma":[0.000011161246,0.00012426126,0.000052443436,0.00009475455,0.000016340437,0.00012940742,0.000008488271,0.00012394495,0.00014354466],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050078374,0.0001410285,0.0011117257,0.00014644065,0.00005196991,0.000020746182,0.0002585979,0.03300473,0.63529617,0.010433651,0.039281134,0.2802488],"study_design_scores_gemma":[0.00014313101,0.000020645673,0.00037277307,0.00003592871,0.0000066291527,0.0000076827455,0.0000063810057,0.20095104,0.7745218,0.0007028976,0.022972224,0.00025882284],"about_ca_topic_score_codex":0.00000822195,"about_ca_topic_score_gemma":0.0000071577156,"teacher_disagreement_score":0.9071225,"about_ca_system_score_codex":0.00006797955,"about_ca_system_score_gemma":0.00001242695,"threshold_uncertainty_score":0.8428998},"labels":[],"label_agreement":null},{"id":"W2127275081","doi":"10.1109/ccece.2009.5090316","title":"Analog placement design with constraints of multiple symmetry groups","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Transitive closure; Computational complexity theory; Topology (electrical circuits); Representation (politics); Graph; Mathematics; Symmetry (geometry); Algorithm; Computer science; Mathematical optimization; Combinatorics; Geometry","score_opus":0.013668960172385027,"score_gpt":0.20572857605736292,"score_spread":0.19205961588497789,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2127275081","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018210232,0.000061816194,0.9602087,0.000011012292,0.00001685967,0.00020665611,0.0000031521722,0.00046570814,0.020815872],"genre_scores_gemma":[0.92944795,0.00001654214,0.07042589,0.000045104338,0.000010339067,0.0000056873655,0.000002565184,0.0000094079105,0.000036525646],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995143,0.000011642068,0.0001404337,0.00008689383,0.00010060595,0.00014612424],"domain_scores_gemma":[0.99974144,0.00004328916,0.000017127151,0.00013273316,0.000022030774,0.000043410255],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010098857,0.00010245928,0.00013757922,0.000078039295,0.000013268371,0.000007509859,0.000077192664,0.00004793696,0.00009717341],"category_scores_gemma":[0.0000067989167,0.0000802188,0.000023065166,0.00012055917,0.000036287845,0.000054349457,0.0000039205133,0.00006239574,0.0000058149026],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00028300317,0.0006406029,0.010409073,0.00028825935,0.0005289849,0.00013210448,0.0010065971,0.048728876,0.5250905,0.035572957,0.03792502,0.339394],"study_design_scores_gemma":[0.0012573161,0.0012023314,0.0050590257,0.00010829819,0.00003913885,0.000039312727,0.0002394146,0.048090015,0.94173145,0.0015457044,0.00018078952,0.0005072271],"about_ca_topic_score_codex":0.0000033494637,"about_ca_topic_score_gemma":0.0000017960974,"teacher_disagreement_score":0.9112377,"about_ca_system_score_codex":0.000021987753,"about_ca_system_score_gemma":0.0000077344375,"threshold_uncertainty_score":0.32712278},"labels":[],"label_agreement":null},{"id":"W2127309005","doi":"10.1109/tvlsi.2008.2008188","title":"Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Multiplexer; Routing (electronic design automation); Field-programmable gate array; Computer science; Logic synthesis; Lookup table; Set (abstract data type); Flexibility (engineering); Logic optimization; Logic family; Logic gate; Arithmetic; Parallel computing; Algorithm; Mathematics; Embedded system; Multiplexing; Programming language; Telecommunications","score_opus":0.039619554507284944,"score_gpt":0.2720311911488703,"score_spread":0.23241163664158537,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2127309005","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07688279,0.00011011822,0.92098534,0.00016909474,0.00040820433,0.00090297306,0.00003927735,0.000108835324,0.00039336295],"genre_scores_gemma":[0.99897754,0.000028710816,0.00068275514,0.00012178256,0.000032747903,0.00010274264,0.00000822654,0.000022629674,0.000022858047],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99773175,0.00032354382,0.0010181819,0.00024736344,0.0003131928,0.0003659578],"domain_scores_gemma":[0.99890006,0.00039124413,0.00015841922,0.0003586328,0.00013217682,0.00005948785],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010609406,0.00026306158,0.00046798395,0.00035173626,0.00012871118,0.000053336113,0.0003109279,0.00022504826,0.000011538684],"category_scores_gemma":[0.00002006202,0.00018491143,0.00015597483,0.0007903241,0.0000781088,0.00017827649,0.0000034989932,0.00052400597,0.0000015390559],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000734766,0.00015825752,0.00008515019,0.000029340257,0.000025223097,0.0000036798738,0.0022397784,0.988837,0.0047643716,0.00039477425,0.000051615625,0.003337311],"study_design_scores_gemma":[0.0006869075,0.00023476072,0.00040167666,0.00072835636,0.00003148869,0.000014138881,0.0079247495,0.98194677,0.0077299266,0.000083741565,0.000016246775,0.00020122336],"about_ca_topic_score_codex":0.00016071447,"about_ca_topic_score_gemma":0.00044545735,"teacher_disagreement_score":0.92209476,"about_ca_system_score_codex":0.0003064076,"about_ca_system_score_gemma":0.00003653455,"threshold_uncertainty_score":0.7540469},"labels":[],"label_agreement":null},{"id":"W2127958790","doi":"10.1109/icecs.2007.4511137","title":"Application of Diversity Controlled Genetic Algorithms to the Design and Optimization of OTA-C IF Filters","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Convergence (economics); Filter (signal processing); Computer science; Optimization problem; Genetic algorithm; Electronic engineering; Algorithm; Engineering; Mathematical optimization; Mathematics","score_opus":0.011505174421973836,"score_gpt":0.20879362762101927,"score_spread":0.19728845319904545,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2127958790","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0049909134,0.000056881745,0.99405456,0.000017598324,0.0000130026365,0.0005210004,0.0000014050164,0.00006838111,0.00027623578],"genre_scores_gemma":[0.7645445,0.000030157682,0.23537672,0.00001629239,0.000007218648,0.000008823954,7.91273e-7,0.000004373174,0.000011115878],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996687,0.000012155946,0.00013033209,0.000055746543,0.00006983396,0.00006321623],"domain_scores_gemma":[0.99974626,0.00007095569,0.000024952074,0.000097947064,0.000036744543,0.000023115548],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00024737365,0.000048964277,0.000105757616,0.00004956776,0.000025872396,0.0000031752706,0.00007271798,0.000031827203,0.0000073051847],"category_scores_gemma":[0.000008566713,0.00003570417,0.000018583145,0.00009283054,0.000014834482,0.00002336909,0.000026294978,0.000021175247,5.6121644e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000055307173,0.0000149438565,0.00063754,0.000021636051,0.00003743549,2.8378673e-7,0.00046747146,0.9328284,0.014003008,0.00011598163,0.00039791386,0.051420048],"study_design_scores_gemma":[0.0004002945,0.000056102414,0.0027733168,0.0000039872875,0.000022363336,7.4369615e-7,0.000042803513,0.95162284,0.04493526,0.000054530836,0.000032745826,0.00005502748],"about_ca_topic_score_codex":0.000038632814,"about_ca_topic_score_gemma":0.0000020605798,"teacher_disagreement_score":0.7595536,"about_ca_system_score_codex":0.000011610186,"about_ca_system_score_gemma":0.0000018063754,"threshold_uncertainty_score":0.1455974},"labels":[],"label_agreement":null},{"id":"W2128239317","doi":"10.1109/cicc.1995.518231","title":"A time-multiplexed FPGA architecture for logic emulation","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":129,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Vedecká Grantová Agentúra MŠVVaŠ SR a SAV","keywords":"Emulation; Logic family; Computer science; Logic synthesis; Logic optimization; USable; Field-programmable gate array; Logic gate; Programmable logic device; Computer architecture; Programmable logic array; Pass transistor logic; Embedded system; Sequential logic; Digital electronics; Resistor–transistor logic; Electronic circuit; Engineering; Electrical engineering; Algorithm","score_opus":0.021509665277858088,"score_gpt":0.2157802822445578,"score_spread":0.19427061696669973,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2128239317","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0059103137,0.0002273678,0.96229595,0.00016365734,0.00006708251,0.0005773907,0.000010191995,0.0027297847,0.028018283],"genre_scores_gemma":[0.93391204,0.000015375654,0.06333153,0.00011898294,0.00009606595,0.000071523355,0.000013310243,0.000030265166,0.0024109106],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99963003,0.000005200384,0.00009410489,0.00008527954,0.000047724614,0.00013764387],"domain_scores_gemma":[0.9997977,0.00004145348,0.000008036888,0.0001089488,0.00001471968,0.00002914417],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003546156,0.00008674042,0.00008652716,0.000054777996,0.000026373817,0.000014029538,0.000059923095,0.00007083566,0.0005180666],"category_scores_gemma":[0.000013642929,0.0000734792,0.000047791702,0.00006288439,0.00000915575,0.000040730978,0.0000052052114,0.0000533885,0.00010866134],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014045629,0.000069303525,0.000048098515,0.00015195526,0.00006498566,0.0000037627399,0.0007957835,0.06625947,0.41118464,0.0014671922,0.19244608,0.32749468],"study_design_scores_gemma":[0.00029926494,0.000069579546,0.00007053331,0.00000994455,0.000009059931,0.0000050539834,0.0000046091873,0.91811115,0.046942107,0.0037583879,0.030500019,0.00022030684],"about_ca_topic_score_codex":0.0000010591016,"about_ca_topic_score_gemma":0.0000015518098,"teacher_disagreement_score":0.9280017,"about_ca_system_score_codex":0.000015992202,"about_ca_system_score_gemma":6.3325865e-7,"threshold_uncertainty_score":0.5672466},"labels":[],"label_agreement":null},{"id":"W2128701724","doi":"10.5555/2016802.2016811","title":"FPGA glitch power analysis and reduction","year":2011,"lang":"en","type":"article","venue":"International Symposium on Low Power Electronics and Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Glitch; Field-programmable gate array; Power analysis; Dynamic demand; Overhead (engineering); Reduction (mathematics); Computer science; Power (physics); Routing (electronic design automation); Embedded system; Algorithm; Mathematics; Cryptography; Telecommunications; Physics","score_opus":0.008595959861145907,"score_gpt":0.20981841352481623,"score_spread":0.2012224536636703,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2128701724","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2843933,0.0021853412,0.65055287,0.00039765006,0.0009178369,0.00060843234,0.000025936699,0.0009685455,0.059950087],"genre_scores_gemma":[0.9970212,0.00093168695,0.0017143405,0.000063431435,0.00003421698,0.000027457629,0.00000801381,0.000026501282,0.00017316909],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991025,0.000026787344,0.00019785155,0.0002590599,0.00017995032,0.00023387861],"domain_scores_gemma":[0.9996389,0.000028465804,0.000036920974,0.00015411379,0.000063725274,0.000077832294],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019945431,0.00017749009,0.00016534183,0.00022974974,0.000050898896,0.00006954634,0.00012843843,0.00010540435,0.00014417115],"category_scores_gemma":[0.000005839009,0.00017214108,0.00006649231,0.00019210813,0.000034345958,0.00016131594,0.000018994258,0.00017121035,0.000009695562],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0013625011,0.0011425962,0.0035912944,0.000085759406,0.009747904,0.000119007724,0.0092598535,0.0057537444,0.7468795,0.16620445,0.014568738,0.04128462],"study_design_scores_gemma":[0.0014231075,0.0024590634,0.008385971,0.00008856387,0.00060396205,0.00021408059,0.00014070737,0.04625448,0.8976183,0.025817825,0.015227169,0.0017668041],"about_ca_topic_score_codex":0.000016529957,"about_ca_topic_score_gemma":0.0000021958786,"teacher_disagreement_score":0.7126279,"about_ca_system_score_codex":0.000092634,"about_ca_system_score_gemma":0.000012509453,"threshold_uncertainty_score":0.70197093},"labels":[],"label_agreement":null},{"id":"W2129159815","doi":"10.5555/1356802.1356851","title":"Symmetry-aware placement with transitive closure graphs for analog layout design","year":2008,"lang":"en","type":"article","venue":"Digital Scholarship - UNLV (University of Nevada Reno)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Transitive closure; Closure (psychology); Transitive relation; Symmetry (geometry); Graph; Set (abstract data type); Space (punctuation); Mathematics; Computer science; Topology (electrical circuits); Algorithm; Discrete mathematics; Combinatorics; Geometry","score_opus":0.027642781294926096,"score_gpt":0.18445765369086053,"score_spread":0.15681487239593445,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2129159815","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.38893119,0.00021731199,0.60353875,0.000056268495,0.000047587113,0.00085420726,0.00050936406,0.00062676764,0.0052185683],"genre_scores_gemma":[0.99438214,0.00005993264,0.00514982,0.00001710558,0.000013295668,0.0000023294363,0.00011878169,0.00003727541,0.0002193427],"study_design_codex":"design_other","study_design_gemma":"observational","domain_scores_codex":[0.9989394,0.000032342745,0.00013816137,0.00027430776,0.00028629278,0.00032950568],"domain_scores_gemma":[0.99931335,0.00010107799,0.000059205595,0.00023211662,0.00014324932,0.00015097758],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00014187474,0.00024278346,0.00031670168,0.00023235008,0.00020928337,0.00004320438,0.00030246263,0.00016235761,0.00002558568],"category_scores_gemma":[0.000012088432,0.00026600013,0.00014835801,0.00041074937,0.00014210273,0.0010909813,0.000024381132,0.0002439694,0.000007935133],"study_design_candidate":"observational","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.033903405,0.007240007,0.24004999,0.00782194,0.019478641,0.01023344,0.0790975,0.080790766,0.07577349,0.052880723,0.11224896,0.28048113],"study_design_scores_gemma":[0.085545845,0.057796173,0.29355463,0.0070236926,0.0052180085,0.0026584633,0.09116823,0.0645967,0.21055281,0.059227888,0.094530426,0.028127111],"about_ca_topic_score_codex":0.000019689987,"about_ca_topic_score_gemma":0.000023901728,"teacher_disagreement_score":0.6054509,"about_ca_system_score_codex":0.000100749145,"about_ca_system_score_gemma":0.000049727943,"threshold_uncertainty_score":0.9999792},"labels":[],"label_agreement":null},{"id":"W2129619153","doi":"10.1109/tvlsl2003.820527","title":"Timing driven gate duplication","year":2004,"lang":"en","type":"article","venue":"eScholarship (California Digital Library)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Tree traversal; Tuple; Gene duplication; Logic gate; Traverse; Computer science; Minification; Algorithm; AND gate; Parallel computing; Mathematics; Discrete mathematics","score_opus":0.013114122795632906,"score_gpt":0.20187340900531348,"score_spread":0.18875928620968058,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2129619153","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7415006,0.00071260065,0.08918742,0.0008638991,0.00028237313,0.0009079236,0.0014007797,0.013648971,0.1514954],"genre_scores_gemma":[0.99408114,0.000043528176,0.0049188696,0.00017777774,0.00011628351,0.0000401043,0.00033148477,0.00011086601,0.00017992654],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99894375,0.000010537026,0.0002834181,0.00024188042,0.00017736955,0.00034306519],"domain_scores_gemma":[0.99942064,0.000027003245,0.00003601767,0.00031888258,0.00001531652,0.00018211182],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00005246249,0.00023318258,0.00017116303,0.00013708504,0.00007433913,0.0006097129,0.00031860633,0.00014297779,0.00012971842],"category_scores_gemma":[0.000031241696,0.00023531199,0.000101092126,0.00030803427,0.00003765644,0.0027577996,0.00006868501,0.00030682026,0.0025550306],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00026596762,0.0015167801,0.13973041,0.0017652983,0.00085391133,0.00069527834,0.00084985985,0.06389214,0.14427723,0.09174641,0.05518562,0.4992211],"study_design_scores_gemma":[0.0017553332,0.00022046802,0.007187657,0.00053768,0.00005459437,0.000095000156,0.000042086263,0.005930822,0.3708587,0.145862,0.46503246,0.0024231842],"about_ca_topic_score_codex":7.1691346e-7,"about_ca_topic_score_gemma":2.029338e-7,"teacher_disagreement_score":0.4967979,"about_ca_system_score_codex":0.00005781528,"about_ca_system_score_gemma":0.000025772903,"threshold_uncertainty_score":0.9982216},"labels":[],"label_agreement":null},{"id":"W2129647912","doi":"10.1007/0-387-34403-9_41","title":"An Effective Refinement Algorithm Based on Multilevel Paradigm for Graph Bipartitioning","year":2006,"lang":"en","type":"book-chapter","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Tabu search; Graph partition; Algorithm; Computer science; Graph; Mathematics; Theoretical computer science","score_opus":0.012119178788564871,"score_gpt":0.22961846378640244,"score_spread":0.21749928499783758,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2129647912","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0000018228301,0.000070793816,0.75669223,0.000008085196,0.00012722026,0.0010249696,0.00021805294,0.0011463605,0.24071045],"genre_scores_gemma":[0.0637656,0.00021893492,0.7222932,0.0012635365,0.0025889329,0.0074445875,0.006631972,0.0017699955,0.19402324],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989417,0.000008617148,0.00027546939,0.00034057526,0.00017600085,0.00025761785],"domain_scores_gemma":[0.9993636,0.000115805255,0.000051829196,0.0003492993,0.00004240192,0.0000770574],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00013178182,0.00041414652,0.00033984915,0.00030218923,0.00007726399,0.000042619664,0.0001223577,0.00032965804,0.00015632606],"category_scores_gemma":[0.000002806338,0.0004015679,0.00019323257,0.000020799365,0.000026682255,0.000059512477,0.0000059580952,0.00022074615,0.000023237768],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000045977486,0.0001579005,0.0000039981555,0.00044868694,0.0002602176,0.00003229096,0.000037710302,0.04223853,0.0008724192,0.095713526,0.112075046,0.7481137],"study_design_scores_gemma":[0.0009730594,0.0010883845,0.00006202026,0.00051648705,0.00012846832,0.0000022047748,0.0000014402513,0.8021477,0.014709894,0.03247145,0.1466377,0.0012612359],"about_ca_topic_score_codex":0.000021482212,"about_ca_topic_score_gemma":0.000010122959,"teacher_disagreement_score":0.75990915,"about_ca_system_score_codex":0.00013161823,"about_ca_system_score_gemma":0.000009796155,"threshold_uncertainty_score":0.9998436},"labels":[],"label_agreement":null},{"id":"W2129946839","doi":"10.1287/ijoc.1080.0296","title":"Accelerating Benders Decomposition by Local Branching","year":2008,"lang":"en","type":"article","venue":"INFORMS journal on computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":164,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Montréal; Université du Québec à Montréal; HEC Montréal","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Benders' decomposition; Branching (polymer chemistry); Mathematical optimization; Branch and bound; Mathematics; Decomposition; Upper and lower bounds; Algorithm; Computer science","score_opus":0.016081907554113695,"score_gpt":0.24108229443550394,"score_spread":0.22500038688139024,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2129946839","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.38863227,0.00010355181,0.6046931,0.000019740615,0.00024899672,0.000050527015,7.9658247e-7,0.00038634066,0.0058646863],"genre_scores_gemma":[0.9913801,0.000062043626,0.007946875,0.0002997747,0.0002674339,7.588507e-7,0.0000047811077,0.000029091321,0.000009150888],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989081,0.000013299059,0.00042873138,0.000085046195,0.00023916604,0.0003256373],"domain_scores_gemma":[0.9995917,0.00006920268,0.000093476636,0.00008618681,0.000040490515,0.00011890939],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00024331624,0.00017177645,0.0001740428,0.0001426107,0.00048824862,0.00012400364,0.00016595516,0.000085316104,0.000018548368],"category_scores_gemma":[0.000012478785,0.00015323194,0.00008698393,0.00012747303,0.000027087706,0.00046833328,0.00002208854,0.00066204753,0.000021515107],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017570927,0.000037301645,0.0010276828,0.000044127217,0.0000866449,0.00013783513,0.0018935151,0.32034844,0.012102207,0.00027240775,0.019634776,0.6443975],"study_design_scores_gemma":[0.00095313083,0.00031677846,0.0010528435,0.0004296831,0.000011057285,0.0034665482,0.00027074874,0.93060577,0.05684577,0.0005042321,0.004814328,0.0007291266],"about_ca_topic_score_codex":0.0000032055343,"about_ca_topic_score_gemma":3.1149037e-7,"teacher_disagreement_score":0.64366835,"about_ca_system_score_codex":0.00015133386,"about_ca_system_score_gemma":0.000017253904,"threshold_uncertainty_score":0.6248617},"labels":[],"label_agreement":null},{"id":"W2130276110","doi":"10.1109/isvlsi.2006.1","title":"A \"Soft++\" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"CMC Microsystems","keywords":"Computer science; Application-specific integrated circuit; Place and route; Benchmark (surveying); Physical design; Field-programmable gate array; Design flow; Embedded system; Overhead (engineering); Computer architecture; Set (abstract data type); Integrated circuit design; Soft error; Electronic engineering; Computer hardware; Circuit design; Engineering","score_opus":0.031757654419559786,"score_gpt":0.24386017304065433,"score_spread":0.21210251862109453,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2130276110","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.34883463,0.00093262736,0.63863146,0.000013449051,0.000016733093,0.00042528243,0.0000018333851,0.0009408163,0.010203152],"genre_scores_gemma":[0.96131104,0.00002246356,0.038385384,0.000013883173,0.00004592936,0.00007610103,9.74063e-7,0.000022790793,0.00012144679],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994879,0.000018386216,0.00009993979,0.00014829202,0.00006812912,0.00017737137],"domain_scores_gemma":[0.99978995,0.000054125772,0.0000085560405,0.000105036,0.000015582784,0.00002674992],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008912192,0.00014229094,0.0001947432,0.000072435396,0.000027935479,0.000019204643,0.00003707063,0.000039059483,0.0000015779922],"category_scores_gemma":[0.000004130645,0.00010352421,0.000014494182,0.00014714847,0.00006148895,0.00008944358,0.000014787998,0.000099226425,0.000002181006],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000569237,0.0043230318,0.014094296,0.0058288416,0.0017408687,0.044164065,0.033773996,0.3282651,0.09028196,0.06366222,0.17209612,0.24120027],"study_design_scores_gemma":[0.003296441,0.00091518566,0.0010717693,0.00022200299,0.00016669491,0.009071034,0.0037177796,0.8699542,0.09562997,0.012771375,0.00084220676,0.0023413002],"about_ca_topic_score_codex":0.00006618499,"about_ca_topic_score_gemma":0.000020395788,"teacher_disagreement_score":0.6124764,"about_ca_system_score_codex":0.00002919016,"about_ca_system_score_gemma":0.0000043821424,"threshold_uncertainty_score":0.4221595},"labels":[],"label_agreement":null},{"id":"W2130529591","doi":"10.1109/cicc.2002.1012766","title":"Nearest neighbour interconnect architecture in deep submicron FPGAs","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Interconnection; Computer science; Architecture; Network topology; Computer architecture; Nearest neighbour; Parallel computing; Performance improvement; Embedded system; Topology (electrical circuits); Engineering; Electrical engineering; Computer network; Artificial intelligence","score_opus":0.004906398154460492,"score_gpt":0.18257057341065003,"score_spread":0.17766417525618955,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2130529591","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.37578714,0.0010574342,0.41715756,0.00008157269,0.0002574319,0.00034177542,0.0000026335704,0.0015846707,0.20372978],"genre_scores_gemma":[0.99335384,0.000045750458,0.006239032,0.00009660024,0.000023466111,0.000016866397,0.0000022476672,0.00003187145,0.0001903268],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99938387,0.000029368533,0.00014856635,0.00012950771,0.000055623663,0.00025307093],"domain_scores_gemma":[0.9997265,0.000032586664,0.0000077961495,0.00017515129,0.000008346209,0.000049654212],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010439614,0.00013609743,0.00013328528,0.0001315243,0.000015049863,0.00002995316,0.000110396184,0.00009254409,0.00043166833],"category_scores_gemma":[0.000026898653,0.00012286624,0.000041710726,0.00015997887,0.000014258676,0.00006239998,0.000010479517,0.00022205595,0.000057652254],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000043856722,0.0002658741,0.021631306,0.0004403985,0.00013957403,0.00037120882,0.0046308446,0.046589546,0.36954072,0.056631975,0.014450112,0.4852646],"study_design_scores_gemma":[0.0013011507,0.00024142886,0.0074570016,0.00015948649,0.000018781966,0.00020596277,0.0003967609,0.017109763,0.85475665,0.0223111,0.09452711,0.0015148057],"about_ca_topic_score_codex":0.000036697515,"about_ca_topic_score_gemma":0.00045491665,"teacher_disagreement_score":0.6175667,"about_ca_system_score_codex":0.000049836497,"about_ca_system_score_gemma":0.0000064016476,"threshold_uncertainty_score":0.501034},"labels":[],"label_agreement":null},{"id":"W2130762555","doi":"10.1109/iccd.1994.331981","title":"An ILP solution for simultaneous scheduling, allocation, and binding in multiple block synthesis","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"Deutsche Forschungsgemeinschaft","keywords":"Computer science; Scheduling (production processes); Integer programming; Block (permutation group theory); Interdependence; Critical path method; Linear programming; Set (abstract data type); High-level synthesis; Mathematical optimization; Job shop scheduling; Processor scheduling; Theoretical computer science; Distributed computing; Parallel computing; Algorithm; Programming language; Mathematics; Embedded system; Engineering; Schedule; Field-programmable gate array","score_opus":0.02182484388445856,"score_gpt":0.22399418965289106,"score_spread":0.20216934576843248,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2130762555","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6356278,0.00027163944,0.3620906,0.00006427315,0.000048956004,0.00041376142,0.0000073018023,0.0009199714,0.00055567856],"genre_scores_gemma":[0.9458449,0.00009551401,0.053863607,0.000012562765,0.000029808645,0.000070613554,0.000002824483,0.000021467951,0.000058705966],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995181,0.000009322245,0.00013757253,0.00012757203,0.00004523616,0.00016222094],"domain_scores_gemma":[0.99962294,0.00019713612,0.000011834091,0.0001044582,0.000021921023,0.000041737072],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010229065,0.000089304085,0.00009531578,0.00010515857,0.00004946038,0.00002741626,0.00005741496,0.00008253657,0.00002682021],"category_scores_gemma":[0.00013580798,0.00009230194,0.000016042319,0.00007511936,0.000012459,0.0001214386,0.000005126165,0.0000499908,0.000007901636],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000152301545,0.00020240057,0.005635056,0.00026537888,0.00004531688,0.000010016759,0.0012596879,0.09916755,0.6307544,0.0005394301,0.0010067982,0.2610987],"study_design_scores_gemma":[0.000120603574,0.000025270567,0.000048152076,0.00002107848,0.0000056119097,0.0000036775568,0.00003957461,0.94635665,0.0528687,0.000040197017,0.0003439883,0.00012649788],"about_ca_topic_score_codex":0.000022272076,"about_ca_topic_score_gemma":0.0000601958,"teacher_disagreement_score":0.84718907,"about_ca_system_score_codex":0.000037704947,"about_ca_system_score_gemma":0.00000158208,"threshold_uncertainty_score":0.3763964},"labels":[],"label_agreement":null},{"id":"W2131004306","doi":"10.1109/tcsii.2005.862174","title":"A connectivity based clustering algorithm with application to VLSI circuit partitioning","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":33,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Very-large-scale integration; Computer science; Benchmark (surveying); Algorithm; Suite; Set (abstract data type); Parallel computing; Data mining; Artificial intelligence; Embedded system","score_opus":0.010564492616238616,"score_gpt":0.1982182144374683,"score_spread":0.18765372182122966,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2131004306","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019887751,0.0002678523,0.9769878,0.000010270348,0.000032283857,0.00031308137,0.000043029944,0.0004466288,0.0020113082],"genre_scores_gemma":[0.99952585,0.0000038403446,0.00015400752,0.000026442407,0.00006268605,0.0001356067,0.000008420924,0.00003362758,0.000049530277],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990171,0.000014382328,0.0002464069,0.000301998,0.00017325673,0.00024685523],"domain_scores_gemma":[0.99963564,0.000045203215,0.000042770276,0.00009097375,0.00006326717,0.0001221454],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011729166,0.00021255724,0.00023719683,0.00016966618,0.00043379096,0.00045210315,0.000048126785,0.00008795236,0.0000019752806],"category_scores_gemma":[7.645326e-7,0.0001954191,0.00003131986,0.00025717725,0.000045523168,0.00045298642,0.0000010866783,0.00013803905,0.0000015574773],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007215203,0.00007131096,0.000116163625,0.00027753814,0.000022221522,0.000007238386,0.00014228512,0.13944542,0.005813326,0.000055380173,0.000013062496,0.8540288],"study_design_scores_gemma":[0.00046449553,0.00033340728,0.00027413285,0.0005050921,0.000042793843,0.000102360136,0.00014639935,0.99219054,0.0048204246,0.00024218668,0.00037157233,0.000506625],"about_ca_topic_score_codex":0.00007500811,"about_ca_topic_score_gemma":0.000037414095,"teacher_disagreement_score":0.9796381,"about_ca_system_score_codex":0.000052320072,"about_ca_system_score_gemma":0.000023665685,"threshold_uncertainty_score":0.796896},"labels":[],"label_agreement":null},{"id":"W2131602584","doi":"10.5555/1899721.1899785","title":"A performance-constrained template-based layout retargeting algorithm for analog integrated circuits","year":2010,"lang":"en","type":"article","venue":"Asia and South Pacific Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Retargeting; Parasitic extraction; Computer science; Integrated circuit layout; Analogue electronics; Set (abstract data type); Integer programming; Algorithm; Standard cell; IC layout editor; Design layout record; Electronic circuit; Circuit extraction; Integrated circuit; Electronic engineering; Engineering; Artificial intelligence; Equivalent circuit","score_opus":0.021984226089467537,"score_gpt":0.21785472112104545,"score_spread":0.1958704950315779,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2131602584","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.034622192,0.000014908321,0.9602291,0.000021363012,0.0002862725,0.0006356148,0.000059610524,0.0013161735,0.0028147441],"genre_scores_gemma":[0.8974142,0.000005580207,0.10218055,0.000012660943,0.00006128226,0.00014953953,0.000085914464,0.000030084746,0.00006015805],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989104,0.000046429053,0.00033977648,0.00026113173,0.00013517801,0.00030704853],"domain_scores_gemma":[0.9992986,0.00013182705,0.00008376335,0.00019842539,0.00017741155,0.000109971596],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005017533,0.00024645726,0.00025797577,0.00018884976,0.00016597597,0.00015141544,0.00013498189,0.00022674495,0.00007504781],"category_scores_gemma":[0.00006526987,0.0002333645,0.000050983796,0.00019352435,0.000091059104,0.0002050443,0.0000067076276,0.00026855242,0.000014047342],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017566033,0.000037118178,0.0019740206,0.00027322376,0.00008514639,0.000006217808,0.0036972328,0.00070482964,0.09676104,0.0008296897,0.0013191538,0.89429474],"study_design_scores_gemma":[0.00043844312,0.00009489277,0.0007371581,0.000069528,0.000024044386,0.000009218217,0.00043243298,0.980134,0.017156163,0.00019598937,0.00040228505,0.00030583228],"about_ca_topic_score_codex":0.0000023116706,"about_ca_topic_score_gemma":0.0000010538851,"teacher_disagreement_score":0.9794292,"about_ca_system_score_codex":0.000018342986,"about_ca_system_score_gemma":0.00010279356,"threshold_uncertainty_score":0.9516328},"labels":[],"label_agreement":null},{"id":"W2131752392","doi":"10.5555/1129601.1129728","title":"Mixed-size placement via line search","year":2005,"lang":"en","type":"article","venue":"International Conference on Computer Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Scaling; Computer science; Line (geometry); Simple (philosophy); Sampling (signal processing); Algorithm; Function (biology); Line search; Mathematical optimization; Mathematics","score_opus":0.08022057527161153,"score_gpt":0.286907533980832,"score_spread":0.2066869587092205,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2131752392","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.002746711,0.000021284568,0.98668516,0.000604867,0.00061094755,0.00023732925,0.000009097079,0.000646333,0.008438276],"genre_scores_gemma":[0.8696286,0.000055008008,0.12880218,0.00039969804,0.0006058209,0.00003964254,0.000013499647,0.000028731782,0.0004268424],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99873793,0.000060647475,0.00029200953,0.00025567747,0.0004031377,0.0002505773],"domain_scores_gemma":[0.999321,0.00017168777,0.000028349283,0.0002200565,0.00016351478,0.00009540727],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002582814,0.00021322918,0.0001675879,0.00015549902,0.000040112096,0.00012809341,0.00047178744,0.00008742437,0.0007827283],"category_scores_gemma":[0.000009390285,0.00021131878,0.00006196337,0.00008050893,0.000028535447,0.00017582803,0.00005914501,0.0002487867,0.0004885947],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014269691,0.0002618102,0.000040617848,0.000027832139,0.00028002055,0.000054783435,0.0004029667,0.32062688,0.03641984,0.0344715,0.052086145,0.5551849],"study_design_scores_gemma":[0.00038932206,0.00021516588,0.00010432181,0.000059678205,0.000004664184,0.000015742284,0.0000058666456,0.9226821,0.07118531,0.0014999744,0.0035929105,0.00024492998],"about_ca_topic_score_codex":0.0000054904276,"about_ca_topic_score_gemma":0.0000024366839,"teacher_disagreement_score":0.86688185,"about_ca_system_score_codex":0.00016499116,"about_ca_system_score_gemma":0.000031798692,"threshold_uncertainty_score":0.86173296},"labels":[],"label_agreement":null},{"id":"W2131973905","doi":"10.1109/ccece.2002.1015261","title":"A tool for automated analog CMOS layout module generation and placement","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University","funders":"","keywords":"CMOS; Integrated circuit layout; IC layout editor; Design layout record; Computer science; Page layout; Process (computing); Electronic engineering; CAD; Electronic design automation; Design flow; Noise (video); Integrated circuit design; Engineering; Integrated circuit; Circuit extraction; Embedded system; Engineering drawing; Electrical engineering; Artificial intelligence","score_opus":0.016632707075611056,"score_gpt":0.2322576612603557,"score_spread":0.21562495418474464,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2131973905","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2256369,0.00012739067,0.7663597,0.000014074908,0.00007375075,0.00045821298,0.000008197034,0.002087927,0.0052338475],"genre_scores_gemma":[0.95789504,0.000012841643,0.041562032,0.000051136478,0.00002231237,0.000095595664,0.000012126976,0.000013454203,0.0003354876],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99969274,0.0000067916585,0.00008875888,0.0000769262,0.000036288784,0.00009850097],"domain_scores_gemma":[0.9998799,0.000008676896,0.0000061876876,0.000069450194,0.000015085778,0.000020693187],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000082713,0.00006521589,0.000064395936,0.000032067044,0.000028596072,0.000023952593,0.000018769237,0.000042119333,0.000038786966],"category_scores_gemma":[0.00000947522,0.00005936582,0.0000139363265,0.000036775462,0.0000043027117,0.000040105002,0.0000027384701,0.000020033665,0.0000032623407],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012197176,0.00008334942,0.0012159961,0.00022241654,0.00016056186,0.0000043007285,0.00044168922,0.072357096,0.60127586,0.038658764,0.26786077,0.017706998],"study_design_scores_gemma":[0.00019765686,0.000041608488,0.000079377045,0.000002861007,0.0000066722937,0.0000024234728,0.000007854378,0.87909985,0.11715045,0.00015204915,0.0031587454,0.00010046587],"about_ca_topic_score_codex":0.000002258376,"about_ca_topic_score_gemma":0.000004204277,"teacher_disagreement_score":0.8067427,"about_ca_system_score_codex":0.000020090556,"about_ca_system_score_gemma":0.000003988637,"threshold_uncertainty_score":0.24208678},"labels":[],"label_agreement":null},{"id":"W2132958139","doi":"10.1109/icm.2003.237880","title":"Congestion driven placement for VLSI standard cell design","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Router; Placement; Very-large-scale integration; Computer science; Interconnection; Routing (electronic design automation); Reduction (mathematics); Network routing; Integrated circuit layout; Chip; Parallel computing; Physical design; Electronic engineering; Embedded system; Integrated circuit; Circuit design; Engineering; Computer network; Mathematics; Telecommunications","score_opus":0.01860362526623188,"score_gpt":0.2198702142903698,"score_spread":0.2012665890241379,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2132958139","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010338876,0.000092688235,0.97437996,0.0000098325645,0.000093691546,0.0004889396,0.000006226217,0.00060202775,0.023292743],"genre_scores_gemma":[0.77677155,0.00005800524,0.22193114,0.000034716944,0.000020449781,0.00014952554,0.00000510835,0.000029596893,0.0009999273],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995573,0.000016799364,0.00010837001,0.000089657515,0.00007098472,0.00015687432],"domain_scores_gemma":[0.9997589,0.000059856437,0.000010075439,0.00009933745,0.000030792813,0.000041042524],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001627144,0.000091489565,0.00009227558,0.00003821797,0.000030451221,0.000020503334,0.000045775152,0.000057576955,0.0001411732],"category_scores_gemma":[0.000014647447,0.000085716114,0.00002972597,0.00004101399,0.0000074683912,0.000052234547,0.0000028125512,0.00004186207,0.000015489846],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000121072815,0.000113639464,0.00026735562,0.0003853493,0.0001136982,0.000008717425,0.00063479604,0.16814087,0.29630306,0.034702677,0.47839805,0.020810701],"study_design_scores_gemma":[0.0005236372,0.0002740459,0.000007624733,0.000011538673,0.000015669191,0.0000015859174,0.00005941385,0.017072784,0.9225801,0.0015334589,0.057714615,0.00020549116],"about_ca_topic_score_codex":6.1823704e-7,"about_ca_topic_score_gemma":8.631921e-7,"teacher_disagreement_score":0.77573764,"about_ca_system_score_codex":0.00006320724,"about_ca_system_score_gemma":0.000012319297,"threshold_uncertainty_score":0.34954017},"labels":[],"label_agreement":null},{"id":"W2133761062","doi":"10.1109/iscas.2007.378191","title":"Two Clustering Preprocessing Techniques for Large-Scale Circuits","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Preprocessor; Computer science; Benchmark (surveying); Electronic circuit; Data mining; Data pre-processing; Scale (ratio); Algorithm; Artificial intelligence; Engineering","score_opus":0.0153265288273615,"score_gpt":0.2738462145749965,"score_spread":0.258519685747635,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2133761062","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0029289231,0.00014079263,0.9201732,0.000007835348,0.00008053464,0.00033690952,0.0000039152806,0.003657423,0.07267042],"genre_scores_gemma":[0.8489698,0.0000132376,0.1502529,0.00009002239,0.00017504096,0.0000667004,0.0000049984446,0.00005400306,0.00037325203],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991137,0.0000034895381,0.00022778695,0.00017731887,0.000087517066,0.00039017908],"domain_scores_gemma":[0.99963653,0.00004380032,0.000020032036,0.00018995933,0.00004568751,0.000063998275],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005276919,0.00013936652,0.00014241938,0.00011373106,0.00007454819,0.00004539973,0.00013397716,0.00009322193,0.000028378094],"category_scores_gemma":[0.000012214958,0.00013827125,0.00005776608,0.00012594064,0.000009668572,0.00018318238,0.000027109114,0.00009484512,0.0000054591133],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012265629,0.00006443017,0.0008202693,0.0006179294,0.000037714068,0.000008785497,0.0009874149,0.00020456556,0.3871803,0.0014489001,0.004860103,0.6037573],"study_design_scores_gemma":[0.00022836907,0.00004187177,0.000115672694,0.000079217,0.000010859994,0.000015231733,0.00015122007,0.034619316,0.94645464,0.0013144626,0.016645884,0.00032322822],"about_ca_topic_score_codex":0.0000042424845,"about_ca_topic_score_gemma":0.000058566482,"teacher_disagreement_score":0.8460409,"about_ca_system_score_codex":0.000051390685,"about_ca_system_score_gemma":0.0000062804675,"threshold_uncertainty_score":0.5638538},"labels":[],"label_agreement":null},{"id":"W2133929151","doi":"10.1109/cicc.1998.695048","title":"A nonlinear programming and local improvement method for standard cell placement","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Very-large-scale integration; Placement; Standard cell; Computer science; Nonlinear system; Electronic circuit; Iterative method; Integrated circuit layout; Parallel computing; Design methods; Computer engineering; Algorithm; Mathematical optimization; Physical design; Circuit design; Integrated circuit; Embedded system; Mathematics; Engineering; Electrical engineering","score_opus":0.012776297606292947,"score_gpt":0.24872264691495968,"score_spread":0.23594634930866673,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2133929151","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010602297,0.00027700592,0.9951443,0.000034352164,0.00003622604,0.00059807574,0.000011657477,0.00048173082,0.0023564214],"genre_scores_gemma":[0.100749455,0.00007767808,0.898285,0.00006442006,0.000045218327,0.00020882463,0.000003838878,0.000030464573,0.000535106],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99943477,0.000004989113,0.0001411158,0.00012826709,0.000084564825,0.00020630112],"domain_scores_gemma":[0.9997833,0.00002903316,0.000011352873,0.00009456593,0.000022428881,0.000059352187],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015995064,0.000110245506,0.00011974153,0.000038003236,0.00003409,0.000033747954,0.000044851367,0.000048907776,0.00007989413],"category_scores_gemma":[0.0000022178222,0.00009611315,0.000031826374,0.00004177155,0.00001159195,0.00004421405,0.000017212269,0.000055658616,0.0000029328917],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011211225,0.000043288557,0.000012158738,0.00021847265,0.000025207151,0.0000017086751,0.00022135193,0.00026871279,0.016139619,0.00014522324,0.0069287457,0.9759843],"study_design_scores_gemma":[0.00054832984,0.00060129893,5.1903606e-7,0.000010521364,0.000017280154,0.000001764492,0.00017602064,0.48695388,0.39924887,0.00008156497,0.11218349,0.00017646948],"about_ca_topic_score_codex":0.000005357414,"about_ca_topic_score_gemma":0.0000032594328,"teacher_disagreement_score":0.97580785,"about_ca_system_score_codex":0.000046488658,"about_ca_system_score_gemma":0.0000023522991,"threshold_uncertainty_score":0.39193806},"labels":[],"label_agreement":null},{"id":"W2134606315","doi":"10.1109/cicc.1991.164058","title":"An efficient eigenvector-node interchange approach for finding netlist partitions","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Netlist; Heuristics; Eigenvalues and eigenvectors; Computer science; Node (physics); Partition (number theory); Benchmark (surveying); Theoretical computer science; Heuristic; Algorithm; Mathematics; Mathematical optimization; Combinatorics; Artificial intelligence","score_opus":0.0666571393386486,"score_gpt":0.2536353325695826,"score_spread":0.186978193230934,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2134606315","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011999529,0.0001429181,0.9629823,0.000017374705,0.000082556,0.00031569824,0.000024104565,0.0012802865,0.023155246],"genre_scores_gemma":[0.943924,0.000016271375,0.05538355,0.00005097694,0.00010210949,0.0002264038,0.00003335514,0.000031750722,0.00023156987],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994337,0.000009617508,0.00012320484,0.00013867549,0.00006107008,0.00023373924],"domain_scores_gemma":[0.99969286,0.000019502497,0.000009261136,0.00019062778,0.0000161125,0.00007161687],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008083281,0.000108524655,0.00010036053,0.000081842125,0.000073345414,0.00004256077,0.00011719714,0.00006222222,0.00028069064],"category_scores_gemma":[0.0000056793283,0.00010171992,0.000053679796,0.00009921183,0.000016543123,0.00006667103,0.000009224437,0.0000698619,0.000022619364],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002089766,0.0016628584,0.0010692856,0.0009525995,0.0002597099,0.000013386158,0.009684101,0.4107467,0.1400654,0.038511444,0.3194888,0.07752481],"study_design_scores_gemma":[0.000103267055,0.000053683572,0.00006701131,0.000008096725,0.000009729276,0.0000031771335,0.00008265282,0.9837398,0.012936451,0.00008680503,0.0027372888,0.00017202355],"about_ca_topic_score_codex":0.000007993912,"about_ca_topic_score_gemma":0.0000047229228,"teacher_disagreement_score":0.93192446,"about_ca_system_score_codex":0.000044756132,"about_ca_system_score_gemma":0.0000010411003,"threshold_uncertainty_score":0.4148018},"labels":[],"label_agreement":null},{"id":"W2137186724","doi":"10.1109/cmpcon.1979.729140","title":"A Parallel Array Of Microprocessors - An Alternative Solution To Diffusion Problems","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Flexibility (engineering); Diffusion; Parallel computing; Architecture; Protocol (science); Compact space; Reduction (mathematics); Scalability; Distributed computing; Embedded system; Operating system; Mathematics","score_opus":0.014677026336944716,"score_gpt":0.2346019831176603,"score_spread":0.2199249567807156,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2137186724","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.26058817,0.00006559674,0.73259115,0.000081086575,0.00002724661,0.00021787433,0.0000027951287,0.0004201253,0.006005951],"genre_scores_gemma":[0.93515146,0.00004143419,0.064426094,0.000045323017,0.000053777658,0.000029083094,0.0000036955676,0.000016206115,0.00023293543],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995173,0.000007460009,0.00014844236,0.00010458906,0.00008634909,0.00013581569],"domain_scores_gemma":[0.9997723,0.0000050191106,0.000017583674,0.00011400114,0.000034027005,0.00005706664],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006593503,0.00008843546,0.00010244279,0.00007921158,0.000018249042,0.000009194269,0.00010751699,0.0000453687,0.000053847765],"category_scores_gemma":[0.0000035794033,0.00007667506,0.000023223665,0.000092199385,0.000010427674,0.00014901283,0.000010734056,0.00005257857,0.00002179028],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000053702906,0.00005223703,0.000079322905,0.000032720378,0.000008462753,2.2755879e-7,0.0012203541,0.010724527,0.9650179,0.00023077404,0.0008310462,0.02179706],"study_design_scores_gemma":[0.00020334458,0.00016737785,0.00034452946,0.00004975144,0.000005866084,0.0000027055635,0.00005141876,0.046939217,0.9465171,0.00074380584,0.004769237,0.00020564183],"about_ca_topic_score_codex":0.00006575289,"about_ca_topic_score_gemma":0.000074995056,"teacher_disagreement_score":0.6745633,"about_ca_system_score_codex":0.000034027897,"about_ca_system_score_gemma":0.000003718532,"threshold_uncertainty_score":0.3126718},"labels":[],"label_agreement":null},{"id":"W2137381762","doi":"10.1145/1391732.1391736","title":"Perturb+mutate","year":2008,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Benchmark (surveying); Computer science; Heuristic; Electronic circuit; Locality; Constant (computer programming); Software; Measure (data warehouse); Algorithm; Artificial intelligence; Physics","score_opus":0.019475283882179516,"score_gpt":0.20685930846730663,"score_spread":0.18738402458512712,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2137381762","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.46506384,0.011875848,0.4457035,0.0013132348,0.0020549248,0.0013962347,0.00007776795,0.014971571,0.057543073],"genre_scores_gemma":[0.9956386,0.0018214746,0.00048695397,0.000026410966,0.000016266062,0.00016041938,0.0000018351849,0.000029521487,0.0018185122],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992355,0.000018034898,0.00022431984,0.00020202702,0.000069605645,0.00025049958],"domain_scores_gemma":[0.99939764,0.000056695535,0.000021783339,0.00044048272,0.000029440675,0.000053960248],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0000856986,0.0001735733,0.0002450911,0.0005040357,0.0002430459,0.000016324442,0.00020322148,0.00033444507,0.00006368518],"category_scores_gemma":[0.0000096779095,0.00016393623,0.00004276874,0.00035373893,0.00012412369,0.00010153369,0.0000012209687,0.0003652997,0.00007916773],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000120110606,0.00046663114,0.0022231701,0.0011008508,0.0013936923,0.0007432761,0.0019893653,0.020629952,0.12237196,0.019645393,0.018371345,0.81094426],"study_design_scores_gemma":[0.003506045,0.0019029395,0.00090158527,0.000889571,0.00024267526,0.015073242,0.0029487598,0.06577487,0.67140245,0.029846828,0.20369557,0.0038154798],"about_ca_topic_score_codex":0.000017348346,"about_ca_topic_score_gemma":0.0000031854017,"teacher_disagreement_score":0.8071288,"about_ca_system_score_codex":0.000031916847,"about_ca_system_score_gemma":0.0000104925875,"threshold_uncertainty_score":0.6685125},"labels":[],"label_agreement":null},{"id":"W2138206217","doi":"10.1109/fpl.2005.1515784","title":"QPF: efficient quadratic placement for FPGAs","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":50,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Benchmark (surveying); Field-programmable gate array; Quadratic equation; Computer science; Electronic circuit; Process (computing); Algorithm; Chip; Mathematical optimization; Mathematics; Embedded system; Engineering; Telecommunications; Geometry; Electrical engineering","score_opus":0.009972897050443194,"score_gpt":0.22406208376840114,"score_spread":0.21408918671795796,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2138206217","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01868008,0.00022125473,0.95150954,0.00015355229,0.000087180604,0.00042976032,0.00000353327,0.0011179142,0.027797163],"genre_scores_gemma":[0.9566281,0.000011791291,0.041833166,0.00013585258,0.00010271094,0.0001284609,0.0000038777494,0.000020864241,0.0011352206],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959004,0.0000030693104,0.00011336792,0.00007473256,0.0000631949,0.00015560459],"domain_scores_gemma":[0.99980974,0.000025599758,0.0000063502357,0.0001095006,0.000012965163,0.000035854384],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008387574,0.00007697105,0.00007446151,0.000038751303,0.000023756491,0.000015300671,0.000060041013,0.000033520602,0.0001746488],"category_scores_gemma":[0.000005049374,0.000066745706,0.000036748082,0.000039649294,0.000005601681,0.000024379464,0.0000066295243,0.00003185889,0.00007640807],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001766579,0.00017768453,0.000032457025,0.0002568641,0.000083257466,0.0000020298448,0.0008439796,0.48532662,0.053725444,0.019874552,0.2767827,0.16287674],"study_design_scores_gemma":[0.00027545769,0.0000570084,0.000017498085,0.000014618251,0.000010398967,0.000001885962,0.000040450173,0.7095678,0.20752166,0.0001498777,0.08216179,0.00018155633],"about_ca_topic_score_codex":0.0000014727174,"about_ca_topic_score_gemma":0.000004754229,"teacher_disagreement_score":0.937948,"about_ca_system_score_codex":0.000050848408,"about_ca_system_score_gemma":0.0000037214352,"threshold_uncertainty_score":0.2721811},"labels":[],"label_agreement":null},{"id":"W2138254350","doi":"","title":"A new algorithm and improved lower bound for point placement on a line in two rounds.","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Upper and lower bounds; Extension (predicate logic); Point (geometry); Algorithm; Graph; Construct (python library); Combinatorics; Line (geometry); Computer science; Mathematics; Discrete mathematics; Geometry","score_opus":0.009662615114425859,"score_gpt":0.2586199862517362,"score_spread":0.24895737113731034,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2138254350","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.027054096,0.000054478183,0.96783364,0.00015102184,0.00030558647,0.0006388542,0.0000070388323,0.0004187479,0.0035365212],"genre_scores_gemma":[0.65090144,0.000031412248,0.3459309,0.00027960163,0.00029375,0.00014555283,0.000009253011,0.000054972228,0.0023531124],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995097,0.0000025437712,0.00013420382,0.00013013477,0.000047538353,0.00017585832],"domain_scores_gemma":[0.9997459,0.000033814067,0.000009662305,0.00013165819,0.000011817614,0.00006714638],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012688595,0.000112910806,0.00011482326,0.00007244331,0.000016328224,0.000047994705,0.00005222937,0.000053085645,0.00006980283],"category_scores_gemma":[0.000009799219,0.00009807696,0.000025053156,0.000047271675,0.0000078887,0.00007107923,0.000014329828,0.00014488837,0.0000037029263],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010602412,0.00014902113,0.000052219002,0.00007264844,0.000052115076,0.000010666689,0.000386776,0.00023030171,0.22765099,0.0033003376,0.019810481,0.7481784],"study_design_scores_gemma":[0.0041392003,0.0010994641,0.000131238,0.00004929987,0.000017793145,0.000013941053,0.000056357476,0.77079916,0.1853956,0.007963021,0.029728837,0.0006060805],"about_ca_topic_score_codex":0.00015392822,"about_ca_topic_score_gemma":0.0004226203,"teacher_disagreement_score":0.77056885,"about_ca_system_score_codex":0.000028390368,"about_ca_system_score_gemma":0.000012770729,"threshold_uncertainty_score":0.39994624},"labels":[],"label_agreement":null},{"id":"W2138616176","doi":"10.1109/mwscas.2002.1187288","title":"Empirical performance prediction for IFFT/FFT cores for OFDM systems-on-a-chip","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Fast Fourier transform; Orthogonal frequency-division multiplexing; Chip; Metric (unit); System on a chip; Design flow; CMOS; Implementation; Performance metric; Electronic engineering; Embedded system; Channel (broadcasting); Algorithm; Engineering; Telecommunications","score_opus":0.03659533878385981,"score_gpt":0.26071284155119523,"score_spread":0.2241175027673354,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2138616176","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07613111,0.00021465708,0.8951037,0.000024530344,0.00077963027,0.0015187594,0.00006638133,0.0016707617,0.024490483],"genre_scores_gemma":[0.9904818,0.000042241183,0.007313002,0.00006187046,0.00014709638,0.0006165692,0.000017247674,0.00004026913,0.001279921],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993494,0.000009932399,0.00019307912,0.00013839643,0.00008626515,0.00022290541],"domain_scores_gemma":[0.9996256,0.00010823633,0.000016986187,0.00015413154,0.000044111952,0.00005093274],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018145912,0.00012787584,0.0001464941,0.00006799683,0.000068626774,0.00003217141,0.00006950359,0.00011023288,0.000015672851],"category_scores_gemma":[0.00003837624,0.00010811051,0.00006165893,0.0000630185,0.000011648948,0.0000986939,0.0000030068604,0.00006554734,0.000010424245],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00021047183,0.00023083448,0.01967201,0.0030224044,0.00024319728,0.0000017842625,0.00047620782,0.020797685,0.017253557,0.044606928,0.8797955,0.013689457],"study_design_scores_gemma":[0.0010314608,0.0011182753,0.0016342923,0.0001187088,0.00004135786,0.000017205373,0.00007899151,0.698638,0.07275466,0.0007754566,0.22335671,0.0004348298],"about_ca_topic_score_codex":0.000001130571,"about_ca_topic_score_gemma":6.73006e-7,"teacher_disagreement_score":0.9143507,"about_ca_system_score_codex":0.000047391382,"about_ca_system_score_gemma":0.000010534135,"threshold_uncertainty_score":0.44086185},"labels":[],"label_agreement":null},{"id":"W2138840350","doi":"10.1109/fpt.2004.1393249","title":"Directional and single-driver wires in FPGA interconnect","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":242,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Interconnection; Capacitance; Computer science; Electronic circuit; Embedded system; Electronic engineering; Electrical engineering; Engineering; Telecommunications; Physics","score_opus":0.009816520485855242,"score_gpt":0.19377983564139512,"score_spread":0.18396331515553987,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2138840350","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8288995,0.00095532293,0.040277958,0.00023020979,0.00012744506,0.00013997096,0.0000023729635,0.0014909066,0.1278763],"genre_scores_gemma":[0.9940059,0.00006639981,0.0055031166,0.000058424816,0.000054835356,0.0000067093047,7.559052e-7,0.0000093777935,0.00029446406],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997332,0.000005274013,0.00007526871,0.000067519184,0.000034111177,0.00008463593],"domain_scores_gemma":[0.9999032,0.00002307586,0.0000033468968,0.00004425015,0.0000051116713,0.00002102998],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003611766,0.000057426907,0.000060353625,0.00007420057,0.000008965036,0.000014143202,0.000029175657,0.000036035784,0.00016013789],"category_scores_gemma":[0.000005205162,0.000053266245,0.000012101296,0.000049034148,0.000012933587,0.000116608244,0.000010413917,0.00005632877,0.0000140680895],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000074074537,0.00006821834,0.005121606,0.000030467112,0.000025518548,0.000009338426,0.0005980478,0.0011135505,0.15497321,0.0017111277,0.012414935,0.82392657],"study_design_scores_gemma":[0.0006208016,0.00012104658,0.016553702,0.00009563739,0.000008870604,0.000062909385,0.00009871532,0.057984706,0.803653,0.0017507749,0.11844501,0.00060484814],"about_ca_topic_score_codex":0.000016818944,"about_ca_topic_score_gemma":0.00016667355,"teacher_disagreement_score":0.8233217,"about_ca_system_score_codex":0.000034575096,"about_ca_system_score_gemma":0.0000014298422,"threshold_uncertainty_score":0.21721345},"labels":[],"label_agreement":null},{"id":"W2139478143","doi":"10.5555/832284.835430","title":"Probabilistic Analysis of Rectilinear Steiner Trees","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Probabilistic logic; Very-large-scale integration; Computer science; Set (abstract data type); Tree (set theory); Interconnection; Algorithm; Mathematical optimization; Theoretical computer science; Mathematics; Combinatorics; Artificial intelligence; Programming language","score_opus":0.018787917547615073,"score_gpt":0.20509535678153984,"score_spread":0.18630743923392476,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2139478143","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.52475584,0.0011602901,0.110110566,0.00006316651,0.000132475,0.00041845153,0.000025696361,0.0031768398,0.3601567],"genre_scores_gemma":[0.99581146,0.00004895706,0.0027465955,0.000007750947,0.000012871489,0.000008181671,0.0000022224524,0.000009771645,0.0013521723],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99962187,0.0000075609505,0.00014628265,0.000071321316,0.00006850656,0.000084453015],"domain_scores_gemma":[0.99974155,0.000028623755,0.0000109888315,0.00017224609,0.00002318113,0.0000234233],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00004720329,0.000064172724,0.00016589332,0.00018626386,0.0000073833453,0.000005590421,0.00006364967,0.00003896434,0.0012061424],"category_scores_gemma":[0.000016150025,0.00005266375,0.00008025832,0.0005785957,0.0000146299635,0.000035611334,0.000005677449,0.00003892766,0.000014324242],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018396726,0.00071941945,0.01696886,0.0005370844,0.008093533,0.000030052126,0.0026119172,0.31500697,0.17464365,0.011457945,0.11633007,0.35358208],"study_design_scores_gemma":[0.000064783526,0.0000440394,0.0019319151,0.0000059589634,0.00034812652,6.39519e-7,0.00001627037,0.9703968,0.024884721,0.00013136254,0.0020427946,0.00013254878],"about_ca_topic_score_codex":0.000014909499,"about_ca_topic_score_gemma":0.000043066422,"teacher_disagreement_score":0.65538985,"about_ca_system_score_codex":0.0000122129495,"about_ca_system_score_gemma":6.956386e-7,"threshold_uncertainty_score":0.99970686},"labels":[],"label_agreement":null},{"id":"W2139577649","doi":"10.1109/ccece.2009.5090314","title":"Performance-constrained parasitic-aware retargeting and optimization of analog layouts","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Retargeting; Parasitic extraction; Computer science; Analogue electronics; Set (abstract data type); Graph; Sensitivity (control systems); Electronic circuit; Electronic engineering; Theoretical computer science; Engineering; Artificial intelligence; Electrical engineering","score_opus":0.007444330700417906,"score_gpt":0.20158416211867478,"score_spread":0.19413983141825686,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2139577649","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.44029725,0.00014197084,0.5195733,0.00004692859,0.000032559667,0.00016345663,0.000004304507,0.0007978158,0.038942438],"genre_scores_gemma":[0.9693275,0.000110438705,0.03048793,0.00002311424,0.000013629521,0.0000013511897,0.0000072959538,0.000006032587,0.000022715118],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99966085,0.000005170612,0.00012877645,0.000061536564,0.00004786352,0.0000958136],"domain_scores_gemma":[0.9998613,0.000010145131,0.000014714638,0.00006516133,0.000022290107,0.000026395744],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006796804,0.00006658356,0.00009772517,0.000054117158,0.000019644714,0.000008240071,0.0000333072,0.00004686338,0.00004450229],"category_scores_gemma":[0.000005695343,0.000061705665,0.000014392218,0.00007516856,0.000015460715,0.00009896367,0.000002279699,0.000042800533,7.3758326e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020852744,0.00005929328,0.020311136,0.00033786296,0.00006364766,0.000009656733,0.0008609106,0.700903,0.08516988,0.0016972072,0.0013577074,0.18920888],"study_design_scores_gemma":[0.0000995202,0.00009051863,0.003731613,0.000034315046,0.00000944832,0.000006516537,0.000031766343,0.93901217,0.05679525,0.00006368531,0.000013097777,0.000112102774],"about_ca_topic_score_codex":0.0000013985464,"about_ca_topic_score_gemma":2.519355e-7,"teacher_disagreement_score":0.52903026,"about_ca_system_score_codex":0.000006886949,"about_ca_system_score_gemma":0.000003439683,"threshold_uncertainty_score":0.2516284},"labels":[],"label_agreement":null},{"id":"W2141752451","doi":"10.1145/1216919.1216946","title":"GlitchLess","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Routing (electronic design automation); Lookup table; Computer science; Filter (signal processing); Path (computing); Critical path method; Embedded system; Power (physics); Place and route; Logic synthesis; Logic gate; Computer hardware; Computer network; Engineering; Algorithm","score_opus":0.005216985359612056,"score_gpt":0.19906182191740326,"score_spread":0.19384483655779122,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2141752451","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018747512,0.000055090706,0.62485075,0.0000046812725,0.00005505983,0.000023347771,1.6863437e-7,0.0011832698,0.3550801],"genre_scores_gemma":[0.9944404,0.000007492653,0.005012351,0.000037007194,0.000036576403,0.0000010135566,3.8485652e-7,0.000007519347,0.0004572949],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9998045,6.997526e-7,0.000047876776,0.000027460665,0.000030068886,0.00008941007],"domain_scores_gemma":[0.9998996,0.000008976055,0.0000014468966,0.00006187086,0.000004829304,0.000023224991],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000083079416,0.000030654126,0.000029079949,0.000024708434,0.0000069356593,0.000004726288,0.00003701596,0.000025385085,0.00010058591],"category_scores_gemma":[0.0000013428556,0.000027032615,0.000011211188,0.00004406733,0.0000039166102,0.000026948708,0.0000033403846,0.000031880212,0.000059947313],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000035961095,0.000020969785,0.0018476492,0.000045058012,0.000024098563,0.000040806142,0.00023529076,0.000109486005,0.18702368,0.05164107,0.06943889,0.6895694],"study_design_scores_gemma":[0.00008087512,0.000011868992,0.0029360356,0.000005729468,0.0000024773285,0.00000825097,0.00004943548,0.0033850141,0.914852,0.0025640442,0.07591974,0.00018449216],"about_ca_topic_score_codex":0.0000027466187,"about_ca_topic_score_gemma":0.000004614773,"teacher_disagreement_score":0.97569287,"about_ca_system_score_codex":0.000008939768,"about_ca_system_score_gemma":6.558592e-7,"threshold_uncertainty_score":0.1102358},"labels":[],"label_agreement":null},{"id":"W2141988600","doi":"10.1109/tcad.2015.2440316","title":"Robust Optimization of Multiple Timing Constraints","year":2015,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; Texas Instruments; Semiconductor Research Corporation","keywords":"Static timing analysis; Computer science; Field-programmable gate array; Electronic circuit; Clock skew; Digital clock manager; Extension (predicate logic); Clock network; Design flow; Computer engineering; Electronic engineering; Clock signal; Computer hardware; Embedded system; Engineering; Electrical engineering","score_opus":0.0778516902545223,"score_gpt":0.22629956962115338,"score_spread":0.1484478793666311,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2141988600","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030475243,0.00019642015,0.9949496,0.0000024175893,0.00068361283,0.00048526944,0.000057352067,0.00033141678,0.00024642723],"genre_scores_gemma":[0.97726583,0.00007092011,0.022536624,0.0000056730137,0.000027958527,0.000031180374,0.000006604501,0.000035771456,0.000019408877],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986889,0.0001272224,0.0005857891,0.00020421056,0.0002076094,0.00018629333],"domain_scores_gemma":[0.99906045,0.00018235536,0.00011496883,0.00021014146,0.00030727687,0.00012478972],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00037100157,0.00022933957,0.00044069602,0.00031183302,0.000044530843,0.000041997075,0.00013508434,0.00018012739,0.00001034822],"category_scores_gemma":[0.000008159916,0.00021161605,0.00006496349,0.00029346542,0.00010126554,0.00015259304,7.675481e-7,0.0001883572,0.0000021125388],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012481474,0.00006111802,0.000008144744,0.00010978065,0.00009122512,0.0000037244401,0.00030037446,0.9632809,0.00946013,0.00003822685,0.00024863752,0.026385235],"study_design_scores_gemma":[0.0005682894,0.00033197532,0.000002869575,0.000398046,0.000033412845,0.000046379548,0.00024082242,0.9522366,0.045924712,0.000011664712,0.000015920234,0.00018933893],"about_ca_topic_score_codex":0.0000876644,"about_ca_topic_score_gemma":0.0000017185213,"teacher_disagreement_score":0.9742183,"about_ca_system_score_codex":0.00007387528,"about_ca_system_score_gemma":0.00006280581,"threshold_uncertainty_score":0.8629452},"labels":[],"label_agreement":null},{"id":"W2142002524","doi":"10.1145/2145694.2145711","title":"Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Noise (video); Algorithm; Computer science; CAD; Electronic circuit; Field-programmable gate array; Power (physics); Heuristic; Electronic engineering; Electronic design automation; Electrical engineering; Computer hardware; Engineering; Artificial intelligence; Embedded system","score_opus":0.009027414032915976,"score_gpt":0.23415769024501226,"score_spread":0.22513027621209628,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142002524","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.98762614,0.00045665,0.0048671598,0.0000062438057,0.00003083508,0.00009100439,0.0000044849185,0.0001392182,0.0067782863],"genre_scores_gemma":[0.9986562,0.0001789249,0.0010618469,0.0000056807953,0.000043018823,0.0000015744412,6.297013e-7,0.000012460325,0.000039674884],"study_design_codex":"observational","study_design_gemma":"observational","domain_scores_codex":[0.99961627,0.000008343831,0.00010146486,0.000055375833,0.00005513116,0.00016340346],"domain_scores_gemma":[0.9997804,0.000036666737,0.000017786579,0.00010217914,0.000011718239,0.00005120506],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001893718,0.00009064215,0.00010010138,0.0000501053,0.000038687253,0.000014331595,0.00004115067,0.00003952038,0.000022587737],"category_scores_gemma":[0.000007717351,0.000054049066,0.000024841927,0.000070188966,0.000031416475,0.00015917057,0.000017951184,0.00009771314,0.0000012793906],"study_design_candidate":"observational","study_design_consensus":"observational","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019014657,0.0000699524,0.61660904,0.00014003705,0.0002698278,0.0000017769004,0.004603262,0.0016062612,0.0476472,0.00014782237,0.0028927482,0.32599306],"study_design_scores_gemma":[0.00028770542,0.0002787648,0.60616314,0.000092863425,0.000034787197,0.000034712193,0.00021839821,0.31259212,0.0798832,0.000035605226,0.000104379294,0.0002743209],"about_ca_topic_score_codex":0.000045844314,"about_ca_topic_score_gemma":3.5783972e-7,"teacher_disagreement_score":0.32571876,"about_ca_system_score_codex":0.000016187727,"about_ca_system_score_gemma":0.0000026797072,"threshold_uncertainty_score":0.2204057},"labels":[],"label_agreement":null},{"id":"W2142395333","doi":"10.1109/fpl.2006.311357","title":"Architecture and CAD for FPGA Clock Networks","year":2006,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Digital clock manager; Clock network; Clock skew; Computer science; Clock gating; Embedded system; Skew; Process (computing); CAD; CPU multiplier; FPGA prototype; Computer hardware; Computer architecture; Clock signal; Engineering; Jitter; Telecommunications; Operating system","score_opus":0.003657012666872999,"score_gpt":0.17736353855774792,"score_spread":0.17370652589087493,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142395333","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005782756,0.00079199404,0.97728086,0.00003934707,0.00004823551,0.00016365189,0.0000033498181,0.00069919426,0.015190609],"genre_scores_gemma":[0.98075014,0.000031704974,0.018137468,0.000054546937,0.00020447368,0.000033010714,0.000007241807,0.00002079393,0.0007606334],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99971086,0.0000023197463,0.000066917695,0.00006713225,0.000024180323,0.00012857564],"domain_scores_gemma":[0.99987674,0.000024662118,0.0000045657584,0.00006647825,0.000006836159,0.000020708902],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000031816857,0.00006941608,0.00006844031,0.000025226884,0.00002203249,0.000016906899,0.000034094784,0.00006399429,0.00001015183],"category_scores_gemma":[0.000001520759,0.000058522703,0.000021252275,0.000033582543,0.00000934613,0.000019544588,0.0000060895045,0.000058065518,8.569469e-7],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019041096,0.000030989224,0.001413678,0.00021148272,0.000050819912,0.0000076514325,0.000100091216,0.15886126,0.012728757,0.03258647,0.40002033,0.39396942],"study_design_scores_gemma":[0.0008322273,0.00017920158,0.0045485278,0.000043315715,0.000040656047,0.000048270344,0.000019471792,0.5121269,0.06475097,0.044323903,0.3722092,0.00087736704],"about_ca_topic_score_codex":0.0000210819,"about_ca_topic_score_gemma":0.000031178377,"teacher_disagreement_score":0.97496736,"about_ca_system_score_codex":0.000006208154,"about_ca_system_score_gemma":0.0000011516753,"threshold_uncertainty_score":0.23864865},"labels":[],"label_agreement":null},{"id":"W2142424442","doi":"10.1109/icvd.1994.282671","title":"A new genetic algorithm for the channel routing problem","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Routing (electronic design automation); Genetic algorithm; Channel (broadcasting); Algorithm; Computer network; Machine learning","score_opus":0.018886702047897445,"score_gpt":0.1999399463439825,"score_spread":0.18105324429608505,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142424442","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000014869245,0.00086758554,0.98946697,0.00011588626,0.000063585,0.00034505114,0.0000015050972,0.0007142603,0.008410263],"genre_scores_gemma":[0.11442313,0.0002858216,0.87679154,0.00016117387,0.00048488923,0.00018872267,0.0000011072344,0.000061093575,0.007602539],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995984,0.00000279486,0.00009702813,0.00007459245,0.000049765742,0.00017744336],"domain_scores_gemma":[0.9997899,0.000040305917,0.00000805784,0.000116713214,0.0000108516015,0.00003415887],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004874953,0.00007885961,0.000064125445,0.000020605432,0.000054604276,0.00002996224,0.00011053292,0.000039555198,0.00014248535],"category_scores_gemma":[0.0000029162836,0.00005348902,0.000040667626,0.000067536894,0.000004751736,0.00003419446,0.000010398294,0.000052487605,0.00002709999],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[1.1929782e-7,0.0000031428685,0.0000019545832,0.0000085415295,0.000015920223,5.670119e-7,0.00020436522,0.0007756148,0.00026359782,0.0001898497,0.050138336,0.948398],"study_design_scores_gemma":[0.00010487756,0.000025605243,0.000020169793,0.000008197343,0.000009889937,0.000006482858,0.000023298866,0.98281974,0.0045496924,0.001098799,0.011233619,0.00009963828],"about_ca_topic_score_codex":0.00002280656,"about_ca_topic_score_gemma":0.0000025006234,"teacher_disagreement_score":0.9820441,"about_ca_system_score_codex":0.0000128036,"about_ca_system_score_gemma":0.0000019954903,"threshold_uncertainty_score":0.21812189},"labels":[],"label_agreement":null},{"id":"W2142533150","doi":"10.1109/tvlsi.2008.2005307","title":"Total Power Modeling in FPGAs Under Spatial Correlation","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Field-programmable gate array; Dissipation; Independence (probability theory); Power (physics); Computer science; Spatial correlation; Dynamic demand; Logic gate; Dependency (UML); Routing (electronic design automation); Electronic engineering; Algorithm; Engineering; Embedded system; Mathematics; Artificial intelligence; Statistics; Physics; Telecommunications","score_opus":0.012394807424171522,"score_gpt":0.21833918065804933,"score_spread":0.20594437323387782,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142533150","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08291871,0.00010408523,0.91210145,0.000042279386,0.0017033475,0.00048689422,0.000042651474,0.0007382167,0.0018623429],"genre_scores_gemma":[0.9989871,0.000034187426,0.00036880083,0.000048325408,0.00009297097,0.00008375788,0.000024977942,0.000042741893,0.0003171294],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983476,0.00008845399,0.00059958425,0.00029878927,0.0003203452,0.00034526235],"domain_scores_gemma":[0.9994457,0.00004008071,0.000049492635,0.00028765743,0.000088530585,0.00008856824],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002768009,0.00029162815,0.00030369594,0.00043316482,0.00012680762,0.00011054812,0.00011425414,0.0003207754,0.000075292126],"category_scores_gemma":[0.0000035088988,0.00029335628,0.00014159737,0.00034767966,0.000014281293,0.0005252634,5.247291e-7,0.00052538887,0.00008618672],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000032899046,0.00014095036,0.000007885626,0.000014454723,0.000017290125,0.0000039511647,0.0005996638,0.98518497,0.008090968,0.00019545846,0.00017321901,0.005538309],"study_design_scores_gemma":[0.00045482803,0.00014342155,0.00009178829,0.00020807474,0.000017546114,0.00002378131,0.0005646265,0.98798585,0.0099865245,0.00015804087,0.00005825881,0.00030723293],"about_ca_topic_score_codex":0.00017541884,"about_ca_topic_score_gemma":0.0003624537,"teacher_disagreement_score":0.9160684,"about_ca_system_score_codex":0.0003511896,"about_ca_system_score_gemma":0.000027249245,"threshold_uncertainty_score":0.99995184},"labels":[],"label_agreement":null},{"id":"W2142611170","doi":"10.1109/ccece.2009.5090269","title":"Artificial neural network application in analog layout placement design","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Computer science; Artificial neural network; Computer architecture; Artificial intelligence","score_opus":0.02002633953648071,"score_gpt":0.2340297920642609,"score_spread":0.2140034525277802,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142611170","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013084891,0.0000865075,0.9777355,0.00007496307,0.000044435194,0.00032218036,4.1320925e-7,0.0006897394,0.007961366],"genre_scores_gemma":[0.9909648,0.000010177872,0.008685716,0.00014984996,0.000110831395,0.00003392576,0.0000055906644,0.000008675123,0.000030440118],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99946105,0.000016759084,0.0001666772,0.00009988568,0.00006519362,0.0001904392],"domain_scores_gemma":[0.99981785,0.000016635007,0.000010394833,0.00011863846,0.000006944814,0.000029546116],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001553375,0.00008464456,0.00008949675,0.00005206948,0.00001860546,0.000017182047,0.00007327206,0.0000553288,0.000023587454],"category_scores_gemma":[0.0000022716522,0.00008230491,0.000018734827,0.0001789578,0.0000050688113,0.000056306715,0.0000032079324,0.00008193082,0.000023654773],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013227279,0.000026614129,0.0004041626,0.0000035196708,0.0000037766172,0.0000035097316,0.000055641416,0.8714717,0.010760855,0.002996777,0.009174508,0.10508569],"study_design_scores_gemma":[0.00008018234,0.00009934612,0.0031392353,0.0000074704208,0.000004697794,0.0000018889045,0.000012381166,0.96881384,0.018384777,0.0087103415,0.00054733956,0.00019849975],"about_ca_topic_score_codex":0.000008329737,"about_ca_topic_score_gemma":0.000018838848,"teacher_disagreement_score":0.9778799,"about_ca_system_score_codex":0.00004041766,"about_ca_system_score_gemma":0.00000342837,"threshold_uncertainty_score":0.3356297},"labels":[],"label_agreement":null},{"id":"W2142756199","doi":"10.1007/978-3-642-03685-9_1","title":"Approximation Algorithms and Hardness Results for Packing Element-Disjoint Steiner Trees in Planar Graphs","year":2009,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Combinatorics; Disjoint sets; Planar graph; Approximation algorithm; Discrete mathematics; Mathematics; Cardinality (data modeling); Computer science; Graph; Algorithm","score_opus":0.017948463206996036,"score_gpt":0.23337833848091166,"score_spread":0.21542987527391563,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142756199","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00016408584,0.00044814916,0.99727523,0.00009238791,0.0002902114,0.00060429494,0.00002973684,0.00020294181,0.0008929682],"genre_scores_gemma":[0.35670444,0.0003361892,0.6418159,0.0003247225,0.00041657465,0.0000714114,0.00010494108,0.000086822765,0.0001389873],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99842757,0.000009057695,0.00040792188,0.0005393024,0.00027095436,0.00034521578],"domain_scores_gemma":[0.9994057,0.00011417564,0.00008237547,0.00029071994,0.00005182358,0.000055204902],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005436782,0.00031460598,0.0003400143,0.00066417636,0.00006439167,0.00013900555,0.00032375014,0.00021877671,0.0000010941104],"category_scores_gemma":[0.000026773727,0.00029109864,0.000050079314,0.00019349185,0.00011976434,0.0002076218,0.000046990455,0.00031135135,5.7865265e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013065359,0.000009767977,0.000016625654,0.000078507896,0.0000072369394,0.000013911215,0.0005660691,0.01758033,0.00091466564,0.0014489448,0.000071799725,0.9792791],"study_design_scores_gemma":[0.0006960762,0.00023357783,0.00027923417,0.0008215357,0.000010733097,0.000016668368,7.7011316e-7,0.8357116,0.007860064,0.15256912,0.0011419092,0.0006587118],"about_ca_topic_score_codex":0.000009248876,"about_ca_topic_score_gemma":0.00010275251,"teacher_disagreement_score":0.97862035,"about_ca_system_score_codex":0.00012678248,"about_ca_system_score_gemma":0.000029535782,"threshold_uncertainty_score":0.9999541},"labels":[],"label_agreement":null},{"id":"W2142966647","doi":"10.5555/1129601.1129691","title":"Timing-aware power noise reduction in layout","year":2005,"lang":"en","type":"article","venue":"International Conference on Computer Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Apache (Canada)","funders":"","keywords":"Noise (video); Computer science; Reduction (mathematics); Noise reduction; Power (physics); Electronic engineering; Dynamic demand; Sizing; Engineering; Artificial intelligence; Mathematics","score_opus":0.057599402202576026,"score_gpt":0.2777333425474824,"score_spread":0.22013394034490635,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2142966647","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0129627,0.000017890778,0.97303814,0.00052226346,0.0007132966,0.00022856958,0.000006702418,0.0005810242,0.011929408],"genre_scores_gemma":[0.9697244,0.000026136051,0.029536828,0.0001624624,0.00028960168,0.000035894493,0.000012549205,0.000024496927,0.00018762334],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990453,0.00004183895,0.0002688163,0.00022975287,0.00022799977,0.00018627624],"domain_scores_gemma":[0.9996043,0.000039174218,0.000033891723,0.00017012745,0.00009923311,0.00005330332],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015705486,0.00017571321,0.00014463282,0.00028643027,0.000022073787,0.0000942242,0.00030536763,0.000094999625,0.0003593601],"category_scores_gemma":[0.0000060585535,0.0001843476,0.000045668025,0.00009564004,0.000021225687,0.00026969644,0.000027856087,0.00022445766,0.00021862178],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00023792486,0.00045920524,0.0003424539,0.00003441929,0.00019332621,0.00012083926,0.0024198303,0.45596465,0.047001854,0.044641074,0.07442714,0.37415728],"study_design_scores_gemma":[0.0004004744,0.00012508986,0.0006024709,0.00013745406,0.0000033400336,0.000031036634,0.000020013453,0.97442734,0.0198662,0.0020953775,0.0019888494,0.0003023341],"about_ca_topic_score_codex":0.0000074858103,"about_ca_topic_score_gemma":0.0000025562122,"teacher_disagreement_score":0.9567617,"about_ca_system_score_codex":0.00017732693,"about_ca_system_score_gemma":0.000026066034,"threshold_uncertainty_score":0.7517477},"labels":[],"label_agreement":null},{"id":"W2143172342","doi":"10.1155/2013/751030","title":"Mesh Partitioning Algorithm Based on Parallel Finite Element Analysis and Its Actualization","year":2013,"lang":"en","type":"article","venue":"Mathematical Problems in Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"National Key Research and Development Program of China; Fonds Spéciaux de Recherche; China Institute of Water Resources and Hydropower Research; National Natural Science Foundation of China","keywords":"Computer science; Graph partition; Parallel computing; Graph; Preprocessor; Software; Finite element method; Domain decomposition methods; Key (lock); Algorithm; Decomposition; Theoretical computer science; Programming language; Engineering","score_opus":0.010271315962459305,"score_gpt":0.20675619929368114,"score_spread":0.19648488333122183,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2143172342","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019800544,0.00006647007,0.99656504,0.00002539155,0.0000185484,0.00037278002,0.0000028304837,0.00044542513,0.0005234759],"genre_scores_gemma":[0.94466907,0.000029792383,0.054837678,0.000023311291,0.000016115262,0.00036223343,0.00001535173,0.000032728218,0.000013737084],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99908245,0.000012720704,0.00033039885,0.00015930175,0.00015820381,0.000256917],"domain_scores_gemma":[0.9995913,0.00015039174,0.000021560349,0.00014088243,0.000021821048,0.00007406372],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020046056,0.00017650897,0.00024630263,0.00033791075,0.000023111681,0.00006407476,0.000073376825,0.00008241381,0.0001956259],"category_scores_gemma":[0.000061435225,0.00016973546,0.000047730944,0.00043426303,0.0000071881,0.00014611069,0.000016499913,0.00014673198,0.0000294358],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[2.2333933e-7,0.000026817037,0.00006519859,0.00025671965,0.000043230542,0.0000012100995,0.00013175923,0.9956085,0.0005318915,0.0011978798,0.000033060856,0.002103494],"study_design_scores_gemma":[0.00014540843,0.000026044025,0.00016159116,0.00016144449,0.000035476412,5.741357e-7,0.0000073926813,0.99508804,0.0012312366,0.0029274959,0.000024814748,0.00019045574],"about_ca_topic_score_codex":0.0000034556465,"about_ca_topic_score_gemma":0.0000010662861,"teacher_disagreement_score":0.942689,"about_ca_system_score_codex":0.00005368913,"about_ca_system_score_gemma":0.0000026760256,"threshold_uncertainty_score":0.6921611},"labels":[],"label_agreement":null},{"id":"W2144655684","doi":"10.1109/fpl.2011.67","title":"Reducing FPGA Router Run-Time through Algorithm and Architecture","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Router; Pathfinder; Algorithm; Overhead (engineering); Parallel computing; Reduction (mathematics); Multipath routing; Static routing; Embedded system; Computer network; Routing protocol; Mathematics","score_opus":0.013153260713161564,"score_gpt":0.1949060365368834,"score_spread":0.18175277582372185,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2144655684","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005380868,0.00030683467,0.8608525,0.00002505784,0.000081657556,0.00013760272,0.0000045720667,0.0014712923,0.13173963],"genre_scores_gemma":[0.18302663,0.00010697398,0.8146722,0.0001642271,0.00015473194,0.000021304058,0.000004634192,0.00006111492,0.0017882326],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99950105,0.000008774726,0.000110754,0.00013686763,0.000058306,0.00018423381],"domain_scores_gemma":[0.9997593,0.000011500932,0.000008885783,0.00016650691,0.000009845655,0.000043930027],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000053185002,0.00012802747,0.000123141,0.000040340474,0.000030063406,0.000019697814,0.00008044716,0.00008338077,0.000399626],"category_scores_gemma":[0.0000025607478,0.000105977764,0.000029335159,0.000061021554,0.000025371792,0.00012233912,0.000027515242,0.000128713,0.000047556507],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000045651695,0.000027260832,0.000045993947,0.000056917168,0.000079740035,0.000032858075,0.0061744,0.00006640739,0.021879967,0.00059013633,0.014930449,0.9561113],"study_design_scores_gemma":[0.00061597896,0.0002849754,0.0012821058,0.00015109,0.00006932945,0.00029921028,0.00015894638,0.03226677,0.89406145,0.031432156,0.037973702,0.0014042772],"about_ca_topic_score_codex":0.00006804802,"about_ca_topic_score_gemma":0.0000010044689,"teacher_disagreement_score":0.954707,"about_ca_system_score_codex":0.000011368729,"about_ca_system_score_gemma":0.0000029337205,"threshold_uncertainty_score":0.43756244},"labels":[],"label_agreement":null},{"id":"W2144723702","doi":"10.1109/ccece.2003.1225998","title":"A heuristic for the POP topological optimization problem in IP networks","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Router; Heuristic; Computer science; Topology (electrical circuits); Port (circuit theory); Interface (matter); Network topology; Computer network; Distributed computing; Mathematics; Engineering; Combinatorics; Parallel computing","score_opus":0.010972568796258375,"score_gpt":0.2140575910034498,"score_spread":0.2030850222071914,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2144723702","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00026003228,0.00017356807,0.995683,0.0001725304,0.000040158036,0.00035956502,5.139758e-7,0.00035738025,0.0029532148],"genre_scores_gemma":[0.9063243,0.00010269515,0.09322816,0.00008698124,0.00004556653,0.00014238125,0.0000033636336,0.0000105753625,0.00005594938],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996814,0.000004664322,0.00009835129,0.000061823775,0.000028784349,0.00012498192],"domain_scores_gemma":[0.9998491,0.00005007292,0.000006168175,0.00007125836,0.00000937801,0.000014018227],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000088545305,0.00005675916,0.000060646336,0.000020893605,0.00002499148,0.000016568509,0.00007047664,0.0000627337,0.000027746557],"category_scores_gemma":[0.000011638339,0.00003600243,0.000020917658,0.000086136446,0.000012134857,0.000032430406,0.0000072703892,0.00006866019,0.0000013054771],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000022209736,0.000007552057,0.000021178965,0.000005875365,0.0000026786872,7.8300036e-7,0.000024969551,0.987872,0.000012628898,0.009492256,0.00034210496,0.0022157722],"study_design_scores_gemma":[0.00020413553,0.000045869856,0.0001363335,0.000012046949,0.0000045814927,0.0000030117042,0.000019866662,0.9910692,0.00027199002,0.007909361,0.00024475844,0.00007883636],"about_ca_topic_score_codex":0.000017387641,"about_ca_topic_score_gemma":0.000014048232,"teacher_disagreement_score":0.9060643,"about_ca_system_score_codex":0.00003194239,"about_ca_system_score_gemma":0.000003592402,"threshold_uncertainty_score":0.14681366},"labels":[],"label_agreement":null},{"id":"W2145101332","doi":"10.1109/fpt.2009.5377654","title":"Area, delay, power, and cost trends for metal-programmable structured ASICs (MPSAs)","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Application-specific integrated circuit; Field-programmable gate array; Computer science; Process (computing); Key (lock); Integrated circuit; Embedded system; Power (physics)","score_opus":0.013914197401761358,"score_gpt":0.2407055842805286,"score_spread":0.22679138687876724,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2145101332","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.031681128,0.0022289278,0.859858,0.0002651626,0.00031255887,0.0010587017,0.000085107094,0.0041683116,0.10034215],"genre_scores_gemma":[0.95837003,0.00006799877,0.040067036,0.00011240817,0.000031205247,0.000040027167,0.000029426577,0.000025626478,0.0012562602],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9993715,0.000004492779,0.00014419244,0.0001470528,0.00007411801,0.00025859938],"domain_scores_gemma":[0.9996901,0.000019248615,0.000014984388,0.00016661145,0.00002651003,0.000082541206],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000073757656,0.00015925565,0.00018157117,0.00009094332,0.000045091714,0.000060805603,0.00008755508,0.00010618652,0.00010026081],"category_scores_gemma":[0.0000068277154,0.00013749435,0.00006216687,0.00013676728,0.000015747552,0.00012289512,0.000008270936,0.00007979535,0.0000014460567],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017398557,0.000025477277,0.00005663551,0.000019590156,0.00007146227,0.0000073849283,0.00009552556,0.00017399258,0.013454727,0.008226097,0.032350082,0.9455016],"study_design_scores_gemma":[0.003098048,0.0017333442,0.002566227,0.00004748903,0.0002661609,0.00017304768,0.00015119641,0.098945044,0.23847762,0.05076722,0.60180265,0.0019719654],"about_ca_topic_score_codex":0.0000055258743,"about_ca_topic_score_gemma":0.000014609552,"teacher_disagreement_score":0.94352967,"about_ca_system_score_codex":0.000021212196,"about_ca_system_score_gemma":0.0000040678174,"threshold_uncertainty_score":0.5606857},"labels":[],"label_agreement":null},{"id":"W2146888824","doi":"10.1109/ecctd.2007.4529654","title":"Clustering algorithms for circuit partitioning and placement problems","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Computer science; Digital electronics; Algorithm; Correlation clustering; Data mining; Computer engineering; Electronic circuit; Artificial intelligence; Engineering","score_opus":0.034607140389724206,"score_gpt":0.24935574639417696,"score_spread":0.21474860600445275,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2146888824","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0037166914,0.00013388894,0.98627716,0.000007872743,0.00006558248,0.00027853707,0.0000018106181,0.0005701867,0.008948278],"genre_scores_gemma":[0.9540247,0.000035769513,0.04545817,0.00004046239,0.00007656478,0.0000748577,0.000005162564,0.000022341284,0.00026198782],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99955535,0.0000016167413,0.0001259498,0.000084221356,0.000047182944,0.0001857037],"domain_scores_gemma":[0.9998467,0.000029973122,0.00000847191,0.000058363752,0.000013026225,0.000043470543],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00024221493,0.00006993702,0.00006794427,0.00004399435,0.000043748096,0.000028100494,0.000029962503,0.000039238403,0.00002148618],"category_scores_gemma":[0.00000370526,0.000068870715,0.000016089163,0.000037434707,0.000008524669,0.00006936623,0.000010537286,0.000037403483,0.0000022112415],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002848231,0.00009419727,0.0038283274,0.0017214795,0.0002290592,0.000017115588,0.0033671309,0.02751495,0.20972204,0.011416986,0.01294664,0.7291136],"study_design_scores_gemma":[0.0012774887,0.0003354451,0.0016550259,0.00019726531,0.000036069065,0.000045124398,0.00045826836,0.6962871,0.26873156,0.004965422,0.025167763,0.00084344344],"about_ca_topic_score_codex":0.0000048915917,"about_ca_topic_score_gemma":0.000016812497,"teacher_disagreement_score":0.95030797,"about_ca_system_score_codex":0.000026534351,"about_ca_system_score_gemma":0.0000017096561,"threshold_uncertainty_score":0.28084663},"labels":[],"label_agreement":null},{"id":"W2147209308","doi":"10.1109/asic.2001.954706","title":"A clustering utility based approach for ASIC design","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Guelph","funders":"","keywords":"Application-specific integrated circuit; Cluster analysis; Computer science; Heuristic; Interconnection; Electronics; Key (lock); Chip; System on a chip; Embedded system; Integrated circuit; Integrated circuit design; Computer engineering; Computer architecture; Engineering; Electrical engineering; Artificial intelligence; Telecommunications","score_opus":0.07999541787729543,"score_gpt":0.22188144737234036,"score_spread":0.14188602949504492,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2147209308","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000074840274,0.00009440068,0.9645072,0.000010700876,0.00003215779,0.00042420262,0.0000028671145,0.001355588,0.033498034],"genre_scores_gemma":[0.6051755,0.0000038463395,0.39440843,0.000042922686,0.000023774854,0.0001271803,0.000002315708,0.000019687011,0.00019632222],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994858,0.0000135831615,0.000118874115,0.00012700893,0.00005911193,0.00019563416],"domain_scores_gemma":[0.99969995,0.000051919313,0.000007606467,0.00018143619,0.000014882491,0.000044233],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001586205,0.00010660572,0.000111795365,0.00004842622,0.000034644196,0.00002389752,0.00009972847,0.00006949107,0.00021519486],"category_scores_gemma":[0.000011818329,0.00009914766,0.00005521395,0.00007872046,0.000011081969,0.000065312895,0.000007448216,0.000059003887,0.000008730435],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006270649,0.00046609898,0.00036783743,0.0015340784,0.00014429775,0.000007983856,0.0005548916,0.14620584,0.036460396,0.00054013764,0.25896275,0.554693],"study_design_scores_gemma":[0.00016805386,0.000032565917,0.000016217242,0.00000428982,0.0000058633686,0.000001353176,0.0000067897945,0.9761095,0.02194829,0.00008598708,0.0014955848,0.00012551584],"about_ca_topic_score_codex":0.0000018829645,"about_ca_topic_score_gemma":4.328435e-7,"teacher_disagreement_score":0.82990366,"about_ca_system_score_codex":0.00002335724,"about_ca_system_score_gemma":0.0000020684495,"threshold_uncertainty_score":0.40431243},"labels":[],"label_agreement":null},{"id":"W2147506855","doi":"10.1109/tvlsi.2004.827562","title":"Design of FPGA interconnect for multilevel metallization","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":46,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Field-programmable gate array; Interconnection; Routing (electronic design automation); Computer science; Exploit; Gate array; Topology (electrical circuits); Embedded system; Arity; Engineering; Electrical engineering; Computer network","score_opus":0.02608449495973388,"score_gpt":0.24309535380356354,"score_spread":0.21701085884382965,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2147506855","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030894582,0.00015201003,0.9929678,0.000014915397,0.0013778313,0.0013627828,0.00020575036,0.0006711695,0.00015829827],"genre_scores_gemma":[0.9870596,0.000093422364,0.011805981,0.00001929951,0.00006540944,0.00064381486,0.000033565062,0.0000710527,0.00020786693],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99850565,0.00008191293,0.00063677964,0.00026921267,0.00023184437,0.0002745783],"domain_scores_gemma":[0.99915475,0.00014438975,0.000099784906,0.00030588658,0.00022102392,0.00007418889],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00040670397,0.00028376945,0.00038645236,0.0003592941,0.000121620906,0.000060681712,0.00017543389,0.00024304164,0.00003083204],"category_scores_gemma":[0.000012726792,0.00026850778,0.00020196711,0.00025871416,0.000032480548,0.00041624528,6.639965e-7,0.00020235858,0.000025315],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000081457496,0.00025176513,9.002772e-7,0.00024409658,0.00015006625,0.0000012442331,0.0012764046,0.83644146,0.15054215,0.0005731606,0.00028916902,0.010148096],"study_design_scores_gemma":[0.00081639417,0.00025604782,0.0000031483094,0.00032715691,0.000067606,0.000010576523,0.0004035889,0.3509498,0.6463414,0.00022609023,0.0003403086,0.00025791427],"about_ca_topic_score_codex":0.000049425107,"about_ca_topic_score_gemma":0.00006440005,"teacher_disagreement_score":0.9839701,"about_ca_system_score_codex":0.00024075813,"about_ca_system_score_gemma":0.000040323514,"threshold_uncertainty_score":0.9999767},"labels":[],"label_agreement":null},{"id":"W2147640578","doi":"10.1287/ijoc.1050.0154","title":"Using Eigenvectors to Partition Circuits","year":2006,"lang":"en","type":"article","venue":"INFORMS journal on computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Partition (number theory); Eigenvalues and eigenvectors; Computer science; Mathematics; Electronic circuit; Arithmetic; Combinatorics; Engineering; Physics; Electrical engineering","score_opus":0.027372000564207362,"score_gpt":0.25504836344767023,"score_spread":0.22767636288346288,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2147640578","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.61080533,0.000031462456,0.38230482,0.000010236239,0.0003723026,0.00006548934,7.420501e-7,0.0002974368,0.006112194],"genre_scores_gemma":[0.9940418,0.000003424694,0.005157769,0.0001374191,0.00062358077,5.805793e-7,0.0000013235054,0.000022433314,0.0000116667725],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99912506,0.0000073410865,0.00033880415,0.00006370286,0.0001824236,0.00028267156],"domain_scores_gemma":[0.9996985,0.000024297395,0.000057231016,0.00008181278,0.000045978293,0.00009215374],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023025517,0.000123693,0.00012544081,0.00021390848,0.00015496349,0.00013346908,0.000107446074,0.00005565902,0.000017695467],"category_scores_gemma":[0.000012465012,0.00010986496,0.000062697465,0.0002015686,0.0000067888286,0.00019921722,0.00001467292,0.00025057333,0.000043565306],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000003082614,0.000016894848,0.0018806976,0.000022196713,0.000021272986,0.000042663272,0.0002160158,0.8577013,0.019268015,0.0009003583,0.0030838274,0.11684366],"study_design_scores_gemma":[0.000943777,0.0005404412,0.020788021,0.0011460506,0.00004020826,0.0014594726,0.00013563469,0.7500122,0.18768886,0.0065201432,0.02913863,0.0015865235],"about_ca_topic_score_codex":0.000009165602,"about_ca_topic_score_gemma":0.0000012441559,"teacher_disagreement_score":0.3832365,"about_ca_system_score_codex":0.00016197127,"about_ca_system_score_gemma":0.000013132505,"threshold_uncertainty_score":0.4480163},"labels":[],"label_agreement":null},{"id":"W2147903260","doi":"10.1109/fpt.2004.1393252","title":"Placement and routing for non-rectangular embedded programmable logic cores in SoC design","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Routing (electronic design automation); Computer science; Programmable logic device; Logic synthesis; Embedded system; Programmable logic array; Computer architecture; Logic gate; Parallel computing; Algorithm","score_opus":0.023506044105524145,"score_gpt":0.2549584049747044,"score_spread":0.23145236086918025,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2147903260","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019027553,0.00025297547,0.97660637,0.000036554175,0.000021993457,0.0010020954,0.0000012362789,0.0005720321,0.0024791874],"genre_scores_gemma":[0.7151115,0.000027259706,0.28438917,0.000041387848,0.000029557052,0.00020249802,0.0000027524793,0.00001951832,0.00017635744],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99936515,0.000009887773,0.00016532079,0.00013183244,0.00005751443,0.00027030846],"domain_scores_gemma":[0.9997936,0.000055269506,0.000013927265,0.000086111766,0.000013599363,0.000037490718],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00028079026,0.00011766094,0.00013786048,0.00006525084,0.000032225606,0.000038882677,0.000059885024,0.000069610476,0.000025119232],"category_scores_gemma":[0.000013987233,0.00010587668,0.000023703129,0.00007553721,0.00001243038,0.00008705959,0.000014088347,0.000063193846,0.0000039219317],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020887644,0.00036107795,0.0026293064,0.00066347414,0.00019839093,0.000030453504,0.005492791,0.30613777,0.15264991,0.0075528133,0.035444245,0.4886309],"study_design_scores_gemma":[0.0007185114,0.00019318375,0.00007842611,0.000045841047,0.000011171507,0.000004568795,0.00022130017,0.88114226,0.114422575,0.0017437586,0.0011408642,0.0002775129],"about_ca_topic_score_codex":0.000007311854,"about_ca_topic_score_gemma":0.000017362858,"teacher_disagreement_score":0.69608396,"about_ca_system_score_codex":0.000055328128,"about_ca_system_score_gemma":0.0000073107267,"threshold_uncertainty_score":0.43175256},"labels":[],"label_agreement":null},{"id":"W2148414872","doi":"10.21236/ada603903","title":"Integration of Physical Design and Sequential Optimization","year":2006,"lang":"en","type":"report","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; Defense Advanced Research Projects Agency","keywords":"Computer science","score_opus":0.031718748905475484,"score_gpt":0.2656318573185264,"score_spread":0.2339131084130509,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2148414872","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000094284456,0.00016545739,0.9469699,0.0000010982234,0.00008725467,0.00020899554,0.000006657666,0.00034976707,0.052116554],"genre_scores_gemma":[0.46812376,0.0020685561,0.52472484,0.000005008031,0.0008616641,0.00009536996,0.0005870243,0.00017654747,0.0033572023],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99941593,0.000014982803,0.00019557493,0.00010646893,0.0001917378,0.00007531857],"domain_scores_gemma":[0.99970204,0.000021336491,0.000048645175,0.00010067702,0.00011020516,0.000017111155],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012930713,0.00014366177,0.00023359156,0.000107720516,0.000009979553,0.000017078924,0.000041675743,0.00018617026,0.000020047179],"category_scores_gemma":[0.000012183876,0.00012643861,0.00004804495,0.00006465014,0.000020728532,0.00006457185,0.000009228144,0.00011740433,6.939688e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005863207,0.000052240106,0.0000057956136,0.00057258323,0.000099364785,0.000005975056,0.00009495252,0.7853238,0.063024715,0.0004131803,0.08723582,0.06316569],"study_design_scores_gemma":[0.0000579659,0.00006517847,0.000012204078,0.00010558269,0.0000663378,0.000010134838,0.0000026879343,0.88478553,0.11305961,0.00025033185,0.0013803317,0.0002040843],"about_ca_topic_score_codex":0.00007914624,"about_ca_topic_score_gemma":0.0000023565342,"teacher_disagreement_score":0.46802947,"about_ca_system_score_codex":0.0000637376,"about_ca_system_score_gemma":0.000045552806,"threshold_uncertainty_score":0.5156017},"labels":[],"label_agreement":null},{"id":"W2149159580","doi":"10.1109/cicc.1993.590820","title":"Multilevel optimization of high speed VLSI interconnects using decomposition","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Very-large-scale integration; Computer science; Decomposition; Parallel computing; Hierarchy; Printed circuit board; Tearing; Electric power transmission; Electronic engineering; Electrical engineering; Engineering; Embedded system","score_opus":0.028166880446567986,"score_gpt":0.2393816415894646,"score_spread":0.2112147611428966,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2149159580","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14340732,0.000039089133,0.85255307,0.0000060393127,0.00007404939,0.00008526121,0.0000023984935,0.00036410693,0.0034686704],"genre_scores_gemma":[0.8505087,0.000025069954,0.14937167,0.000012715611,0.000020996607,0.0000010642777,0.0000046354353,0.000015458725,0.00003970225],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99962986,0.000008676942,0.00014966891,0.000068666894,0.000055130127,0.0000879944],"domain_scores_gemma":[0.9998181,0.000016358019,0.00001944783,0.00009222269,0.0000308621,0.000023033013],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003081313,0.00007433435,0.000100805875,0.000089893416,0.000014822829,0.000010253853,0.000051568484,0.00005617809,0.00056279846],"category_scores_gemma":[0.000005938055,0.00007493937,0.000026552732,0.00007362213,0.000009618024,0.00013818755,0.000009374137,0.000040921102,0.000007757012],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000001982595,0.000032401902,0.00003371322,0.00004255157,0.000018995737,0.0000019169836,0.0001554178,0.82649297,0.1631114,0.00035767438,0.0006202862,0.00913068],"study_design_scores_gemma":[0.00010335583,0.000016097507,0.000033655415,0.000026267093,0.0000060067737,0.000004106238,0.000007530748,0.76319224,0.23646554,0.00006775567,0.000008177196,0.000069242575],"about_ca_topic_score_codex":0.000029262712,"about_ca_topic_score_gemma":0.0000012676945,"teacher_disagreement_score":0.70710135,"about_ca_system_score_codex":0.00003332682,"about_ca_system_score_gemma":8.944035e-7,"threshold_uncertainty_score":0.6162249},"labels":[],"label_agreement":null},{"id":"W2149504570","doi":"10.1108/02644400310502973","title":"Subdomain cluster generation for domain decomposition methods using graph partitioning optimization","year":2003,"lang":"en","type":"article","venue":"Engineering Computations","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Domain decomposition methods; Graph partition; Computer science; Parallel computing; Decomposition; Cluster (spacecraft); Heuristic; Decomposition method (queueing theory); Software; Graph; Load balancing (electrical power); Domain (mathematical analysis); Mathematical optimization; Theoretical computer science; Mathematics; Finite element method; Chemistry; Engineering; Programming language","score_opus":0.02363652411567258,"score_gpt":0.30661947565827613,"score_spread":0.28298295154260356,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2149504570","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013535707,0.0001523518,0.98465097,0.000014161805,0.0003508989,0.00039463263,0.000008813589,0.0007698774,0.0001225873],"genre_scores_gemma":[0.2748886,0.000006147418,0.72476584,0.000016580798,0.000084954576,0.000095969364,0.00009364298,0.000044515175,0.000003780624],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992047,0.00006301022,0.0002735227,0.00016324357,0.00007690567,0.00021864589],"domain_scores_gemma":[0.9995632,0.00015775947,0.000032653577,0.00011950704,0.000068178866,0.000058656315],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00036506547,0.00016175011,0.00014198422,0.00023706391,0.00017331385,0.00008341823,0.00005210415,0.00008853138,0.000012552206],"category_scores_gemma":[0.000051980234,0.00020038069,0.00007815298,0.00029848242,0.0000102760205,0.00022978541,0.0000052817645,0.00008974816,0.000001524646],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[7.219874e-7,0.000009399463,0.000006244393,0.000029968174,0.000023489678,3.101029e-7,0.0001233693,0.95545614,0.038026866,0.005817262,0.00023054883,0.00027568845],"study_design_scores_gemma":[0.0002454437,0.00001958053,0.000012146112,0.000026100823,0.000025367794,0.000014751838,0.000016016444,0.9792103,0.017907431,0.0017638438,0.0005370601,0.00022193053],"about_ca_topic_score_codex":0.0000014663466,"about_ca_topic_score_gemma":8.20614e-7,"teacher_disagreement_score":0.2613529,"about_ca_system_score_codex":0.00010909822,"about_ca_system_score_gemma":0.000012745711,"threshold_uncertainty_score":0.8171287},"labels":[],"label_agreement":null},{"id":"W2149846723","doi":"10.1109/iscas.2010.5537167","title":"Symmetry-aware analog layout placement design handling substrate-sharing constraints","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Transitive closure; Computer science; Representation (politics); Graph; Computational complexity theory; Transitive relation; Set (abstract data type); Time complexity; Topology (electrical circuits); Algorithm; Mathematical optimization; Theoretical computer science; Mathematics; Combinatorics","score_opus":0.022977196984071916,"score_gpt":0.23527665101562487,"score_spread":0.21229945403155295,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2149846723","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11219237,0.000047958252,0.85764873,0.00001353572,0.0003482763,0.0003110412,0.000008426697,0.0018118512,0.02761781],"genre_scores_gemma":[0.9773232,0.00001574981,0.022264652,0.000040129544,0.00008346036,0.000031036176,0.000010290688,0.000040281546,0.00019124213],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99898434,0.000011378256,0.0002570734,0.00023171793,0.00014838041,0.00036713388],"domain_scores_gemma":[0.9994596,0.00006270678,0.00002449472,0.00028417283,0.00004147006,0.00012750762],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00033656202,0.00021066597,0.00019236718,0.00013847934,0.0000782954,0.00010390713,0.00023447815,0.00016349736,0.0008302835],"category_scores_gemma":[0.000018747467,0.00019937952,0.00005644381,0.00015335488,0.00005859572,0.00013970883,0.00003144217,0.00037686527,0.000085837324],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006121623,0.00018819983,0.018565023,0.00038647567,0.00047493094,0.00022989669,0.0009432047,0.029855888,0.85452104,0.025626961,0.012712886,0.056434277],"study_design_scores_gemma":[0.0007065356,0.00013366815,0.0007345828,0.00009402459,0.000047787955,0.000060192113,0.00031425882,0.22758965,0.7667898,0.0020392856,0.0005686808,0.0009215411],"about_ca_topic_score_codex":0.000016624888,"about_ca_topic_score_gemma":0.000030620922,"teacher_disagreement_score":0.8651308,"about_ca_system_score_codex":0.000033261884,"about_ca_system_score_gemma":0.000019533898,"threshold_uncertainty_score":0.90910226},"labels":[],"label_agreement":null},{"id":"W2150022482","doi":"10.1109/fccm.2012.25","title":"ZUMA: An Open FPGA Overlay Architecture","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":116,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"TRIUMF","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Computer science; Netlist; Overlay; Architecture; Embedded system; Computer architecture; Suite; Benchmark (surveying); Compiler; Bitstream; Computer hardware; Operating system; Decoding methods; Telecommunications","score_opus":0.019693992566802015,"score_gpt":0.25741650922623527,"score_spread":0.23772251665943325,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2150022482","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0539709,0.00048348773,0.26199573,0.000090118854,0.0003862849,0.00052750454,0.0000094209645,0.0031358334,0.67940074],"genre_scores_gemma":[0.98174554,0.00001087047,0.016879221,0.00014842514,0.00016583061,0.00002419268,0.000006222892,0.000030328743,0.0009893526],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99953634,0.000012991096,0.00008051866,0.00007387683,0.0000627114,0.00023359034],"domain_scores_gemma":[0.99963254,0.000011348066,0.0000062380004,0.00023126777,0.0000069611638,0.000111671354],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000115652525,0.000096353,0.000096649615,0.000037365433,0.000027324992,0.000054159897,0.00028000356,0.00006426763,0.0006242416],"category_scores_gemma":[0.000003958353,0.00007826495,0.00001799743,0.00006497683,0.000008918407,0.00035805113,0.000057101664,0.00010755101,0.00008355422],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020700709,0.00029065687,0.0032137923,0.00010545675,0.00011498898,0.000010832037,0.0029352745,0.001218044,0.16205443,0.027702138,0.25016773,0.552166],"study_design_scores_gemma":[0.0005091645,0.00024926945,0.011241345,0.00003342295,0.000028088725,0.000071574716,0.00012927892,0.0027231928,0.38092315,0.0062940246,0.59673285,0.0010646334],"about_ca_topic_score_codex":0.0000334632,"about_ca_topic_score_gemma":0.00001212959,"teacher_disagreement_score":0.92777467,"about_ca_system_score_codex":0.000019141664,"about_ca_system_score_gemma":0.0000034867944,"threshold_uncertainty_score":0.68350077},"labels":[],"label_agreement":null},{"id":"W2150098004","doi":"10.1145/503048.503052","title":"Circuit design of routing switches","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":69,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Computer science; Benchmark (surveying); Very-large-scale integration; Electronic circuit; Transistor; Logic gate; Degradation (telecommunications); Electronic engineering; Embedded system; Electrical engineering; Engineering; Algorithm; Telecommunications; Voltage","score_opus":0.053136683840399636,"score_gpt":0.19464615835084725,"score_spread":0.14150947451044762,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2150098004","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030604277,0.00021557022,0.9172256,0.0000049553482,0.000029325727,0.00007447841,4.1873557e-7,0.000866186,0.078523055],"genre_scores_gemma":[0.9916593,0.000052208736,0.007840664,0.00001305073,0.000019651665,0.0000053176973,1.7394238e-7,0.0000142821345,0.0003953841],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99966043,0.000005248271,0.00011776489,0.000052355754,0.000056331442,0.00010788884],"domain_scores_gemma":[0.9998228,0.000030197374,0.000010251694,0.00010526323,0.000010619689,0.00002089351],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000075603806,0.00006013825,0.00008705206,0.000039715487,0.000011150816,0.000006551423,0.00007262981,0.000041652744,0.0004063522],"category_scores_gemma":[0.000009478045,0.000055676224,0.000023771257,0.000079551726,0.000008695925,0.00005301555,0.0000057730917,0.00004599077,0.000038491125],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000013448073,0.000042021322,0.0012330305,0.00012017276,0.000077274,0.000007827735,0.0013274974,0.011549135,0.7846755,0.0074642724,0.034185942,0.15931602],"study_design_scores_gemma":[0.00011022189,0.00004624344,0.00019022722,0.00002994412,0.000009908504,0.0000068902486,0.000049517406,0.30547395,0.6915942,0.0017661292,0.0005181874,0.00020463046],"about_ca_topic_score_codex":0.0000048420993,"about_ca_topic_score_gemma":2.0399884e-7,"teacher_disagreement_score":0.9885988,"about_ca_system_score_codex":0.000016190523,"about_ca_system_score_gemma":0.0000012774016,"threshold_uncertainty_score":0.44492716},"labels":[],"label_agreement":null},{"id":"W2150281391","doi":"10.1109/cicc.1997.606687","title":"Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":149,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Logic block; Computer science; Lookup table; Cluster (spacecraft); Key (lock); Parallel computing; Routing (electronic design automation); Cluster size; Block (permutation group theory); Logic gate; Logic synthesis; Logic optimization; Computer architecture; Arithmetic; Computer hardware; Embedded system; Algorithm; Mathematics; Computer network; Operating system","score_opus":0.02618504134952716,"score_gpt":0.22059743236395774,"score_spread":0.19441239101443059,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2150281391","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09628887,0.00058707927,0.8634665,0.0002863886,0.00011528716,0.00073436234,0.000008963113,0.0022933688,0.036219202],"genre_scores_gemma":[0.9846057,0.000038830323,0.014073801,0.00035526758,0.00004051872,0.000078097175,0.0000017375104,0.000028001423,0.0007780453],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992867,0.000004532804,0.000170384,0.00020234438,0.00007507539,0.0002609797],"domain_scores_gemma":[0.99957633,0.00012837784,0.000015722215,0.00018915483,0.000023893523,0.00006654926],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000111718975,0.00015267068,0.00015842606,0.00005212376,0.000059216458,0.000052108408,0.00013532834,0.000098567136,0.0002950896],"category_scores_gemma":[0.000052746294,0.00013435776,0.000048706956,0.000097689284,0.000023486446,0.0000643839,0.000026161362,0.00008622979,0.0000075731505],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002478337,0.0020937577,0.025292497,0.005361964,0.00051666715,0.00015949238,0.0052744835,0.1371414,0.14722781,0.018962674,0.39056742,0.26715398],"study_design_scores_gemma":[0.00047205613,0.00013661607,0.000057398112,0.00003831992,0.00001350796,0.000006191924,0.000013253421,0.9793212,0.016555892,0.0013105028,0.0018195517,0.0002555564],"about_ca_topic_score_codex":0.0000055146975,"about_ca_topic_score_gemma":0.0000044709354,"teacher_disagreement_score":0.8883168,"about_ca_system_score_codex":0.000027214115,"about_ca_system_score_gemma":0.0000022741465,"threshold_uncertainty_score":0.547895},"labels":[],"label_agreement":null},{"id":"W2150336620","doi":"10.1287/ijoc.1040.0127","title":"Integer Linear Programming Models for Global Routing","year":2006,"lang":"en","type":"article","venue":"INFORMS journal on computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Integer programming; Branch and price; Branch and cut; Linear programming; Mathematical optimization; Integer (computer science); Mathematics; Linear programming relaxation; Routing (electronic design automation); Branch and bound; Computer science; Programming language","score_opus":0.016612840833262452,"score_gpt":0.25495493552169163,"score_spread":0.23834209468842918,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2150336620","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.032484423,0.00008991202,0.9576182,0.000023182798,0.0003827553,0.00020711719,0.0000025677864,0.00066814985,0.008523691],"genre_scores_gemma":[0.91298324,0.0000046254613,0.086022854,0.00007781859,0.00085116463,0.0000042134243,0.000004591978,0.00002878332,0.000022728605],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986924,0.0000064403625,0.00054097566,0.00009942266,0.00019655396,0.00046422207],"domain_scores_gemma":[0.9995256,0.00006382273,0.000120894925,0.000100281344,0.00010987606,0.00007952499],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00045907963,0.00019431816,0.00020612315,0.00008922534,0.00021585508,0.0002083182,0.00019662379,0.00010287163,0.0000021982937],"category_scores_gemma":[0.000026755424,0.00016140101,0.00015619816,0.00016461544,0.000015444339,0.00035520774,0.000029203042,0.00035186298,0.000006170698],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011965362,0.000019381092,0.00030425284,0.00003789409,0.000029267585,0.000012026491,0.000103189945,0.64604217,0.00008406703,0.010628153,0.000978207,0.34174946],"study_design_scores_gemma":[0.00035504394,0.00011892326,0.00006145889,0.00020611919,0.0000090813255,0.0001717715,0.0000469673,0.9832591,0.0010461013,0.008325826,0.006156056,0.00024357461],"about_ca_topic_score_codex":0.000006867514,"about_ca_topic_score_gemma":0.0000015533737,"teacher_disagreement_score":0.88049877,"about_ca_system_score_codex":0.00020616066,"about_ca_system_score_gemma":0.000023648454,"threshold_uncertainty_score":0.6581742},"labels":[],"label_agreement":null},{"id":"W2150787480","doi":"10.1109/tcad.2006.882119","title":"Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":127,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Heuristics; Lookup table; Computer science; Heuristic; Field-programmable gate array; Minification; Enhanced Data Rates for GSM Evolution; Parallel computing; Node (physics); Algorithm; Computer hardware; Artificial intelligence","score_opus":0.026212895875709748,"score_gpt":0.20879863204576316,"score_spread":0.18258573617005341,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2150787480","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005772795,0.00026067303,0.99186504,0.000014126941,0.00049544947,0.00090833195,0.00007727401,0.00054085965,0.000065424916],"genre_scores_gemma":[0.98710096,0.000037474292,0.012513743,0.000010884957,0.000035031626,0.00021534514,0.000017020662,0.00004456186,0.000025005866],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99863636,0.00006685512,0.0006484041,0.0002638648,0.00012320642,0.00026128607],"domain_scores_gemma":[0.99923885,0.00023740923,0.000094890354,0.00021116907,0.00017679369,0.000040917654],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00022006656,0.0002595807,0.00044119815,0.00092238263,0.00006951434,0.000052641142,0.00013881618,0.0002948918,0.0000026390255],"category_scores_gemma":[0.0000049909645,0.0002539835,0.00006568387,0.0006295838,0.000053584386,0.000074955395,4.7994405e-7,0.000211661,9.682038e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015883139,0.00012425914,0.000031881904,0.00027576866,0.00004145557,0.0000074317813,0.000052428146,0.9370815,0.028161649,0.00026367544,0.00057316024,0.03337087],"study_design_scores_gemma":[0.00068363844,0.0002803442,0.000020881072,0.0005197821,0.000021441976,0.000017242579,0.00006647057,0.93511564,0.062595636,0.00023436516,0.0001967981,0.0002477846],"about_ca_topic_score_codex":0.00008566275,"about_ca_topic_score_gemma":0.000011292245,"teacher_disagreement_score":0.9813281,"about_ca_system_score_codex":0.00011692328,"about_ca_system_score_gemma":0.000047023066,"threshold_uncertainty_score":0.99999124},"labels":[],"label_agreement":null},{"id":"W2151538019","doi":"10.1109/cicc.1995.518134","title":"BALLISTIC: an analog layout language","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Porting; Assembly language; Code (set theory); Parameterized complexity; Graphics; High-level programming language; Electronic circuit; Programming language; Routing (electronic design automation); Computer graphics (images); Electrical engineering; Embedded system; Engineering; Algorithm; Programming paradigm; Software","score_opus":0.01559915807385621,"score_gpt":0.20732591722434085,"score_spread":0.19172675915048465,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2151538019","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07695304,0.0007207476,0.110578604,0.0000321556,0.000114358416,0.000120922385,0.000010729216,0.0044974964,0.80697197],"genre_scores_gemma":[0.9937414,0.000027453481,0.0045566517,0.00008714007,0.00006323971,0.0000050579893,0.0000048952597,0.000013601165,0.0015005845],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996869,0.000005914605,0.000067386085,0.00006764927,0.00005165954,0.00012047498],"domain_scores_gemma":[0.99977744,0.000007740379,0.0000036143947,0.0001531451,0.000006519953,0.00005153219],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000029887995,0.000065863285,0.00006418751,0.000024315974,0.000014408585,0.000020123205,0.00008432396,0.0000428457,0.002140803],"category_scores_gemma":[0.0000044079106,0.00005818334,0.00001866523,0.000060155573,0.000008106381,0.00008148936,0.0000057395864,0.000057133453,0.00022070631],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000035866922,0.00022711542,0.0022494588,0.00014101296,0.00010451405,0.00031801546,0.005211883,0.0019787408,0.10037741,0.02529739,0.2550043,0.6090866],"study_design_scores_gemma":[0.00045440145,0.00023968575,0.0024953827,0.000027787635,0.00003795106,0.000038220634,0.00052030315,0.8554311,0.07459374,0.0009835624,0.064093284,0.0010846269],"about_ca_topic_score_codex":0.00002447352,"about_ca_topic_score_gemma":0.000024246876,"teacher_disagreement_score":0.91678834,"about_ca_system_score_codex":0.000011280525,"about_ca_system_score_gemma":3.760352e-7,"threshold_uncertainty_score":0.99877137},"labels":[],"label_agreement":null},{"id":"W2151614223","doi":"10.1109/fpl.2007.4380635","title":"Improving Timing-Driven FPGA Packing with Physical Information","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":47,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Field-programmable gate array; Computer science; Cluster analysis; Path (computing); Placement; Critical path method; Parallel computing; Computer engineering; Embedded system; Physical design; Computer network; Artificial intelligence; Engineering; Circuit design","score_opus":0.006557993342052479,"score_gpt":0.20227910757881648,"score_spread":0.195721114236764,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2151614223","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08917005,0.0000040989376,0.87231314,0.0000055360456,0.000027452044,0.0000916388,5.698799e-7,0.0010585969,0.03732889],"genre_scores_gemma":[0.9841961,0.0000012622249,0.01564485,0.000042029194,0.00006779083,0.0000045871925,0.000004455735,0.000012335235,0.000026556543],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999585,0.0000018960964,0.000098902005,0.00004558675,0.000097134165,0.000171519],"domain_scores_gemma":[0.99980885,0.00001910465,0.000016579888,0.00009287274,0.000023934745,0.000038646253],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007680181,0.000082492115,0.0000726373,0.00007031315,0.000029257902,0.000035989022,0.000056489644,0.000036590813,0.000011789128],"category_scores_gemma":[0.000004523751,0.00006509182,0.000019264633,0.000097459444,0.000010617808,0.00048543955,0.0000111606405,0.000092794966,0.000032884604],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018874103,0.00002800964,0.0011148322,0.0001666863,0.00004403619,0.0000125463575,0.0025436252,0.005258443,0.06062326,0.0031995606,0.0018232828,0.92516685],"study_design_scores_gemma":[0.00040102075,0.00018648684,0.0023430053,0.000060702416,0.000023189614,0.000022792732,0.00039939658,0.377106,0.61400026,0.00022994773,0.0046996167,0.00052760233],"about_ca_topic_score_codex":0.000013494562,"about_ca_topic_score_gemma":0.000006500899,"teacher_disagreement_score":0.9246392,"about_ca_system_score_codex":0.000035440113,"about_ca_system_score_gemma":0.0000044866997,"threshold_uncertainty_score":0.26543674},"labels":[],"label_agreement":null},{"id":"W2152362440","doi":"10.1145/503048.503059","title":"Integrated retiming and placement for field programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":54,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Retiming; Computer science; Field-programmable gate array; Routing (electronic design automation); Gate array; Combinational logic; Parallel computing; Electronic circuit; Algorithm; Logic gate; Embedded system; Engineering","score_opus":0.021977691626485916,"score_gpt":0.21168669329966935,"score_spread":0.18970900167318344,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2152362440","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008839051,0.0003465276,0.95497996,0.00015233195,0.000074500356,0.000562369,0.0000027537885,0.0013181054,0.033724397],"genre_scores_gemma":[0.8815672,0.00022501532,0.114392504,0.00014427057,0.000042575204,0.00022070318,0.0000060606776,0.00003077529,0.0033709009],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996356,0.0000029789412,0.0000916886,0.00008332363,0.000034506134,0.0001519525],"domain_scores_gemma":[0.9998387,0.000030233328,0.0000067932515,0.00007565362,0.000014387763,0.000034243167],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000057395257,0.00007792269,0.00007788369,0.000032358403,0.000030063286,0.00003319318,0.000038058457,0.00004897752,0.0001989768],"category_scores_gemma":[0.00001110949,0.00006620973,0.000018630988,0.000048721715,0.000006386787,0.000053554275,0.0000067936885,0.00005532327,0.0000050591552],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000028949826,0.00007199936,0.00024595414,0.00043309975,0.00011521245,0.000008208977,0.0011897488,0.0012212419,0.04197097,0.0030515385,0.2964395,0.65522355],"study_design_scores_gemma":[0.00035336614,0.00029145408,0.0000037033433,0.00005411644,0.000015284895,0.000005920946,0.00015628118,0.6980168,0.20891552,0.0006408843,0.091287956,0.00025868465],"about_ca_topic_score_codex":0.0000068507047,"about_ca_topic_score_gemma":0.0000050427698,"teacher_disagreement_score":0.87272817,"about_ca_system_score_codex":0.00001321837,"about_ca_system_score_gemma":8.961135e-7,"threshold_uncertainty_score":0.26999542},"labels":[],"label_agreement":null},{"id":"W2153007772","doi":"10.1109/isqed.2011.5770732","title":"Enhancement of incremental design for FPGAs using circuit similarity","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Netlist; Similarity (geometry); Computer science; Circuit extraction; Matching (statistics); Design flow; Algorithm; Physical design; Field-programmable gate array; Process (computing); Plug-in; Feature (linguistics); Logic synthesis; Electronic circuit; Computer engineering; Theoretical computer science; Circuit design; Logic gate; Artificial intelligence; Computer hardware; Equivalent circuit; Embedded system; Mathematics; Engineering; Programming language; Image (mathematics)","score_opus":0.1564762563193712,"score_gpt":0.26235752824947883,"score_spread":0.10588127193010763,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2153007772","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.035830136,0.00005063651,0.95488524,8.046256e-7,0.00005577095,0.00037139663,0.000004235823,0.00019405465,0.00860771],"genre_scores_gemma":[0.8140482,0.00001036383,0.18584138,0.00001524463,0.000014089459,0.000027534252,0.0000015655963,0.000015211151,0.00002645212],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99950624,0.000010095548,0.00017826016,0.0000853505,0.000070752205,0.0001493342],"domain_scores_gemma":[0.9997774,0.000019857194,0.000021504195,0.00012107984,0.000030178919,0.00002999194],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019247147,0.00008891436,0.00012222987,0.00004909777,0.000021870941,0.0000043640393,0.00009046045,0.0000515272,0.00028124926],"category_scores_gemma":[0.000006062182,0.000087485016,0.00004450601,0.000049630376,0.00001627595,0.000076053475,0.000013621599,0.000035826946,0.0000021521046],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014208731,0.00007251645,0.00018259518,0.00013040287,0.00006298523,9.737648e-7,0.00042776336,0.0001709997,0.9907958,0.002157049,0.0011851678,0.004799531],"study_design_scores_gemma":[0.00013175939,0.000085878884,0.000037637652,0.00001700312,0.000017098988,0.000001034088,0.00002615409,0.02072699,0.97623676,0.002525251,0.00008885179,0.000105600324],"about_ca_topic_score_codex":0.000037012196,"about_ca_topic_score_gemma":0.000002023357,"teacher_disagreement_score":0.77821803,"about_ca_system_score_codex":0.00004538582,"about_ca_system_score_gemma":0.000008890262,"threshold_uncertainty_score":0.35675356},"labels":[],"label_agreement":null},{"id":"W2153245554","doi":"10.1109/tcad.2005.852040","title":"Calligrapher: a new layout-migration engine for hard intellectual property libraries","year":2005,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":29,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Datapath; Standard cell; Metric (unit); Solver; Process (computing); Constraint (computer-aided design); Page layout; Computer engineering; Parallel computing; Integrated circuit; Programming language; Mathematics; Operating system; Engineering","score_opus":0.039085538524315996,"score_gpt":0.21243984616758857,"score_spread":0.1733543076432726,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2153245554","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0034461997,0.000742056,0.99314034,0.00004550489,0.00056295237,0.0011307411,0.00006907647,0.00078902935,0.000074091426],"genre_scores_gemma":[0.9750623,0.00032495317,0.023423065,0.000043107408,0.00020520935,0.00026165374,0.000014170623,0.0000722304,0.000593318],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985225,0.00008662375,0.0006138753,0.00030776858,0.00018030505,0.0002889054],"domain_scores_gemma":[0.99906933,0.0003059927,0.00007265201,0.00024323925,0.00015930342,0.00014948646],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002342102,0.00034828772,0.000489709,0.00036845997,0.0001084515,0.00016744439,0.00018506314,0.00023331735,0.000026486789],"category_scores_gemma":[0.000008915417,0.00025674579,0.00013216282,0.00036592953,0.000052566913,0.00033297695,8.1871195e-7,0.0002575913,0.00000695754],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008039116,0.00013587726,0.0000027961255,0.0002498687,0.000317905,0.0000025205402,0.0026563678,0.5081458,0.03152004,0.00021770889,0.021837134,0.4348336],"study_design_scores_gemma":[0.00054547476,0.0007817448,0.0000027506899,0.00033274398,0.00005639551,0.000038152735,0.00012316422,0.88182724,0.10952602,0.000048592457,0.0063816123,0.0003361208],"about_ca_topic_score_codex":0.0001491789,"about_ca_topic_score_gemma":0.000026145395,"teacher_disagreement_score":0.9716161,"about_ca_system_score_codex":0.00007183275,"about_ca_system_score_gemma":0.00009407892,"threshold_uncertainty_score":0.9999885},"labels":[],"label_agreement":null},{"id":"W2153585893","doi":"10.1145/611817.611838","title":"Using logic duplication to improve performance in FPGAs","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Path (computing); Computer science; Critical path method; Programmable logic device; Logic synthesis; Logic optimization; Logic gate; Parallel computing; Gene duplication; Data deduplication; Algorithm; Embedded system; Engineering; Programming language","score_opus":0.025479367273861124,"score_gpt":0.2480734802009621,"score_spread":0.22259411292710096,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2153585893","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.49317488,0.000047850695,0.45122525,0.000014076534,0.00006537765,0.00022046792,3.6271402e-7,0.0003963777,0.054855354],"genre_scores_gemma":[0.9667802,0.00001572174,0.03299743,0.000064365544,0.000009791582,0.000019805182,3.6357082e-7,0.000009689059,0.00010267582],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99967784,0.0000047456447,0.00008921969,0.00007514369,0.00003526148,0.000117777796],"domain_scores_gemma":[0.9998465,0.0000047244857,0.0000049374266,0.00010925999,0.000009467733,0.000025111676],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008352053,0.000055750723,0.000055009965,0.00006776468,0.000011566293,0.000009290374,0.0000431297,0.000037479807,0.000035752248],"category_scores_gemma":[0.000007823649,0.000052820436,0.000009395108,0.00014899278,0.0000030641863,0.00007597648,0.000004590665,0.000048805745,0.00003486823],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000028892237,0.000029197812,0.005448648,0.0000727355,0.000005611234,0.0000021701712,0.0001979168,0.035857733,0.9094557,0.013440227,0.000471199,0.03501596],"study_design_scores_gemma":[0.00013123339,0.00005429595,0.0034531043,0.000021784464,0.0000027022254,0.000006368708,0.000025280551,0.17376955,0.8171729,0.0011020019,0.004007265,0.00025352425],"about_ca_topic_score_codex":0.0000073534093,"about_ca_topic_score_gemma":0.0000036349315,"teacher_disagreement_score":0.47360528,"about_ca_system_score_codex":0.000055666645,"about_ca_system_score_gemma":0.0000043023665,"threshold_uncertainty_score":0.2153955},"labels":[],"label_agreement":null},{"id":"W2154356865","doi":"10.1109/cicc.2003.1249360","title":"Architecture of datapath-oriented coarse-grain logic and routing for FPGAs","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Datapath; Field-programmable gate array; Routing (electronic design automation); Computer architecture; Computer science; Architecture; Logic synthesis; Set (abstract data type); Parallel computing; Reconfigurability; Embedded system; Logic gate; Algorithm; Programming language; Geography","score_opus":0.01192976122594891,"score_gpt":0.22541987254509474,"score_spread":0.21349011131914583,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2154356865","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.033945195,0.00012247794,0.9621603,0.00005221844,0.00004245263,0.00025577736,0.00003126596,0.00041703854,0.0029732573],"genre_scores_gemma":[0.8849038,0.000012288983,0.11489139,0.000046406643,0.000025382022,0.000017039249,0.000018655688,0.000017029794,0.00006803421],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995643,0.000004742107,0.00013474976,0.0001033601,0.00004926745,0.00014357333],"domain_scores_gemma":[0.99977666,0.000029535195,0.000016916629,0.00012504437,0.000018481212,0.000033343476],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001022991,0.00009084979,0.00012684661,0.00005087596,0.00002266045,0.000007737129,0.00006274983,0.000056839184,0.0000109878765],"category_scores_gemma":[0.000030088919,0.00007616674,0.000024417312,0.00007013181,0.000025960744,0.00004012124,0.000018488725,0.00006604999,9.607795e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000051519095,0.000121162506,0.0004429425,0.0009562859,0.00015273136,0.000016034894,0.0029418173,0.016958829,0.59075785,0.22742316,0.0045965887,0.1555811],"study_design_scores_gemma":[0.002777124,0.0006837267,0.000416986,0.0003198116,0.00007429017,0.00006854886,0.0005147971,0.042387713,0.8447331,0.09507933,0.012059805,0.00088473264],"about_ca_topic_score_codex":0.000018882944,"about_ca_topic_score_gemma":0.000014683223,"teacher_disagreement_score":0.8509586,"about_ca_system_score_codex":0.000013410928,"about_ca_system_score_gemma":0.0000054968987,"threshold_uncertainty_score":0.31059897},"labels":[],"label_agreement":null},{"id":"W2155316178","doi":"10.1145/1950413.1950457","title":"Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":83,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Logic block; Block (permutation group theory); Verilog; Field-programmable gate array; Computer architecture; Logic synthesis; Hierarchy; Interconnection; Theoretical computer science; Key (lock); Parallel computing; Logic gate; Embedded system; Algorithm; Mathematics","score_opus":0.06117116452925328,"score_gpt":0.21318732548179994,"score_spread":0.15201616095254666,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2155316178","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17731792,0.00016101029,0.816642,0.000015297988,0.000009462896,0.00022397161,0.0000030097124,0.00040195268,0.005225362],"genre_scores_gemma":[0.8917249,0.000042787524,0.10808823,0.000043178265,0.000015526895,0.000029081317,0.0000029977932,0.00001660396,0.000036733472],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996384,0.000007216623,0.0000741593,0.00011690235,0.00003065223,0.00013268215],"domain_scores_gemma":[0.99983686,0.000024628933,0.000009287377,0.00007371647,0.0000151523855,0.000040373736],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005600105,0.00010714415,0.00011008133,0.00006712555,0.000037794165,0.000028888426,0.000039861603,0.000046285168,0.000022794971],"category_scores_gemma":[0.000004164847,0.00007676935,0.000013345089,0.000031359763,0.00004416462,0.000075946395,0.000015472531,0.00006904866,2.1666601e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00037091115,0.00010946723,0.0061060954,0.0010184593,0.00032544255,0.000025073507,0.011282191,0.000605789,0.40350673,0.053815648,0.0030259788,0.51980823],"study_design_scores_gemma":[0.0033799578,0.0044291024,0.010791698,0.0005790223,0.0002199235,0.0006900806,0.002224945,0.39811456,0.31144154,0.2605946,0.005113451,0.0024210885],"about_ca_topic_score_codex":0.000020571651,"about_ca_topic_score_gemma":0.00004634461,"teacher_disagreement_score":0.7144069,"about_ca_system_score_codex":0.000008175392,"about_ca_system_score_gemma":0.0000017332509,"threshold_uncertainty_score":0.31305632},"labels":[],"label_agreement":null},{"id":"W2155560344","doi":"10.1109/mnrc.2008.4683373","title":"A spatial computing architecture for implementing computational circuits","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Computer architecture; Scalability; Debugging; Field-programmable gate array; Electronic circuit; Computer engineering; Design flow; Encoding (memory); Benchmark (surveying); Architecture; Parallel computing; Embedded system; Artificial intelligence; Engineering; Programming language","score_opus":0.022263233234602265,"score_gpt":0.24349149889025562,"score_spread":0.22122826565565334,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2155560344","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.037350014,0.000025729056,0.9570591,0.000021031236,0.000058269787,0.00020819374,0.000010864074,0.0008160506,0.0044507724],"genre_scores_gemma":[0.9285836,0.0000013856079,0.07110385,0.00006601242,0.00014736484,0.000011695589,0.000028518802,0.000020630221,0.00003692977],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999435,0.0000056233707,0.0001543121,0.000098134806,0.00008401021,0.00022289006],"domain_scores_gemma":[0.99979115,0.00007288585,0.0000156771,0.000056813285,0.000030475492,0.000032982793],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007464079,0.000089624096,0.00009801662,0.00005908999,0.0001279697,0.000012706005,0.000068859496,0.00003461132,0.00003642528],"category_scores_gemma":[0.000007172326,0.00008914008,0.000050750055,0.000053846303,0.000013151507,0.000030416577,0.000015976331,0.00006828891,0.00000440016],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000006707092,0.000054769625,0.005185426,0.0002833848,0.00016372102,0.000022767974,0.00297309,0.17653453,0.022596741,0.0053074416,0.029378498,0.7574929],"study_design_scores_gemma":[0.0007261853,0.00007991029,0.0038594762,0.00002538011,0.00001158087,0.00012717713,0.000041515275,0.95797527,0.018890653,0.00565564,0.012175281,0.00043191368],"about_ca_topic_score_codex":0.000013158406,"about_ca_topic_score_gemma":0.000008794768,"teacher_disagreement_score":0.8912336,"about_ca_system_score_codex":0.00001770809,"about_ca_system_score_gemma":0.000010016018,"threshold_uncertainty_score":0.3635027},"labels":[],"label_agreement":null},{"id":"W2156091563","doi":"10.1109/fpl.2008.4630008","title":"MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Arctic Goose Joint Venture; National Natural Science Foundation of China","keywords":"Field-programmable gate array; Computer science; Lookup table; Macro; Algorithm; Heterogeneous network; Computer engineering; Parallel computing; Computer hardware; Telecommunications; Wireless; Wireless network","score_opus":0.00853833330748312,"score_gpt":0.19763630868556784,"score_spread":0.1890979753780847,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2156091563","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04334419,0.00011663306,0.9528032,0.000019858571,0.000033516695,0.0007166357,0.0000069565763,0.0021674936,0.0007915427],"genre_scores_gemma":[0.6202926,0.000015821402,0.3790741,0.000017290004,0.000017547798,0.0004796113,0.0000086592845,0.00003121524,0.00006316699],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994381,0.0000052047567,0.00011712628,0.00015553957,0.00006587217,0.00021814807],"domain_scores_gemma":[0.99971426,0.00003892156,0.000018576353,0.00015177901,0.000044138713,0.000032335683],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004052775,0.00014770629,0.00016577932,0.00019176844,0.00007785218,0.000010111482,0.00008277414,0.00011950686,0.000012542249],"category_scores_gemma":[0.0000074801546,0.00012482653,0.00003629233,0.00020263468,0.000044254615,0.00007286502,0.000011733959,0.00008219201,0.000011533425],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000118547705,0.000043739332,0.00019593822,0.00009076878,0.00016996013,0.00011130354,0.0003572983,0.012367012,0.016982581,0.00019971502,0.0013854955,0.96808434],"study_design_scores_gemma":[0.00039400964,0.00030786145,0.00007148244,0.000039877934,0.000012571973,0.00063947897,0.000019036243,0.75891805,0.23676047,0.001295796,0.001289226,0.00025215204],"about_ca_topic_score_codex":0.000004654786,"about_ca_topic_score_gemma":0.0000026426576,"teacher_disagreement_score":0.9678322,"about_ca_system_score_codex":0.00005976907,"about_ca_system_score_gemma":0.0000069604007,"threshold_uncertainty_score":0.50902784},"labels":[],"label_agreement":null},{"id":"W2156657748","doi":"10.1109/ccece.1999.807236","title":"Design and characterization of an embedded ASIC DRAM","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"University of Alberta","funders":"","keywords":"Dram; Microelectronics; Embedded system; Application-specific integrated circuit; Universal memory; Computer science; Macro; Chip; CAS latency; Process variation; Process (computing); Engineering; Computer hardware; Operating system; Semiconductor memory; Electrical engineering; Computer memory; Programming language; Memory controller; Telecommunications; Memory refresh","score_opus":0.011139310511142836,"score_gpt":0.20579650255794707,"score_spread":0.19465719204680423,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2156657748","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.34904566,0.000011821732,0.6477202,0.0000012021017,0.000018940702,0.000090334746,4.5927334e-7,0.00023548448,0.002875872],"genre_scores_gemma":[0.96602345,0.000026704165,0.033837922,0.000011609605,0.000005546635,0.0000066254647,0.0000037377106,0.00001136117,0.00007303305],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997579,0.00002036257,0.00007742869,0.00005101343,0.000033125558,0.000060161412],"domain_scores_gemma":[0.99987036,0.000007884324,0.000008966012,0.000076731296,0.000011612047,0.00002446529],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008054449,0.000049140028,0.000065287524,0.000035667596,0.000009204266,0.00000944061,0.00002393825,0.0000381852,0.00005311581],"category_scores_gemma":[0.0000036766219,0.000045942674,0.0000064884116,0.000052216717,0.000008257293,0.00011594552,0.0000017514539,0.000024026462,0.0000018799913],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000108905,0.0000093543,0.00003264804,0.000014812147,0.0000044054486,5.5336426e-7,0.00012088873,0.000063550026,0.98843354,0.001280569,0.000028802686,0.010009803],"study_design_scores_gemma":[0.000071072696,0.000051186118,0.0007212392,0.0000051183756,0.0000038632816,0.000003950541,0.000010103538,0.019681348,0.9786288,0.0005488904,0.00020165532,0.00007277354],"about_ca_topic_score_codex":6.263283e-7,"about_ca_topic_score_gemma":1.3540645e-7,"teacher_disagreement_score":0.6169778,"about_ca_system_score_codex":0.0000042312136,"about_ca_system_score_gemma":0.0000031550821,"threshold_uncertainty_score":0.1873488},"labels":[],"label_agreement":null},{"id":"W2156813734","doi":"10.1109/mwscas.2007.4488680","title":"Efficient volterra series based sensitivity analysis of mildly nonlinear circuits","year":2007,"lang":"en","type":"article","venue":"Conference proceedings","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Volterra series; Hessian matrix; Sensitivity (control systems); Jacobian matrix and determinant; Speedup; Nonlinear system; Computer science; Electronic circuit; Series (stratigraphy); Frequency domain; Algorithm; Mathematics; Applied mathematics; Electronic engineering; Parallel computing; Engineering; Physics","score_opus":0.016879216511048886,"score_gpt":0.23073481855126204,"score_spread":0.21385560204021314,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2156813734","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6833364,0.000029104362,0.31184366,0.000019998472,0.00006024585,0.00012903663,0.000019250381,0.000440516,0.0041218363],"genre_scores_gemma":[0.9963494,0.000006530682,0.0035223926,0.00002413999,0.0000361352,0.000006091175,0.00000954466,0.000018911756,0.000026878646],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99900866,0.000003877091,0.00028668976,0.0002049908,0.00021142777,0.00028433016],"domain_scores_gemma":[0.9993512,0.000039361807,0.00006480505,0.000114051545,0.00034247158,0.0000880797],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005183314,0.00017432137,0.00034188727,0.00043842485,0.000038463455,0.00003577028,0.00011609414,0.00011338441,0.000043932458],"category_scores_gemma":[0.00005579685,0.00017704288,0.00011508483,0.00089582935,0.00008108269,0.000080081714,0.000021244241,0.00014068554,0.0000044997323],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000038570284,0.00015032072,0.016852489,0.00051199266,0.000565863,0.000016369035,0.0029333092,0.0068581356,0.94927275,0.0018956691,0.00050725124,0.020397263],"study_design_scores_gemma":[0.00010216,0.000050086335,0.013432381,0.000054389206,0.00021194937,0.0000031854538,0.00020419681,0.7002508,0.28519496,0.000023192042,0.00024233214,0.00023034778],"about_ca_topic_score_codex":0.000011734064,"about_ca_topic_score_gemma":0.000013984005,"teacher_disagreement_score":0.6933927,"about_ca_system_score_codex":0.000041658426,"about_ca_system_score_gemma":0.000024519513,"threshold_uncertainty_score":0.72195995},"labels":[],"label_agreement":null},{"id":"W2156912292","doi":"10.1109/asic.1995.580750","title":"High-level analog synthesis using signal flow graph transformations","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Signal-flow graph; Realizability; Computer science; Transfer function; Graph; High-level synthesis; Analog signal; SIGNAL (programming language); Control flow graph; Theoretical computer science; Algorithm; Topology (electrical circuits); Mathematics; Computer hardware; Programming language; Digital signal processing; Electrical engineering; Engineering","score_opus":0.03921932070267154,"score_gpt":0.2018993032004975,"score_spread":0.16267998249782598,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2156912292","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010129155,0.00012196303,0.97478485,0.000035661702,0.000056209898,0.00009969489,0.0000375803,0.0010167597,0.013718117],"genre_scores_gemma":[0.9177874,0.00009668,0.08193698,0.00003094706,0.000036879384,0.000017711305,0.0000028946495,0.000021405502,0.00006912595],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994432,0.0000116836345,0.00017602157,0.00007995636,0.00009989115,0.00018924805],"domain_scores_gemma":[0.9997682,0.000031170923,0.000008776641,0.00011910325,0.000018119847,0.000054618475],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000058601327,0.000118508535,0.00012837989,0.00016401109,0.000071121045,0.000030018096,0.00009450533,0.00007654127,0.0019824326],"category_scores_gemma":[0.0000038829603,0.00011081637,0.000072340634,0.00022221467,0.000017004215,0.00022142676,0.0000036778224,0.0000856516,0.000057530833],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004983485,0.00017491754,0.00012509315,0.00023746167,0.0003515267,0.000030592753,0.0012292247,0.17423958,0.15870361,0.005757686,0.041917793,0.61722755],"study_design_scores_gemma":[0.00009035244,0.000015150476,0.00013761863,0.000027400523,0.0000412238,0.000014498586,0.000026799733,0.8528111,0.14506102,0.0010232962,0.00047331388,0.00027825343],"about_ca_topic_score_codex":0.00003535775,"about_ca_topic_score_gemma":0.0000097447155,"teacher_disagreement_score":0.9076582,"about_ca_system_score_codex":0.000029102797,"about_ca_system_score_gemma":0.0000021704316,"threshold_uncertainty_score":0.9989299},"labels":[],"label_agreement":null},{"id":"W2156995134","doi":"10.5555/1870926.1871047","title":"A power optimization method for CMOS op-amps using sub-space based geometric programming","year":2010,"lang":"en","type":"article","venue":"Design, Automation, and Test in Europe","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"York University","funders":"","keywords":"Geometric programming; Monomial; CMOS; Convex optimization; Mathematical optimization; Transistor; Space (punctuation); Regular polygon; Computer science; Constraint (computer-aided design); Power (physics); Voltage; Electronic engineering; Topology (electrical circuits); Mathematics; Engineering; Electrical engineering; Discrete mathematics","score_opus":0.015562163227364962,"score_gpt":0.25389846106551606,"score_spread":0.2383362978381511,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2156995134","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011753801,0.00010879338,0.9861061,0.000023283566,0.00013160978,0.0008427066,0.00000702656,0.00087569037,0.00015097884],"genre_scores_gemma":[0.28066447,0.000021089181,0.7190875,0.00002780165,0.000036060555,0.00007544126,0.000016593727,0.000058667178,0.00001241105],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99901086,0.000070303024,0.0003020503,0.00022855814,0.00012604262,0.00026220272],"domain_scores_gemma":[0.99881107,0.0006677717,0.00007163429,0.00018667057,0.00019365152,0.00006917863],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00083921145,0.00019245116,0.0001972266,0.00053598295,0.00010437979,0.0001388968,0.000110336376,0.00012325347,0.000017380562],"category_scores_gemma":[0.0009039198,0.00019703244,0.000029792987,0.0012699171,0.000024563416,0.00026891805,0.00001196692,0.00015682659,0.0000020000998],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025299332,0.00030131463,0.005638452,0.00048248633,0.000042614098,0.000019107196,0.00076735276,0.64677054,0.25652698,0.0010208461,0.0011016122,0.08730338],"study_design_scores_gemma":[0.00038215466,0.00009021205,0.0013366679,0.00003719853,0.000017019169,0.000013335467,0.0000075710473,0.9634317,0.032657165,0.00007400248,0.0017056213,0.00024731335],"about_ca_topic_score_codex":0.000009794035,"about_ca_topic_score_gemma":0.000003435976,"teacher_disagreement_score":0.31666118,"about_ca_system_score_codex":0.00003022428,"about_ca_system_score_gemma":0.00004313124,"threshold_uncertainty_score":0.80347496},"labels":[],"label_agreement":null},{"id":"W2157958003","doi":"10.1109/iccd.1994.331954","title":"Routing architectures for hierarchical field programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":56,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Granularity; Computer science; Architecture; Set (abstract data type); Electronic circuit; Hierarchical routing; Computer architecture; Programmable logic array; Programmable Array Logic; Logic gate; Gate array; Logic synthesis; Parallel computing; Embedded system; Computer engineering; Routing protocol; Static routing; Engineering; Logic family; Algorithm; Electrical engineering","score_opus":0.016905989154600756,"score_gpt":0.22069264977099234,"score_spread":0.20378666061639159,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2157958003","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018863218,0.00016726428,0.917601,0.00029606768,0.00009994237,0.0004984626,0.000003063399,0.002418433,0.060052566],"genre_scores_gemma":[0.9366431,0.000011170032,0.062063754,0.00015757741,0.00012882934,0.00011576744,0.0000017329803,0.000027683913,0.0008503317],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993745,0.000007058539,0.00013381321,0.000119320895,0.000066591,0.0002987058],"domain_scores_gemma":[0.99968636,0.0000989257,0.00000896604,0.00013588893,0.0000115241555,0.000058326863],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000074090654,0.00011046071,0.00011379316,0.000049925602,0.000054791362,0.000037876052,0.000108246524,0.00007524595,0.00019895892],"category_scores_gemma":[0.000033187705,0.000093812036,0.00007002104,0.00007123797,0.0000122135625,0.00001884801,0.000012087926,0.00014785244,0.000015307021],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015133704,0.00006574339,0.0003226864,0.00020275066,0.00007551188,0.00000969976,0.0008333717,0.0065565943,0.012984384,0.005896715,0.046200506,0.9268369],"study_design_scores_gemma":[0.00035040246,0.00027889846,0.00003570307,0.00003952136,0.000015078173,0.000017899652,0.000025227557,0.7888394,0.16586637,0.011625328,0.032487836,0.00041835842],"about_ca_topic_score_codex":0.000005629675,"about_ca_topic_score_gemma":0.000006273679,"teacher_disagreement_score":0.92641854,"about_ca_system_score_codex":0.000010819595,"about_ca_system_score_gemma":0.00000147779,"threshold_uncertainty_score":0.38255438},"labels":[],"label_agreement":null},{"id":"W2158515581","doi":"10.5755/j01.eee.19.10.2464","title":"Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics","year":2013,"lang":"en","type":"article","venue":"Elektronika ir Elektrotechnika","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Semtech (Canada)","funders":"","keywords":"Sizing; Heuristics; Biasing; Cascode; Transconductance; Electronic engineering; Computer science; Electronic circuit; Operational amplifier; Current mirror; Mathematical optimization; Amplifier; Engineering; Electrical engineering; Voltage; Mathematics; Transistor; CMOS","score_opus":0.011770308963011131,"score_gpt":0.19996341638769213,"score_spread":0.188193107424681,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2158515581","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10516897,0.0077356678,0.87079275,0.0001163217,0.0005003808,0.0027104178,0.00019399956,0.007375705,0.005405815],"genre_scores_gemma":[0.992423,0.0006856998,0.005089373,0.000092677925,0.00017889477,0.0007145705,0.00023100832,0.00025655967,0.0003281886],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9965499,0.00011119551,0.00071539276,0.0006725039,0.0006562415,0.0012947388],"domain_scores_gemma":[0.99834865,0.00010561637,0.00016960081,0.000829654,0.00019634218,0.00035010852],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00034445254,0.0008144454,0.00069483084,0.00034136837,0.00020868814,0.0002643177,0.0007339869,0.00037792616,0.00041523966],"category_scores_gemma":[0.000064428146,0.0007244768,0.00015578017,0.00084087736,0.00016471384,0.00061927096,0.00007385519,0.0012870769,0.00034756452],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023570768,0.00037614774,0.004104884,0.00038129793,0.00039325783,0.000038980976,0.0002513644,0.0004928591,0.22439614,0.00073697494,0.17496267,0.59384185],"study_design_scores_gemma":[0.0038870708,0.0017218803,0.0031011298,0.0013321786,0.00036811936,0.00017792286,0.00038779492,0.03158962,0.4327724,0.005105214,0.5138074,0.0057492713],"about_ca_topic_score_codex":0.00009989198,"about_ca_topic_score_gemma":0.000010011813,"teacher_disagreement_score":0.88725406,"about_ca_system_score_codex":0.00047745425,"about_ca_system_score_gemma":0.00007821489,"threshold_uncertainty_score":0.99952066},"labels":[],"label_agreement":null},{"id":"W2159649114","doi":"10.5555/602902.602925","title":"General models for optimum arbitrary-dimension FPGA switch box designs","year":2000,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Topology (electrical circuits); Network topology; Dimension (graph theory); Mathematics; Embedded system; Computer network; Combinatorics","score_opus":0.028076585010745888,"score_gpt":0.23506388613176424,"score_spread":0.20698730112101835,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2159649114","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03907755,0.00029228505,0.89522284,0.00004757318,0.000080234066,0.0004786502,0.000009492279,0.0018433325,0.06294804],"genre_scores_gemma":[0.6661548,0.00022444835,0.3272114,0.00033615288,0.00016647835,0.00015299188,0.000024733054,0.000087701635,0.0056413193],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991754,0.000009384694,0.00019933806,0.00018874617,0.00010172724,0.0003253892],"domain_scores_gemma":[0.99962723,0.000025534728,0.0000090433505,0.00022577276,0.000024908326,0.000087494074],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000102782324,0.00018024676,0.00017592471,0.000062534185,0.000058408958,0.00003409263,0.00012961615,0.00013345602,0.0005568328],"category_scores_gemma":[0.000001537916,0.00016594498,0.00009228531,0.0000879687,0.000012086539,0.00023629755,0.000008244037,0.0000992723,0.00004987467],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007018157,0.00010262798,0.000009872008,0.000084412626,0.00010065458,0.000016845253,0.0002840279,0.47481018,0.17097689,0.009473448,0.16605249,0.17801838],"study_design_scores_gemma":[0.00026884687,0.000086447224,0.0000057563484,0.000013621954,0.000013621225,0.000008119202,0.0000047538197,0.76396674,0.21804392,0.012773534,0.0045369356,0.0002776835],"about_ca_topic_score_codex":0.000019400486,"about_ca_topic_score_gemma":0.0000022511003,"teacher_disagreement_score":0.6270772,"about_ca_system_score_codex":0.000035448116,"about_ca_system_score_gemma":0.000011154959,"threshold_uncertainty_score":0.676704},"labels":[],"label_agreement":null},{"id":"W2159928318","doi":"10.1109/glsv.1995.516055","title":"Parallel hierarchical global routing for general cell layout","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Speedup; Computer science; Routing (electronic design automation); Parallel computing; Decomposition; Simple (philosophy); Integer programming; Algorithm; Computer network","score_opus":0.018963534811120376,"score_gpt":0.22365778026597358,"score_spread":0.2046942454548532,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2159928318","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022822753,0.0002348642,0.80894935,0.00008749272,0.00012229968,0.0002350368,0.00001652273,0.0014593012,0.16607238],"genre_scores_gemma":[0.8557637,0.000024127972,0.14184573,0.00013718085,0.00018499498,0.000037339258,0.000005162031,0.000020363792,0.0019814358],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993934,0.000007029051,0.0001397286,0.00011845284,0.000069869326,0.00027153964],"domain_scores_gemma":[0.99977154,0.000019725103,0.000008381649,0.00012095116,0.000011798399,0.0000676253],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0000526022,0.000110437686,0.00011132613,0.000017867536,0.00003997753,0.000028938428,0.00011051702,0.000084015264,0.00017707453],"category_scores_gemma":[0.0000058908126,0.00010114048,0.000071140916,0.00006184247,0.000012048066,0.000055196604,0.00001544061,0.00007476346,0.000052455634],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002946247,0.00028656534,0.0054050726,0.00030805814,0.00013031416,0.00004049489,0.0007093122,0.020332891,0.021277182,0.15625095,0.6315437,0.16368598],"study_design_scores_gemma":[0.0004699196,0.000071110604,0.00025704183,0.0000069205676,0.000011581523,0.000008885354,0.000011966693,0.97044766,0.0063855066,0.0039538527,0.018060094,0.00031546515],"about_ca_topic_score_codex":0.000007801284,"about_ca_topic_score_gemma":0.0000031940724,"teacher_disagreement_score":0.9501148,"about_ca_system_score_codex":0.000039028913,"about_ca_system_score_gemma":0.000002037365,"threshold_uncertainty_score":0.41243893},"labels":[],"label_agreement":null},{"id":"W2160595395","doi":"10.1109/mwscas.1990.140679","title":"Applying simulated evolution to scheduling in high level synthesis","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Heuristics; Scheduling (production processes); Computer science; Probabilistic logic; Mathematical optimization; Greedy algorithm; Theoretical computer science; Algorithm; Mathematics; Artificial intelligence","score_opus":0.03396459389540897,"score_gpt":0.2157652595090148,"score_spread":0.1818006656136058,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2160595395","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.38361958,0.00016073111,0.60481364,0.000056779572,0.00008212405,0.00032395977,0.0000033771603,0.0016614317,0.009278392],"genre_scores_gemma":[0.9737501,0.000012633953,0.025892453,0.00003561258,0.000027065895,0.000088092755,5.5673047e-7,0.000023709981,0.00016978371],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994342,0.000010289089,0.00015666797,0.00011702318,0.000081188955,0.00020063623],"domain_scores_gemma":[0.9997498,0.000054455424,0.0000068259596,0.0001277655,0.000013652511,0.000047529444],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008860677,0.000098528944,0.0001185802,0.00019601385,0.000023379003,0.000018073517,0.00008306448,0.00008134559,0.00024129912],"category_scores_gemma":[0.000047686903,0.00010183168,0.00002214233,0.00030131804,0.0000042259794,0.0000974316,0.0000142577655,0.00009206522,0.00017387308],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000037915656,0.00004433851,0.0019676182,0.00005776438,0.0000224944,0.00001367243,0.00019437907,0.7575823,0.11158816,0.0017354877,0.0012153331,0.12557463],"study_design_scores_gemma":[0.00010881654,0.000012747191,0.0016261569,0.00008007161,0.000005544352,0.0000017587512,0.000037920814,0.9414934,0.055451795,0.00029176014,0.0006329085,0.00025711046],"about_ca_topic_score_codex":0.00010620419,"about_ca_topic_score_gemma":0.000017886248,"teacher_disagreement_score":0.5901305,"about_ca_system_score_codex":0.0001230533,"about_ca_system_score_gemma":0.0000014991974,"threshold_uncertainty_score":0.41525754},"labels":[],"label_agreement":null},{"id":"W2161653569","doi":"10.1109/ccece.1997.614777","title":"A clustering algorithm for circuit partitioning","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Netlist; Computer science; Cluster analysis; Simulated annealing; Tabu search; Algorithm; Benchmark (surveying); Algorithm design; Parallel computing; Artificial intelligence","score_opus":0.03459231613347618,"score_gpt":0.2129012160972475,"score_spread":0.1783088999637713,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2161653569","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00013387276,0.0001361692,0.96061265,0.0000127123485,0.00008087728,0.00012299047,0.00000352501,0.001153492,0.037743732],"genre_scores_gemma":[0.78508854,0.00007891452,0.2122213,0.00012013854,0.00021377769,0.00022265337,0.000005411473,0.000048792917,0.0020004883],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99965066,0.0000022315533,0.000089482615,0.00006862019,0.000038617818,0.00015037371],"domain_scores_gemma":[0.9998554,0.000017826242,0.0000053654044,0.00007915132,0.000011446477,0.000030826723],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000040795738,0.000062510946,0.00006613694,0.000035151977,0.000037516445,0.000026859618,0.000047706744,0.00003787552,0.00034638282],"category_scores_gemma":[0.000003381721,0.00006424264,0.000034648303,0.000048302256,0.000005618535,0.00008145065,0.0000059127633,0.00003777391,0.00004157704],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[1.6040278e-7,0.000010043123,0.000015839902,0.00003526337,0.00001749127,0.0000023360983,0.00015550453,0.0006436107,0.003363621,0.00052362715,0.02127591,0.9739566],"study_design_scores_gemma":[0.00010244568,0.000020234944,0.000011091669,0.000011852523,0.0000041466346,0.0000064195815,0.000012839017,0.9773683,0.010038467,0.00066523824,0.011647018,0.000111961956],"about_ca_topic_score_codex":0.0000017730001,"about_ca_topic_score_gemma":0.0000016856957,"teacher_disagreement_score":0.9767247,"about_ca_system_score_codex":0.000019498455,"about_ca_system_score_gemma":5.4122916e-7,"threshold_uncertainty_score":0.3792649},"labels":[],"label_agreement":null},{"id":"W2161942462","doi":"10.1109/tcad.2008.915545","title":"Scalable Synthesis and Clustering Techniques Using Decision Diagrams","year":2008,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Speedup; Binary decision diagram; Computer science; Scalability; Field-programmable gate array; Cluster analysis; Leverage (statistics); Logic synthesis; Electronic design automation; Parallel computing; Reduction (mathematics); Data-flow analysis; Design flow; Theoretical computer science; Algorithm; Data flow diagram; Logic gate; Mathematics; Computer hardware; Embedded system","score_opus":0.03977928161711857,"score_gpt":0.22769522824453112,"score_spread":0.18791594662741254,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2161942462","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06374064,0.0005112992,0.9340667,0.0000018793667,0.00038211796,0.00053022767,0.000024945135,0.0006628394,0.00007931582],"genre_scores_gemma":[0.9735601,0.0010322303,0.025205579,0.000009330143,0.000044682543,0.00007351626,9.180565e-7,0.000058314963,0.000015313635],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99846685,0.00012429952,0.00057976024,0.00032787156,0.00021945067,0.00028175284],"domain_scores_gemma":[0.9989696,0.00041605823,0.00008212294,0.00027373625,0.00012841243,0.0001300364],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00034092503,0.00033552953,0.00056139706,0.00042818655,0.00021479426,0.00008764896,0.0001481707,0.00024749394,0.000006523777],"category_scores_gemma":[0.0000064290616,0.00029766318,0.00007721531,0.00033641243,0.00010728112,0.00023108485,0.0000022538304,0.0002619859,0.0000017322527],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000043923024,0.00014170629,0.00005326689,0.0003940921,0.00022739946,0.000059021164,0.0004569767,0.23992364,0.18146668,0.000036160734,0.00033298176,0.5768641],"study_design_scores_gemma":[0.00017787972,0.00023996182,0.000021140673,0.0010218866,0.000042708678,0.000452408,0.000053453245,0.79750925,0.20007461,0.000035196237,0.00005715344,0.00031434232],"about_ca_topic_score_codex":0.00019616976,"about_ca_topic_score_gemma":0.0000041751928,"teacher_disagreement_score":0.9098195,"about_ca_system_score_codex":0.00009839487,"about_ca_system_score_gemma":0.000032475382,"threshold_uncertainty_score":0.99994755},"labels":[],"label_agreement":null},{"id":"W2162180547","doi":"10.1109/iscas.2005.1466066","title":"Fast Integer Linear Programming Based Models for VLSI Global Routing","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Router; Integer programming; Computer science; Routing (electronic design automation); Very-large-scale integration; Mathematical optimization; Pruning; Tree (set theory); Minification; Linear programming; Global optimization; Parallel computing; Algorithm; Mathematics; Computer network; Embedded system","score_opus":0.018846671850123925,"score_gpt":0.25098185101314974,"score_spread":0.2321351791630258,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162180547","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0012352681,0.00006116229,0.98401636,0.00008074037,0.000050173883,0.00034366173,0.000009094863,0.0019302748,0.012273239],"genre_scores_gemma":[0.6619219,0.0000017001216,0.33763584,0.00009441707,0.00014076203,0.00006768088,0.000008123588,0.000022282296,0.00010726617],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99927527,0.0000054663724,0.00019021083,0.00014085186,0.0000854874,0.00030271348],"domain_scores_gemma":[0.9997154,0.000023720137,0.00001481747,0.00014180334,0.000042833435,0.00006144796],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013408235,0.00014078656,0.00013056962,0.00003296021,0.000042428037,0.000041369258,0.00011764024,0.000091143556,0.000027357557],"category_scores_gemma":[0.000011940595,0.00012926654,0.00008399405,0.000107811386,0.000011494818,0.00018555835,0.000014021543,0.00007888813,0.000014062604],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010458563,0.000051142324,0.00013325148,0.00008296663,0.000032378706,0.0000015829287,0.00011514924,0.2873867,0.0013441651,0.008578305,0.0032878995,0.69897604],"study_design_scores_gemma":[0.00019182268,0.000031146115,0.000003630582,0.00002429796,0.000008480189,0.0000017672829,0.000030546344,0.97570956,0.014069981,0.0003579364,0.009399863,0.00017096165],"about_ca_topic_score_codex":0.000011220641,"about_ca_topic_score_gemma":0.000019356135,"teacher_disagreement_score":0.69880503,"about_ca_system_score_codex":0.00009837432,"about_ca_system_score_gemma":0.000012350546,"threshold_uncertainty_score":0.52713364},"labels":[],"label_agreement":null},{"id":"W2162557036","doi":"10.1109/pads.2007.4","title":"A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Netlist; Computer science; Verilog; Algorithm; Very-large-scale integration; Hypergraph; Speedup; Parallel computing; Logic synthesis; Algorithm design; Theoretical computer science; Logic gate; Mathematics; Field-programmable gate array; Embedded system","score_opus":0.025883688928128645,"score_gpt":0.2677548274825193,"score_spread":0.24187113855439063,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162557036","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0004606488,0.000024220417,0.9974347,0.0000055585356,0.000072185205,0.00029332805,0.000015284942,0.0010890858,0.0006049896],"genre_scores_gemma":[0.6781272,0.0000031904442,0.32165226,0.00001731449,0.000067280766,0.000029264818,0.00005902908,0.000016492348,0.000027910448],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995174,0.000005523016,0.00014364283,0.0000830167,0.000057775775,0.0001926794],"domain_scores_gemma":[0.99968284,0.00014399544,0.000012643838,0.00007939175,0.000039473456,0.00004165299],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017603644,0.00007979688,0.00008084014,0.000046014306,0.000050336257,0.000021084887,0.00004567898,0.00006824788,0.00003772808],"category_scores_gemma":[0.000013884602,0.00008044876,0.000032579646,0.00009524786,0.00000881884,0.0000997131,0.0000052235537,0.00004225035,0.000009606162],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014565392,0.000027696467,0.00009576338,0.00002778409,0.00004412564,0.0000058267997,0.000114944094,0.64667624,0.01427488,0.00060262455,0.0046396377,0.3334759],"study_design_scores_gemma":[0.00016008264,0.000044189488,0.00015716297,0.000007743102,0.000007734133,9.3610635e-7,0.00001079985,0.9421131,0.053645868,0.00089073426,0.0028496236,0.00011205201],"about_ca_topic_score_codex":0.0000021891128,"about_ca_topic_score_gemma":0.0000015458595,"teacher_disagreement_score":0.6776666,"about_ca_system_score_codex":0.000050561383,"about_ca_system_score_gemma":0.000003860929,"threshold_uncertainty_score":0.3280605},"labels":[],"label_agreement":null},{"id":"W2162628682","doi":"10.1145/611817.611842","title":"Automatic transistor and physical design of FPGA tiles from an architectural specification","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Computer science; Place and route; Netlist; Schematic; Design layout record; Router; Embedded system; Lookup table; Computer hardware; Process (computing); Integrated circuit layout; Computer architecture; Integrated circuit; Electrical engineering; Engineering; Circuit extraction; Operating system; Voltage","score_opus":0.01827725736220543,"score_gpt":0.2206740602273176,"score_spread":0.20239680286511216,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162628682","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.58052003,0.000063676176,0.41822785,0.000004725486,0.000014310254,0.000097884644,0.000003162439,0.00029236876,0.00077599485],"genre_scores_gemma":[0.9487943,0.0000073018177,0.051136564,0.0000053315707,0.000018940691,0.000009513202,0.000003410658,0.000013143876,0.000011485559],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996439,0.00003278557,0.00010282078,0.00008575304,0.000059891558,0.00007482373],"domain_scores_gemma":[0.99977607,0.000047738475,0.000011143016,0.00012077508,0.000008364635,0.000035926754],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000045723842,0.00007865513,0.00011879361,0.000036136164,0.000012587457,0.000009178447,0.000045537967,0.000030347062,0.00006693455],"category_scores_gemma":[0.000005523484,0.0000675338,0.00001979992,0.000045265144,0.000026235268,0.00006368795,0.0000012856923,0.000045377048,0.0000034532386],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000067299916,0.000086950255,0.00007294585,0.000069781214,0.00004097239,0.0000014648994,0.003604279,0.0012983662,0.8059718,0.00175931,0.00035557497,0.18673183],"study_design_scores_gemma":[0.00017667796,0.00010404945,0.0040777745,0.000018486484,0.000024512909,0.0000057924626,0.000092638984,0.23428857,0.75435317,0.006557345,0.00011335757,0.00018762381],"about_ca_topic_score_codex":0.000010084357,"about_ca_topic_score_gemma":0.0000019748827,"teacher_disagreement_score":0.36827427,"about_ca_system_score_codex":0.000010090077,"about_ca_system_score_gemma":0.0000039494676,"threshold_uncertainty_score":0.27539483},"labels":[],"label_agreement":null},{"id":"W2162694675","doi":"10.1109/iccd.2008.4751836","title":"A parallel Steiner tree heuristic for macro cell routing","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Steiner tree problem; Computer science; Routing (electronic design automation); Tree (set theory); Heuristic; Parameterized complexity; Very-large-scale integration; Macro; Set (abstract data type); Parallel computing; Algorithm; Mathematical optimization; Mathematics; Computer network; Combinatorics; Artificial intelligence; Embedded system","score_opus":0.018186451578640152,"score_gpt":0.2069256173150415,"score_spread":0.18873916573640134,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162694675","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01785623,0.0001833924,0.90557706,0.000019534256,0.0000785944,0.0002668332,0.0000054370935,0.0013450485,0.07466789],"genre_scores_gemma":[0.9413224,0.000045872068,0.053387783,0.00005285998,0.000082960614,0.000060367252,0.000005286512,0.000035068082,0.0050074044],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99947,0.0000046517744,0.00014320499,0.00010437518,0.000059387694,0.00021837547],"domain_scores_gemma":[0.9997418,0.000048019298,0.000011443624,0.00013579681,0.000018083736,0.00004487493],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000050426228,0.00010889314,0.000121197496,0.00003817118,0.00005341394,0.000010541285,0.00008844523,0.000057314006,0.00005045989],"category_scores_gemma":[0.000009534999,0.00009726642,0.000060185037,0.000055735345,0.00001226359,0.000049660735,0.00001053604,0.00006206301,0.00003305015],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000079528385,0.0002769577,0.0033443929,0.0008365722,0.00016159909,0.0002026457,0.0027786475,0.012387313,0.15290195,0.009485995,0.75791293,0.05963146],"study_design_scores_gemma":[0.0029935355,0.00046228676,0.002221229,0.000066487344,0.000072966825,0.00012345563,0.00018915704,0.62460726,0.29899493,0.003500613,0.065042004,0.0017260878],"about_ca_topic_score_codex":0.000010006911,"about_ca_topic_score_gemma":0.000004780598,"teacher_disagreement_score":0.92346615,"about_ca_system_score_codex":0.000019818544,"about_ca_system_score_gemma":0.0000059981135,"threshold_uncertainty_score":0.39664096},"labels":[],"label_agreement":null},{"id":"W2162705435","doi":"10.1109/tvlsi.2003.812369","title":"Further improve circuit partitioning using GBAW logic perturbation techniques","year":2003,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Hypergraph; Graph partition; Computer science; Electronic circuit; Benchmark (surveying); Graph; Logic synthesis; Logic gate; Partition (number theory); Parallel computing; Logic optimization; Algorithm; Theoretical computer science; Mathematics; Engineering","score_opus":0.021252731122555588,"score_gpt":0.23291846541657654,"score_spread":0.21166573429402097,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162705435","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008258531,0.00021468847,0.9818049,0.000015918977,0.0016836771,0.0007952137,0.00008669064,0.0017308056,0.005409544],"genre_scores_gemma":[0.99546075,0.00006432625,0.0030219404,0.00006565394,0.00013991901,0.0003813135,0.000018827908,0.00009015955,0.0007570892],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.998044,0.00019374189,0.0006161166,0.00038448974,0.00033267765,0.00042894488],"domain_scores_gemma":[0.9991172,0.000070800685,0.000107379616,0.0004075055,0.00018594397,0.00011118348],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004950545,0.00037399572,0.0003496677,0.00036062466,0.00030941897,0.00020931443,0.00014141745,0.0003693575,0.00016817158],"category_scores_gemma":[0.00001231715,0.00036114437,0.00019750764,0.0004129992,0.000043802494,0.00063727953,7.209639e-7,0.00046583824,0.00006831367],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000057823647,0.00075614324,0.000098449585,0.0005213894,0.00035017432,0.000024536323,0.004668498,0.12866403,0.8263472,0.010704658,0.0016165496,0.026190586],"study_design_scores_gemma":[0.00039865286,0.00021138912,0.000009208813,0.0004481887,0.000096158066,0.00008076644,0.001518317,0.28651968,0.7055196,0.001319722,0.0031258096,0.0007524723],"about_ca_topic_score_codex":0.000049790673,"about_ca_topic_score_gemma":0.000053638978,"teacher_disagreement_score":0.9872022,"about_ca_system_score_codex":0.00043714923,"about_ca_system_score_gemma":0.00004219966,"threshold_uncertainty_score":0.99988407},"labels":[],"label_agreement":null},{"id":"W2163480916","doi":"10.1109/icpads.2000.857720","title":"Some space considerations of VLSI systolic array mappings","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Regina","funders":"","keywords":"Systolic array; Nested loop join; Very-large-scale integration; Loop (graph theory); Transformation (genetics); Algorithm; Computer science; Transformation matrix; Space (punctuation); Matrix (chemical analysis); Variable (mathematics); Array data structure; Mathematics; Parallel computing; Combinatorics; Physics; Mathematical analysis","score_opus":0.019342595885688953,"score_gpt":0.19340886197251025,"score_spread":0.1740662660868213,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2163480916","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.052071996,0.005545304,0.39620447,0.001797288,0.00052870746,0.0008615431,0.000025565698,0.006106829,0.53685826],"genre_scores_gemma":[0.9893565,0.00013637397,0.009199194,0.000071888935,0.000051971696,0.000012853762,7.236521e-7,0.000014563108,0.0011559408],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99961036,0.0000068105505,0.00013871107,0.00006603585,0.0000647239,0.000113371476],"domain_scores_gemma":[0.99974895,0.000032731852,0.0000140140155,0.00014817079,0.000022039381,0.000034086075],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000036366804,0.00007524254,0.000119936216,0.00007546734,0.00002340141,0.000013387765,0.00004219393,0.000050975435,0.0005968918],"category_scores_gemma":[0.000014313864,0.00007203935,0.0000349198,0.0000698712,0.000022041355,0.000107978034,0.000004752921,0.000060760765,0.000083835184],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[3.911615e-7,0.000042143725,0.000115036906,0.00017373191,0.00006161982,0.000008316806,0.00092144095,0.0006695339,0.6543261,0.14649963,0.19626987,0.00091221137],"study_design_scores_gemma":[0.00023145729,0.00005174463,0.00016368691,0.000073238196,0.000021862055,0.000048152524,0.00011271391,0.018411875,0.9507627,0.013681903,0.016068904,0.0003717763],"about_ca_topic_score_codex":0.000012341571,"about_ca_topic_score_gemma":0.0000027675808,"teacher_disagreement_score":0.93728447,"about_ca_system_score_codex":0.000015640242,"about_ca_system_score_gemma":0.0000022949916,"threshold_uncertainty_score":0.6535546},"labels":[],"label_agreement":null},{"id":"W2163517325","doi":"10.5555/1356802.1356854","title":"Large-scale fixed-outline floorplanning design using convex optimization techniques","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Waterloo","funders":"","keywords":"Floorplan; Mathematical optimization; Minification; Voronoi diagram; Computer science; Convex optimization; Regular polygon; Global optimization; Graph; Mathematics; Theoretical computer science","score_opus":0.0293150775017935,"score_gpt":0.23663767064324662,"score_spread":0.20732259314145313,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2163517325","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0043396703,0.00017660168,0.9867352,0.000009679934,0.00007585031,0.00029330453,0.000005208512,0.0037673556,0.0045971004],"genre_scores_gemma":[0.28099403,0.0001633249,0.7183339,0.00008801705,0.000105638625,0.000025908479,0.000017101076,0.00006256413,0.00020949595],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990773,0.00003210866,0.00026241734,0.00017806177,0.00014135936,0.0003087157],"domain_scores_gemma":[0.99959725,0.000031740376,0.000029612678,0.00021020498,0.000059418668,0.00007176056],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020309394,0.00019524634,0.000218414,0.0001585236,0.00014029365,0.000025446912,0.0001309368,0.00016328896,0.00022301156],"category_scores_gemma":[0.000012863778,0.00019272433,0.00005159747,0.00022567468,0.000031056043,0.00024802095,0.000026503772,0.00015164164,0.000014198102],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020114832,0.000093093695,0.0011115663,0.000079577396,0.000061962455,0.00008928265,0.0014061668,0.86865807,0.106414616,0.00014115545,0.019620731,0.0023036897],"study_design_scores_gemma":[0.0001107474,0.00003319675,0.00001815703,0.000029078383,0.000010050683,0.000063930354,0.000046505127,0.7535102,0.24497548,0.000040149025,0.00093449804,0.00022802378],"about_ca_topic_score_codex":0.00000894748,"about_ca_topic_score_gemma":6.5748935e-7,"teacher_disagreement_score":0.27665436,"about_ca_system_score_codex":0.000062193845,"about_ca_system_score_gemma":0.000018503928,"threshold_uncertainty_score":0.78590703},"labels":[],"label_agreement":null},{"id":"W2163661406","doi":"10.1016/j.disopt.2012.10.002","title":"A bad example for the iterative rounding method for mincost <mml:math xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" altimg=\"si52.gif\" display=\"inline\" overflow=\"scroll\"><mml:mi>k</mml:mi></mml:math>-connected spanning subgraphs","year":2012,"lang":"en","type":"article","venue":"Discrete Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University; University of Waterloo","funders":"","keywords":"Rounding; Mathematics; Norm (philosophy); Algorithm; Discrete mathematics; Iterative method; Iterative refinement; Relaxation (psychology); Computer science; Combinatorics","score_opus":0.021739337531294353,"score_gpt":0.2639957199895441,"score_spread":0.2422563824582497,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2163661406","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17644794,0.00038006922,0.821523,0.000055826054,0.00042766178,0.00027400933,0.00012467889,0.00033196117,0.00043486652],"genre_scores_gemma":[0.7591885,0.00012976797,0.23806322,0.00013598205,0.00045260237,0.0010340171,0.0007784248,0.00017523093,0.000042297874],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983074,0.00006355561,0.0004419438,0.00034693655,0.0002554895,0.0005846597],"domain_scores_gemma":[0.99832815,0.000805949,0.00022951506,0.00042398443,0.000087371656,0.00012505805],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00076232746,0.00031159472,0.00020873161,0.00012751795,0.0005156173,0.00030153882,0.00027195987,0.0003106475,0.000022512522],"category_scores_gemma":[0.000320588,0.00031212263,0.00029404974,0.00030514173,0.000064137246,0.00081666297,0.00008605369,0.00022173602,0.000014344604],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012368307,0.000030316023,0.00002004251,0.00017935614,0.0002230201,0.00000262111,0.002143817,0.11130063,0.0032211335,0.8808284,0.0004714951,0.0014555143],"study_design_scores_gemma":[0.000492869,0.00015861061,0.000029141393,0.00016099852,0.00022661069,0.000020369016,0.00044307855,0.9800216,0.016386354,0.00020183047,0.0015234278,0.0003351181],"about_ca_topic_score_codex":0.00009959757,"about_ca_topic_score_gemma":0.000028526649,"teacher_disagreement_score":0.88062656,"about_ca_system_score_codex":0.00002930746,"about_ca_system_score_gemma":0.000042173848,"threshold_uncertainty_score":0.99993306},"labels":[],"label_agreement":null},{"id":"W2163716961","doi":"10.5755/j01.itc.40.4.981","title":"A HYBRID GENETIC ALGORITHM FOR PARTITIONING OF DATA MODEL IN DISTRIBUTION MANAGEMENT SYSTEMS","year":2011,"lang":"en","type":"article","venue":"Information Technology And Control","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Particle swarm optimization; Genetic algorithm; Algorithm; Estimation of distribution algorithm; Mathematical optimization; Mathematics; Machine learning","score_opus":0.013685633900061576,"score_gpt":0.20069229830943766,"score_spread":0.18700666440937608,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2163716961","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003317742,0.00021652463,0.9953267,0.000008354663,0.000022226046,0.00038856984,0.00024493318,0.00020775765,0.00026716696],"genre_scores_gemma":[0.9738249,0.00008556143,0.025754863,0.0000077242175,0.0000027990607,0.00021593903,0.00010330016,0.0000028930895,0.0000020206678],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959254,0.0000029757146,0.00023443517,0.00004759526,0.00003145008,0.000090983754],"domain_scores_gemma":[0.9997604,0.000005825302,0.00004169925,0.00015808448,0.000024635372,0.000009349947],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010571376,0.000052313197,0.000095597454,0.0001730936,0.000019719208,0.000007037134,0.000112545305,0.000064796535,8.287003e-7],"category_scores_gemma":[0.0000044394724,0.000053951942,0.00000776949,0.0000728718,0.00002465131,0.00037795748,0.00002068434,0.000044999306,0.0000011241891],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015955848,0.000019557825,0.00028646973,0.0002591991,0.000060220416,0.0000013787496,0.00011462138,0.004213516,0.000085330226,0.045765217,0.00041522886,0.9487633],"study_design_scores_gemma":[0.0005182098,0.000025174912,0.00017503089,0.000027017086,0.000014695804,0.0000048504685,0.000063050145,0.9908398,0.0012539552,0.00662089,0.00040079167,0.000056543533],"about_ca_topic_score_codex":0.0000037780098,"about_ca_topic_score_gemma":3.5425643e-7,"teacher_disagreement_score":0.98662627,"about_ca_system_score_codex":0.0000127074845,"about_ca_system_score_gemma":0.0000030577237,"threshold_uncertainty_score":0.22000964},"labels":[],"label_agreement":null},{"id":"W2164114092","doi":"10.1109/delta.2002.994649","title":"A novel analytical model for evaluation of substrate crosstalk in VLSI circuits","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Crosstalk; Very-large-scale integration; Computer science; Electronic circuit; Electronic engineering; Computer architecture; Electrical engineering; Engineering; Embedded system","score_opus":0.08816011737603942,"score_gpt":0.31464825146451714,"score_spread":0.22648813408847773,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2164114092","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21794432,0.00004073985,0.7669339,0.0000029446658,0.000014941609,0.00026810964,0.0000068582444,0.00008161767,0.01470658],"genre_scores_gemma":[0.99333227,0.0000036223048,0.006498453,0.0000070428655,0.0000039660035,0.000054188116,0.0000031573722,0.000012648497,0.00008463945],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994553,0.000008061729,0.00018636166,0.000085422136,0.00013569223,0.00012921575],"domain_scores_gemma":[0.99975413,0.000023382316,0.000011925713,0.000098637945,0.00008816502,0.000023753508],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005539841,0.00006751186,0.0001093638,0.0000793461,0.000007810124,0.000009252241,0.00004299103,0.00006552287,0.000027850743],"category_scores_gemma":[0.00005554844,0.00006643497,0.000035962177,0.00011900628,0.000012258853,0.00007351374,0.0000020031916,0.00004232788,9.679198e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005568371,0.00014634838,0.00064189493,0.00012513257,0.000035892634,4.6266496e-7,0.0003711839,0.7415104,0.18970218,0.05710502,0.0004402213,0.009915735],"study_design_scores_gemma":[0.0005257325,0.000013006456,0.0003909943,0.00000816615,0.000014598234,0.0000010125173,0.0000133740305,0.938183,0.0555112,0.0052551557,0.0000095034,0.00007423797],"about_ca_topic_score_codex":0.000004978897,"about_ca_topic_score_gemma":0.00003211276,"teacher_disagreement_score":0.77538794,"about_ca_system_score_codex":0.00004838902,"about_ca_system_score_gemma":0.000036958412,"threshold_uncertainty_score":0.27091396},"labels":[],"label_agreement":null},{"id":"W2164340799","doi":"10.1109/fpl.2013.6645503","title":"Titan: Enabling large and complex benchmarks in academic CAD","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":133,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Stratix; Field-programmable gate array; Computer science; Benchmark (surveying); Titan (rocket family); Computer architecture; CAD; Architecture; Electronic design automation; Parallel computing; Software; Embedded system; Operating system; Engineering","score_opus":0.01999264766098574,"score_gpt":0.24533398569114792,"score_spread":0.22534133803016218,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2164340799","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8029617,0.0029264754,0.032254566,0.00029583686,0.00014731681,0.00070064206,0.0000068654335,0.0013212074,0.15938537],"genre_scores_gemma":[0.9972026,0.00027722577,0.0021655322,0.0001118453,0.00002811874,0.000023504805,0.0000067046094,0.00001221029,0.00017230467],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995386,0.0000069374464,0.00012464146,0.00008474801,0.000047952417,0.0001971071],"domain_scores_gemma":[0.99984324,0.000023500766,0.000006219756,0.000074232375,0.000008674097,0.000044125787],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000090594134,0.00007757781,0.00009652853,0.00008266863,0.000016047974,0.00001870061,0.00006486808,0.000102650534,0.0009335221],"category_scores_gemma":[0.0000073193196,0.000070898415,0.00001086466,0.00008260859,0.000009497797,0.00015371121,0.000023921497,0.00020074351,0.00003673562],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000045359257,0.000059201542,0.066086195,0.0003810252,0.00005568461,0.000026532478,0.0026397735,0.00032730878,0.4652727,0.027945314,0.34152946,0.09567229],"study_design_scores_gemma":[0.0017688671,0.00012211557,0.19309926,0.00024946776,0.000019962003,0.000042657586,0.0010701054,0.57563764,0.044992916,0.020163396,0.16109286,0.0017407719],"about_ca_topic_score_codex":0.000081113016,"about_ca_topic_score_gemma":0.000027485867,"teacher_disagreement_score":0.5753103,"about_ca_system_score_codex":0.00001994448,"about_ca_system_score_gemma":0.0000022632228,"threshold_uncertainty_score":0.99997973},"labels":[],"label_agreement":null},{"id":"W2165102380","doi":"10.1109/iscas.1990.112038","title":"On the design of a parallel algorithm for VLSI layout compaction","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Dual (grammatical number); Shortest path problem; Very-large-scale integration; Computation; Path (computing); Graph; Graph theory; Algorithm; Mathematical optimization; Theoretical computer science; Parallel computing; Mathematics; Programming language","score_opus":0.05215500958859865,"score_gpt":0.22709906953688572,"score_spread":0.17494405994828707,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2165102380","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00024825567,0.00005757595,0.99178505,0.000056772533,0.000039463237,0.00032571645,0.000004019687,0.0002938086,0.007189328],"genre_scores_gemma":[0.83363336,0.00006350581,0.16516696,0.00012151619,0.00004692918,0.00011417943,0.000001921091,0.000026853788,0.00082475913],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999685,0.000013008013,0.00009445686,0.000051949544,0.000059293252,0.00009627527],"domain_scores_gemma":[0.9996805,0.00015852619,0.000012876201,0.00011512104,0.000016656568,0.000016286964],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000094466675,0.00006757886,0.00008294237,0.00003126896,0.000025017818,0.000008427752,0.000069724716,0.00003938559,0.00019390376],"category_scores_gemma":[0.000008524366,0.00004374209,0.000038731294,0.000049771515,0.000011487064,0.000033744738,0.0000027026033,0.00004855923,0.000019731688],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016691958,0.0001644582,0.000010096593,0.000060880942,0.00014276196,0.0000017073958,0.0006389112,0.05794301,0.014852654,0.023593467,0.5187026,0.38387275],"study_design_scores_gemma":[0.00011983691,0.00010941621,0.000011199595,0.000009343574,0.0000061274445,0.0000013306906,0.000021544272,0.97475874,0.021463202,0.0022445885,0.0011873227,0.000067346125],"about_ca_topic_score_codex":0.000004261974,"about_ca_topic_score_gemma":3.56319e-7,"teacher_disagreement_score":0.91681576,"about_ca_system_score_codex":0.000014712514,"about_ca_system_score_gemma":9.797598e-7,"threshold_uncertainty_score":0.21231101},"labels":[],"label_agreement":null},{"id":"W2165433638","doi":"10.1109/mwscas.1996.594197","title":"An efficient interior point approach for QP and LP models of the relative placement problem","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Interior point method; Quadratic programming; Linear programming; Mathematical optimization; Point (geometry); Computer science; Graph; Quadratic equation; Iterative method; Algorithm; Mathematics; Theoretical computer science; Geometry","score_opus":0.022457155257393082,"score_gpt":0.2085352540782423,"score_spread":0.18607809882084922,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2165433638","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.015411357,0.00010526294,0.96129763,0.00001933163,0.000014544102,0.00070374476,0.000006196715,0.00015702037,0.022284938],"genre_scores_gemma":[0.91049826,0.000008817388,0.089155436,0.000013765248,0.0000064388937,0.00009607293,0.0000010330189,0.0000132722125,0.0002069359],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99958813,0.000011344718,0.00013639785,0.000099958634,0.00006291009,0.000101234386],"domain_scores_gemma":[0.9997775,0.000014604448,0.00001906162,0.00014363264,0.000019928224,0.00002527533],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010859532,0.0000797767,0.0000954957,0.000028810866,0.000026145293,0.000010675971,0.000081384045,0.000038844406,0.000019312263],"category_scores_gemma":[0.0000023958357,0.000051076633,0.000032720036,0.000046711477,0.000024286075,0.00006826939,0.000021491891,0.00005253601,3.2370068e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004811303,0.0004618045,0.00008841077,0.00078824005,0.00019611948,4.9191044e-7,0.019239018,0.7799736,0.06583829,0.10352177,0.008720652,0.021123465],"study_design_scores_gemma":[0.00016130363,0.00010580806,0.000008281872,0.000018975135,0.000009201294,0.0000014975284,0.00013964983,0.97227377,0.025926318,0.0012371016,0.000045602057,0.00007249232],"about_ca_topic_score_codex":0.0000032550017,"about_ca_topic_score_gemma":7.5655163e-7,"teacher_disagreement_score":0.8950869,"about_ca_system_score_codex":0.0000239719,"about_ca_system_score_gemma":0.0000014512074,"threshold_uncertainty_score":0.20828447},"labels":[],"label_agreement":null},{"id":"W2165602035","doi":"10.1109/ccece.2004.1345063","title":"Global routing for VLSI standard cells","year":2004,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Speedup; Routing (electronic design automation); Very-large-scale integration; Parallel computing; Integer programming; Heuristic; Path (computing); Linear programming; Set (abstract data type); Computation; Integer (computer science); Mathematical optimization; Algorithm; Mathematics; Embedded system; Computer network","score_opus":0.007696700446813141,"score_gpt":0.22452739007306344,"score_spread":0.2168306896262503,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2165602035","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008247079,0.000052165316,0.9579623,0.000028967654,0.00012688416,0.00017224083,0.00002894688,0.0012413517,0.032140076],"genre_scores_gemma":[0.93016464,0.000010184947,0.06960214,0.000050519575,0.00005975288,0.000015516394,0.0000023533892,0.000013803039,0.000081091035],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99959654,0.0000015726114,0.000095916206,0.00007507913,0.00005884054,0.00017203316],"domain_scores_gemma":[0.9998436,0.000008309593,0.000006413023,0.00008679058,0.000018774612,0.000036139325],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006507281,0.000075283315,0.000083666346,0.000013629746,0.000027589678,0.000024624713,0.00006701395,0.00004935943,0.000023569175],"category_scores_gemma":[0.000004765515,0.000069884874,0.00004302803,0.00006437724,0.000006934185,0.000056386263,0.000008060425,0.000027171773,0.00001224159],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007483226,0.000094809766,0.0010603295,0.0004707391,0.00022500807,0.00003506415,0.00072511897,0.15192962,0.140606,0.3329275,0.12024975,0.25160122],"study_design_scores_gemma":[0.0010816978,0.00020367345,0.00011901506,0.00005056437,0.00002055851,0.000007969714,0.000075224845,0.007572841,0.918316,0.039397318,0.032681145,0.00047396813],"about_ca_topic_score_codex":0.000012281537,"about_ca_topic_score_gemma":0.0000116258025,"teacher_disagreement_score":0.92191756,"about_ca_system_score_codex":0.000120446304,"about_ca_system_score_gemma":0.000010817271,"threshold_uncertainty_score":0.28498223},"labels":[],"label_agreement":null},{"id":"W2165921360","doi":"10.1109/cicc.1990.124814","title":"The effect of switch box flexibility on routability of field programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":28,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Flexibility (engineering); Field-programmable gate array; Routing (electronic design automation); Interconnection; Computer science; Channel (broadcasting); Gate array; Set (abstract data type); Logic gate; Field (mathematics); Logic synthesis; Embedded system; Engineering; Algorithm; Computer network; Mathematics","score_opus":0.011321006485805227,"score_gpt":0.22671275671378524,"score_spread":0.21539175022798002,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2165921360","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.89515,0.00029748218,0.024635542,0.00009983425,0.00013100632,0.0010076505,0.0000045048905,0.0007758401,0.077898115],"genre_scores_gemma":[0.9990762,0.000032510205,0.0006266813,0.0000069176235,0.00001305608,0.00004027519,4.545171e-7,0.000010553086,0.00019338945],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99927694,0.000051448336,0.00024870396,0.000118431824,0.00012868375,0.00017576755],"domain_scores_gemma":[0.99903977,0.0004081267,0.000030503716,0.00046504833,0.000025751855,0.000030790135],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00051169755,0.00011217549,0.00020254297,0.00002052582,0.00003206694,0.0000101893465,0.00015523417,0.00007597298,0.00013892642],"category_scores_gemma":[0.000106187006,0.000067141686,0.000096887525,0.00011575887,0.0000420819,0.00004215206,0.000015772383,0.00012974255,0.0000080974705],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00034127466,0.00039916942,0.035378885,0.0021537223,0.00025253734,0.0000038518933,0.0008803705,0.0051560104,0.08647458,0.0029769095,0.010689366,0.85529333],"study_design_scores_gemma":[0.00015968834,0.00088114117,0.00034457495,0.000023200735,0.000010411422,5.433034e-7,0.000009478511,0.017191965,0.97984093,0.0005522408,0.0008986042,0.000087227716],"about_ca_topic_score_codex":0.00005183637,"about_ca_topic_score_gemma":0.000017251114,"teacher_disagreement_score":0.89336634,"about_ca_system_score_codex":0.000020458696,"about_ca_system_score_gemma":0.000001828938,"threshold_uncertainty_score":0.27379584},"labels":[],"label_agreement":null},{"id":"W2166086163","doi":"10.1109/icvd.1993.669687","title":"Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and A Unified Approach to VLSI Layout Compaction and Wire Balancing","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Initialization; Computer science; Dual (grammatical number); Parallel computing; Very-large-scale integration; Benchmark (surveying); Mathematical optimization; Multiprocessing; Constraint (computer-aided design); Graph; Algorithm; Theoretical computer science; Mathematics; Embedded system","score_opus":0.019789919869932726,"score_gpt":0.25215277749692183,"score_spread":0.2323628576269891,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2166086163","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07967799,0.0004118904,0.8838156,0.00016144318,0.000055579072,0.00082087226,0.00000903889,0.0015893175,0.0334583],"genre_scores_gemma":[0.6528041,0.000021203796,0.3464852,0.00024357087,0.00014423124,0.00004713385,0.000009167775,0.000028923223,0.00021652813],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99911493,0.000034116045,0.00018649438,0.00026593122,0.000118151984,0.00028038555],"domain_scores_gemma":[0.99960184,0.0000659933,0.000023403249,0.00014375901,0.00002439045,0.00014063712],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002590287,0.00020306467,0.00024855803,0.0000809907,0.000079393736,0.00007109763,0.000060833518,0.00011445478,0.000013080087],"category_scores_gemma":[0.000015383413,0.00018130279,0.000023809409,0.00014672674,0.000013420505,0.00017535605,0.000029235196,0.00017474171,0.000005493517],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00033428083,0.00022888085,0.0013577609,0.0006310757,0.00023115163,0.000010087131,0.0070025385,0.6585794,0.027231013,0.0025853617,0.025015105,0.27679336],"study_design_scores_gemma":[0.0008700777,0.00012801602,0.0048349514,0.000090057045,0.000032254527,0.000043825894,0.0003668899,0.9841845,0.006352415,0.00011874015,0.002479647,0.000498606],"about_ca_topic_score_codex":0.000030081002,"about_ca_topic_score_gemma":0.000021340446,"teacher_disagreement_score":0.5731261,"about_ca_system_score_codex":0.000051018425,"about_ca_system_score_gemma":0.0000070793853,"threshold_uncertainty_score":0.7393313},"labels":[],"label_agreement":null},{"id":"W2166289398","doi":"10.1109/fpt.2009.5377668","title":"Self-hosted placement for massively parallel processor arrays","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Placer mining; Massively parallel; Computer science; Parallel computing; Simulated annealing; Placement; Workstation; Computational science; Physical design; Algorithm; Integrated circuit; Geology; Operating system","score_opus":0.011565182860145287,"score_gpt":0.22775225539301525,"score_spread":0.21618707253286995,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2166289398","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014755444,0.00012886594,0.95828104,0.00027300316,0.000056999826,0.0008003788,0.0000055437495,0.0031416859,0.035836935],"genre_scores_gemma":[0.70036155,0.00007788657,0.29764697,0.00034566328,0.0000957594,0.0002441528,0.000015474967,0.000032581487,0.0011799829],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994388,0.0000033645874,0.00014222894,0.0001177477,0.00007949527,0.00021837054],"domain_scores_gemma":[0.99977195,0.000016353515,0.000015250837,0.00010927965,0.000035871493,0.00005129524],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000060797192,0.00012307442,0.0001184328,0.00004719912,0.000034248562,0.000025300049,0.00010118853,0.00006708701,0.000037564303],"category_scores_gemma":[0.0000062001764,0.00010742584,0.000041557727,0.000073741816,0.000003862558,0.00008340261,0.0000041375324,0.000053233416,0.000018444436],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00026439643,0.00087130454,0.0002452392,0.0016779606,0.0004878357,0.000030300167,0.0030388741,0.017767554,0.16300835,0.050370537,0.6431588,0.11907886],"study_design_scores_gemma":[0.003071095,0.0015464709,0.00068495056,0.00009654651,0.00009665409,0.000015322697,0.00027599596,0.3266676,0.43546358,0.0150206,0.21551606,0.0015451451],"about_ca_topic_score_codex":4.4985202e-7,"about_ca_topic_score_gemma":7.0910795e-7,"teacher_disagreement_score":0.698886,"about_ca_system_score_codex":0.0000399092,"about_ca_system_score_gemma":0.000009440354,"threshold_uncertainty_score":0.43806985},"labels":[],"label_agreement":null},{"id":"W2166604263","doi":"10.1109/ipdps.2013.50","title":"Multi-threaded Graph Partitioning","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":152,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Ministry of Economy, Trade and Industry; National Science Foundation","keywords":"Computer science; Parallel computing; Thread (computing); Speedup; Graph partition; Threading (protein sequence); Graph; Synchronization (alternating current); Multithreading; Theoretical computer science; Distributed computing; Programming language","score_opus":0.01698447838718365,"score_gpt":0.20653044797419595,"score_spread":0.1895459695870123,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2166604263","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06797847,0.00020289242,0.8765237,0.000071051436,0.00013508525,0.00028540773,0.0000011442154,0.004378212,0.050424032],"genre_scores_gemma":[0.9564337,0.00002376929,0.042890605,0.00006020254,0.000021943752,0.000079359605,0.0000024963329,0.000014130438,0.00047377113],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999697,0.000003885198,0.00007898263,0.00005669855,0.000038216658,0.00012520138],"domain_scores_gemma":[0.9998406,0.000008271905,0.000004336293,0.00009317431,0.000014914877,0.000038695624],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000024969993,0.000060064143,0.000055062923,0.000039904033,0.000023120427,0.000030370187,0.000049386334,0.000038621758,0.00084960763],"category_scores_gemma":[0.0000031537031,0.000053140033,0.000025190402,0.00006636637,0.000010422119,0.00013788478,0.0000059072718,0.000052639614,0.00048625842],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[9.743923e-7,0.00008293591,0.0063666333,0.0000896442,0.000088686116,0.000007597047,0.00052051444,0.0017375728,0.6961716,0.0061255833,0.21339948,0.07540882],"study_design_scores_gemma":[0.0006089725,0.00006520934,0.02886036,0.000057467772,0.000017141947,0.000014687744,0.00021754132,0.2073717,0.74027,0.013903166,0.007761291,0.00085243996],"about_ca_topic_score_codex":0.00004383759,"about_ca_topic_score_gemma":0.000005814992,"teacher_disagreement_score":0.8884553,"about_ca_system_score_codex":0.000007832078,"about_ca_system_score_gemma":0.0000011399042,"threshold_uncertainty_score":0.9302608},"labels":[],"label_agreement":null},{"id":"W2167561823","doi":"10.1109/cicc.2001.929727","title":"A novel FPGA architecture supporting wide shallow memories","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Field-programmable gate array; Block (permutation group theory); Routing (electronic design automation); Degradation (telecommunications); Logic block; Architecture; Megabit; Computer hardware; Path (computing); Memory architecture; Embedded system; Chip; Computer architecture; Computer network; Telecommunications","score_opus":0.015370271547065278,"score_gpt":0.2058589559590611,"score_spread":0.19048868441199582,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2167561823","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017962134,0.00028915136,0.78791755,0.00034797125,0.00016272621,0.00020063689,0.000007317383,0.003674567,0.18943797],"genre_scores_gemma":[0.9591304,0.000027130454,0.038178094,0.00021524957,0.0000950996,0.000020378133,0.000003053901,0.00004026882,0.0022903192],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99928784,0.000004432076,0.00018320263,0.00012964198,0.00011268002,0.00028220325],"domain_scores_gemma":[0.9996728,0.000044271812,0.000016882304,0.00018553849,0.00001540374,0.00006511017],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00007372987,0.00014508826,0.00013987851,0.000072677845,0.000040901705,0.000038396265,0.00013510132,0.00007743083,0.0010879866],"category_scores_gemma":[0.00003706619,0.00012690082,0.000058980215,0.00012352125,0.000021341557,0.00008801594,0.000021520193,0.00016744336,0.000068718924],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008034179,0.0001832755,0.003404243,0.00044623957,0.00023089355,0.00012932968,0.0055706617,0.008592576,0.38109925,0.003213456,0.15459333,0.44252872],"study_design_scores_gemma":[0.0010042118,0.00021873582,0.0023381459,0.00015239713,0.00006741315,0.00032314463,0.00042675232,0.1484335,0.69266033,0.0061283903,0.14623143,0.0020155534],"about_ca_topic_score_codex":0.00000879241,"about_ca_topic_score_gemma":0.000024598357,"teacher_disagreement_score":0.94116825,"about_ca_system_score_codex":0.00002024286,"about_ca_system_score_gemma":0.0000022422403,"threshold_uncertainty_score":0.9998252},"labels":[],"label_agreement":null},{"id":"W2167700307","doi":"10.1109/isqed.2007.159","title":"Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Field-programmable gate array; Simulated annealing; Temperature gradient; Thermal; Computer science; Placement; Annealing (glass); Chip; Algorithm; Electronic engineering; Materials science; Embedded system; Engineering; Physics; Physical design; Thermodynamics; Circuit design","score_opus":0.02636385647325473,"score_gpt":0.26769226260448264,"score_spread":0.2413284061312279,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2167700307","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.05162152,0.0000667073,0.94208723,0.000009464977,0.000035270565,0.00033292506,0.00000630125,0.000604812,0.005235765],"genre_scores_gemma":[0.9497889,0.000010985832,0.049413204,0.00011757589,0.00004645878,0.000028248223,0.000007956327,0.000044170425,0.00054245966],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993557,0.00000255098,0.00015096866,0.00009589187,0.00007532881,0.0003195867],"domain_scores_gemma":[0.9997801,0.000026182446,0.000012734285,0.00010903542,0.000025596806,0.000046321005],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019867542,0.000111666144,0.00010136672,0.000066441375,0.00004111011,0.000015352278,0.00006849338,0.000052790423,0.000060212642],"category_scores_gemma":[0.0000031753107,0.00010292841,0.000042483825,0.00005721224,0.0000059650924,0.000071854396,0.000007524486,0.00005699265,0.0000071101063],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000024810237,0.00003653173,0.000034730907,0.00015485025,0.000052650914,0.0000030886881,0.00034553904,0.1423769,0.8408584,0.0034018117,0.005362223,0.0073484415],"study_design_scores_gemma":[0.0001167121,0.0000219333,0.0000028052516,0.0000080519585,0.0000069880225,8.927059e-7,0.000012536549,0.69043505,0.3088426,0.00024689263,0.0002018814,0.00010367916],"about_ca_topic_score_codex":0.0000038146864,"about_ca_topic_score_gemma":0.0000035226428,"teacher_disagreement_score":0.89816743,"about_ca_system_score_codex":0.000087573935,"about_ca_system_score_gemma":0.000009996802,"threshold_uncertainty_score":0.4197299},"labels":[],"label_agreement":null},{"id":"W2167788667","doi":"10.1109/iwsoc.2005.29","title":"A structure based clustering algorithm with applications to VLSI physical design","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Cluster analysis; Benchmark (surveying); Computer science; Very-large-scale integration; Suite; Algorithm; Algorithm design; Canopy clustering algorithm; Correlation clustering; Data mining; Artificial intelligence","score_opus":0.00938799234256803,"score_gpt":0.22388603059894352,"score_spread":0.21449803825637548,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2167788667","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00060474273,0.000011908711,0.9960464,0.000080847654,0.0000076002516,0.0004448873,0.000008416558,0.0011215258,0.0016736479],"genre_scores_gemma":[0.40780926,6.039977e-7,0.59168345,0.00015043166,0.00013269938,0.00013784018,0.0000032932787,0.00002540392,0.000056996436],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994992,0.0000070666542,0.000078863886,0.00013946931,0.000098482844,0.00017691548],"domain_scores_gemma":[0.99965835,0.000020653928,0.000007013393,0.00020389579,0.000022250455,0.00008783509],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000027856431,0.00012942027,0.00010905438,0.00006422987,0.000036843005,0.0000309296,0.00011634743,0.000041585467,0.00005531971],"category_scores_gemma":[9.850869e-7,0.00010398272,0.000021584256,0.00018568902,0.000009781459,0.000075695316,0.000011360339,0.00009176983,0.000035587847],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005889984,0.000032844404,0.000005369555,0.000022172488,0.000021434209,0.0000019549898,0.00015970237,0.31428316,0.04600615,0.00020723352,0.0028388049,0.6364153],"study_design_scores_gemma":[0.00012542984,0.000059623693,0.00002811532,0.000009597113,0.000009108892,0.0000048861284,0.000009345825,0.8247288,0.1645013,0.00010892971,0.010222545,0.00019233233],"about_ca_topic_score_codex":0.0000028676516,"about_ca_topic_score_gemma":0.000009267255,"teacher_disagreement_score":0.63622296,"about_ca_system_score_codex":0.000047165253,"about_ca_system_score_gemma":0.000009870839,"threshold_uncertainty_score":0.42402923},"labels":[],"label_agreement":null},{"id":"W2167812696","doi":"10.1109/iscas.1998.705260","title":"Utility function based hybrid algorithm for channel routing","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Tabu search; Computer science; Router; Routing (electronic design automation); Algorithm; Mathematical optimization; Benchmark (surveying); Channel (broadcasting); Convergence (economics); Heuristic; Graph; Theoretical computer science; Mathematics; Artificial intelligence","score_opus":0.02601384334861889,"score_gpt":0.2032406609655718,"score_spread":0.17722681761695291,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2167812696","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00030494123,0.00007674454,0.98665607,0.000028757844,0.00017207213,0.00020669072,0.000012689894,0.0015121344,0.011029914],"genre_scores_gemma":[0.9662222,0.000006251475,0.033029262,0.000097783806,0.00011446367,0.000050979776,0.000011200096,0.000023102173,0.00044470432],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99953,0.0000060124644,0.00011590459,0.00011170247,0.000058245132,0.00017809967],"domain_scores_gemma":[0.99977076,0.000032750042,0.000009899126,0.00012495,0.000025066609,0.000036552872],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010200754,0.00009128221,0.000088266206,0.00004175596,0.000052168758,0.000018372248,0.000049871054,0.000040751416,0.0003191316],"category_scores_gemma":[0.000009417979,0.00008871015,0.000056792753,0.00005675614,0.0000070405754,0.000080320126,0.0000048584207,0.000057861,0.000024863104],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000024288336,0.000035572877,0.000023892511,0.000043572738,0.000019093797,0.0000014318317,0.00002504446,0.0003164338,0.0011841927,0.00012972696,0.05040749,0.9478111],"study_design_scores_gemma":[0.00015156792,0.00003610172,0.00005673891,0.0000059022277,0.0000075060116,0.000001140815,0.0000073233314,0.95191956,0.04126229,0.00031883662,0.0061254227,0.000107623484],"about_ca_topic_score_codex":0.0000057652355,"about_ca_topic_score_gemma":0.0000010638297,"teacher_disagreement_score":0.9659173,"about_ca_system_score_codex":0.000017266599,"about_ca_system_score_gemma":0.0000015184617,"threshold_uncertainty_score":0.3617495},"labels":[],"label_agreement":null},{"id":"W2167881201","doi":"10.1109/ccece.2008.4564673","title":"An effective congestion-based integer programming model for VLSI global routing","year":2008,"lang":"en","type":"article","venue":"Conference proceedings - Canadian Conference on Electrical and Computer Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Integer programming; Computer science; Very-large-scale integration; Routing (electronic design automation); Router; Parallel computing; Steiner tree problem; Mathematical optimization; Algorithm; Computer network; Mathematics; Embedded system","score_opus":0.01575072268814795,"score_gpt":0.21224252778328503,"score_spread":0.19649180509513708,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2167881201","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08565686,0.000055679364,0.9120183,0.00007791239,0.000097300355,0.0007822089,0.000023520934,0.00092788425,0.00036033173],"genre_scores_gemma":[0.9819068,0.000021452517,0.017376842,0.000134715,0.00013403056,0.0003538621,0.000017562545,0.000046234294,0.000008543023],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982219,0.000006693775,0.00027692845,0.0005009402,0.00016864686,0.00082493864],"domain_scores_gemma":[0.9988043,0.00005696486,0.000039513547,0.00011950891,0.00032318322,0.00065653515],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00013325374,0.00042535702,0.00038243437,0.00026048237,0.00020579326,0.0002499085,0.00029700188,0.00024003307,0.0000048769593],"category_scores_gemma":[0.000040398678,0.00044818784,0.00007019105,0.00034138662,0.000060024853,0.0002776967,0.00001443094,0.00038880503,0.0000025212396],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010345917,0.00016980896,0.008232769,0.0005797764,0.00020310278,0.00006189105,0.0019811115,0.12791161,0.004910947,0.20409977,0.0010297633,0.650716],"study_design_scores_gemma":[0.0003344261,0.00043645498,0.0015808234,0.0001422756,0.000017885872,0.000032157415,0.000009820602,0.9954714,0.00076488365,0.0005183145,0.00014248157,0.0005490508],"about_ca_topic_score_codex":0.00039492402,"about_ca_topic_score_gemma":0.00025506245,"teacher_disagreement_score":0.8962499,"about_ca_system_score_codex":0.0003437731,"about_ca_system_score_gemma":0.00025019262,"threshold_uncertainty_score":0.999797},"labels":[],"label_agreement":null},{"id":"W2168380569","doi":"10.1016/s0377-0427(00)00399-x","title":"Refining an approximate inverse","year":2000,"lang":"en","type":"article","venue":"Journal of Computational and Applied Mathematics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Preconditioner; Robustness (evolution); Factorization; Computation; Mathematics; Inverse; Exploit; Graph; Algorithm; Incomplete LU factorization; Iterative method; Mathematical optimization; Computer science; Matrix decomposition; Discrete mathematics","score_opus":0.015247306102368558,"score_gpt":0.22310895216774512,"score_spread":0.20786164606537658,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2168380569","genre_codex":"empirical","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7130779,0.00009393823,0.2648826,0.000043846914,0.000038892933,0.00006534554,0.0000035449257,0.00015625443,0.02163772],"genre_scores_gemma":[0.4635236,0.000035335033,0.53624153,0.000059879807,0.00007363844,0.0000018205812,0.0000022646589,0.000015572032,0.00004633975],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994955,0.0000031963712,0.00026327636,0.000036305275,0.00013210678,0.00006959664],"domain_scores_gemma":[0.9997785,0.000040092025,0.000056959958,0.00003890673,0.00002857836,0.0000569534],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014774865,0.00007286684,0.00014261971,0.00005371072,0.000029915616,0.000029555655,0.00006030329,0.000032060143,0.00005842062],"category_scores_gemma":[0.0000018864124,0.000060962142,0.000022821341,0.000050690433,0.000019148247,0.00009559751,0.000004267879,0.000096492295,0.0000058674505],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000038003567,0.00027244698,0.000020564945,0.00051156076,0.00014394814,0.000025005089,0.004309328,0.56627196,0.0073239147,0.09087924,0.004727345,0.32547668],"study_design_scores_gemma":[0.00079258456,0.000156243,0.00017346222,0.00013242714,0.000054263714,0.000493246,0.0003144967,0.5801967,0.003005732,0.41003495,0.0043118014,0.00033412027],"about_ca_topic_score_codex":1.0748519e-7,"about_ca_topic_score_gemma":8.280852e-8,"teacher_disagreement_score":0.32514253,"about_ca_system_score_codex":0.000009204942,"about_ca_system_score_gemma":0.000007971245,"threshold_uncertainty_score":0.2485964},"labels":[],"label_agreement":null},{"id":"W2169476075","doi":"10.1109/fpt.2009.5377689","title":"Congestion-driven regional re-clustering for low-cost FPGAs","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Interconnection; Computer science; Cluster analysis; Channel (broadcasting); White spaces; Constraint (computer-aided design); Implementation; Parallel computing; Selection (genetic algorithm); Embedded system; Computer engineering; Computer network; Engineering; Operating system","score_opus":0.026827795946442155,"score_gpt":0.25071521453288237,"score_spread":0.2238874185864402,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2169476075","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004721705,0.000094012714,0.96671146,0.0005622499,0.00014664732,0.0005388474,0.000007832903,0.0017806741,0.025436545],"genre_scores_gemma":[0.96768814,0.000059748105,0.03079584,0.0004240354,0.0001711835,0.000062111874,0.000022924416,0.00002364989,0.0007523347],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994967,0.0000042538522,0.00013356359,0.00011276093,0.000068748974,0.0001839486],"domain_scores_gemma":[0.9997341,0.000035277662,0.0000119479,0.00013479305,0.000030198034,0.00005365677],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005620763,0.00010509129,0.0001081972,0.000055475102,0.000039106224,0.00002672584,0.000097421485,0.00007712455,0.00007078801],"category_scores_gemma":[0.000009698102,0.00010254377,0.00005067917,0.000056840505,0.000010574,0.00010186113,0.0000062870195,0.000067762805,0.000021653626],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007244375,0.000105383726,0.00021660188,0.00022332199,0.000086697524,0.000022384967,0.0005318654,0.07763985,0.0874306,0.01695447,0.5299632,0.2867532],"study_design_scores_gemma":[0.0013220009,0.00031924975,0.0037454148,0.0002599492,0.00003819008,0.00004442765,0.000082893835,0.7843027,0.06114151,0.008958633,0.13869627,0.0010887346],"about_ca_topic_score_codex":0.0000029213272,"about_ca_topic_score_gemma":0.000010733363,"teacher_disagreement_score":0.96296644,"about_ca_system_score_codex":0.000038807233,"about_ca_system_score_gemma":0.000005797169,"threshold_uncertainty_score":0.41816136},"labels":[],"label_agreement":null},{"id":"W2171697180","doi":"10.1109/glsv.1995.516024","title":"Optimizing wiring space in slicing floorplans","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Floorplan; Slicing; Computer science; Heuristic; Space (punctuation); Integrated circuit layout; Mirroring; Branch and bound; Mathematical optimization; Topology (electrical circuits); Algorithm; Parallel computing; Mathematics; Integrated circuit; Embedded system; Combinatorics; Artificial intelligence","score_opus":0.01400861194722146,"score_gpt":0.18702510514803822,"score_spread":0.17301649320081675,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2171697180","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18691465,0.0009808578,0.33214787,0.00015059102,0.0001769766,0.00021851608,0.0000010953103,0.0032476033,0.4761618],"genre_scores_gemma":[0.975575,0.00013852204,0.023656044,0.00003591181,0.00003620881,0.000008353439,4.2811146e-7,0.00002340129,0.0005261737],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99952847,0.0000058930873,0.00011431717,0.000089115485,0.000057358262,0.00020482318],"domain_scores_gemma":[0.99982417,0.000018218849,0.000005775128,0.000114220966,0.0000044799144,0.000033152148],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006346119,0.00008941682,0.000099872006,0.00011629783,0.00001765478,0.000021992751,0.00007539415,0.000051720282,0.00026476113],"category_scores_gemma":[0.000005158118,0.000090724694,0.000021680555,0.00014532568,0.0000058395576,0.00011913852,0.000012681488,0.0001257336,0.000070131326],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000059706317,0.00018459542,0.01356998,0.00042428766,0.000096424206,0.00039857085,0.013807539,0.4101241,0.3813447,0.009447767,0.052397262,0.118198805],"study_design_scores_gemma":[0.00023932023,0.00001973729,0.00044191873,0.00010299288,0.000004225554,0.0000162667,0.00016132853,0.8948407,0.10010115,0.0001336605,0.003590874,0.00034778405],"about_ca_topic_score_codex":0.000033199558,"about_ca_topic_score_gemma":0.0000333176,"teacher_disagreement_score":0.7886603,"about_ca_system_score_codex":0.000041500378,"about_ca_system_score_gemma":6.914913e-7,"threshold_uncertainty_score":0.36996457},"labels":[],"label_agreement":null},{"id":"W2172056907","doi":"10.1109/ccece.2011.6030638","title":"Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Parallel computing; Field-programmable gate array; Very-large-scale integration; Algorithm; Routing (electronic design automation); Exploit; Embedded system","score_opus":0.2045496872603078,"score_gpt":0.3211113345375101,"score_spread":0.11656164727720231,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2172056907","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.475325,0.000007908726,0.5217216,0.000007806115,0.00004035213,0.00068128144,0.000014186204,0.00084010646,0.0013617846],"genre_scores_gemma":[0.65535456,0.0000041110366,0.34434295,0.000105246014,0.000026278734,0.00006680661,0.00000383214,0.00005273685,0.0000434672],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99918884,0.000011673475,0.00015249112,0.00018734763,0.000100164616,0.00035945512],"domain_scores_gemma":[0.9995138,0.000024494442,0.000008923455,0.0002232734,0.00008950455,0.0001399846],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000101672325,0.00018007556,0.00018215892,0.00011277633,0.000080228536,0.00009309961,0.00015700255,0.000059044425,0.000117134914],"category_scores_gemma":[0.0000050646745,0.00014440293,0.000030346731,0.0001836617,0.000021151116,0.0003722891,0.000032280244,0.000085590655,0.000019774056],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00093975436,0.0005421085,0.03333846,0.0012123525,0.0009091825,0.0002084418,0.014125303,0.05591062,0.6609264,0.014129315,0.028920155,0.18883792],"study_design_scores_gemma":[0.00044982077,0.00037454537,0.002859624,0.00007235158,0.00002900851,0.000020986063,0.00007814077,0.50093526,0.49295855,0.000067077315,0.001554843,0.00059978163],"about_ca_topic_score_codex":0.00030159403,"about_ca_topic_score_gemma":0.00003603344,"teacher_disagreement_score":0.44502464,"about_ca_system_score_codex":0.000046863293,"about_ca_system_score_gemma":0.000015421692,"threshold_uncertainty_score":0.58885807},"labels":[],"label_agreement":null},{"id":"W2172219312","doi":"10.1109/newcas.2004.1359038","title":"Performance of probabilistic approaches to Steiner tree problem","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Heuristics; Computer science; Probabilistic logic; Heuristic; Class (philosophy); Tree (set theory); Mathematical optimization; Automation; Theoretical computer science; Algorithm; Artificial intelligence; Mathematics; Engineering; Combinatorics","score_opus":0.06073061505041603,"score_gpt":0.22675602689848376,"score_spread":0.16602541184806774,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2172219312","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.97115266,0.0034281958,0.0075213914,0.00035318307,0.00064224587,0.0029482616,0.00016045863,0.0007664237,0.013027194],"genre_scores_gemma":[0.9980541,0.00008924251,0.00011695108,0.00005310967,0.00036618445,0.00021980295,0.000010054516,0.000095271134,0.0009952743],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99761003,0.000084659485,0.00074234273,0.00045379557,0.00046813465,0.00064100605],"domain_scores_gemma":[0.99876577,0.00009740206,0.0001295134,0.000641472,0.00011708262,0.0002487402],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006191143,0.000495669,0.0006378069,0.00021164585,0.00019732738,0.000097081625,0.00042639798,0.00022040664,0.000008465794],"category_scores_gemma":[0.000018980445,0.00034907417,0.00010529983,0.00055120024,0.00014681295,0.00022153929,0.0000314193,0.0003842362,0.00004389082],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009242236,0.00032635464,0.00096827256,0.0014802628,0.00020471169,0.000022720631,0.006452213,0.8958222,0.0012719458,0.003160803,0.0037849748,0.08641311],"study_design_scores_gemma":[0.041193116,0.028592017,0.051316313,0.073999055,0.0038989196,0.007091,0.07382948,0.4837556,0.046845697,0.012780179,0.13883004,0.037868608],"about_ca_topic_score_codex":0.00009615313,"about_ca_topic_score_gemma":0.00008290565,"teacher_disagreement_score":0.41206664,"about_ca_system_score_codex":0.0001340469,"about_ca_system_score_gemma":0.00006622601,"threshold_uncertainty_score":0.9998961},"labels":[],"label_agreement":null},{"id":"W2172234488","doi":"10.1145/1391469.1391671","title":"Automated transistor sizing for FPGA architecture exploration","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Sizing; Computer architecture; Routing (electronic design automation); Transistor; Architecture; Embedded system; Quality (philosophy); Logic synthesis; Logic gate; Engineering; Electrical engineering","score_opus":0.028053586477289134,"score_gpt":0.2232644264827875,"score_spread":0.19521084000549835,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2172234488","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009947861,0.00012486913,0.97857165,0.00007530479,0.00007922326,0.00025636712,0.0000049938426,0.007057982,0.0038817308],"genre_scores_gemma":[0.94607824,0.000039495815,0.05341867,0.000051299474,0.00006410036,0.000098893965,0.000016184078,0.000030014004,0.00020307982],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996269,0.0000052924424,0.00010777112,0.00008031628,0.000053358002,0.00012638998],"domain_scores_gemma":[0.99983335,0.00002320731,0.0000069872963,0.00008774802,0.000018195822,0.000030497773],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000035788595,0.00008594944,0.00008992601,0.000059859212,0.000057463025,0.000007776266,0.000051608546,0.000061313476,0.00001966272],"category_scores_gemma":[0.00000625873,0.00007850859,0.000046687215,0.00007410407,0.000011025911,0.00010804759,0.0000018584897,0.000050756575,0.000007568237],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000042787688,0.00007078431,0.000043508713,0.0003779179,0.000111971676,0.000022679094,0.0068464167,0.052695513,0.67525136,0.0012515812,0.13972224,0.12356324],"study_design_scores_gemma":[0.0004901545,0.00012535139,0.00013590211,0.000027229295,0.000017188928,0.000035695768,0.000063996806,0.30220857,0.64916444,0.001489856,0.04580673,0.00043489435],"about_ca_topic_score_codex":0.0000029967946,"about_ca_topic_score_gemma":0.0000057139705,"teacher_disagreement_score":0.9361304,"about_ca_system_score_codex":0.000022849636,"about_ca_system_score_gemma":0.000006108958,"threshold_uncertainty_score":0.32014874},"labels":[],"label_agreement":null},{"id":"W2173609013","doi":"10.1155/2008/736203","title":"The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units","year":2008,"lang":"en","type":"article","venue":"International Journal of Reconfigurable Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Engineering and Physical Sciences Research Council","keywords":"Field-programmable gate array; Computer science; Interface (matter); Parallel computing; Floating point; Routing (electronic design automation); Point (geometry); Embedded system; Algorithm; Mathematics; Geometry","score_opus":0.020211464836332294,"score_gpt":0.2426125445848633,"score_spread":0.22240107974853102,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2173609013","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.72537315,0.0017523014,0.2546256,0.0012420603,0.0019089845,0.00035376343,0.0000074183304,0.00032782863,0.01440892],"genre_scores_gemma":[0.99129415,0.00021449594,0.0079766,0.00007811128,0.00025397658,0.0000022026668,0.0000029714963,0.000037198435,0.0001402704],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99815917,0.00009402697,0.0008315205,0.0001512033,0.00043563853,0.00032845367],"domain_scores_gemma":[0.99818754,0.00049805356,0.00034619088,0.0001581505,0.0007231866,0.00008685551],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00082384335,0.0002325837,0.00032905908,0.0003384479,0.0001284485,0.00012318892,0.0007160466,0.00007938132,0.0000329145],"category_scores_gemma":[0.00031534553,0.00016634699,0.00008807068,0.00036552624,0.0000983728,0.00023414755,0.0000342294,0.0006395042,0.000008546077],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0006115009,0.00026878974,0.0036018912,0.000107931744,0.0013161452,0.0028783681,0.008771898,0.68819964,0.04109699,0.0031614825,0.015037059,0.23494828],"study_design_scores_gemma":[0.005630768,0.0012279508,0.0019349634,0.0029299315,0.000063565705,0.013701498,0.0027671766,0.8180308,0.13501522,0.005851903,0.011516637,0.0013296102],"about_ca_topic_score_codex":0.00002748809,"about_ca_topic_score_gemma":0.000037382957,"teacher_disagreement_score":0.26592106,"about_ca_system_score_codex":0.00020834687,"about_ca_system_score_gemma":0.00010530801,"threshold_uncertainty_score":0.6783433},"labels":[],"label_agreement":null},{"id":"W2180689556","doi":"10.1007/s00453-011-9540-3","title":"Approximation Algorithms and Hardness Results for Packing Element-Disjoint Steiner Trees in Planar Graphs","year":2011,"lang":"en","type":"article","venue":"Algorithmica","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":19,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Combinatorics; Disjoint sets; Planar graph; Mathematics; Approximation algorithm; Discrete mathematics; Graph","score_opus":0.030268888774087295,"score_gpt":0.22878516744079802,"score_spread":0.19851627866671073,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2180689556","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06507426,0.000918019,0.92162,0.00013950058,0.0006761128,0.0023420425,0.00039589257,0.0016897295,0.007144416],"genre_scores_gemma":[0.8589651,0.000133033,0.14024033,0.00003285516,0.0000937256,0.00029526593,0.00011193013,0.00005841042,0.00006935612],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99898607,0.000019674928,0.00034735777,0.00024490818,0.00010698185,0.00029502818],"domain_scores_gemma":[0.9996353,0.00003719557,0.000045845307,0.00018799736,0.000032684613,0.0000610161],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00029074244,0.00018307389,0.00021196768,0.00020902943,0.0000450986,0.000028962382,0.0001127567,0.00010631595,0.000005534758],"category_scores_gemma":[0.00001982319,0.00017683009,0.00004578249,0.00015542736,0.00003120848,0.00020040364,0.000017147413,0.00011297039,0.000002597385],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00025271287,0.00029204864,0.0010388736,0.0004198598,0.00025185675,0.00005741125,0.009376421,0.0001257467,0.026090544,0.009364454,0.011971599,0.94075847],"study_design_scores_gemma":[0.0074158106,0.0009235389,0.01574159,0.0004934729,0.00013079772,0.000051851504,0.0014997157,0.5737147,0.32917702,0.059207845,0.009550546,0.002093141],"about_ca_topic_score_codex":0.00006332905,"about_ca_topic_score_gemma":0.000039102637,"teacher_disagreement_score":0.93866533,"about_ca_system_score_codex":0.000036913927,"about_ca_system_score_gemma":0.000006686973,"threshold_uncertainty_score":0.72109216},"labels":[],"label_agreement":null},{"id":"W2184772890","doi":"","title":"A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs","year":2010,"lang":"en","type":"dissertation","venue":"TSpace (University of Toronto)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Computer science; Programmable Array Logic; Logic synthesis; Hierarchy; Computer architecture; Programmable logic device; Combinational logic; Data flow diagram; Parallel computing; Algorithm; Theoretical computer science; Computer engineering; Logic optimization; Logic gate; Embedded system","score_opus":0.009493425309748777,"score_gpt":0.22572680610396334,"score_spread":0.21623338079421456,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2184772890","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7866079,0.0049092947,0.18648556,0.000027631828,0.00064945786,0.0009891689,0.00015848933,0.00085652835,0.019315936],"genre_scores_gemma":[0.9100609,0.0009974311,0.08489918,0.0000051732072,0.000117301555,0.0000033493761,0.00048018788,0.000069862006,0.0033666503],"study_design_codex":"design_other","study_design_gemma":"qualitative","domain_scores_codex":[0.9994685,0.000012659088,0.00007039218,0.00017368852,0.00010075586,0.00017399764],"domain_scores_gemma":[0.9996484,0.00002348117,0.000057950372,0.00015360577,0.000047016445,0.00006953631],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007315351,0.00016729413,0.0002595932,0.000054659722,0.000092360715,0.000017491511,0.00013748274,0.0003684717,0.00036867685],"category_scores_gemma":[0.0000051414668,0.00022153731,0.00009942815,0.000021030004,0.00003144836,0.00020308542,0.00001533492,0.0002095595,0.0000014282657],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":true,"about_ca_topic_consensus":true,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003522549,0.000020673277,0.0000072173484,0.00035074502,0.000091318856,0.000013244896,0.024797093,0.0000029698583,0.059769202,0.00006956767,0.00031247953,0.9145303],"study_design_scores_gemma":[0.011489513,0.004200847,0.11763302,0.003446605,0.0036912644,0.0001993626,0.3357392,0.33573198,0.14835377,0.0020769,0.027726097,0.009711445],"about_ca_topic_score_codex":0.0077960864,"about_ca_topic_score_gemma":0.0320425,"teacher_disagreement_score":0.90481883,"about_ca_system_score_codex":0.00009836186,"about_ca_system_score_gemma":0.00001687937,"threshold_uncertainty_score":0.99881107},"labels":[],"label_agreement":null},{"id":"W2220797983","doi":"","title":"Distance domination and amplifier placement problems","year":2006,"lang":"en","type":"article","venue":"ANU Open Research (Australian National University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Trinity College","funders":"","keywords":"Mathematics; Combinatorics; Statistics","score_opus":0.08081579605710654,"score_gpt":0.3144525488639169,"score_spread":0.23363675280681034,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2220797983","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1047062,0.00010890758,0.028357042,0.0026931006,0.00010950584,0.0030651803,0.00020008312,0.00047595624,0.86028403],"genre_scores_gemma":[0.94121075,0.000057935602,0.001269959,0.000006827701,0.00003675421,0.000007965362,0.0000616088,0.000010385121,0.05733779],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"not_applicable","domain_scores_codex":[0.99907833,0.000053771815,0.00009003062,0.00017442311,0.00038326925,0.00022018807],"domain_scores_gemma":[0.9995528,0.00006344436,0.0000145785525,0.000083329425,0.00022500522,0.000060832655],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004863726,0.000077244935,0.00007573267,0.00025293563,0.00016081784,0.00015540875,0.00029179928,0.000060637438,0.000098414974],"category_scores_gemma":[0.000013043058,0.000087713575,0.00001565421,0.00047283043,0.000088075045,0.0005134478,0.0000937548,0.0001703763,0.000021700862],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006985914,0.00013958065,0.0021245365,0.00013172068,0.0000571807,0.00006486171,0.00015369123,0.003036431,0.012577346,0.61979985,0.3587721,0.003072839],"study_design_scores_gemma":[0.0011515422,0.00010837091,0.008083013,0.00008840331,0.000007915074,0.0000068412473,0.0002820279,0.0020698144,0.012264014,0.030216897,0.94535244,0.00036871742],"about_ca_topic_score_codex":0.0002937397,"about_ca_topic_score_gemma":0.0001167985,"teacher_disagreement_score":0.8365046,"about_ca_system_score_codex":0.00026616454,"about_ca_system_score_gemma":0.000038810846,"threshold_uncertainty_score":0.35768557},"labels":[],"label_agreement":null},{"id":"W2248178880","doi":"","title":"Proceedings of the 2007 international workshop on System level interconnect prediction","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"IBM; Interconnection; Computer science; Architecture; Implementation; Engineering; Telecommunications; Software engineering; History","score_opus":0.019970193540213746,"score_gpt":0.22229727023138987,"score_spread":0.2023270766911761,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2248178880","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18763301,0.000032031156,0.1746558,0.000057725094,0.0015668974,0.0003051662,0.000014530145,0.0011582134,0.6345766],"genre_scores_gemma":[0.99845225,0.000005892798,0.00068422826,0.000023364433,0.00014061801,0.0000066931716,9.4052456e-7,0.000012589523,0.00067342835],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995154,0.0000014136173,0.00017548248,0.00007214662,0.00014026462,0.0000952707],"domain_scores_gemma":[0.99980694,0.000027553486,0.00002523316,0.00006203134,0.0000584614,0.000019762601],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023944737,0.00006999692,0.00006551335,0.000081077036,0.000016280082,0.000012971196,0.00016543889,0.00006548119,0.000036249636],"category_scores_gemma":[0.00001736922,0.000048071495,0.0000424802,0.000099475415,0.000013059406,0.00007977502,0.000019618948,0.000105034,0.0000062859053],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00019523088,0.00022621856,0.026264457,0.0008552444,0.0005096534,0.000006682022,0.002252487,0.001386397,0.26061878,0.29718858,0.22093943,0.18955687],"study_design_scores_gemma":[0.0004565262,0.000102713784,0.038143117,0.0012449556,0.000026917827,0.00004620887,0.0029053509,0.025845774,0.9198854,0.00029804112,0.01073439,0.00031062184],"about_ca_topic_score_codex":0.0000050104154,"about_ca_topic_score_gemma":0.0000023078912,"teacher_disagreement_score":0.8108192,"about_ca_system_score_codex":0.000098703145,"about_ca_system_score_gemma":0.0000023167531,"threshold_uncertainty_score":0.19602987},"labels":[],"label_agreement":null},{"id":"W2281941492","doi":"10.1109/reconfig.2015.7393356","title":"Scalable analytic placement for FPGA on GPGPU","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Scalability; Parallel computing; Placement; Routing (electronic design automation); Critical path method; Path (computing); Gate array; Embedded system; Physical design; Circuit design","score_opus":0.03932186761777701,"score_gpt":0.2565174618796524,"score_spread":0.2171955942618754,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2281941492","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008741758,0.00012849916,0.6698364,0.00014258944,0.00026701303,0.0005793671,0.000008589145,0.0018325299,0.31846327],"genre_scores_gemma":[0.98274606,0.000009117472,0.010626006,0.00015812853,0.00007849457,0.000086149,0.000007445724,0.000026858037,0.006261722],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995947,0.000003320863,0.000088783156,0.00008190469,0.00008246517,0.00014881302],"domain_scores_gemma":[0.99974024,0.000021144599,0.0000059437252,0.00013511084,0.000024522089,0.00007304283],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012943249,0.00007583231,0.00008702861,0.000053646698,0.0000137143215,0.00001832411,0.00006598699,0.00003904974,0.000068016736],"category_scores_gemma":[0.000012876555,0.000064127176,0.000029629064,0.00006153104,0.0000052981336,0.00004286087,0.0000070781743,0.00003662592,0.00009831461],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000028496197,0.000051320585,0.00009285739,0.000057386627,0.000051809966,0.0000023855075,0.00011326769,0.01781539,0.0022649933,0.0051928298,0.9616962,0.012633077],"study_design_scores_gemma":[0.0013742689,0.0008681671,0.00006373457,0.000049568567,0.00003951179,0.000003647016,0.00018769274,0.35164016,0.3619616,0.0061297514,0.27712646,0.00055543147],"about_ca_topic_score_codex":0.000005517855,"about_ca_topic_score_gemma":0.0000030797605,"teacher_disagreement_score":0.9740043,"about_ca_system_score_codex":0.000069059315,"about_ca_system_score_gemma":0.000008113059,"threshold_uncertainty_score":0.26150304},"labels":[],"label_agreement":null},{"id":"W2283189482","doi":"10.1109/fpt.2015.7393136","title":"HETRIS: Adaptive floorplanning for heterogeneous FPGAs","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Floorplan; Field-programmable gate array; Scalability; Computer science; Control reconfiguration; Computer architecture; Embedded system; Parallel computing","score_opus":0.05768860992558055,"score_gpt":0.2488131203642336,"score_spread":0.19112451043865303,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2283189482","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011224616,0.00080232514,0.9606875,0.000018854409,0.00023159616,0.0003173244,0.000011970542,0.0019914727,0.024714319],"genre_scores_gemma":[0.9619501,0.000009300872,0.03737321,0.0000610942,0.00011423346,0.00007489445,0.000006099328,0.000033944074,0.00037708328],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995245,0.0000057871002,0.00010936947,0.00009790144,0.00007425677,0.00018823029],"domain_scores_gemma":[0.99971056,0.00002657303,0.000009131133,0.00011526848,0.000044784956,0.00009366083],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009838108,0.00010168204,0.00011301887,0.00006026839,0.000020283062,0.000020171405,0.00008712156,0.00006631328,0.000014727688],"category_scores_gemma":[0.00001633057,0.00009323973,0.000044801356,0.000065508604,0.0000089525565,0.000072102885,0.00001202721,0.00005268077,0.00003879703],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018510742,0.000106497784,0.00042352953,0.00016121594,0.0004300706,0.00010885598,0.0025258649,0.15896516,0.018511446,0.0063913125,0.6681705,0.14402041],"study_design_scores_gemma":[0.0010374367,0.00072041433,0.000018703397,0.000044290373,0.0000364681,0.00008361911,0.00034049043,0.48919794,0.41302097,0.0072132577,0.087558724,0.000727682],"about_ca_topic_score_codex":0.000008080488,"about_ca_topic_score_gemma":0.0000030801093,"teacher_disagreement_score":0.9507255,"about_ca_system_score_codex":0.00004515742,"about_ca_system_score_gemma":0.00000884417,"threshold_uncertainty_score":0.3802206},"labels":[],"label_agreement":null},{"id":"W2289241984","doi":"10.1109/rsp.2015.7416557","title":"Hard block reduction and synthesis improvements in Odin II","year":2015,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Netlist; Computer science; Verilog; Field-programmable gate array; Block (permutation group theory); Reduction (mathematics); Computer architecture; For loop; Embedded system; Routing (electronic design automation); Abstract syntax tree; Tree (set theory); Gate array; Programming language; Computer hardware; Loop (graph theory); Parsing","score_opus":0.022120522314660877,"score_gpt":0.21504763624582604,"score_spread":0.19292711393116516,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2289241984","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9824295,0.00013694794,0.0016486958,0.00007121266,0.00011664489,0.0001414775,0.0000013365507,0.00051065395,0.014943509],"genre_scores_gemma":[0.9961674,0.000042473555,0.0031423834,0.000008561192,0.000026146987,0.000027667189,4.345048e-7,0.000009804386,0.0005751031],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997025,0.00000551566,0.00008217426,0.00007243191,0.000048791124,0.00008856512],"domain_scores_gemma":[0.9998695,0.000004501132,0.000005416151,0.00007136112,0.0000092494565,0.00003993134],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010522991,0.00005602627,0.000066096865,0.000064538835,0.000011422029,0.000010662268,0.00003109054,0.000042253665,0.000011354128],"category_scores_gemma":[0.000013100684,0.000052441945,0.000007835738,0.000056987537,0.0000071289724,0.000085168154,0.000016120595,0.000043200653,0.000005947064],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001829047,0.00011924459,0.0020683096,0.00008565963,0.000045052195,0.000007984839,0.0012058818,0.00030416818,0.6956485,0.0006353764,0.060657844,0.23920368],"study_design_scores_gemma":[0.00044164638,0.00012190583,0.0019997032,0.00004577267,0.000012737933,0.000017285936,0.00030177966,0.012067279,0.97804743,0.0016741579,0.00496395,0.00030634773],"about_ca_topic_score_codex":0.000052009727,"about_ca_topic_score_gemma":0.0000043576356,"teacher_disagreement_score":0.28239894,"about_ca_system_score_codex":0.0000367476,"about_ca_system_score_gemma":0.0000034818552,"threshold_uncertainty_score":0.21385205},"labels":[],"label_agreement":null},{"id":"W2289721043","doi":"10.14288/1.0073893","title":"A power evaluation framework for FPGA applications and CAD experimentation","year":2013,"lang":"en","type":"article","venue":"cIRcle (University of British Columbia)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"CAD; Computer science; Field-programmable gate array; Power (physics); Engineering; Engineering drawing; Embedded system","score_opus":0.010194416734755428,"score_gpt":0.20984990429816006,"score_spread":0.19965548756340462,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2289721043","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6438889,0.00030863544,0.35373244,0.00002017634,0.000029538713,0.00094599527,0.00003540358,0.00015605782,0.00088284456],"genre_scores_gemma":[0.98174167,0.000064994005,0.018053684,0.000012381985,0.000012182976,0.000044980072,0.000017588784,0.000010334104,0.000042209882],"study_design_codex":"design_other","study_design_gemma":"observational","domain_scores_codex":[0.9996296,0.00001041919,0.000058341393,0.00012307435,0.00008918912,0.000089336456],"domain_scores_gemma":[0.999681,0.000029568031,0.000027017652,0.00010380542,0.00011733291,0.0000412506],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007601488,0.000023704451,0.00008391712,0.000024424678,0.000085063446,0.00005370639,0.00006967028,0.00007805744,0.00013505759],"category_scores_gemma":[0.000008185267,0.00008704512,0.000029623809,0.00008180454,0.00004528983,0.00023064649,0.000013438715,0.000043308406,0.0000071637314],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000010427889,0.000027917586,0.00054917944,0.0000581135,0.000023984392,4.9080876e-7,0.00039456988,0.000022140868,0.004366245,0.000036128597,0.0052070078,0.9893132],"study_design_scores_gemma":[0.00065256644,0.000083386105,0.9640182,0.00009156234,0.00004806913,0.000009546926,0.00233236,0.009737836,0.00016091466,0.021816446,0.0007905817,0.0002584789],"about_ca_topic_score_codex":0.0033444113,"about_ca_topic_score_gemma":0.0015945694,"teacher_disagreement_score":0.9890547,"about_ca_system_score_codex":0.00004141815,"about_ca_system_score_gemma":0.000009531471,"threshold_uncertainty_score":0.50557715},"labels":[],"label_agreement":null},{"id":"W2293375234","doi":"10.1145/2847263.2847319","title":"Low-Swing Signaling for FPGA Power Reduction (Abstract Only)","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Embedded system; Overhead (engineering); Swing; Reduction (mathematics); Routing (electronic design automation); Energy consumption; Interconnection; Efficient energy use; Computer hardware; Engineering; Electrical engineering; Telecommunications","score_opus":0.012451481615193908,"score_gpt":0.22461752298963253,"score_spread":0.21216604137443862,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2293375234","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15956761,0.000068286914,0.821395,0.00013296252,0.00045003172,0.00030504866,0.000007155308,0.0019656334,0.016108291],"genre_scores_gemma":[0.9912704,0.000018348059,0.0076502375,0.00001667825,0.00015343152,0.000027503798,0.0000017323325,0.000036336827,0.00082531816],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99943554,0.0000035150701,0.00016075345,0.00012574822,0.0000701538,0.00020425582],"domain_scores_gemma":[0.9997282,0.000048916256,0.000016044303,0.0001307438,0.00003222438,0.000043866257],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013670784,0.00010593354,0.00009797209,0.00006967387,0.000037272202,0.000022357624,0.00007381793,0.000083209685,0.00029795218],"category_scores_gemma":[0.000018282037,0.00007530214,0.000066972294,0.00005144134,0.000011376816,0.00021751126,0.000006636876,0.00004764165,0.000039050577],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004893137,0.000009756528,0.00000973936,0.000024035184,0.000015764013,8.535602e-7,0.000041584408,0.00007622383,0.9220572,0.0005961126,0.0057863104,0.0713775],"study_design_scores_gemma":[0.00016824527,0.00003889725,0.000079506186,0.00008243794,0.000005971336,0.000008095067,0.00003238531,0.00018139285,0.9930333,0.0013643343,0.004831147,0.0001743078],"about_ca_topic_score_codex":0.0000026586147,"about_ca_topic_score_gemma":6.473262e-7,"teacher_disagreement_score":0.8317028,"about_ca_system_score_codex":0.00005291422,"about_ca_system_score_gemma":0.000009255809,"threshold_uncertainty_score":0.32623675},"labels":[],"label_agreement":null},{"id":"W2299845815","doi":"","title":"Area optimizations in fpga architecture and cad","year":2005,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Multiplexer; Embedded system; Routing (electronic design automation); Static random-access memory; Flexibility (engineering); Gate array; Computer architecture; Computer hardware; Multiplexing","score_opus":0.00656325611663158,"score_gpt":0.1908285388090456,"score_spread":0.18426528269241402,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2299845815","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03455649,0.0005090424,0.8624518,0.00042722773,0.000022753724,0.00015784023,0.0000044462254,0.0009717786,0.10089861],"genre_scores_gemma":[0.9495212,0.00010733444,0.049931947,0.00007198264,0.000022095826,0.000010599451,0.000002251572,0.000009729152,0.00032289952],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9997808,0.0000030868869,0.00006081308,0.000051243012,0.00002458998,0.00007947801],"domain_scores_gemma":[0.99990016,0.000010286997,0.0000026337855,0.000059799175,0.000003677096,0.000023446939],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000022663296,0.000049660735,0.00004967256,0.00006878548,0.000009956419,0.000010709602,0.000030043468,0.0000374216,0.00008135955],"category_scores_gemma":[0.0000037138948,0.000044218195,0.0000075292096,0.00007053985,0.000007702305,0.000041880325,0.0000068408094,0.00006762706,0.000003914677],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000024084447,0.00003285025,0.0019077478,0.00003510083,0.000014470372,0.000007778756,0.0010553438,0.6979125,0.0062359073,0.0024727522,0.013504253,0.27681887],"study_design_scores_gemma":[0.00070507434,0.00005607404,0.0072180545,0.00006849976,0.000013701516,0.000061683466,0.000100756006,0.8444082,0.06823076,0.0035240783,0.074859336,0.00075374934],"about_ca_topic_score_codex":0.0000074836053,"about_ca_topic_score_gemma":0.000095245065,"teacher_disagreement_score":0.9149647,"about_ca_system_score_codex":0.000011760242,"about_ca_system_score_gemma":0.0000019451866,"threshold_uncertainty_score":0.18031657},"labels":[],"label_agreement":null},{"id":"W2301743601","doi":"10.14778/2904483.2904486","title":"Leopard","year":2016,"lang":"en","type":"article","venue":"Proceedings of the VLDB Endowment","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":93,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Computer science; Graph; Space partitioning; Vertex (graph theory); Algorithm; Theoretical computer science","score_opus":0.0057559873206896065,"score_gpt":0.165789516692164,"score_spread":0.1600335293714744,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2301743601","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.789663,0.00064914045,0.0029961888,0.0017218998,0.0006808917,0.00094638066,0.000017766692,0.0016489439,0.20167577],"genre_scores_gemma":[0.99851036,0.00010758085,0.00077722315,0.000025017376,0.000045950135,0.000039230905,4.5040657e-8,0.000015685002,0.0004789241],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995028,9.398415e-7,0.00013429836,0.00007969975,0.00013604791,0.00014625488],"domain_scores_gemma":[0.99981534,0.000011471581,0.000032470496,0.000072596515,0.00003951891,0.000028589533],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009377203,0.00008634578,0.00009610636,0.000034306126,0.000021735346,0.000009290191,0.00024886854,0.000032229458,0.00003227071],"category_scores_gemma":[0.000018069877,0.000043574903,0.00005997138,0.00008095094,0.00003220766,0.00009079252,0.00005384014,0.000041507577,0.000015666252],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000033924628,0.000012228031,0.0018368239,0.000050289,0.000022553566,9.198606e-8,0.00008398108,0.0000019066997,0.95410043,0.005848942,0.020100024,0.017939309],"study_design_scores_gemma":[0.00014037227,0.000023901446,0.0008005056,0.00008881865,0.000009032894,0.000003433562,0.000015158841,0.000028412027,0.9833267,0.004602714,0.010882595,0.00007836067],"about_ca_topic_score_codex":0.0000022798317,"about_ca_topic_score_gemma":2.1931349e-7,"teacher_disagreement_score":0.20884733,"about_ca_system_score_codex":0.000046246583,"about_ca_system_score_gemma":0.0000029958708,"threshold_uncertainty_score":0.17769329},"labels":[],"label_agreement":null},{"id":"W2313156072","doi":"10.5121/ijdps.2012.3607","title":"Implementation of Network Community Profile using Local Spectral algorithm and its application in Community Networking","year":2012,"lang":"en","type":"article","venue":"International Journal of Distributed and Parallel systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Algorithm","score_opus":0.025726424227720417,"score_gpt":0.29558177104358424,"score_spread":0.2698553468158638,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2313156072","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.54157877,0.0020142924,0.45591262,0.00000729257,0.00026016752,0.00012692137,0.00005387196,0.000014128828,0.00003195832],"genre_scores_gemma":[0.99828213,0.00023380364,0.0010787286,0.0000038109058,0.00032095247,0.0000057325688,0.000066434804,0.000008012872,3.9573914e-7],"study_design_codex":"observational","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99902475,0.00020866383,0.00044644615,0.000029211958,0.00015007955,0.00014082005],"domain_scores_gemma":[0.99948573,0.00008128042,0.00020868077,0.000056592107,0.00011218022,0.00005552621],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00087462243,0.000086843575,0.0001869068,0.00007090633,0.00005904413,0.000025588834,0.00013792147,0.00005835401,0.000002032903],"category_scores_gemma":[0.0000042951933,0.00008448266,0.0000270469,0.000086758526,0.000023874334,0.0002342386,0.0000339473,0.00034011842,1.6493665e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017460961,0.0005457802,0.539563,0.00073053763,0.0010088003,0.000017240129,0.006282437,0.20683013,0.010227112,0.004055313,0.0011669447,0.2293981],"study_design_scores_gemma":[0.0024365305,0.00027432397,0.14906523,0.0010729778,0.00009072978,0.0007576091,0.0073097423,0.83212876,0.0039178133,0.0013453476,0.0011243287,0.0004766363],"about_ca_topic_score_codex":0.00059628027,"about_ca_topic_score_gemma":0.00004185138,"teacher_disagreement_score":0.6252986,"about_ca_system_score_codex":0.00010091672,"about_ca_system_score_gemma":0.000011062062,"threshold_uncertainty_score":0.3445103},"labels":[],"label_agreement":null},{"id":"W2336236367","doi":"10.1145/2899381","title":"Eh?Placer","year":2016,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Calgary","funders":"Chinese University of Hong Kong; University of Hong Kong; Alberta Innovates - Technology Futures","keywords":"Placer mining; Computer science; Variety (cybernetics); Process (computing); Physical design; Focus (optics); Margin (machine learning); Industrial engineering; Geology; Artificial intelligence; Programming language; Integrated circuit; Machine learning","score_opus":0.015155866589129945,"score_gpt":0.21903710167187923,"score_spread":0.20388123508274927,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2336236367","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0017981959,0.00043052936,0.9952655,0.00007556629,0.00022033988,0.00045282938,0.0000100206125,0.0012234146,0.00052364555],"genre_scores_gemma":[0.99597377,0.00026752506,0.0026321493,0.0000076134193,0.000029464885,0.00019721333,0.0000011944472,0.00003999968,0.0008510462],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.998862,0.0000943292,0.00036362512,0.00015649931,0.00021300757,0.00031049157],"domain_scores_gemma":[0.9991031,0.00026884652,0.00006393427,0.00046523238,0.000051409246,0.000047446476],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003226266,0.00016751196,0.0002136596,0.00024246106,0.000050411796,0.000017629734,0.00023292981,0.00013498864,0.00017754319],"category_scores_gemma":[0.000018102335,0.00012913828,0.00007980857,0.0002332979,0.000026566326,0.0002094763,0.0000010912279,0.00010652896,0.00012623516],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007235008,0.00015349415,0.000014009172,0.00024742784,0.0004278286,0.000002491943,0.0002824233,0.09224038,0.500372,0.004180956,0.0044464665,0.39756018],"study_design_scores_gemma":[0.0013460601,0.0009078667,0.00010835094,0.00063056254,0.000093674906,0.000068054476,0.00006212446,0.11618189,0.86897653,0.0038491762,0.0071048704,0.0006708182],"about_ca_topic_score_codex":0.000007084663,"about_ca_topic_score_gemma":0.0000015993662,"teacher_disagreement_score":0.9941756,"about_ca_system_score_codex":0.00026649045,"about_ca_system_score_gemma":0.000045388184,"threshold_uncertainty_score":0.5266106},"labels":[],"label_agreement":null},{"id":"W2405015892","doi":"10.1090/conm/588/11713","title":"Using graph partitioning for efficient network modularity optimization","year":2013,"lang":"en","type":"other","venue":"Contemporary mathematics - American Mathematical Society","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Modularity (biology); Mathematics; Graph; Graph partition; Theoretical computer science; Combinatorics; Computer science; Biology; Evolutionary biology","score_opus":0.040738291521766744,"score_gpt":0.26554876489335394,"score_spread":0.2248104733715872,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2405015892","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000038465674,0.00085772236,0.89447683,0.000015794265,0.0001387687,0.0019437702,0.00008458137,0.0020905784,0.100353464],"genre_scores_gemma":[0.0019975184,0.000138622,0.9847984,0.000095828735,0.0004572647,0.00061053847,0.00012911178,0.0011867621,0.010585965],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997737,0.000046044104,0.00081861933,0.0004217332,0.00036857635,0.00060801883],"domain_scores_gemma":[0.9983073,0.00026545732,0.000488642,0.00065292313,0.00007944505,0.00020625413],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00043980882,0.0006558769,0.0012234662,0.000094331706,0.0001496504,0.00014146554,0.0003533753,0.00041374058,0.00048502747],"category_scores_gemma":[0.000062488994,0.00062266394,0.0006080265,0.00041731406,0.00036728708,0.00007760185,0.00007970941,0.0003458812,0.000043832824],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000027501485,0.0003151977,0.00000868656,0.0048653465,0.00076863845,0.00000252297,0.00069324934,0.16740048,0.000104955674,0.015843479,0.8096312,0.000363445],"study_design_scores_gemma":[0.00021835747,0.000042010386,3.7351455e-7,0.0009707833,0.0001332197,0.000005529465,0.00023546634,0.9762144,0.00005280793,0.01576161,0.005654569,0.0007108506],"about_ca_topic_score_codex":0.000018629655,"about_ca_topic_score_gemma":4.7367053e-7,"teacher_disagreement_score":0.8088139,"about_ca_system_score_codex":0.00012740021,"about_ca_system_score_gemma":0.00005445287,"threshold_uncertainty_score":0.99962246},"labels":[],"label_agreement":null},{"id":"W2481354194","doi":"10.1109/ipdpsw.2016.16","title":"Parallel Graph Partitioning on a CPU-GPU Architecture","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"Concordia University","funders":"Natural Sciences and Engineering Research Council of Canada; Nvidia","keywords":"Computer science; Parallel computing; Architecture; Graph; Computer architecture; Theoretical computer science","score_opus":0.009441816210775193,"score_gpt":0.2002424908063714,"score_spread":0.19080067459559621,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2481354194","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012737639,0.00006134287,0.914256,0.0003247954,0.00008161658,0.00011315284,0.000004570902,0.0020148272,0.07040608],"genre_scores_gemma":[0.99113053,0.000049358783,0.007719551,0.00015266796,0.00006593902,0.00004118789,0.0000013188117,0.000021966598,0.00081748446],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99954695,0.0000093995095,0.00009066169,0.00010118401,0.00007647657,0.00017534588],"domain_scores_gemma":[0.99973947,0.000038142774,0.0000073311835,0.00015696956,0.0000082694105,0.0000497973],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000046077475,0.000097439355,0.0000791796,0.00007241786,0.000029059163,0.000014195382,0.00007466311,0.000054869746,0.0002846907],"category_scores_gemma":[0.000006192118,0.000059231395,0.00004661266,0.00006786602,0.000017892016,0.000045392895,0.000007445708,0.00006865742,0.00014789624],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000052878935,0.00009953155,0.0019225638,0.00009556098,0.00016542623,0.000056607154,0.0004915974,0.0078645665,0.16129507,0.08517838,0.17424159,0.5685362],"study_design_scores_gemma":[0.0024615047,0.0008557478,0.007737781,0.00083772937,0.000048674057,0.00007662446,0.00006583412,0.0036794532,0.49947524,0.29459873,0.18784887,0.0023138076],"about_ca_topic_score_codex":0.0000030976325,"about_ca_topic_score_gemma":0.000007833389,"teacher_disagreement_score":0.9783929,"about_ca_system_score_codex":0.000015559994,"about_ca_system_score_gemma":0.0000025127722,"threshold_uncertainty_score":0.31171635},"labels":[],"label_agreement":null},{"id":"W2508502534","doi":"10.1109/isvlsi.2016.23","title":"Routing-Aware Incremental Timing-Driven Placement","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Calgary","funders":"","keywords":"Placement; Routing (electronic design automation); Computer science; CONTEST; Static timing analysis; Network routing; Physical design; Computer network; Embedded system; Circuit design","score_opus":0.01736856733150907,"score_gpt":0.22469682497569854,"score_spread":0.20732825764418947,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2508502534","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.070468836,0.000031655476,0.8492059,0.0001670921,0.00021008434,0.00029315235,0.0000143050265,0.0031555966,0.076453365],"genre_scores_gemma":[0.9962607,0.000021885884,0.0024317822,0.000052317293,0.000055766664,0.000020957417,0.000002535576,0.000021739224,0.0011323045],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99949294,0.0000066752414,0.00012151089,0.00009851275,0.00009746907,0.00018289474],"domain_scores_gemma":[0.99977493,0.000023278586,0.00001000577,0.00013348901,0.000011048766,0.000047236575],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000059370563,0.00009803743,0.00007980304,0.000040614937,0.00002649144,0.000013083653,0.00009677555,0.000043844073,0.0008988435],"category_scores_gemma":[0.0000047526873,0.00006523476,0.000030307398,0.00003887014,0.0000123817,0.00008648707,0.000032891472,0.00003645259,0.00022154574],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016556793,0.000071358874,0.010622991,0.00006488336,0.00015130627,0.000026234711,0.00043198964,0.00034009237,0.7004219,0.004942129,0.19231236,0.09059817],"study_design_scores_gemma":[0.0008977248,0.00017155748,0.0008780548,0.0001628852,0.000020299807,0.000012933283,0.00017954469,0.01919792,0.96128374,0.00027155504,0.0162862,0.00063758856],"about_ca_topic_score_codex":0.0000063853936,"about_ca_topic_score_gemma":0.000004810585,"teacher_disagreement_score":0.92579186,"about_ca_system_score_codex":0.000088488894,"about_ca_system_score_gemma":0.0000043393766,"threshold_uncertainty_score":0.9841706},"labels":[],"label_agreement":null},{"id":"W2514038949","doi":"10.1109/iscas.2016.7527478","title":"Efficient ILP-based variant-grid analog router","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Router; Computer science; Routing (electronic design automation); Static routing; Policy-based routing; Integer programming; Linear programming; Link-state routing protocol; Equal-cost multi-path routing; Multipath routing; Computer network; Distributed computing; Routing protocol; Algorithm","score_opus":0.006799162086376307,"score_gpt":0.1844894108303515,"score_spread":0.17769024874397518,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2514038949","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011987344,0.00003530358,0.9550258,0.00016453011,0.00021849727,0.000097104064,0.000010786605,0.0014645514,0.030996084],"genre_scores_gemma":[0.9925692,0.0000048755546,0.0066681993,0.00014438515,0.000092074704,0.000016056534,0.0000015774085,0.000021135296,0.0004825008],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999493,0.0000094909765,0.000113335496,0.00011013752,0.000085606545,0.00018845504],"domain_scores_gemma":[0.9996753,0.00003837725,0.000007854775,0.00020599102,0.00001708126,0.00005542861],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008603206,0.00009847257,0.00009134426,0.00007080095,0.000017978293,0.000014207505,0.00009985352,0.000059288654,0.00059749366],"category_scores_gemma":[0.0000068703926,0.000059438462,0.000045461526,0.000071627,0.0000152270395,0.000022794336,0.000009869935,0.000038984945,0.00023773915],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000033098237,0.00022736196,0.0016426776,0.00013087854,0.00015395731,0.0002122645,0.00018676119,0.022401528,0.49613857,0.01759757,0.2379809,0.22329444],"study_design_scores_gemma":[0.0014978274,0.00019839969,0.0035104684,0.00016750582,0.000040071074,0.000024475508,0.000012440035,0.33505076,0.5835625,0.000887525,0.07396328,0.0010847747],"about_ca_topic_score_codex":0.000006759191,"about_ca_topic_score_gemma":0.0000026775624,"teacher_disagreement_score":0.9805819,"about_ca_system_score_codex":0.000038348677,"about_ca_system_score_gemma":0.000007564745,"threshold_uncertainty_score":0.65421367},"labels":[],"label_agreement":null},{"id":"W2517156619","doi":"10.1109/fccm.2016.43","title":"An Empirical Analysis of the Fidelity of VPR Area Models","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Adder; Computer science; Multiplexer; Point (geometry); Fidelity; Multiplexing; Mathematics; Latency (audio); Telecommunications","score_opus":0.03698574710576573,"score_gpt":0.2757968774740671,"score_spread":0.23881113036830137,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2517156619","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.38440153,0.000016907366,0.6102698,0.000034064517,0.000009958307,0.00003829319,0.000016383443,0.00011600374,0.005097054],"genre_scores_gemma":[0.9982588,0.0000143720545,0.0016403355,0.000018052262,0.000004288757,0.000002599515,6.6514843e-7,0.0000050414033,0.000055794313],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959135,0.000017826802,0.00016715504,0.00006356687,0.000091625836,0.00006848639],"domain_scores_gemma":[0.9995422,0.00003360553,0.000019763154,0.00034343323,0.000038068767,0.000022938972],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001062551,0.00005068268,0.0001541009,0.00006882468,0.0000067223405,0.0000019087283,0.0001504148,0.000044877597,0.00012576624],"category_scores_gemma":[0.000007842727,0.000024009678,0.000107403044,0.00027845174,0.00002811343,0.000074461896,0.000014121012,0.000024561969,5.311009e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001923205,0.0002143709,0.10220781,0.00007007585,0.0015530408,9.453029e-7,0.00082667934,0.08341722,0.73851484,0.006597527,0.010417263,0.05616098],"study_design_scores_gemma":[0.00008010854,0.000030895848,0.031082105,0.000014821298,0.00022380642,2.384948e-7,0.000019160661,0.64581555,0.31603563,0.0065159616,0.000075910924,0.00010581957],"about_ca_topic_score_codex":0.00003333502,"about_ca_topic_score_gemma":0.000026132817,"teacher_disagreement_score":0.6138573,"about_ca_system_score_codex":0.000012177064,"about_ca_system_score_gemma":0.000005158269,"threshold_uncertainty_score":0.13770522},"labels":[],"label_agreement":null},{"id":"W2520963437","doi":"10.1109/hpcsim.2016.7568334","title":"Metis-CIC: A new mesh partitioning heuristic for parallel preconditioned iterative methods in CFD","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Ministry of Economy, Trade and Industry; National Natural Science Foundation of China","keywords":"Computer science; Metis; Parallel computing; Graph partition; Computational fluid dynamics; Iterative method; Rate of convergence; Mathematical optimization; Convergence (economics); Linear system; Heuristic; Algorithm; Graph; Theoretical computer science; Mathematics; Artificial intelligence","score_opus":0.032146468942669856,"score_gpt":0.33349344940318465,"score_spread":0.3013469804605148,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2520963437","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0006374736,0.00013386463,0.99225134,0.00016641515,0.00008617321,0.00041077522,0.000016102184,0.00054468,0.0057532033],"genre_scores_gemma":[0.26438946,0.00005916924,0.7320248,0.000082532024,0.00008747096,0.00050499383,0.00001363427,0.000035536053,0.0028024218],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992402,0.000055758646,0.00025466798,0.00016711323,0.000053294312,0.00022891883],"domain_scores_gemma":[0.99937814,0.00036594342,0.000024413568,0.00013280402,0.00002832973,0.000070384755],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00025476317,0.00013387855,0.00019642807,0.000114301765,0.00003272542,0.000033481647,0.000081505816,0.00007827293,0.0005419227],"category_scores_gemma":[0.00010229279,0.00009869292,0.00006030767,0.000105197345,0.000016262013,0.00024542696,0.000010621175,0.000056435427,0.000023600594],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010392812,0.00012153832,0.00078542024,0.0002588342,0.00030362987,0.000017617253,0.0027192894,0.0015183077,0.21966687,0.1242854,0.15937905,0.49084014],"study_design_scores_gemma":[0.0033246055,0.00040561374,0.00240723,0.00050271145,0.00007166679,0.000021177273,0.00013057917,0.03883928,0.5359565,0.3945548,0.022628069,0.001157755],"about_ca_topic_score_codex":0.0000144711485,"about_ca_topic_score_gemma":0.00003530268,"teacher_disagreement_score":0.48968238,"about_ca_system_score_codex":0.000063693464,"about_ca_system_score_gemma":0.000016479535,"threshold_uncertainty_score":0.59336734},"labels":[],"label_agreement":null},{"id":"W2524902150","doi":"10.1109/fpl.2016.7577325","title":"An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Adder; Multiplexer; Computer science; Field-programmable gate array; Ranking (information retrieval); Artificial intelligence; Computer hardware; Multiplexing","score_opus":0.044407031306817585,"score_gpt":0.25365957023683466,"score_spread":0.20925253893001708,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2524902150","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9102097,0.00013979644,0.08059442,0.00072836207,0.000064334665,0.0008153037,0.000016055097,0.00010939026,0.0073226],"genre_scores_gemma":[0.99959177,0.000017411145,0.00019010673,0.000080213926,0.000018323162,0.000062392166,7.8265924e-7,0.000017970837,0.000021014232],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99900407,0.00016708203,0.0002601292,0.000114318376,0.00031615063,0.00013825322],"domain_scores_gemma":[0.9988236,0.00053774775,0.00006007018,0.00051434786,0.000048941267,0.000015307722],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0007544918,0.00012646469,0.00014695607,0.00006746287,0.000039060073,0.000009333845,0.0004056328,0.000060185226,0.000079532416],"category_scores_gemma":[0.00009546902,0.000045679582,0.00008531576,0.00014052165,0.000073014744,0.00006946842,0.000012089892,0.00011543078,5.1536495e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012983927,0.00013441802,0.0006571184,0.00007251893,0.000096306685,5.595287e-7,0.011245036,0.24463859,0.47532886,0.0044408804,0.00107097,0.2621849],"study_design_scores_gemma":[0.00068707764,0.00012409505,0.0059038587,0.0003997501,0.0000610355,0.0000024291905,0.0002843899,0.4382308,0.50424683,0.049750492,0.00008099434,0.0002282345],"about_ca_topic_score_codex":0.000044349887,"about_ca_topic_score_gemma":0.0001416868,"teacher_disagreement_score":0.26195666,"about_ca_system_score_codex":0.000041793493,"about_ca_system_score_gemma":0.000025414985,"threshold_uncertainty_score":0.18627594},"labels":[],"label_agreement":null},{"id":"W2525927134","doi":"10.1109/fpl.2016.7577358","title":"Model-based optimization of High Level Synthesis directives","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Compiler; Field-programmable gate array; Directive; High-level synthesis; Design space exploration; Process (computing); Datapath; Abstraction layer; Construct (python library); Computer architecture; Variety (cybernetics); Design flow; Abstraction; Embedded system; Programming language; Software; Artificial intelligence","score_opus":0.023727555119895428,"score_gpt":0.20607732414602595,"score_spread":0.1823497690261305,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2525927134","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0037016526,0.000016757915,0.9890192,0.000034435256,0.000018846826,0.000053168427,0.000015951695,0.0004849408,0.0066550197],"genre_scores_gemma":[0.85118973,0.000024618068,0.14857537,0.00000598237,0.0000067271712,0.000019747982,4.83329e-7,0.00001434392,0.00016298279],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99971145,0.000007671537,0.000091550326,0.00006371081,0.000053766686,0.000071865565],"domain_scores_gemma":[0.9997556,0.0000748987,0.000011741387,0.00011121536,0.000028142822,0.000018359702],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000045255507,0.00006137165,0.000090529655,0.00006042534,0.000008627216,0.0000030382732,0.00005608037,0.000043698976,0.000126632],"category_scores_gemma":[0.000026704118,0.00004068805,0.000025897076,0.000050787137,0.00001620825,0.0000737267,0.000004536769,0.000013379539,0.0000033271872],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000054619823,0.000019081932,0.000079377285,0.000028376962,0.000018182265,2.531818e-7,0.000016161423,0.86501205,0.08150883,0.0017482311,0.000823759,0.050740216],"study_design_scores_gemma":[0.00004293314,0.0000056153585,0.00008129238,0.000023419188,0.000004208253,7.625457e-8,0.0000010057822,0.47254342,0.5268908,0.000348203,0.000007385271,0.00005163065],"about_ca_topic_score_codex":0.000008475022,"about_ca_topic_score_gemma":0.000001394772,"teacher_disagreement_score":0.8474881,"about_ca_system_score_codex":0.000021798518,"about_ca_system_score_gemma":0.0000067762385,"threshold_uncertainty_score":0.16592105},"labels":[],"label_agreement":null},{"id":"W2527244689","doi":"10.1109/fpl.2016.7577326","title":"The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":28,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Network topology; Routing (electronic design automation); Interconnection; Computer science; Field-programmable gate array; Layer (electronics); Topology (electrical circuits); Electronic engineering; Materials science; Embedded system; Engineering; Electrical engineering; Computer network; Nanotechnology","score_opus":0.1897463588851081,"score_gpt":0.2843065463874937,"score_spread":0.0945601875023856,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2527244689","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15747845,0.0004838161,0.81787103,0.0015553175,0.0006380333,0.00069600635,0.000053233987,0.0014659619,0.019758131],"genre_scores_gemma":[0.99824506,0.00012367404,0.0014068548,0.000018092218,0.000050288236,0.000011513451,2.9623004e-7,0.00000668433,0.00013755517],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99953544,0.000011140585,0.000116042065,0.00006935571,0.00008687449,0.00018112062],"domain_scores_gemma":[0.999376,0.00038644142,0.000021096206,0.0001708769,0.000030098769,0.000015502486],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020941214,0.00007948723,0.00010089131,0.000010106814,0.00021494707,0.000016968042,0.0002745643,0.000026847916,0.00002627297],"category_scores_gemma":[0.000055349807,0.000033462806,0.00007990725,0.000054688506,0.00007088107,0.000103673956,0.0001757125,0.000028025537,0.0000037795965],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000095504205,0.00003680785,0.026258795,0.00008732058,0.0009641078,0.0000040435384,0.0011248452,0.00062385196,0.101356335,0.24276377,0.019042078,0.60764253],"study_design_scores_gemma":[0.0015791102,0.0002944972,0.035025883,0.000099648256,0.00026620523,0.0000143833,0.0060793264,0.016278066,0.859888,0.036071975,0.04354706,0.00085582724],"about_ca_topic_score_codex":0.000046568122,"about_ca_topic_score_gemma":0.000022403889,"teacher_disagreement_score":0.8407666,"about_ca_system_score_codex":0.00003836838,"about_ca_system_score_gemma":0.0000030885471,"threshold_uncertainty_score":0.16532208},"labels":[],"label_agreement":null},{"id":"W2532502681","doi":"10.1109/tic-sth.2009.5444435","title":"A comparison of hardware acceleration methods for VLSI Maze routing","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Speedup; Computer science; Hardware acceleration; Software; Parallel computing; Very-large-scale integration; Routing (electronic design automation); Computer hardware; Acceleration; Path (computing); Embedded system; Field-programmable gate array; Computer architecture; Operating system","score_opus":0.07467330716448682,"score_gpt":0.41918760334419114,"score_spread":0.3445142961797043,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2532502681","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0031029265,0.00013073228,0.9885832,0.000035284986,0.00004500848,0.00020517397,0.0000015647659,0.0005053176,0.007390794],"genre_scores_gemma":[0.609288,0.0000035189928,0.39058346,0.00001989606,0.00002303863,0.000009138791,0.0000046883206,0.0000065361137,0.000061738254],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99956316,0.000013883755,0.00020445892,0.00007017957,0.00003958032,0.00010871095],"domain_scores_gemma":[0.999768,0.000051615785,0.000024439782,0.00009851183,0.000037256887,0.00002014569],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018542148,0.000071700175,0.00016569153,0.000045404886,0.000017605133,0.00001701967,0.00006837741,0.00005967552,0.000027441898],"category_scores_gemma":[0.000026416605,0.00006714026,0.000047907055,0.00006939529,0.000004406926,0.00008504005,0.000004252903,0.00004961613,0.000001159986],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004774059,0.00002553355,0.00025401905,0.00004407653,0.000013273874,8.403475e-8,0.0004906366,0.0010340342,0.3454319,0.004966625,0.004096158,0.6436389],"study_design_scores_gemma":[0.000089409405,0.00008054475,0.00043255222,0.0000134091815,0.000008377537,4.14698e-7,0.00004845144,0.27042836,0.72477597,0.0013182886,0.002721211,0.0000830216],"about_ca_topic_score_codex":0.000002416679,"about_ca_topic_score_gemma":9.961614e-7,"teacher_disagreement_score":0.6435559,"about_ca_system_score_codex":0.00001761269,"about_ca_system_score_gemma":0.000003510089,"threshold_uncertainty_score":0.27379003},"labels":[],"label_agreement":null},{"id":"W2533618188","doi":"","title":"Deterministic, Weak-scaling Parallelism for Wirelength- and Timing-driven FPGA Placement, Suitable for Multicore and Manycore Architectures","year":2015,"lang":"en","type":"dissertation","venue":"The Atrium (University of Guelph)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; Strong","keywords":"Parallel computing; Parallelism (grammar); Field-programmable gate array; Scaling; Computer science; Multi-core processor; Computer architecture; Computational science; Embedded system; Mathematics","score_opus":0.023731692589929295,"score_gpt":0.24518031155717868,"score_spread":0.22144861896724938,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2533618188","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.93599993,0.0024226867,0.056070413,0.000098717566,0.00040067616,0.002646493,0.00049405673,0.00040142133,0.0014656341],"genre_scores_gemma":[0.9868872,0.00034750073,0.010765131,0.0000068908803,0.00009104657,0.000009140201,0.00032955135,0.00005186922,0.001511678],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992594,0.000018813245,0.0001402248,0.00022485243,0.000115433875,0.00024128075],"domain_scores_gemma":[0.99927664,0.00022867305,0.00011554522,0.00019741754,0.000103677376,0.000078075835],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018761079,0.00023263066,0.00035605478,0.00013145721,0.00020710881,0.000024699824,0.00025146335,0.00024280963,0.000007900446],"category_scores_gemma":[0.000034764707,0.00023253723,0.00009679472,0.000050823688,0.000070833245,0.000055333723,0.000045298388,0.00017347909,7.197013e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0071503515,0.00027709734,0.0006076231,0.02654385,0.003149827,0.000061619205,0.102351844,0.024892863,0.38900235,0.002879827,0.09790924,0.34517348],"study_design_scores_gemma":[0.010840405,0.0020693277,0.018269915,0.001814093,0.0044745007,0.00006530471,0.0572488,0.8344575,0.010594205,0.015342691,0.041212354,0.003610909],"about_ca_topic_score_codex":0.000056857596,"about_ca_topic_score_gemma":0.0001502395,"teacher_disagreement_score":0.80956465,"about_ca_system_score_codex":0.000034866098,"about_ca_system_score_gemma":0.000028053062,"threshold_uncertainty_score":0.9482593},"labels":[],"label_agreement":null},{"id":"W2536590467","doi":"10.1109/icm.2011.6177347","title":"A new hardware abstraction-based framework to cope with analog design challenges","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"École de Technologie Supérieure","funders":"","keywords":"Computer science; Abstraction; Microelectronics; Variety (cybernetics); Context (archaeology); Computer architecture; Wireless; Electronic design automation; Reliability (semiconductor); Design process; Design technology; Design methods; Process (computing); Embedded system; Systems engineering; Telecommunications; Engineering; Work in process; Electrical engineering","score_opus":0.06364044899990705,"score_gpt":0.22509007569813036,"score_spread":0.16144962669822333,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2536590467","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00018774424,0.00024900114,0.95283,0.000089741014,0.000058839945,0.00023682366,0.000001318929,0.0013848713,0.044961624],"genre_scores_gemma":[0.5336716,0.0000525574,0.46587846,0.00010357807,0.000048433154,0.000036877707,8.87284e-7,0.000033799413,0.00017379638],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994037,0.000011712921,0.00011312538,0.00016046938,0.000107865686,0.00020308989],"domain_scores_gemma":[0.99947816,0.00005932892,0.000013198447,0.00025541068,0.000033278502,0.00016062554],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000077974684,0.00015343683,0.0001386189,0.0001012066,0.000027096648,0.00001975033,0.0001359688,0.000116599826,0.0009741859],"category_scores_gemma":[0.000011897641,0.00012446493,0.000028255683,0.00013380194,0.000008168768,0.00008585044,0.000005930436,0.00015106877,0.00017589095],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00064921513,0.00036920095,0.0013265935,0.00050299265,0.00065438496,0.0003481937,0.009257907,0.050374135,0.009099391,0.028583674,0.23764393,0.6611904],"study_design_scores_gemma":[0.0013518595,0.0036423483,0.023576852,0.0011037209,0.0001820332,0.00005066907,0.0013835427,0.014462636,0.89207697,0.019180534,0.039680332,0.0033085253],"about_ca_topic_score_codex":0.00007920299,"about_ca_topic_score_gemma":0.000044480206,"teacher_disagreement_score":0.88297755,"about_ca_system_score_codex":0.000030699073,"about_ca_system_score_gemma":0.000031060692,"threshold_uncertainty_score":0.9999391},"labels":[],"label_agreement":null},{"id":"W2547196265","doi":"10.1109/icaci.2012.6463129","title":"Performance analysis of the graph-partitioning algorithms used in OpenFOAM","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Polygon mesh; Graph partition; Parallel computing; Execution time; Overhead (engineering); Load balancing (electrical power); Metis; Algorithm; Distributed computing; Graph; Theoretical computer science; Mathematics; Operating system; Computer graphics (images)","score_opus":0.016344447999904133,"score_gpt":0.22717134385647356,"score_spread":0.2108268958565694,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2547196265","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9753968,0.0000821315,0.01306742,0.0000069684356,0.000056297526,0.000077180586,0.0000017502855,0.00011447794,0.011196935],"genre_scores_gemma":[0.99834234,0.000028394183,0.0015248253,0.000011738989,0.000011090882,0.000013316645,0.0000018275824,0.0000059564723,0.000060495073],"study_design_codex":"observational","study_design_gemma":"observational","domain_scores_codex":[0.9996108,0.000010630363,0.00013290481,0.00003870404,0.00007504439,0.00013194712],"domain_scores_gemma":[0.9997973,0.000013844535,0.000014197278,0.00014599966,0.0000089828845,0.000019663066],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016448385,0.000051622468,0.00011203688,0.00016138745,0.000017706227,0.000005871167,0.00009867528,0.000030822735,0.00010530867],"category_scores_gemma":[0.0000034195104,0.000036350066,0.000059714897,0.00085242017,0.000014488632,0.00016768894,0.00001526678,0.00006023954,0.00000355687],"study_design_candidate":"observational","study_design_consensus":"observational","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[8.5054546e-7,0.000026952097,0.9686301,0.000020486828,0.00015225747,1.1957499e-7,0.00058623153,0.01640182,0.0076744636,0.0005042413,0.00029840728,0.005704122],"study_design_scores_gemma":[0.000073165305,0.00000744664,0.6800895,0.000016359465,0.000090959635,4.5537814e-7,0.00005717792,0.21131526,0.108055025,0.000027172806,0.00016709963,0.00010037647],"about_ca_topic_score_codex":0.00003956803,"about_ca_topic_score_gemma":0.000032767537,"teacher_disagreement_score":0.28854054,"about_ca_system_score_codex":0.000016016882,"about_ca_system_score_gemma":0.0000022205065,"threshold_uncertainty_score":0.14823127},"labels":[],"label_agreement":null},{"id":"W2553967290","doi":"","title":"On Pin-to-wire Routing in FPGAs","year":2012,"lang":"en","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"University of Toronto","keywords":"Field-programmable gate array; Routing (electronic design automation); Engineering; Computer science; Electrical engineering; Embedded system","score_opus":0.013613438925035385,"score_gpt":0.29796324605193175,"score_spread":0.2843498071268964,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2553967290","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.68162656,0.0007022915,0.0019111672,0.00004673048,0.0011329451,0.0005941171,0.000004487139,0.0014850755,0.31249663],"genre_scores_gemma":[0.98989546,0.000033499502,0.00047205534,0.000033704517,0.00014928317,0.000059759357,0.0000934058,0.00009407293,0.009168758],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992416,0.000013814197,0.00015613121,0.00015448018,0.00013320794,0.00030074688],"domain_scores_gemma":[0.9996379,0.000034239296,0.000028823322,0.00021130063,0.000015612039,0.000072124785],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011536788,0.00022371822,0.0002247586,0.00022934361,0.000022163675,0.000021015656,0.00013451643,0.0002680813,0.00012391368],"category_scores_gemma":[0.00003220908,0.00024280093,0.00004712346,0.00018089866,0.000002635471,0.000041358682,0.0000071731174,0.0003708064,0.0002697926],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00028292194,0.0003925036,0.0016444603,0.0033869934,0.00028849236,0.0001902816,0.14578022,0.011669276,0.25381732,0.024360688,0.17029895,0.3878879],"study_design_scores_gemma":[0.0020403212,0.00086253375,0.09885767,0.012621708,0.00027824918,0.000024828534,0.01672289,0.0142630115,0.7712028,0.004322047,0.06974085,0.009063081],"about_ca_topic_score_codex":0.000100167745,"about_ca_topic_score_gemma":0.00020845655,"teacher_disagreement_score":0.5173855,"about_ca_system_score_codex":0.00012055574,"about_ca_system_score_gemma":0.000011932749,"threshold_uncertainty_score":0.99011344},"labels":[],"label_agreement":null},{"id":"W2560928762","doi":"10.1109/cicc.1988.20786","title":"Integration of algorithmic VLSI synthesis with testability incorporation","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Testability; Very-large-scale integration; Computer science; Design for testing; Tree (set theory); High-level synthesis; Computer engineering; Computer architecture; Algorithm; Theoretical computer science; Reliability engineering; Mathematics; Embedded system; Engineering","score_opus":0.00949885690245675,"score_gpt":0.18655112771892474,"score_spread":0.177052270816468,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2560928762","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10307339,0.00002152875,0.87214804,0.0000066330344,0.000020813543,0.0001664817,0.0000024975907,0.0003836558,0.024176983],"genre_scores_gemma":[0.9215262,0.000007779021,0.0783868,0.0000033272333,0.0000053937947,0.000032023312,0.0000019243894,0.000010069214,0.00002646974],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996362,0.000022246104,0.00013241603,0.000071626644,0.00007331615,0.00006419803],"domain_scores_gemma":[0.99972785,0.00004716812,0.000020935175,0.00013577883,0.000049481412,0.000018790888],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014763813,0.000071594826,0.00009478893,0.000050207873,0.0000122651645,0.0000075967673,0.00003559704,0.000043923046,0.00007321493],"category_scores_gemma":[0.000050116512,0.000053781463,0.0000165385,0.00014045888,0.000021601536,0.00012051958,0.0000018147346,0.00004663116,0.0000035267428],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013547352,0.00013285715,0.0060085445,0.00016768335,0.000049635935,0.000002565337,0.00034647173,0.0012947513,0.7964257,0.022256056,0.0008443449,0.17245784],"study_design_scores_gemma":[0.000045188528,0.000050669412,0.001244841,0.000019480169,0.000009039079,0.0000031350778,0.000062178144,0.008973451,0.9876522,0.0017238152,0.00012518615,0.00009082221],"about_ca_topic_score_codex":0.00001720243,"about_ca_topic_score_gemma":0.000026580004,"teacher_disagreement_score":0.81845284,"about_ca_system_score_codex":0.000031511787,"about_ca_system_score_gemma":0.000011248599,"threshold_uncertainty_score":0.21931444},"labels":[],"label_agreement":null},{"id":"W2562600912","doi":"10.1109/cicc.1991.164142","title":"Optimal synthesis of high performance architectures","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Computer science; Asynchronous communication; Key (lock); Integer programming; Interconnection; Mathematical optimization; Linear programming; Interface (matter); Computer architecture; Distributed computing; Parallel computing; Computer network; Algorithm; Operating system; Mathematics","score_opus":0.007987585156057598,"score_gpt":0.17327746363008986,"score_spread":0.16528987847403226,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2562600912","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9375787,0.00013285817,0.01545976,0.000015501155,0.000029291115,0.000048887694,0.0000024745366,0.00055169617,0.046180874],"genre_scores_gemma":[0.98321855,0.00009202656,0.016428808,0.00000816587,0.000020572808,0.000011169169,1.7059237e-7,0.000012126379,0.00020839316],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99969965,0.000003875872,0.000089857465,0.00004967513,0.00005924554,0.000097708005],"domain_scores_gemma":[0.99982375,0.000029386869,0.0000073593383,0.00011303959,0.0000072821585,0.00001918821],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000027161292,0.00006287916,0.000091688555,0.000053656455,0.0000110620385,0.0000039564707,0.000081673585,0.000033637556,0.00061324995],"category_scores_gemma":[0.000006223143,0.000052081436,0.000022630382,0.00005685749,0.00001722952,0.000022753273,0.000007795512,0.000049552735,0.000026139674],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008232307,0.00006957967,0.0011262161,0.00038359873,0.000095298106,0.0000060983175,0.00043210998,0.13985859,0.04866612,0.0010445014,0.01621745,0.7920922],"study_design_scores_gemma":[0.000032655164,0.000031303276,0.0015433732,0.00001898171,0.0000059231243,0.000005365973,0.0000044093995,0.114657916,0.8831434,0.000036996735,0.00042103903,0.00009859992],"about_ca_topic_score_codex":0.0000066636217,"about_ca_topic_score_gemma":4.064527e-7,"teacher_disagreement_score":0.8344773,"about_ca_system_score_codex":0.0000060592847,"about_ca_system_score_gemma":5.767924e-7,"threshold_uncertainty_score":0.6714657},"labels":[],"label_agreement":null},{"id":"W2578575989","doi":"10.1145/3039902.3039907","title":"An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug","year":2017,"lang":"en","type":"article","venue":"ACM SIGARCH Computer Architecture News","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Debugging; Overlay; Field-programmable gate array; Computer science; Observability; Embedded system; Background debug mode interface; Software; TRACE (psycholinguistics); Computer hardware; Real-time computing; Operating system","score_opus":0.015100499825445566,"score_gpt":0.2633789226388761,"score_spread":0.24827842281343052,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2578575989","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.034591924,0.00019944903,0.96250314,0.0002795015,0.00038944735,0.0008178806,0.000024775169,0.000975554,0.0002183142],"genre_scores_gemma":[0.4286548,0.000057239526,0.5698047,0.00018845494,0.0010448898,0.00011166103,0.000023167957,0.00009819487,0.000016832382],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99818736,0.000043937125,0.00040456766,0.0005145546,0.00016224329,0.00068732153],"domain_scores_gemma":[0.99803025,0.00025637134,0.00012936187,0.0012889315,0.00005264367,0.00024241814],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00042903185,0.0003784883,0.00043587317,0.00020431173,0.0005414617,0.00046078596,0.0010216096,0.0001610249,0.000009142341],"category_scores_gemma":[0.000103840146,0.00035654695,0.00013739736,0.00005921498,0.00008613799,0.00031328344,0.0003282846,0.00040770872,0.0000014665649],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001026928,0.000013636045,0.00011077161,0.00011920218,0.00005475701,0.000011360259,0.0009496459,0.00034586163,0.028622428,0.000009403215,0.0006050719,0.9691476],"study_design_scores_gemma":[0.0018941218,0.0007451313,0.004093049,0.00019944811,0.000044924072,0.0001373987,0.000048219976,0.9011872,0.045867953,0.008045443,0.03651507,0.0012220889],"about_ca_topic_score_codex":0.00005362933,"about_ca_topic_score_gemma":0.000025235233,"teacher_disagreement_score":0.9679255,"about_ca_system_score_codex":0.000038225804,"about_ca_system_score_gemma":0.000025337251,"threshold_uncertainty_score":0.99988866},"labels":[],"label_agreement":null},{"id":"W2588897393","doi":"10.1109/aspdac.2017.7858368","title":"Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits","year":2017,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":38,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Ministry of Economic Affairs","keywords":"Parasitic extraction; Sizing; Computer science; Heuristic; Geometric programming; CMOS; Electronic engineering; Electronic circuit; Analogue electronics; Process (computing); Computer engineering; Convex optimization; Regular polygon; Computer architecture; Engineering; Electrical engineering; Mathematics; Artificial intelligence; Machine learning","score_opus":0.07764127263365753,"score_gpt":0.3247736203931772,"score_spread":0.24713234775951967,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2588897393","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024980683,0.000119827964,0.9686248,0.000065606604,0.00012818883,0.0003426961,0.000026538995,0.0006246661,0.005087005],"genre_scores_gemma":[0.9655429,0.000018867784,0.034050003,0.00009713032,0.000046060897,0.00008915688,0.000013295077,0.000033261054,0.00010930843],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992948,0.000040250237,0.00015254895,0.00020775305,0.000050116385,0.0002545307],"domain_scores_gemma":[0.99918485,0.00033297285,0.000040856234,0.00029953598,0.00007566963,0.00006611082],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00033892225,0.00016561408,0.00026598512,0.000102887374,0.00018533532,0.00008603579,0.00017520157,0.0001554373,0.000029427261],"category_scores_gemma":[0.00020312968,0.00014833827,0.000056346635,0.000039512346,0.00006959746,0.0001328322,0.000014025643,0.00012810699,0.0000034867785],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008748189,0.00009414232,0.014291407,0.00073382456,0.00056595623,0.00008358702,0.0009532613,0.00077852566,0.42540872,0.019313635,0.0071716337,0.5305178],"study_design_scores_gemma":[0.0012710631,0.00038372044,0.019151544,0.00012894308,0.00011888953,0.000024997711,0.00036067862,0.13585463,0.82835925,0.011753829,0.0018110261,0.0007814401],"about_ca_topic_score_codex":0.000093098606,"about_ca_topic_score_gemma":0.000066958295,"teacher_disagreement_score":0.94056225,"about_ca_system_score_codex":0.000041994426,"about_ca_system_score_gemma":0.000019085004,"threshold_uncertainty_score":0.6049059},"labels":[],"label_agreement":null},{"id":"W2593282265","doi":"10.1109/mwscas.2016.7869975","title":"Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Field-programmable gate array; Computer science; Multiplexing; Benchmark (surveying); Routing (electronic design automation); Electronic circuit; Logic synthesis; Time-division multiplexing; Logic gate; Parallel computing; Embedded system; Computer hardware; Algorithm; Engineering; Electrical engineering","score_opus":0.03631318421026875,"score_gpt":0.31575396757101515,"score_spread":0.2794407833607464,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2593282265","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.91082656,0.00046515322,0.0861266,0.000011420799,0.00003421874,0.00027455995,0.000003448216,0.0003964834,0.0018615685],"genre_scores_gemma":[0.9885368,0.000002392456,0.011343636,0.00000416119,0.000016801889,0.000019302095,0.0000015804413,0.000014248044,0.00006108432],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994828,0.000026314488,0.00017027979,0.000095362535,0.00011972848,0.000105495674],"domain_scores_gemma":[0.9997673,0.00005939362,0.00002449564,0.000095402305,0.000023414355,0.000029995432],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015025208,0.00008843625,0.00013245398,0.000053925054,0.000020769085,0.0000073064402,0.000049633727,0.000045642697,0.00013893799],"category_scores_gemma":[0.00002835404,0.00005981932,0.000023028793,0.000032370208,0.000029924044,0.000038127968,0.00001911101,0.000033539778,0.0000064836954],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004229356,0.00002119609,0.0018096816,0.0000065675745,0.000010953644,8.04261e-8,0.00041698353,0.00029212827,0.93753856,0.000017885714,0.0001709309,0.05971079],"study_design_scores_gemma":[0.0003957284,0.000035839188,0.0018072249,0.000026592987,0.000005792424,9.4463974e-7,0.0000571011,0.18986173,0.8076801,0.000028549242,0.000020295243,0.00008014175],"about_ca_topic_score_codex":0.000011926207,"about_ca_topic_score_gemma":0.00000336602,"teacher_disagreement_score":0.1895696,"about_ca_system_score_codex":0.000027492877,"about_ca_system_score_gemma":0.0000037848765,"threshold_uncertainty_score":0.24393609},"labels":[],"label_agreement":null},{"id":"W2598631327","doi":"10.1145/2990299.2990305","title":"Automatic detection and elision of reset sub-circuits","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Verilog; Computer science; Reset (finance); Field-programmable gate array; Routing (electronic design automation); Electronic circuit; Embedded system; Hardware description language; Application-specific integrated circuit; Computer hardware; Electrical engineering; Engineering","score_opus":0.008464199203003852,"score_gpt":0.20043207918533745,"score_spread":0.1919678799823336,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2598631327","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7502169,0.000108912885,0.24446142,0.00001737219,0.000043198495,0.00007564922,0.0000013899221,0.0006046757,0.0044704643],"genre_scores_gemma":[0.999534,0.000121474324,0.0002752162,0.0000030399583,0.000011699096,0.0000044760427,1.3309683e-7,0.000007707716,0.0000422593],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9997447,0.0000074942623,0.00009194717,0.000048179038,0.000048447742,0.000059236707],"domain_scores_gemma":[0.9998381,0.00003674211,0.000009509963,0.000083310144,0.000013489,0.000018857436],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007775554,0.000042400065,0.00006412068,0.00005828617,0.000009478683,0.0000028716065,0.000027748658,0.00003931394,0.000054159107],"category_scores_gemma":[0.000019882416,0.000025835896,0.000009247095,0.000049050588,0.000016912532,0.000072073606,0.000006612011,0.000017357708,0.00000728511],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[2.1700058e-7,0.0000010746594,0.00008159451,0.000021088768,0.0000020488158,1.6381587e-7,0.000015350668,5.2774305e-7,0.670422,0.000104722065,0.00042630034,0.32892486],"study_design_scores_gemma":[0.00009794476,0.00004985129,0.003898133,0.000066805216,0.0000031344307,0.0000038965422,0.000004708793,0.0047333324,0.98871255,0.0021124298,0.00026108007,0.000056133747],"about_ca_topic_score_codex":0.0000064274145,"about_ca_topic_score_gemma":0.000005648633,"teacher_disagreement_score":0.32886875,"about_ca_system_score_codex":0.000010894415,"about_ca_system_score_gemma":0.0000010585748,"threshold_uncertainty_score":0.105355725},"labels":[],"label_agreement":null},{"id":"W2604877941","doi":"10.1145/3024063","title":"Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow","year":2017,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Verilog; Computer science; FPGA prototype; Bitstream; Embedded system; Routing (electronic design automation); Application-specific integrated circuit; Standard cell; Reconfigurable computing; Computer architecture; Computer hardware; Integrated circuit; Algorithm; Operating system","score_opus":0.012995821058801689,"score_gpt":0.21814816057302946,"score_spread":0.2051523395142278,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2604877941","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.049886413,0.006110908,0.9019556,0.002552373,0.0020570853,0.0018592149,0.0005066679,0.0037811773,0.031290554],"genre_scores_gemma":[0.9955742,0.0005885174,0.0011539962,0.00004088245,0.000028511386,0.00027524374,0.000003158169,0.000053157994,0.002282342],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99864393,0.000040177914,0.0003354769,0.00034222327,0.00014392372,0.00049427256],"domain_scores_gemma":[0.9982691,0.00013197283,0.000087315864,0.0013601448,0.000060647195,0.00009085032],"candidate_categories":["sts"],"consensus_categories":[],"category_scores_codex":[0.00046602273,0.00028039466,0.0004205105,0.0002579189,0.0013196656,0.00025209476,0.0008438416,0.00043604866,0.00006209963],"category_scores_gemma":[0.0000640412,0.0002301604,0.00006230949,0.0002228851,0.00014801018,0.0002079936,0.00000949616,0.0005783578,0.00006679018],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020394182,0.0002658464,0.0015076036,0.0011938075,0.0009517697,0.00008096112,0.0011105827,0.045373335,0.15867582,0.0024278737,0.07290586,0.7153026],"study_design_scores_gemma":[0.00071342615,0.00044287552,0.000041302923,0.00036928087,0.00012846205,0.000117227,0.0016752509,0.02724003,0.8335628,0.001887046,0.1328656,0.0009566975],"about_ca_topic_score_codex":0.00013353632,"about_ca_topic_score_gemma":0.000025070614,"teacher_disagreement_score":0.9456878,"about_ca_system_score_codex":0.00008200329,"about_ca_system_score_gemma":0.000022548573,"threshold_uncertainty_score":0.9999805},"labels":[],"label_agreement":null},{"id":"W2611347473","doi":"10.1109/rsp.2014.6966904","title":"System-on-chip processor using different FPGA architectures in the VTR CAD flow","year":2014,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Field-programmable gate array; Adder; Verilog; Computer science; Embedded system; Block (permutation group theory); Routing (electronic design automation); Design flow; Computer architecture; Computer hardware; FPGA prototype; Electronic design automation; Logic synthesis; Logic gate","score_opus":0.02149867666359571,"score_gpt":0.24139686002116073,"score_spread":0.21989818335756503,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2611347473","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5904331,0.0005878299,0.3792236,0.00009466224,0.00080003013,0.0020020974,0.000043618886,0.0025562234,0.024258804],"genre_scores_gemma":[0.9967638,0.000017665003,0.0023754328,0.00009508382,0.00034721178,0.00026753603,0.000015642932,0.00007889682,0.000038679536],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984063,0.0001334996,0.00039591946,0.00037227577,0.00032272533,0.000369297],"domain_scores_gemma":[0.99902785,0.00013122804,0.00006183416,0.00070062344,0.000024254383,0.000054185475],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00032858254,0.00048369222,0.0005077275,0.00026187088,0.000054144362,0.00013500196,0.0006745753,0.00037333023,0.000014513731],"category_scores_gemma":[0.000025461655,0.00029214084,0.00014549764,0.00009340862,0.000028834838,0.000013462405,0.00013986237,0.0011147229,0.0000107077],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003244877,0.0001259881,0.00047722913,0.009864048,0.00018051684,0.00005468361,0.003295077,0.94918424,0.0028042763,0.0014585181,0.0023597826,0.030163199],"study_design_scores_gemma":[0.00027711535,0.000074211515,0.0013926942,0.0024664316,0.00007335124,0.000048585753,0.00017311441,0.9656958,0.024621274,0.0038352835,0.00031700914,0.0010251466],"about_ca_topic_score_codex":0.00010054114,"about_ca_topic_score_gemma":0.00007510014,"teacher_disagreement_score":0.4063307,"about_ca_system_score_codex":0.00016493582,"about_ca_system_score_gemma":0.000022598864,"threshold_uncertainty_score":0.9999531},"labels":[],"label_agreement":null},{"id":"W2612563535","doi":"10.1109/tvlsi.2017.2691409","title":"Leveraging Unused Resources for Energy Optimization of FPGA Interconnect","year":2017,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Dynamic demand; Equal-cost multi-path routing; Interconnection; Routing (electronic design automation); Static routing; Electronic engineering; Computer network; Engineering; Power (physics); Routing protocol; Physics","score_opus":0.017562840011441167,"score_gpt":0.23286284547607924,"score_spread":0.21530000546463807,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2612563535","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00938889,0.00012106901,0.98642236,0.00003356615,0.0016226029,0.00043085072,0.00014818314,0.00049472944,0.0013377625],"genre_scores_gemma":[0.99629325,0.00010136578,0.0024510156,0.000018652065,0.00012676371,0.0003053713,0.000020775298,0.00006610052,0.0006166864],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986294,0.000070783586,0.00054444943,0.00027404362,0.00021568163,0.0002656433],"domain_scores_gemma":[0.9988654,0.000114769224,0.00018296899,0.0005737022,0.00019136052,0.00007176047],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003382109,0.0002587293,0.00037032395,0.0003213277,0.00040236523,0.00021026222,0.00032064537,0.00021919243,0.000035469573],"category_scores_gemma":[0.000017011831,0.0002504263,0.00020934448,0.00011119012,0.00005057894,0.00052019075,0.0000016611225,0.00017776845,0.0000045787197],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00013334738,0.00019474061,0.000019536856,0.00033472554,0.00021500702,0.0000025453255,0.0023699715,0.9349224,0.03441249,0.00038246825,0.0015015852,0.025511188],"study_design_scores_gemma":[0.0005742482,0.00013817196,0.000011679292,0.00042093982,0.000049038706,0.0000072029434,0.0006856579,0.7256324,0.2698153,0.000046850713,0.0023522985,0.00026618043],"about_ca_topic_score_codex":0.00017939296,"about_ca_topic_score_gemma":0.00016991334,"teacher_disagreement_score":0.9869044,"about_ca_system_score_codex":0.00013340554,"about_ca_system_score_gemma":0.000019356708,"threshold_uncertainty_score":0.9999948},"labels":[],"label_agreement":null},{"id":"W2617507377","doi":"10.4236/ajor.2017.73014","title":"System Reliability Evaluation for Imperfect Networks Using Polygon-to-Chain Reduction","year":2017,"lang":"en","type":"article","venue":"American Journal of Operations Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université Laval","funders":"","keywords":"Polygon (computer graphics); Computation; Reliability (semiconductor); Algorithm; Reduction (mathematics); Computer science; Series (stratigraphy); Mathematical optimization; Node (physics); Process (computing); Mathematics; Theoretical computer science","score_opus":0.08582483862008403,"score_gpt":0.4240188789983182,"score_spread":0.3381940403782342,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2617507377","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.61343026,0.000099634744,0.38508788,0.00023502778,0.00029099375,0.00062958733,0.0000044011317,0.000034999928,0.0001872237],"genre_scores_gemma":[0.976585,0.00004038301,0.022749241,0.0000032817632,0.0005088855,0.00006907575,0.0000019045027,0.000025643796,0.00001664062],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984717,0.00028769753,0.00037215897,0.00012942406,0.00046883998,0.00027017493],"domain_scores_gemma":[0.9978431,0.00008892239,0.00007039636,0.00042941398,0.001436606,0.00013159518],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.005756536,0.00009020644,0.00021948502,0.0003189218,0.00076600054,0.00028450624,0.00032356492,0.000045616398,0.000007832507],"category_scores_gemma":[0.00063261925,0.00008095776,0.0000805455,0.00024460434,0.00014991977,0.00038362603,0.000031737738,0.00032571124,0.000002194959],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000056615747,0.000022914677,0.00012732069,0.000026451138,0.000041197723,0.0000018118084,0.00033435156,0.8548483,0.053247027,0.00015398861,0.0010005243,0.09013949],"study_design_scores_gemma":[0.00019759021,0.0005763108,0.00053457153,0.00011944132,0.000023734701,0.000079705744,0.0007969031,0.9902081,0.007190195,0.000034499128,0.0001384371,0.000100520985],"about_ca_topic_score_codex":0.0002523174,"about_ca_topic_score_gemma":0.000014457533,"teacher_disagreement_score":0.36315468,"about_ca_system_score_codex":0.00059986586,"about_ca_system_score_gemma":0.00017834785,"threshold_uncertainty_score":0.5891534},"labels":[],"label_agreement":null},{"id":"W2619603071","doi":"10.1145/3035464","title":"A Fast Hierarchical Adaptive Analog Routing Algorithm Based on Integer Linear Programming","year":2017,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Foundation for Innovation","keywords":"Computer science; Static routing; Equal-cost multi-path routing; Multipath routing; Link-state routing protocol; Destination-Sequenced Distance Vector routing; Policy-based routing; Routing (electronic design automation); Dynamic Source Routing; Integer programming; Distributed computing; Algorithm; Computer network; Routing protocol","score_opus":0.022845966572676617,"score_gpt":0.2574228208277125,"score_spread":0.23457685425503588,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2619603071","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00041550107,0.00006185264,0.9970661,0.000055619617,0.00019133321,0.00083741813,0.000014311909,0.00091029063,0.0004476008],"genre_scores_gemma":[0.94379956,0.00001564107,0.055681832,0.000011128756,0.00006484537,0.0002878584,0.000007824362,0.00005419256,0.000077107536],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982655,0.00016243997,0.0004790961,0.00028154082,0.0003502766,0.0004611206],"domain_scores_gemma":[0.99849087,0.00028686455,0.00019338031,0.00084557955,0.00010384503,0.00007946317],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006390199,0.00027166907,0.00035329693,0.00034187586,0.00033367018,0.00010762325,0.0004954532,0.00020503199,0.00002192075],"category_scores_gemma":[0.00006631799,0.00026556654,0.0001470238,0.00018462676,0.00006995202,0.00023308222,0.000003561663,0.00050854165,0.000025283765],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000077971155,0.00019158292,0.0000074679765,0.00009979432,0.00019949372,0.000006170395,0.00025981772,0.470132,0.0029340559,0.00084124546,0.00009275911,0.52515763],"study_design_scores_gemma":[0.00045473996,0.0008341072,0.000050267325,0.0003265038,0.000041177253,0.000010590907,0.00005733149,0.9786587,0.01897444,0.0001941531,0.00015538855,0.00024263523],"about_ca_topic_score_codex":0.000052196443,"about_ca_topic_score_gemma":0.000005548763,"teacher_disagreement_score":0.94338405,"about_ca_system_score_codex":0.00032703497,"about_ca_system_score_gemma":0.000100217396,"threshold_uncertainty_score":0.9999797},"labels":[],"label_agreement":null},{"id":"W2718700547","doi":"","title":"Airspace block organization with metaheurisitics and partitioning packages","year":2013,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Block (permutation group theory); Computer science; Mathematics; Combinatorics","score_opus":0.0056661503549899055,"score_gpt":0.17591502781415244,"score_spread":0.17024887745916253,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2718700547","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21534681,0.0010210958,0.766763,0.00032668648,0.00016908633,0.0006903243,0.000013003033,0.004361143,0.011308905],"genre_scores_gemma":[0.9726432,0.0005642985,0.026117973,0.000033688637,0.00006600714,0.000033813903,0.000035730875,0.0000692336,0.00043605347],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994459,0.000013794458,0.00012150502,0.00018093901,0.00009772199,0.00014012557],"domain_scores_gemma":[0.9995637,0.0000206142,0.00003032761,0.00022135934,0.000105925035,0.00005807181],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005045222,0.00019899945,0.00019422217,0.00007097613,0.000040364557,0.00015516736,0.00007381245,0.00018229368,0.000101627964],"category_scores_gemma":[0.000012639532,0.00016658734,0.000014568185,0.00009011642,0.000024936227,0.00008585042,0.000087659326,0.00025109536,0.000020845377],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017637803,0.0003191708,0.06460366,0.010801571,0.004125067,0.00021529917,0.011219392,0.30163538,0.05988428,0.067560986,0.45220956,0.027407976],"study_design_scores_gemma":[0.001011117,0.00034370943,0.01566975,0.0014763714,0.00108655,0.00025643283,0.0008738927,0.14656898,0.7958765,0.022827057,0.009123235,0.0048864246],"about_ca_topic_score_codex":0.000022344526,"about_ca_topic_score_gemma":0.0000063311386,"teacher_disagreement_score":0.7572964,"about_ca_system_score_codex":0.0000257628,"about_ca_system_score_gemma":0.000012141128,"threshold_uncertainty_score":0.6793235},"labels":[],"label_agreement":null},{"id":"W2752793715","doi":"10.1109/tcad.2017.2748027","title":"Automatic Selection of Process Corner Simulations for Faster Design Verification","year":2017,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Bottleneck; Benchmark (surveying); Process (computing); Set (abstract data type); Computer science; Transistor; Algorithm; Power (physics); Selection (genetic algorithm); Voltage; Process corners; Speedup; Die (integrated circuit); Integrated circuit; Engineering; Parallel computing; Electrical engineering; Artificial intelligence; Embedded system","score_opus":0.05011577823575271,"score_gpt":0.2648827685851671,"score_spread":0.21476699034941443,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2752793715","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022599727,0.000046493227,0.9751132,0.0000046256096,0.00048272137,0.0013613491,0.000073008436,0.0002883036,0.00003058532],"genre_scores_gemma":[0.9924102,0.000023308128,0.0072514587,0.0000040050577,0.000036686495,0.00019299555,0.0000062112485,0.000042092543,0.000033074448],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99872375,0.00010067621,0.0005908806,0.00023736918,0.0001632863,0.00018404117],"domain_scores_gemma":[0.9986868,0.00026260427,0.00025714378,0.00033553285,0.00039677534,0.00006112382],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00029933476,0.00023273122,0.00041992616,0.0002721179,0.00024388277,0.000120746874,0.00021125503,0.0001874497,0.000010708394],"category_scores_gemma":[0.00001158628,0.00021162999,0.00007687703,0.0001521499,0.00006902077,0.00028902604,5.435087e-7,0.0001449761,0.0000014142205],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002977324,0.00011652416,0.000018781151,0.0005935725,0.00018437029,4.966291e-7,0.00038611403,0.8204331,0.10207558,0.0000909337,0.00019140654,0.075879365],"study_design_scores_gemma":[0.00041096174,0.00042912152,0.00008234526,0.00037983755,0.000065851,0.0000111357485,0.000045676454,0.8546543,0.14362173,0.000111117515,0.000013022337,0.00017490612],"about_ca_topic_score_codex":0.000035694244,"about_ca_topic_score_gemma":0.0000025585214,"teacher_disagreement_score":0.9698104,"about_ca_system_score_codex":0.00006114373,"about_ca_system_score_gemma":0.00005909462,"threshold_uncertainty_score":0.863002},"labels":[],"label_agreement":null},{"id":"W2782281681","doi":"10.1109/tcad.2018.2789728","title":"Density-Uniformity-Aware Analog Layout Retargeting","year":2018,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Research and Development Corporation of Newfoundland and Labrador; Canada Foundation for Innovation","keywords":"Retargeting; Computer science; Process (computing); Electronic engineering; Capacitance; Set (abstract data type); Integrated circuit layout; Place and route; Integrated circuit; Electrical engineering; Engineering; Artificial intelligence; Routing (electronic design automation)","score_opus":0.025244253969223664,"score_gpt":0.2188628959097165,"score_spread":0.19361864194049283,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2782281681","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024474515,0.00016355985,0.97258276,0.0000057887423,0.0010829762,0.0004804401,0.000046988604,0.0007746777,0.0003882815],"genre_scores_gemma":[0.9970912,0.00008418701,0.0024841165,0.00003108792,0.00014627511,0.000031638112,0.000006332749,0.00005430922,0.00007085687],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982723,0.00017553532,0.00062392146,0.0003374332,0.00024015382,0.00035067045],"domain_scores_gemma":[0.99888587,0.00017019478,0.00010536409,0.0003525409,0.0003427455,0.00014328654],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00048773372,0.00034773382,0.000541755,0.00039797585,0.00020668592,0.00010809187,0.00022090769,0.00026356918,0.000021898031],"category_scores_gemma":[0.0000043125924,0.0003102429,0.00010734079,0.0004430681,0.00012276295,0.00019306847,0.0000014812815,0.00038191144,0.000020960284],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015734807,0.000524292,0.00031899798,0.0014192496,0.001654854,0.00014175111,0.003769842,0.3929523,0.19442475,0.0010546484,0.008418799,0.39516318],"study_design_scores_gemma":[0.00038044906,0.0007754903,0.00004479299,0.00057950127,0.00006328122,0.00012784508,0.00018908698,0.8934839,0.1036555,0.00009022054,0.00018184602,0.00042812838],"about_ca_topic_score_codex":0.00016326408,"about_ca_topic_score_gemma":0.000013635943,"teacher_disagreement_score":0.9726167,"about_ca_system_score_codex":0.00009450201,"about_ca_system_score_gemma":0.000045184595,"threshold_uncertainty_score":0.999935},"labels":[],"label_agreement":null},{"id":"W2783307004","doi":"","title":"EVE, a CAD tool providing placement and pipelining assistance for high-speed FPGA circuit designs","year":2001,"lang":"en","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computer science; Field-programmable gate array; Critical path method; Electronic circuit; Event (particle physics); Path (computing); Digital electronics; Computer architecture; Place and route; Virtex; Parallel computing; Computer engineering; Embedded system; Electrical engineering; Engineering; Operating system","score_opus":0.0394614255143726,"score_gpt":0.30216115643246927,"score_spread":0.2626997309180967,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2783307004","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2796407,0.007384785,0.648226,0.00007421497,0.0015126301,0.0053884666,0.00006714069,0.0039984724,0.053707547],"genre_scores_gemma":[0.9195679,0.0011076438,0.01581943,0.000069537564,0.0005235818,0.000949327,0.0007659854,0.00040345418,0.060793143],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99861324,0.000021055801,0.00033832298,0.0003915759,0.00021460497,0.00042118574],"domain_scores_gemma":[0.99933064,0.0001272411,0.00012418284,0.0002524435,0.00008743362,0.00007805273],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002602289,0.00040372458,0.0004364811,0.00017288837,0.00012713532,0.000115986164,0.00015912502,0.00036456934,0.000041925887],"category_scores_gemma":[0.0000675678,0.00044990372,0.00007488222,0.00015321866,0.000012870216,0.00011418886,0.000010309653,0.00029570935,0.0000063751895],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0010450246,0.00026787037,0.00048505625,0.014478339,0.0013771942,0.00016493398,0.056478903,0.004612997,0.60497534,0.010171509,0.12690495,0.17903785],"study_design_scores_gemma":[0.0073715323,0.0013403381,0.0024930427,0.008373472,0.0017390918,0.00007159268,0.02137221,0.045698058,0.82169455,0.009877696,0.07059568,0.009372751],"about_ca_topic_score_codex":0.000028228356,"about_ca_topic_score_gemma":0.000045867535,"teacher_disagreement_score":0.6399272,"about_ca_system_score_codex":0.00019965845,"about_ca_system_score_gemma":0.000058857662,"threshold_uncertainty_score":0.99979526},"labels":[],"label_agreement":null},{"id":"W2783721252","doi":"","title":"Packing Boundary-Anchored Rectangles.","year":2017,"lang":"en","type":"article","venue":"Canadian Conference on Computational Geometry","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Manitoba; Carleton University; University of Waterloo","funders":"","keywords":"Computer science; Boundary (topology); Mathematics","score_opus":0.032501644865725335,"score_gpt":0.2521070399376369,"score_spread":0.21960539507191157,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2783721252","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.24417792,0.0006161429,0.12212721,0.002873222,0.0026739724,0.0007602264,0.0005397443,0.001528736,0.6247028],"genre_scores_gemma":[0.9969712,0.000018400548,0.0023310971,0.00025918373,0.00012864808,0.0000137870575,0.000053023214,0.00002708604,0.00019759154],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99915797,0.000011687006,0.00014727289,0.00019179969,0.00017623947,0.00031504693],"domain_scores_gemma":[0.9991783,0.000043478234,0.00004198928,0.00032430538,0.00011072059,0.00030120806],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000110462446,0.0001543964,0.00015109917,0.00034196503,0.00044616687,0.00044018,0.0003807525,0.00010488646,0.00033904702],"category_scores_gemma":[0.00007392006,0.0001764213,0.000045879548,0.00010145179,0.00009121789,0.000170391,0.000015602169,0.00020932616,0.00016823747],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017136477,0.000039098537,0.009891798,0.00012860274,0.00023020366,0.0003587259,0.0004452628,0.023032732,0.0008249695,0.18961756,0.09689086,0.67852306],"study_design_scores_gemma":[0.0013521529,0.00029097687,0.23432434,0.0006125451,0.000044940927,0.000084596795,0.00016942769,0.41670993,0.0027420847,0.19060428,0.15057346,0.0024912662],"about_ca_topic_score_codex":0.0024445057,"about_ca_topic_score_gemma":0.007613354,"teacher_disagreement_score":0.75279325,"about_ca_system_score_codex":0.00022840998,"about_ca_system_score_gemma":0.00030994375,"threshold_uncertainty_score":0.71942514},"labels":[],"label_agreement":null},{"id":"W2785649635","doi":"10.1109/fpt.2017.8280115","title":"Automatic circuit design and modelling for heterogeneous FPGAs","year":2017,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Field-programmable gate array; Standard cell; Routing (electronic design automation); Block (permutation group theory); Computer architecture; Embedded system; Floorplan; Verilog; Place and route; Design flow; Computer hardware; Stratix; Integrated circuit","score_opus":0.06489352580945308,"score_gpt":0.2474589058206374,"score_spread":0.18256538001118433,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2785649635","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017998999,0.00016132258,0.97899854,0.0000088590805,0.000050034592,0.00031315215,0.0000014634514,0.0008443697,0.0016232452],"genre_scores_gemma":[0.8829636,0.000053365333,0.11674049,0.000014979799,0.000028271706,0.0000631853,6.0721175e-7,0.000026253814,0.00010925831],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959946,0.0000046133423,0.00009962479,0.00009938673,0.00004229149,0.00015463549],"domain_scores_gemma":[0.9996294,0.000041612322,0.000017771657,0.00025278257,0.00001336408,0.000045111454],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011562588,0.0000930149,0.00011266593,0.000030410245,0.00014796157,0.000122601,0.0001312464,0.000057977148,0.00001756424],"category_scores_gemma":[0.000008899857,0.00008680709,0.000029260413,0.0000073783717,0.000018817755,0.00011045868,0.000013600244,0.00003527883,0.0000051334337],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000006593628,0.000019664261,0.000051356754,0.00049990794,0.00014034324,0.0000188988,0.00043351314,0.64186805,0.01853557,0.004593725,0.0038466663,0.32998574],"study_design_scores_gemma":[0.00009936236,0.000029156046,0.000005557629,0.000016111691,0.000010311552,0.000011021826,0.000002021693,0.95365644,0.03584845,0.009966737,0.00023987038,0.00011498378],"about_ca_topic_score_codex":0.000006327319,"about_ca_topic_score_gemma":7.424769e-7,"teacher_disagreement_score":0.8649646,"about_ca_system_score_codex":0.000017894476,"about_ca_system_score_gemma":0.000004727377,"threshold_uncertainty_score":0.35398903},"labels":[],"label_agreement":null},{"id":"W2789985954","doi":"10.1145/3130265.3130326","title":"Simulation-based circuit-activity estimation for FPGAs containing hard blocks","year":2017,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Computer science; Field-programmable gate array; Benchmark (surveying); Verilog; Electronic circuit; Routing (electronic design automation); Embedded system; Electronic design automation; Software; Computer hardware; Electronic engineering; Computer architecture; Engineering; Electrical engineering","score_opus":0.05441265144530018,"score_gpt":0.29824117160330593,"score_spread":0.24382852015800577,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2789985954","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03492048,0.0000069447183,0.95825356,0.000039736122,0.000098890756,0.0003094677,0.000007264311,0.0007692778,0.0055944026],"genre_scores_gemma":[0.98147446,4.933653e-7,0.018225392,0.000028320808,0.000049727336,0.00007159218,0.000007393593,0.000022770608,0.000119872784],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99956656,0.0000054628154,0.000102498285,0.00011082985,0.000070814625,0.00014383873],"domain_scores_gemma":[0.9993114,0.0002599893,0.000043117376,0.00029743343,0.000049948583,0.00003810577],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014513219,0.00009924436,0.00012152268,0.000042995613,0.0002098067,0.00011840518,0.00011902986,0.00007613602,0.000044601173],"category_scores_gemma":[0.00024466563,0.00010176958,0.000051742278,0.00001571271,0.000017614826,0.00022075522,0.0000070693795,0.000058034955,0.000005928194],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010666575,0.000011867735,0.00057607057,0.00004983726,0.000016771424,8.330612e-7,0.000040324063,0.88352376,0.0078770025,0.0005030969,0.00024215465,0.10714761],"study_design_scores_gemma":[0.00027123268,0.000035756977,0.0014926285,0.000020282421,0.000009576548,1.08508885e-7,0.000002332774,0.95003957,0.046557486,0.0010414566,0.00040033585,0.00012926698],"about_ca_topic_score_codex":0.00002472446,"about_ca_topic_score_gemma":0.000006913688,"teacher_disagreement_score":0.94655395,"about_ca_system_score_codex":0.00004370103,"about_ca_system_score_gemma":0.000013219182,"threshold_uncertainty_score":0.4150043},"labels":[],"label_agreement":null},{"id":"W2794259726","doi":"10.1145/3182394","title":"An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures","year":2018,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":16,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Multiplexer; Computer science; Adder; Field-programmable gate array; Ranking (information retrieval); Computer engineering; Algorithm; Artificial intelligence; Computer hardware; Multiplexing","score_opus":0.04023300561660837,"score_gpt":0.2535090742876795,"score_spread":0.21327606867107113,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2794259726","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.93791234,0.000844825,0.0553291,0.0009433107,0.00030988516,0.0014798081,0.00004250478,0.00026977694,0.002868426],"genre_scores_gemma":[0.99950063,0.000072123694,0.00006935899,0.00003171397,0.000013681355,0.00026682147,0.0000011586417,0.00001975996,0.000024739844],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9988122,0.00019457318,0.00040546773,0.00019880992,0.00019727764,0.00019166461],"domain_scores_gemma":[0.9984099,0.00044457873,0.000108698885,0.00092769234,0.00009132118,0.000017772774],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00082925486,0.00017727113,0.0002736121,0.00034977542,0.0002050247,0.000017267022,0.0005871752,0.00025821594,0.00003696123],"category_scores_gemma":[0.00006701446,0.00009690915,0.000073410534,0.00051663205,0.0003147841,0.00006746018,0.0000021455098,0.0004291012,9.656039e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00031582816,0.0003683604,0.00045722345,0.0003982228,0.0004950406,0.0000021023814,0.009913299,0.3960536,0.15207775,0.006758704,0.00030060144,0.43285927],"study_design_scores_gemma":[0.0009591386,0.0006979385,0.00078540837,0.0010048606,0.0001781789,0.000060372233,0.0032129413,0.46400502,0.48616925,0.042231005,0.00030546638,0.00039042233],"about_ca_topic_score_codex":0.00008450775,"about_ca_topic_score_gemma":0.00021275177,"teacher_disagreement_score":0.43246883,"about_ca_system_score_codex":0.00004340277,"about_ca_system_score_gemma":0.0000313273,"threshold_uncertainty_score":0.39518404},"labels":[],"label_agreement":null},{"id":"W2799971163","doi":"10.1109/iscas.2018.8351431","title":"Layout-dependent effects aware g<sub>m</sub>/i<sub>D</sub>-based many-objective sizing optimization for analog integrated circuits","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Sizing; Parasitic extraction; Computer science; Analogue electronics; Nonlinear programming; Electronic circuit; Electronic engineering; Interconnection; Mathematical optimization; Nonlinear system; Engineering; Mathematics; Electrical engineering","score_opus":0.009012290998788246,"score_gpt":0.21499087578384327,"score_spread":0.205978584785055,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2799971163","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18732695,0.000093648196,0.8076879,0.000018304365,0.0004249672,0.0012614992,0.000046618683,0.0023275546,0.00081259414],"genre_scores_gemma":[0.9942037,0.000044565382,0.0044880537,0.0002386915,0.00029236538,0.00038816972,0.00016986721,0.00016249256,0.000012116273],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.998011,0.00008796964,0.00043769946,0.0005360826,0.00028484326,0.0006424333],"domain_scores_gemma":[0.9986899,0.00025362003,0.000098464305,0.00041239054,0.00036627855,0.00017933037],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00033986993,0.00049328397,0.00045726716,0.00041064428,0.00020385635,0.0001297279,0.0002663345,0.00038376753,0.000021235328],"category_scores_gemma":[0.00013621507,0.00047840097,0.0001827857,0.0004927017,0.000072278344,0.00039957723,0.00003876467,0.00029637152,0.00005271732],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004279878,0.00008534148,0.00013094571,0.00034219614,0.00017297693,0.000020382806,0.00029574666,0.04150956,0.9020748,0.0002736879,0.0020770526,0.052974522],"study_design_scores_gemma":[0.00055997155,0.00028768397,0.00014790517,0.00013401774,0.000059336056,0.000004313135,0.000043839973,0.35158092,0.6465673,0.00018618605,0.00003252225,0.00039604437],"about_ca_topic_score_codex":0.00002394982,"about_ca_topic_score_gemma":0.000072683324,"teacher_disagreement_score":0.8068767,"about_ca_system_score_codex":0.00039682124,"about_ca_system_score_gemma":0.00008058694,"threshold_uncertainty_score":0.99976677},"labels":[],"label_agreement":null},{"id":"W2800418272","doi":"10.1145/3158215","title":"Eh?Legalizer","year":2018,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo; University of Calgary","funders":"Alberta Innovates - Technology Futures; CMC Microsystems","keywords":"Legalization; Computer science; Robustness (evolution); Scalability; Routing (electronic design automation); Standard cell; Floorplan; Mathematical optimization; Process (computing); Parallel computing; Algorithm; Embedded system; Mathematics; Integrated circuit","score_opus":0.017845804125772382,"score_gpt":0.23808365911985227,"score_spread":0.22023785499407988,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2800418272","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0023538757,0.00032254888,0.9930903,0.000029743276,0.0003516586,0.00048064033,0.0000059051517,0.0013241591,0.0020412095],"genre_scores_gemma":[0.9938015,0.00007497507,0.005400153,0.000014666026,0.00007623803,0.00014835878,0.000002991392,0.000042781216,0.0004383343],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9987934,0.000094630544,0.00038779018,0.00016623235,0.00022967244,0.00032824345],"domain_scores_gemma":[0.99914575,0.00011725152,0.00006653518,0.00051386806,0.0001082966,0.00004830778],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003470774,0.00017658478,0.00022647205,0.00027239806,0.00008737158,0.000032055228,0.00027289044,0.00014425041,0.00018677904],"category_scores_gemma":[0.000015607677,0.00017731645,0.000078173725,0.00036779462,0.000051286468,0.00019575372,0.0000012641948,0.00016154288,0.00017612962],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00022027621,0.00054468546,0.000023921988,0.000850995,0.0013767448,0.0000063520483,0.0024246275,0.28234443,0.4547756,0.020558603,0.03407747,0.2027963],"study_design_scores_gemma":[0.0005842936,0.0011968312,0.00006116905,0.00019122145,0.00007718896,0.00005206702,0.00007760625,0.43727857,0.54823303,0.0024412437,0.009346448,0.00046034594],"about_ca_topic_score_codex":0.00001832911,"about_ca_topic_score_gemma":0.0000035868945,"teacher_disagreement_score":0.9914476,"about_ca_system_score_codex":0.00019110322,"about_ca_system_score_gemma":0.000051231247,"threshold_uncertainty_score":0.7230755},"labels":[],"label_agreement":null},{"id":"W2800869073","doi":"10.1109/iscas.2018.8351560","title":"Fast Performance Evaluation for Analog Circuit Synthesis Frameworks","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Computer science; Network topology; Schematic; Analogue electronics; Graph; Electronic circuit; Computer engineering; Algorithm; Topology (electrical circuits); Theoretical computer science; Electronic engineering; Engineering; Electrical engineering","score_opus":0.02707449811160098,"score_gpt":0.2559348126299347,"score_spread":0.22886031451833375,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2800869073","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07670498,0.000053434986,0.8746686,0.000020214584,0.00017084034,0.00034072463,0.000004099345,0.0007046094,0.04733247],"genre_scores_gemma":[0.99124575,0.000023664985,0.0081295045,0.00005698627,0.000214203,0.00022187209,0.0000035922806,0.000020215775,0.00008418617],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99952465,0.000007887487,0.000107475804,0.00009863554,0.00010921415,0.00015215564],"domain_scores_gemma":[0.99962527,0.00007224662,0.00001141065,0.00016152173,0.000101667814,0.00002791562],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00028640358,0.00007955211,0.00008387359,0.00006159615,0.00005408003,0.00002252931,0.00009079606,0.00015713932,0.0004664139],"category_scores_gemma":[0.00006818447,0.00007318338,0.000032632728,0.00009257789,0.000022233535,0.00010999247,0.000005813251,0.000084320505,0.00005905261],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000034425905,0.000008705062,0.00030327484,0.000037744594,0.000026445317,7.909854e-8,0.00014294675,0.00036355495,0.0051384824,0.0007432723,0.009607807,0.9836242],"study_design_scores_gemma":[0.00008691365,0.000091692425,0.0018716835,0.00004806811,0.000038574737,0.0000017030814,0.000041008458,0.7991108,0.19419777,0.002064989,0.0022448655,0.00020193185],"about_ca_topic_score_codex":0.000002337724,"about_ca_topic_score_gemma":0.000004849002,"teacher_disagreement_score":0.98342234,"about_ca_system_score_codex":0.000043472584,"about_ca_system_score_gemma":0.00000841458,"threshold_uncertainty_score":0.5106905},"labels":[],"label_agreement":null},{"id":"W2801467633","doi":"10.1109/isqed.2018.8357272","title":"Parasitic-aware gm/I&lt;inf&gt;D&lt;/inf&gt;-based many-objective analog/RF circuit sizing","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Parasitic extraction; Sizing; CMOS; Comparator; Electronic engineering; Computer science; Electrical engineering; Engineering; Voltage","score_opus":0.015300919450181241,"score_gpt":0.2329725486858125,"score_spread":0.21767162923563124,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2801467633","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.060504526,0.00041983408,0.7670558,0.00010472369,0.00061355217,0.00082600676,0.00006478711,0.0055444855,0.16486625],"genre_scores_gemma":[0.9945946,0.000037741334,0.0032579887,0.0004949727,0.0004969163,0.00010171713,0.000038114944,0.00013452845,0.0008434328],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.997666,0.000059968726,0.0004994426,0.0005394442,0.00039224053,0.0008428852],"domain_scores_gemma":[0.99855167,0.00017786656,0.0000738937,0.0007238964,0.00022609024,0.00024660706],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00033304474,0.00050963607,0.0004998621,0.00036273568,0.00022309335,0.00014207719,0.0004432484,0.00035571144,0.0010451095],"category_scores_gemma":[0.00006153644,0.00050720386,0.0002133261,0.0005452994,0.00016229997,0.0003433136,0.000044156986,0.00033989034,0.00062880904],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000112947804,0.000498182,0.008695989,0.0008163899,0.0009806027,0.000530125,0.0028120857,0.0026511592,0.74364203,0.033871647,0.10990121,0.095487654],"study_design_scores_gemma":[0.0017885588,0.0011257189,0.016615365,0.00043482933,0.00025392268,0.000078108475,0.0003245071,0.10435115,0.8302599,0.005191659,0.036680046,0.0028962255],"about_ca_topic_score_codex":0.00006954946,"about_ca_topic_score_gemma":0.0001472257,"teacher_disagreement_score":0.9340901,"about_ca_system_score_codex":0.00027262457,"about_ca_system_score_gemma":0.00007411239,"threshold_uncertainty_score":0.9998681},"labels":[],"label_agreement":null},{"id":"W28414101","doi":"10.1016/j.pneurobio.2017.04.002","title":"A Novel Floorplanning for Hierarchical VLSI Design.","year":2009,"lang":"en","type":"article","venue":"Computers and Their Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Government of Jiangsu Province; National Natural Science Foundation of China","keywords":"Floorplan; Very-large-scale integration; Computer science; Computer architecture; Physical design; Integrated circuit layout; Parallel computing; Integrated circuit design; Embedded system; Integrated circuit; Circuit design","score_opus":0.019428657818499746,"score_gpt":0.22927292271664956,"score_spread":0.2098442648981498,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W28414101","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00033174793,0.00023325431,0.99795187,0.00015866072,0.000020610058,0.0004561817,0.000012785928,0.00045357874,0.00038131358],"genre_scores_gemma":[0.689495,0.000030993375,0.30985674,0.00020043906,0.00012212119,0.0002524577,0.000016598802,0.000014090979,0.000011570361],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99963576,0.0000034327286,0.00009385715,0.00011797699,0.00002269805,0.00012625741],"domain_scores_gemma":[0.99971604,0.00007892994,0.000010150038,0.0001256663,0.000014399196,0.00005479789],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000059501926,0.00009187343,0.000096900105,0.00004641868,0.00008933688,0.000034883094,0.00009955259,0.0000437337,7.686783e-7],"category_scores_gemma":[0.0000012047113,0.000080598096,0.00003109619,0.000073493895,0.000018363357,0.000035648227,0.000009157909,0.00006332272,0.0000014553502],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000072667103,0.00007053949,0.0000047916833,0.0000341024,0.00003580886,3.080755e-7,0.0005039912,0.0029348256,0.07813647,0.050531372,0.006948227,0.8607923],"study_design_scores_gemma":[0.0004914561,0.0001529866,0.00037537472,0.00003982343,0.00001503343,0.000034442077,0.000025825124,0.8754174,0.013473184,0.052640248,0.05696486,0.00036934434],"about_ca_topic_score_codex":3.6291883e-7,"about_ca_topic_score_gemma":6.8616146e-8,"teacher_disagreement_score":0.8724826,"about_ca_system_score_codex":0.000009117663,"about_ca_system_score_gemma":0.0000044443505,"threshold_uncertainty_score":0.32866952},"labels":[],"label_agreement":null},{"id":"W2883647869","doi":"10.1145/3195800","title":"Wotan","year":2018,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Benchmark (surveying); Field-programmable gate array; Routing (electronic design automation); Parallel computing; Lookup table; Embedded system","score_opus":0.014460874857942226,"score_gpt":0.2214055918945223,"score_spread":0.20694471703658007,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2883647869","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20443708,0.004165736,0.6800349,0.0010528298,0.0027712195,0.0011069482,0.00005458717,0.012623437,0.09375326],"genre_scores_gemma":[0.99784446,0.0002754132,0.00060879,0.000025597134,0.000040564773,0.00011440519,9.020031e-7,0.000025160165,0.001064723],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99931437,0.000015225018,0.00019474323,0.00018688255,0.000056036075,0.0002327685],"domain_scores_gemma":[0.9993849,0.0000381159,0.000019271594,0.00047109468,0.000040515108,0.00004614096],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000117812095,0.0001455159,0.0001923322,0.00047036575,0.00017862521,0.000030240717,0.00020771692,0.00032767202,0.00012521085],"category_scores_gemma":[0.000008993505,0.000138998,0.000028426795,0.00039266585,0.00015628582,0.000083166226,0.0000012312141,0.00026526387,0.00014314259],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000042405587,0.000117938536,0.00046771413,0.0002955765,0.00042470833,0.00003178156,0.00037967102,0.0004985154,0.082854666,0.018444585,0.0068190405,0.8896234],"study_design_scores_gemma":[0.0010787869,0.0014906484,0.00023229951,0.0004783904,0.000105089275,0.00090008223,0.0014636548,0.018854128,0.7782409,0.025429642,0.17038877,0.0013375788],"about_ca_topic_score_codex":0.00001208103,"about_ca_topic_score_gemma":0.000010471525,"teacher_disagreement_score":0.8882858,"about_ca_system_score_codex":0.000028137652,"about_ca_system_score_gemma":0.000006668584,"threshold_uncertainty_score":0.5668174},"labels":[],"label_agreement":null},{"id":"W2887357719","doi":"10.5555/3199700.3199819","title":"DATC RDF: robust design flow database","year":2017,"lang":"en","type":"article","venue":"International Conference on Computer Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary; Microsemi (Canada)","funders":"","keywords":"Computer science; RDF; Database; Design flow; Physical design; Database design; Data mining; Information retrieval; Circuit design; Semantic Web; Embedded system","score_opus":0.16137316123309314,"score_gpt":0.29884269166096666,"score_spread":0.13746953042787352,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2887357719","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00014598784,0.000018708386,0.9878664,0.0003164856,0.0014948533,0.00032795654,0.00005298619,0.00068185356,0.0090947775],"genre_scores_gemma":[0.56232285,0.00011133209,0.43642974,0.00022751528,0.0004990377,0.000063277505,0.000054301086,0.000047752852,0.0002441613],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99847597,0.000088823865,0.0003175164,0.00040738852,0.00040336038,0.00030696855],"domain_scores_gemma":[0.99852014,0.00015673345,0.00010262411,0.00089406193,0.00019495464,0.00013146202],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00041821538,0.00031286982,0.00024845265,0.00018872129,0.00021021152,0.0007166558,0.0015719219,0.000119526114,0.00042240546],"category_scores_gemma":[0.000055804343,0.00031095167,0.000075597905,0.00004006083,0.00007994094,0.0006657638,0.00016352166,0.00031109917,0.00033980553],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00025653522,0.00025891353,0.00012085807,0.00006179671,0.0005030969,0.00049872644,0.0003635332,0.32918757,0.017721813,0.036031757,0.24131745,0.37367794],"study_design_scores_gemma":[0.00043207692,0.00013710916,0.0001775402,0.00016983852,0.000011151453,0.000022149166,0.0000038314747,0.9797432,0.013774372,0.0037648939,0.001395109,0.0003687705],"about_ca_topic_score_codex":0.000017350945,"about_ca_topic_score_gemma":0.0000020689317,"teacher_disagreement_score":0.65055555,"about_ca_system_score_codex":0.00009485697,"about_ca_system_score_gemma":0.000059621205,"threshold_uncertainty_score":0.99993426},"labels":[],"label_agreement":null},{"id":"W28973634","doi":"10.7326/m16-2871","title":"Enhancing and Using an Automatic Design System for Creating FPGAs","year":2005,"lang":"en","type":"article","venue":"Annals of Internal Medicine","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"National Heart, Lung, and Blood Institute; National Institute on Aging; American College of Cardiology Foundation; Natural Sciences and Engineering Research Council of Canada; Agency for Healthcare Research and Quality; University of Toronto","keywords":"Field-programmable gate array; Computer science; Embedded system; Computer architecture; Reconfigurable computing; Task (project management); Page layout; Circuit design; Architecture; Application-specific integrated circuit; Integrated circuit layout; Computer hardware; Integrated circuit; Engineering; Systems engineering; Operating system","score_opus":0.07016267351587435,"score_gpt":0.3337723562325478,"score_spread":0.26360968271667345,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W28973634","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.29014954,0.0010873283,0.7076148,0.000053823365,0.00007953436,0.000194991,0.0000019490888,0.00025328863,0.0005647714],"genre_scores_gemma":[0.94805175,0.00003788709,0.05141403,0.00009666942,0.000344255,0.000012823792,9.030747e-7,0.000026621421,0.0000150758615],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99918544,0.000026186644,0.0003920785,0.00010647746,0.000113508766,0.00017628941],"domain_scores_gemma":[0.9994739,0.00016303812,0.00007973088,0.00011551673,0.000084974046,0.00008281412],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00058935315,0.00012547865,0.00028820007,0.00012887383,0.000033383276,0.000010093057,0.00010005541,0.000051075538,0.000013309746],"category_scores_gemma":[0.00010373,0.00010349785,0.000029711522,0.000054540145,0.000036861053,0.00016187587,0.000010961633,0.00006846457,6.636214e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000041911033,0.00003443659,0.00013248583,0.0018180028,0.00016142534,0.000011796108,0.0033113044,0.0051239394,0.861937,0.0005231853,0.0011195868,0.12578492],"study_design_scores_gemma":[0.00019935514,0.00033726761,0.00003632198,0.0021054358,0.000024747043,0.000049732345,0.00033242587,0.4845835,0.5120513,0.000103573184,0.00008808972,0.00008826284],"about_ca_topic_score_codex":0.000063732215,"about_ca_topic_score_gemma":0.0000049532664,"teacher_disagreement_score":0.6579022,"about_ca_system_score_codex":0.000023837647,"about_ca_system_score_gemma":0.0000069578623,"threshold_uncertainty_score":0.422052},"labels":[],"label_agreement":null},{"id":"W2897505503","doi":"10.1145/3233244","title":"GPlace3.0","year":2018,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":60,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Router; Parallel computing; Routing (electronic design automation); Reduction (mathematics); Benchmark (surveying); Embedded system; Computer engineering; Algorithm; Computer network; Mathematics","score_opus":0.01641232852791342,"score_gpt":0.232863703928349,"score_spread":0.21645137540043558,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2897505503","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0029904735,0.00028049675,0.99295765,0.000024932793,0.0003044591,0.00045592352,0.0000052575156,0.0013045206,0.0016762894],"genre_scores_gemma":[0.99389565,0.00007317639,0.005440502,0.000010893702,0.00006673197,0.00012960105,0.0000026038867,0.000037271067,0.000343594],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988996,0.00008617914,0.00035162418,0.0001517403,0.00020660665,0.00030424536],"domain_scores_gemma":[0.9991947,0.00013593966,0.00006119482,0.0004695884,0.00009408311,0.0000445044],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00034548025,0.00016118448,0.00020633246,0.00025749544,0.00008231545,0.000026126243,0.0002559004,0.0001313707,0.0001461457],"category_scores_gemma":[0.000015245885,0.00016356743,0.000066436885,0.0003419121,0.000046177694,0.00016340853,0.0000011283865,0.00015116722,0.00017312469],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000209741,0.00043645612,0.000020159398,0.0007094403,0.0010582936,0.0000045944516,0.0019816794,0.36137968,0.38392133,0.012563436,0.024029074,0.21368611],"study_design_scores_gemma":[0.0004704187,0.0011157232,0.000045948105,0.00015064866,0.000055368437,0.000042369542,0.00007566571,0.5074853,0.48400038,0.001822643,0.004377157,0.00035839452],"about_ca_topic_score_codex":0.000011727495,"about_ca_topic_score_gemma":0.0000032054813,"teacher_disagreement_score":0.99090517,"about_ca_system_score_codex":0.00018643825,"about_ca_system_score_gemma":0.000047345795,"threshold_uncertainty_score":0.66700864},"labels":[],"label_agreement":null},{"id":"W2905187565","doi":"10.1109/fpl.2018.00054","title":"Multi-fidelity Optimization for High-Level Synthesis Directives","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"High-level synthesis; High fidelity; Computer science; Fidelity; Design space exploration; Field-programmable gate array; Design flow; Electronic design automation; Computer architecture; CAD; Embedded system; Computer engineering; Engineering; Engineering drawing","score_opus":0.03676464153402379,"score_gpt":0.2557620574418277,"score_spread":0.2189974159078039,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2905187565","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00267905,0.000025846717,0.9929672,0.000019443192,0.00011661927,0.00020681157,0.000024290664,0.0011221992,0.0028385532],"genre_scores_gemma":[0.5391974,0.00001496216,0.46045113,0.000016589469,0.00006714367,0.00007982475,0.0000027090957,0.000016374222,0.00015389657],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999593,0.0000096008125,0.00011281623,0.000115451236,0.00004288541,0.00012624187],"domain_scores_gemma":[0.99966794,0.00008141083,0.000011456587,0.00013173654,0.00007878955,0.000028649078],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000110575056,0.00008618952,0.00009910718,0.000046979105,0.00005042843,0.000018561617,0.000071972485,0.00006567838,0.00018211517],"category_scores_gemma":[0.00009510009,0.000077647295,0.000030346995,0.00006561043,0.000025465915,0.00010862196,0.000009258411,0.000026185879,0.000013481313],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010304502,0.00038778098,0.0009900854,0.00050237466,0.00047962798,0.0000022793984,0.0011845918,0.036352362,0.2788722,0.011842193,0.07210242,0.597181],"study_design_scores_gemma":[0.000107748536,0.000030852047,0.0012397621,0.000013515812,0.000012963701,4.572472e-7,0.000016491866,0.50752056,0.49000406,0.00038817362,0.00050775893,0.00015765095],"about_ca_topic_score_codex":0.000027908285,"about_ca_topic_score_gemma":0.000016243283,"teacher_disagreement_score":0.59702337,"about_ca_system_score_codex":0.00003065979,"about_ca_system_score_gemma":0.000004205127,"threshold_uncertainty_score":0.31663647},"labels":[],"label_agreement":null},{"id":"W2907894052","doi":"10.22215/etd/2015-11198","title":"Lightweight Robust Optimizer for Distributed Application Deployment in Multi-Clouds","year":2015,"lang":"en","type":"dissertation","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Computer science; Software deployment; Cloud computing; Distributed computing; Simulated annealing; Graph; Power consumption; Enhanced Data Rates for GSM Evolution; Graph partition; Bin packing problem; Bin; Parallel computing; Mathematical optimization; Theoretical computer science; Algorithm; Power (physics); Mathematics; Artificial intelligence","score_opus":0.028067011463482974,"score_gpt":0.2756158198303103,"score_spread":0.24754880836682733,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2907894052","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0021572697,0.00065937045,0.98964024,0.000015786174,0.00032596337,0.001856093,0.0001403301,0.0013210395,0.003883899],"genre_scores_gemma":[0.46979406,0.0010453733,0.4246993,0.0000793666,0.0005503603,0.016898666,0.07019447,0.00087482965,0.015863536],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99895626,0.0000099818,0.00037328343,0.000270161,0.00014035567,0.00024998176],"domain_scores_gemma":[0.99946505,0.000025634097,0.000056264777,0.00025538538,0.000120801036,0.00007687323],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00015219579,0.00029098516,0.00032214384,0.000148946,0.000023559822,0.0000329722,0.00018817848,0.0004423493,0.000024404319],"category_scores_gemma":[0.000015177578,0.00027935114,0.00008184841,0.0001662221,0.0000053542535,0.00007404452,0.0000073514593,0.00018568468,0.000019796122],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00052921876,0.0014067978,0.00055234315,0.00440055,0.0006780379,0.0000227528,0.0027443292,0.22521977,0.03894109,0.0041985763,0.57661486,0.14469165],"study_design_scores_gemma":[0.0023192405,0.00010379485,0.0006142967,0.00024641925,0.00012984964,0.0000020104435,0.0003425998,0.85261244,0.096815586,0.001310493,0.044062216,0.0014410715],"about_ca_topic_score_codex":0.000042239782,"about_ca_topic_score_gemma":0.00039523674,"teacher_disagreement_score":0.62739265,"about_ca_system_score_codex":0.00026058438,"about_ca_system_score_gemma":0.00003286729,"threshold_uncertainty_score":0.99996585},"labels":[],"label_agreement":null},{"id":"W2908823030","doi":"10.4324/9781315276649-11","title":"Getting beneath the surface","year":2018,"lang":"en","type":"book-chapter","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Geology; Surface (topology); Geometry; Mathematics","score_opus":0.014791398428957665,"score_gpt":0.19787153718355344,"score_spread":0.18308013875459578,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2908823030","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000040177172,0.0007604787,0.010453026,0.00003164781,0.00017100127,0.00015748627,0.000008110288,0.0013284114,0.98704964],"genre_scores_gemma":[0.0055421363,0.000409083,0.004379372,0.00014587933,0.0005074874,0.0000040503865,0.0000110463225,0.00014304354,0.9888579],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9994314,0.0000028325956,0.00015453083,0.00013352044,0.00012012242,0.00015764678],"domain_scores_gemma":[0.9995213,0.000041003932,0.00002439586,0.0003525999,0.000030209487,0.000030455649],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00011895843,0.00022128018,0.00016437533,0.000026531996,0.00005279926,0.000037679514,0.00022835754,0.00023783593,0.0024068959],"category_scores_gemma":[0.0000026643388,0.00014776728,0.00008369595,0.000010122196,0.000042691725,0.00003232676,0.00004040213,0.0002592471,0.0005392095],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000216458,0.0000034815928,0.000005210122,0.00013526306,0.00026270456,0.000021726853,0.00040842275,0.00027377356,0.0023424714,0.18150039,0.78283954,0.03220486],"study_design_scores_gemma":[0.00003293979,0.00002688697,0.0000025283935,0.00009825441,0.000033386066,0.000010081179,0.0000074761806,0.002211072,0.004847751,0.02386224,0.9684592,0.0004081927],"about_ca_topic_score_codex":0.000004376568,"about_ca_topic_score_gemma":0.000006931671,"teacher_disagreement_score":0.18561965,"about_ca_system_score_codex":0.000033577806,"about_ca_system_score_gemma":0.0000072179446,"threshold_uncertainty_score":0.99850506},"labels":[],"label_agreement":null},{"id":"W2911319947","doi":"10.1109/rsp.2018.8631999","title":"Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Field-programmable gate array; Computer science; Verilog; Software deployment; Embedded system; Leverage (statistics); Computer architecture; Hardware description language; Computer hardware; High-level synthesis; Routing (electronic design automation); Operating system","score_opus":0.03138668725022993,"score_gpt":0.24326996544594884,"score_spread":0.2118832781957189,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2911319947","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019507874,0.000035300483,0.8174287,0.00009416631,0.00015629567,0.00048552002,0.000011014054,0.001803879,0.17803434],"genre_scores_gemma":[0.95385176,0.00003054423,0.04373608,0.00020458261,0.00020365231,0.00052560517,0.0000021672954,0.00006506591,0.0013805173],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99933916,0.000008689069,0.00014103537,0.0001480079,0.00009574804,0.0002673861],"domain_scores_gemma":[0.99961054,0.00007213047,0.00001097521,0.00020678776,0.000038495436,0.00006107326],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016770502,0.00013513277,0.00016904746,0.00007624577,0.000055207616,0.000031226074,0.00013631542,0.00008055196,0.0004893544],"category_scores_gemma":[0.00004110425,0.00011707744,0.00008014583,0.000071461174,0.000023463479,0.00005996804,0.00000897867,0.000045395216,0.0000600721],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000119984536,0.00018277408,0.0000074269183,0.0002525669,0.000275918,0.000008890234,0.0006053603,0.001233163,0.040305678,0.024190964,0.20616412,0.72665316],"study_design_scores_gemma":[0.00034423865,0.00025599834,0.000024050645,0.000034240144,0.000027252367,0.0000025080747,0.000040344083,0.01779027,0.94719934,0.0032836164,0.030730637,0.00026753015],"about_ca_topic_score_codex":0.000012209837,"about_ca_topic_score_gemma":0.0000021069275,"teacher_disagreement_score":0.951901,"about_ca_system_score_codex":0.000074533375,"about_ca_system_score_gemma":0.000011604419,"threshold_uncertainty_score":0.53580874},"labels":[],"label_agreement":null},{"id":"W2911751195","doi":"10.1145/3301298","title":"COFFE 2","year":2019,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":62,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Field-programmable gate array; Lookup table; Block (permutation group theory); Embedded system; Computer architecture; Interface (matter); Computer hardware; Parallel computing; Operating system","score_opus":0.009955210054345838,"score_gpt":0.2020108655535977,"score_spread":0.19205565549925188,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2911751195","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6526063,0.0071654622,0.21895956,0.0009675942,0.003460394,0.0021646137,0.000070581016,0.012402207,0.10220329],"genre_scores_gemma":[0.9967395,0.00037863868,0.00027108035,0.000022263814,0.000010263209,0.00011273237,0.0000016698938,0.000025622328,0.0024382444],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99932975,0.000014872604,0.00019052021,0.00018899546,0.000060531638,0.00021533387],"domain_scores_gemma":[0.9993651,0.000056269848,0.00002010561,0.0004973747,0.00002237271,0.00003877772],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010936096,0.0001463925,0.00023086711,0.0004531491,0.000075977834,0.000026938467,0.0001987859,0.0003304955,0.00018218376],"category_scores_gemma":[0.0000048131915,0.00014006736,0.000034271543,0.00031147464,0.000045053737,0.00008909716,0.0000011750265,0.0003247182,0.0002939869],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007078728,0.00021932907,0.0037279187,0.001431427,0.0008397597,0.00005110801,0.00037456947,0.0151008945,0.19788466,0.03928079,0.006415865,0.73460287],"study_design_scores_gemma":[0.00296334,0.0017357087,0.0006868807,0.0010852452,0.00016804233,0.0013148393,0.002814981,0.05708344,0.65422606,0.024401074,0.25089225,0.0026280892],"about_ca_topic_score_codex":0.000010398001,"about_ca_topic_score_gemma":0.0000025265958,"teacher_disagreement_score":0.7319748,"about_ca_system_score_codex":0.000028003104,"about_ca_system_score_gemma":0.000006653786,"threshold_uncertainty_score":0.57117814},"labels":[],"label_agreement":null},{"id":"W2921296408","doi":"10.48550/arxiv.1903.05304","title":"On the depth of cutting planes","year":2019,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Polyhedron; Intersection (aeronautics); Cutting-plane method; Simplex; Mathematics; Plane (geometry); Geometry; Parametric statistics; Combinatorics; Algorithm; Integer programming; Engineering","score_opus":0.0607409193743733,"score_gpt":0.15933847223704323,"score_spread":0.09859755286266993,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2921296408","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.83785003,0.00010046589,0.094050035,0.000015188267,0.00038748878,0.00042046476,0.000035201483,0.00063433376,0.06650678],"genre_scores_gemma":[0.9991919,0.0001623377,0.00009478458,0.000021197848,0.0000326272,6.078979e-7,0.00000957891,0.000027693319,0.00045929218],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993944,0.000037693804,0.000116263946,0.0002431339,0.00004697365,0.00016151414],"domain_scores_gemma":[0.99912107,0.00018160787,0.00007358534,0.0005613139,0.000031196483,0.000031237952],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001217172,0.00018930584,0.00021797749,0.00011863423,0.00003199882,0.000013864083,0.00048308965,0.00020826844,0.00005132275],"category_scores_gemma":[0.000017278146,0.0001661238,0.00011888091,0.00012652547,0.000041661526,0.000037727274,0.00017141752,0.00044514218,0.00005930947],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001995836,0.000027920507,0.0026000324,0.00035382464,0.00016899072,0.00005286976,0.00017886698,0.8879606,0.0005440179,0.10391711,0.0036206879,0.00055511936],"study_design_scores_gemma":[0.0004956455,0.00016851441,0.0022891855,0.0010983862,0.00024483894,0.0000061099227,0.00037145911,0.87645555,0.031561397,0.08426123,0.0018089786,0.001238718],"about_ca_topic_score_codex":0.000033369244,"about_ca_topic_score_gemma":0.0000059637796,"teacher_disagreement_score":0.16134185,"about_ca_system_score_codex":0.000058786503,"about_ca_system_score_gemma":0.000020469673,"threshold_uncertainty_score":0.67743325},"labels":[],"label_agreement":null},{"id":"W2925797319","doi":"10.1145/3317575","title":"An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement","year":2019,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Placement; Algorithm; Very-large-scale integration; Design flow; Electronic circuit; Physical design; Circuit design; Embedded system; Electrical engineering","score_opus":0.010827797269848546,"score_gpt":0.23349491403872633,"score_spread":0.2226671167688778,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2925797319","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007923501,0.00009466415,0.98839265,0.000014801754,0.00028580974,0.002457999,0.000020814552,0.0006596394,0.00015014487],"genre_scores_gemma":[0.9151698,0.00006142309,0.08386758,0.00001504142,0.00001736105,0.00063817634,0.000013415347,0.000052339004,0.00016488647],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99831903,0.00018073327,0.0005385374,0.00026587586,0.0002767458,0.000419084],"domain_scores_gemma":[0.998988,0.00016154283,0.00006870356,0.0006313179,0.000060910843,0.000089566005],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005800955,0.00023311863,0.00038091643,0.00049645646,0.000034282726,0.000042472322,0.00032898612,0.00015594221,0.00015825873],"category_scores_gemma":[0.0000058758555,0.00024810436,0.00006991516,0.00044817946,0.000009218364,0.0002433742,0.0000018663575,0.00021159941,0.00016639841],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004112554,0.00009109968,0.000002470447,0.00005440055,0.000047144164,7.5367956e-7,0.00020260981,0.9101994,0.06421139,0.000021746535,0.000121639736,0.025006207],"study_design_scores_gemma":[0.00081535685,0.0005627109,0.00001724884,0.00011547228,0.000017903329,0.0000047461294,0.00008636886,0.81710017,0.18084921,0.00003570418,0.00017866035,0.00021647694],"about_ca_topic_score_codex":0.000030264877,"about_ca_topic_score_gemma":0.000010065687,"teacher_disagreement_score":0.9072463,"about_ca_system_score_codex":0.00052424974,"about_ca_system_score_gemma":0.00006737524,"threshold_uncertainty_score":0.99999714},"labels":[],"label_agreement":null},{"id":"W2943340242","doi":"10.1109/icm.2018.8704066","title":"An Effective FPGA Placement Flow Selection Framework using Machine Learning","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Benchmark (surveying); Computer science; Selection (genetic algorithm); Flow (mathematics); CONTEST; Placement; CAD; Design flow; Parallel computing; Computer engineering; Computer architecture; Embedded system; Machine learning; Circuit design; Physical design; Engineering drawing; Mathematics; Engineering","score_opus":0.008083971132520039,"score_gpt":0.25359297142447385,"score_spread":0.2455090002919538,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2943340242","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.12189407,0.000057353453,0.87387997,0.0000025835354,0.00014567711,0.00019808354,8.0908063e-7,0.0015629457,0.0022585304],"genre_scores_gemma":[0.88766426,0.000008105914,0.111925885,0.000027802338,0.00028437382,0.000017571456,0.0000041361636,0.000034390127,0.000033499688],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994166,0.00004651763,0.00010347501,0.00014467619,0.00009233761,0.00019638136],"domain_scores_gemma":[0.99975467,0.000034308483,0.000014429065,0.0001029535,0.000039368642,0.000054253665],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016093235,0.00012851603,0.00010784809,0.00008546779,0.00012659837,0.00004160565,0.00006279681,0.000113056725,0.0003422267],"category_scores_gemma":[0.000017675746,0.000121928264,0.000026591288,0.00017952052,0.000018793316,0.00014738088,0.000011615199,0.00024522032,0.000036446778],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008268408,0.000119904995,0.010402054,0.000088669156,0.00025678158,0.000006565357,0.0022725516,0.22686666,0.53321743,0.0008057729,0.00089141406,0.22498953],"study_design_scores_gemma":[0.00006458196,0.00028369334,0.00021395306,0.000022816188,0.000012754273,0.0000053401695,0.000018462473,0.7378284,0.26057374,0.0002713903,0.00057069,0.00013418394],"about_ca_topic_score_codex":0.000055492834,"about_ca_topic_score_gemma":0.000023942466,"teacher_disagreement_score":0.76577014,"about_ca_system_score_codex":0.000096935764,"about_ca_system_score_gemma":0.0000039760193,"threshold_uncertainty_score":0.497209},"labels":[],"label_agreement":null},{"id":"W2943505044","doi":"10.1109/iscas.2019.8702574","title":"Graph-Grammar-Based Analog Circuit Topology Synthesis","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Computer science; Network topology; Topology (electrical circuits); Analogue electronics; Grammar; Algorithm; Circuit extraction; Electronic circuit; Theoretical computer science; Equivalent circuit; Electrical engineering; Engineering","score_opus":0.009702553313871999,"score_gpt":0.19216780046778428,"score_spread":0.1824652471539123,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2943505044","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15810095,0.00028073875,0.43848997,0.00015889127,0.00054803217,0.00047530045,0.000012323756,0.0046463283,0.3972875],"genre_scores_gemma":[0.9976227,0.000018772784,0.0017367622,0.00015379385,0.000025173724,0.00003221824,0.0000032487799,0.000025354402,0.00038194237],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994222,0.00001718754,0.0001275936,0.00013409184,0.00007329129,0.0002256669],"domain_scores_gemma":[0.9995495,0.00010210992,0.00001076119,0.0002727048,0.00001567781,0.000049261558],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000092556016,0.000115928255,0.00016676018,0.00014425498,0.000017272321,0.00001498312,0.00014587658,0.00011617877,0.0018709453],"category_scores_gemma":[0.000012240526,0.00010621268,0.00007706681,0.00015023512,0.000023035307,0.00004830613,0.000008229343,0.0000918088,0.0003394056],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000341179,0.00023267083,0.07614766,0.00074147683,0.0004774389,0.00009783823,0.00021391928,0.0062629213,0.40206888,0.15047514,0.078260794,0.28498715],"study_design_scores_gemma":[0.0006347974,0.00028854742,0.00827374,0.00007775818,0.00008661254,0.00002467987,0.00010496168,0.03384358,0.8882049,0.023378726,0.04364487,0.0014368326],"about_ca_topic_score_codex":0.00003571895,"about_ca_topic_score_gemma":0.000012937921,"teacher_disagreement_score":0.83952177,"about_ca_system_score_codex":0.000024937011,"about_ca_system_score_gemma":0.0000085326565,"threshold_uncertainty_score":0.9990415},"labels":[],"label_agreement":null},{"id":"W2945806107","doi":"10.1145/3316781.3317743","title":"A Flat Timing-Driven Placement Flow for Modern FPGAs","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":18,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Benchmark (surveying); Computer science; Suite; Parallel computing; Embedded system","score_opus":0.016342300333233688,"score_gpt":0.22390130738401534,"score_spread":0.20755900705078165,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2945806107","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013781538,0.00010243753,0.9528375,0.000030905696,0.00018644883,0.0006811054,0.00001383937,0.0012305302,0.031135675],"genre_scores_gemma":[0.90167564,0.000025614945,0.09373249,0.000098540884,0.00007175101,0.00012792612,0.000029564017,0.000050888375,0.0041875513],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99953675,0.0000028022757,0.00010274435,0.00010924769,0.000069548485,0.00017887639],"domain_scores_gemma":[0.9997512,0.000027024209,0.000007556568,0.00016466656,0.000013097497,0.000036454905],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000047916074,0.000098201584,0.00010998448,0.00004118599,0.000016218451,0.000018646388,0.000085224885,0.00005882946,0.00031686813],"category_scores_gemma":[0.0000022808442,0.00008861737,0.000039554754,0.000027695512,0.000003930072,0.00006657308,0.000015358024,0.000047798098,0.00017356926],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000050447845,0.000048589012,0.0003649641,0.0005120414,0.00020703078,0.000004092563,0.0012488576,0.45500848,0.2705395,0.003920362,0.20217869,0.065916955],"study_design_scores_gemma":[0.00023404718,0.00006399465,0.0000059078047,0.000011933263,0.000006801565,0.0000012003918,0.000015348678,0.95230657,0.0332664,0.000622521,0.01332785,0.00013743575],"about_ca_topic_score_codex":0.000002246982,"about_ca_topic_score_gemma":0.000002520706,"teacher_disagreement_score":0.88789415,"about_ca_system_score_codex":0.00003704262,"about_ca_system_score_gemma":0.0000049377168,"threshold_uncertainty_score":0.36137116},"labels":[],"label_agreement":null},{"id":"W2949081670","doi":"10.48550/arxiv.1305.0172","title":"An Optimal Algorithm for the Euclidean Bottleneck Full Steiner Tree Problem","year":2013,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Steiner tree problem; Combinatorics; k-minimum spanning tree; Mathematics; K-ary tree; Disjoint sets; Logarithm; Matching (statistics); Tree (set theory); Spanning tree; Euclidean minimum spanning tree; Discrete mathematics; Gomory–Hu tree; Upper and lower bounds; Minimum degree spanning tree; Tree structure; Binary tree","score_opus":0.04220076924491658,"score_gpt":0.1779886769648603,"score_spread":0.1357879077199437,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2949081670","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.030681487,0.00023370623,0.9636283,0.0000258388,0.000317254,0.0013145463,0.00010244362,0.0012452651,0.0024511477],"genre_scores_gemma":[0.95030797,0.0005573324,0.046652067,0.000037853355,0.00036742404,0.000042276617,0.00009462647,0.00014119885,0.0017992724],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99858195,0.00004959201,0.0002277513,0.0006169186,0.00007290212,0.0004509144],"domain_scores_gemma":[0.9985132,0.000108114014,0.00009643649,0.0009890054,0.00013533578,0.00015791017],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00022028686,0.00043557349,0.0003579694,0.00016743371,0.0001406883,0.00012496053,0.0010515699,0.00042910542,0.00010290771],"category_scores_gemma":[0.0000056837594,0.0003910672,0.00026419657,0.00018428334,0.000089062676,0.0002656671,0.00025025455,0.00056958606,0.00005237789],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005037131,0.00014420804,0.000099714,0.00034994454,0.00059695105,0.00007939532,0.00034745582,0.8347308,0.0013117504,0.007954214,0.0138987,0.14043652],"study_design_scores_gemma":[0.00034776345,0.00015564713,0.000076061784,0.00006013474,0.0001833797,0.0000038955604,0.0001069235,0.9874371,0.0011582829,0.0055581187,0.0043523503,0.00056033547],"about_ca_topic_score_codex":0.000078129524,"about_ca_topic_score_gemma":0.000027563185,"teacher_disagreement_score":0.9196265,"about_ca_system_score_codex":0.00015448904,"about_ca_system_score_gemma":0.000044784196,"threshold_uncertainty_score":0.99985415},"labels":[],"label_agreement":null},{"id":"W2949216549","doi":"10.1109/fpt.2018.00026","title":"Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":23,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Parallel computing; Kernel (algebra); Field-programmable gate array; Overhead (engineering); Correctness; Static timing analysis; Application-specific integrated circuit; Speedup; Multi-core processor; Compiler; Central processing unit; Embedded system; Computer hardware; Algorithm; Operating system","score_opus":0.028441975187797126,"score_gpt":0.2460384257316878,"score_spread":0.21759645054389068,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2949216549","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015111815,0.000049735114,0.9966374,0.000016580294,0.000025289366,0.00023019171,0.0000023466373,0.00040960542,0.0011176734],"genre_scores_gemma":[0.4581176,0.000024837651,0.5415688,0.000031945063,0.00003812522,0.00003768105,0.0000064013598,0.000014715629,0.00015984676],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995791,0.000008744036,0.0001189966,0.00012055599,0.000034264594,0.00013834279],"domain_scores_gemma":[0.999768,0.000039573297,0.000015044628,0.000103061764,0.000041335305,0.000032938136],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000104921164,0.000091942056,0.00012465907,0.00012564252,0.000048625032,0.000047118498,0.000048848353,0.000060737333,0.00004645129],"category_scores_gemma":[0.000009017727,0.00008142949,0.000040164192,0.00015031312,0.0000231697,0.00011898276,0.000009984345,0.000025500389,0.0000020807129],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000118932796,0.00005753151,0.0021807365,0.00018374708,0.0018702936,0.000002041132,0.0015866394,0.77861744,0.12778865,0.0009636949,0.012772026,0.07385828],"study_design_scores_gemma":[0.00012588059,0.000059123726,0.00017528079,0.000003247397,0.00010995382,5.7828197e-7,0.000022723658,0.9783732,0.020719826,0.00020291578,0.000088205605,0.00011904034],"about_ca_topic_score_codex":0.000006192775,"about_ca_topic_score_gemma":0.0000069451385,"teacher_disagreement_score":0.45660642,"about_ca_system_score_codex":0.000011231457,"about_ca_system_score_gemma":0.000002856158,"threshold_uncertainty_score":0.33205983},"labels":[],"label_agreement":null},{"id":"W2951713654","doi":"10.1109/fpt.2018.00040","title":"Synthesizable Heterogeneous FPGA Fabrics","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Stratix; Field-programmable gate array; Verilog; Computer science; Embedded system; Application-specific integrated circuit; Reuse; Computer architecture; Parallel computing; Computer hardware; Engineering","score_opus":0.010337273248006614,"score_gpt":0.20104452661585184,"score_spread":0.19070725336784522,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2951713654","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03453579,0.0002612844,0.63112706,0.000025866393,0.0003054633,0.0001478937,0.000003497875,0.0041866414,0.32940647],"genre_scores_gemma":[0.99145645,0.000035065033,0.0074294503,0.000093852235,0.00013953277,0.000009245638,7.514405e-7,0.000026226293,0.00080945325],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995937,0.0000050532735,0.00008577448,0.00008211834,0.00006157191,0.0001718095],"domain_scores_gemma":[0.9997394,0.000015200924,0.000005160684,0.00017549645,0.000021472846,0.000043265587],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000047444246,0.00008128476,0.00007707882,0.00004036732,0.000032224107,0.000022827817,0.00010259519,0.000056172925,0.00060674065],"category_scores_gemma":[0.0000066859548,0.00007304022,0.00002757935,0.000079155914,0.00002538962,0.000051700903,0.000014009881,0.000041055027,0.00048487002],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000014200334,0.000103148355,0.0008912945,0.00016780896,0.00019922105,0.00008974974,0.0004914345,0.0017139777,0.20797065,0.0051041157,0.35606444,0.42718998],"study_design_scores_gemma":[0.000035225803,0.000055985955,0.000021121245,0.00000763169,0.0000050654744,0.000014284836,0.0000069368907,0.018524272,0.92038894,0.0008743856,0.059903927,0.00016223475],"about_ca_topic_score_codex":0.000007238087,"about_ca_topic_score_gemma":0.00000668464,"teacher_disagreement_score":0.9569206,"about_ca_system_score_codex":0.000019660756,"about_ca_system_score_gemma":0.000003100428,"threshold_uncertainty_score":0.66433847},"labels":[],"label_agreement":null},{"id":"W2952969041","doi":"10.48550/arxiv.1509.01190","title":"Advanced Multilevel Node Separator Algorithms","year":2015,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Iterated local search; Computer science; Graph; Graph partition; Algorithm; Iterated function; Separator (oil production); Theoretical computer science; Local search (optimization); Mathematics","score_opus":0.07977483864723559,"score_gpt":0.19768250421305283,"score_spread":0.11790766556581725,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2952969041","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21631029,0.00051784626,0.76000684,0.000010075849,0.0012174739,0.00066810736,0.00023460582,0.0036131083,0.017421626],"genre_scores_gemma":[0.99257314,0.00035597445,0.005315853,0.000027232018,0.0001206565,0.0000041379694,0.00005713471,0.00008133453,0.0014645531],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987219,0.000039770468,0.00019162592,0.00059228414,0.000078309684,0.00037613235],"domain_scores_gemma":[0.99875,0.000032573997,0.00007511868,0.0007569433,0.00015165472,0.0002337552],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00013600317,0.00041479856,0.0004080394,0.0002130661,0.000051956893,0.000037833695,0.00061899767,0.00048450127,0.000051587038],"category_scores_gemma":[0.00001793979,0.00050954864,0.00016985186,0.00020741546,0.000061654115,0.00018575693,0.00036317218,0.0006735548,0.00018809675],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000031455696,0.00006323492,0.0003433391,0.00022753837,0.00019286315,0.00039136634,0.0002233848,0.97938323,0.00096902746,0.0016715624,0.010780444,0.005722555],"study_design_scores_gemma":[0.0006173213,0.00003570264,0.00018138367,0.00013277186,0.0000945268,0.0000044587464,0.000065795546,0.9775138,0.0034861977,0.00995343,0.00700872,0.0009059002],"about_ca_topic_score_codex":0.000034654364,"about_ca_topic_score_gemma":0.000007824234,"teacher_disagreement_score":0.7762628,"about_ca_system_score_codex":0.00036682127,"about_ca_system_score_gemma":0.00008620734,"threshold_uncertainty_score":0.9997356},"labels":[],"label_agreement":null},{"id":"W2954158457","doi":"10.1016/j.dam.2019.06.007","title":"Spectral bounds for graph partitioning with prescribed partition sizes","year":2019,"lang":"en","type":"article","venue":"Discrete Applied Mathematics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal; Group for Research in Decision Analysis; HEC Montréal","funders":"Agence Nationale de la Recherche","keywords":"Adjacency matrix; Graph partition; Eigenvalues and eigenvectors; Mathematics; Combinatorics; Graph energy; Strength of a graph; Graph; Adjacency list; Partition (number theory); Spectral graph theory; Undirected graph; Discrete mathematics; Line graph; Voltage graph","score_opus":0.008739207267766799,"score_gpt":0.20691535695033877,"score_spread":0.19817614968257197,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2954158457","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.177443,0.00006276128,0.7801807,0.000024728819,0.00007433659,0.0014135736,0.000034445256,0.0012517131,0.03951473],"genre_scores_gemma":[0.90507054,0.000013415544,0.09421213,0.000020164749,0.000051222833,0.00042294466,0.000054310643,0.000061779894,0.00009351305],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992131,0.0000027261924,0.00021307745,0.00015189307,0.00013929326,0.00027993493],"domain_scores_gemma":[0.99957055,0.00005895987,0.00004627999,0.00025158373,0.000022238684,0.00005040414],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010284564,0.00017705011,0.00022385461,0.000053065363,0.000057589503,0.00007727038,0.000102895276,0.000070393806,0.00006209573],"category_scores_gemma":[0.0000042381407,0.00014936502,0.000059673537,0.00010623445,0.000031996133,0.00010853822,0.000010525752,0.00008895612,0.000038735747],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010165476,0.00015374241,0.000307584,0.0026007353,0.00033717256,0.000003535935,0.004014218,0.008337423,0.23753761,0.73897856,0.0060738386,0.0015539218],"study_design_scores_gemma":[0.0020921421,0.00048776352,0.0002879549,0.00043833477,0.0002535007,0.00001660748,0.0011018735,0.089840226,0.4918954,0.40778068,0.0043836115,0.0014219118],"about_ca_topic_score_codex":8.552911e-7,"about_ca_topic_score_gemma":0.0000033201377,"teacher_disagreement_score":0.7276275,"about_ca_system_score_codex":0.000025652105,"about_ca_system_score_gemma":0.000007783687,"threshold_uncertainty_score":0.6090929},"labels":[],"label_agreement":null},{"id":"W2957361546","doi":"10.1145/3337801.3337818","title":"Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Application-specific integrated circuit; Embedded system; Standard cell; Computer science; Floorplan; Physical design; FPGA prototype; System on a chip; Computer hardware; Computer architecture; Circuit design; Integrated circuit; Operating system","score_opus":0.018915354305505973,"score_gpt":0.22631722286808173,"score_spread":0.20740186856257575,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2957361546","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.006562412,0.000027631526,0.9764531,0.000057147125,0.00006832018,0.00069306657,0.000019605144,0.0010031271,0.015115551],"genre_scores_gemma":[0.876848,0.0000022589188,0.12243247,0.000085143154,0.00003641721,0.000114786555,0.0000028909444,0.000033976747,0.00044409165],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99947834,0.00001460195,0.00010694523,0.00012454724,0.0000869849,0.00018856519],"domain_scores_gemma":[0.99923974,0.0004722883,0.000010898041,0.00018904488,0.000044531298,0.000043481596],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00011359872,0.00011533017,0.0001640673,0.00004625735,0.00004518105,0.00004639561,0.000054977234,0.000053610234,0.00033640114],"category_scores_gemma":[0.000024602938,0.000104608356,0.00006570424,0.00004827775,0.000012034612,0.00008207711,0.000004411974,0.000059145914,0.00009677663],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000053263346,0.00014757113,0.00005478005,0.00030986566,0.000053848547,0.0000047049625,0.00023275508,0.33959264,0.46768284,0.0117173735,0.17809896,0.002051411],"study_design_scores_gemma":[0.0002452426,0.00011347632,0.0000013729637,0.000009071795,0.000010926698,6.6090917e-7,0.000013219815,0.30112228,0.691065,0.005256459,0.0020298667,0.00013237778],"about_ca_topic_score_codex":0.0000020794591,"about_ca_topic_score_gemma":8.636562e-7,"teacher_disagreement_score":0.8702856,"about_ca_system_score_codex":0.000038512295,"about_ca_system_score_gemma":0.00003989299,"threshold_uncertainty_score":0.4265805},"labels":[],"label_agreement":null},{"id":"W2981891337","doi":"10.1109/dsd.2019.00031","title":"Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Computer science; Correctness; Traverse; Parallel computing; Node (physics); Electronic circuit; Process (computing); Digital electronics; Sequential logic; Field-programmable gate array; Graph; Speedup; Computer engineering; Logic gate; Algorithm; Computer hardware; Theoretical computer science; Programming language","score_opus":0.019647996097110428,"score_gpt":0.22780727086889085,"score_spread":0.20815927477178042,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2981891337","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.12505874,0.000039338203,0.80382353,0.000005791463,0.000053991513,0.0004533368,0.0000014237205,0.000858567,0.06970528],"genre_scores_gemma":[0.9977124,0.0000013797714,0.001826112,0.000020593236,0.000028527207,0.000018291346,0.00001813637,0.00002087747,0.0003537337],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994574,0.0000063525035,0.00010469841,0.000119361386,0.00018528051,0.00012686002],"domain_scores_gemma":[0.99971944,0.000030215697,0.000017855291,0.0001516864,0.00005471503,0.000026102723],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000107740256,0.00009410463,0.00008353901,0.000051203606,0.00001551578,0.00007037602,0.00005816074,0.000055551624,0.00027181243],"category_scores_gemma":[0.000010161526,0.000075201824,0.000020888943,0.00008230567,0.0000059987883,0.00040615402,0.000007925888,0.000060063747,0.0001601459],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007747038,0.000015496513,0.0030406844,0.000051591393,0.000023213826,0.0000011317733,0.00010854781,0.8511763,0.0098775625,0.0012974055,0.00013177027,0.13426852],"study_design_scores_gemma":[0.00025908434,0.00007820742,0.0009785417,0.00001062616,0.000009994637,0.0000018936224,0.00002724556,0.99553084,0.0011535877,0.001650328,0.0001434087,0.00015625033],"about_ca_topic_score_codex":0.0000049567934,"about_ca_topic_score_gemma":0.0000016419023,"teacher_disagreement_score":0.8726536,"about_ca_system_score_codex":0.000060807648,"about_ca_system_score_gemma":0.000011512634,"threshold_uncertainty_score":0.30666414},"labels":[],"label_agreement":null},{"id":"W2983726556","doi":"10.1109/fpl.2019.00060","title":"A Deep Learning Framework to Predict Routability for FPGA Circuit Placement","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Convolutional neural network; Deep learning; Placement; Computer architecture; Computer engineering; Artificial intelligence; Gate array; Parallel computing; Artificial neural network; State (computer science); Algorithm; Embedded system; Circuit design; Physical design","score_opus":0.011468532993046529,"score_gpt":0.22942320961472107,"score_spread":0.21795467662167453,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2983726556","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04769552,0.000047759357,0.93694913,0.000025473635,0.0001701642,0.0009084699,0.0000026100972,0.0013056177,0.01289526],"genre_scores_gemma":[0.9758742,0.0000059664717,0.02304031,0.00009666617,0.00006870307,0.00021077694,0.000005309426,0.000034465585,0.0006636143],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99924344,0.000012666632,0.00016961739,0.00019312925,0.00011442547,0.00026673952],"domain_scores_gemma":[0.9994984,0.00013480194,0.000011735106,0.0002408496,0.000028854985,0.000085341584],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023401216,0.00012511882,0.0001598998,0.00005273069,0.000032156873,0.00003275957,0.00012709823,0.00011316532,0.000573043],"category_scores_gemma":[0.00007613989,0.000119630335,0.000062803345,0.00010048936,0.0000054351567,0.00006758656,0.000026133439,0.00017254302,0.00015609164],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00016503842,0.00024607728,0.08905943,0.0017109559,0.00039313125,0.0000043554724,0.0076654437,0.5002209,0.042496733,0.026761955,0.013924357,0.3173516],"study_design_scores_gemma":[0.0015407014,0.0024516557,0.011564369,0.00039549253,0.00008748843,0.000008455173,0.0013710012,0.70164484,0.09925679,0.025783466,0.15378602,0.0021097073],"about_ca_topic_score_codex":0.000004985881,"about_ca_topic_score_gemma":0.000003059541,"teacher_disagreement_score":0.92817867,"about_ca_system_score_codex":0.00009085904,"about_ca_system_score_gemma":0.000006139801,"threshold_uncertainty_score":0.6274419},"labels":[],"label_agreement":null},{"id":"W2991030845","doi":"10.1145/3339985.3358497","title":"Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Netlist; Verilog; Computer science; Field-programmable gate array; Hardware description language; Computer architecture; Routing (electronic design automation); Computer hardware; Embedded system","score_opus":0.009178310594513977,"score_gpt":0.19826280809694197,"score_spread":0.18908449750242798,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2991030845","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.95514524,0.00031287584,0.02504005,0.00007424768,0.00023230466,0.0003669981,0.0000055629935,0.000613488,0.018209262],"genre_scores_gemma":[0.9954244,0.00012396224,0.0023415466,0.00008203024,0.000071761395,0.00002481041,0.000020183406,0.000025330166,0.0018860047],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99926805,0.000015560727,0.00020876496,0.00019230896,0.00009101472,0.0002243059],"domain_scores_gemma":[0.9997264,0.000014019003,0.00001399625,0.000178234,0.00001563152,0.00005172059],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017013683,0.00013844013,0.00017778607,0.000118419564,0.00003491797,0.000035833145,0.00007804186,0.00010404575,0.00080648507],"category_scores_gemma":[0.0000058858905,0.00012719177,0.000023892593,0.00014084992,0.0000143386,0.00014562055,0.000022620241,0.0001236485,0.00006816182],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007365671,0.0006871029,0.18702634,0.00084242196,0.00038235987,0.00021651496,0.0038885353,0.03736153,0.3836987,0.053132314,0.2833125,0.049378045],"study_design_scores_gemma":[0.0014438002,0.0005882455,0.0064118756,0.00005068496,0.000030038485,0.000029149873,0.000018984483,0.5148798,0.41828355,0.0043912022,0.05277006,0.0011025976],"about_ca_topic_score_codex":0.000028409224,"about_ca_topic_score_gemma":0.00008670367,"teacher_disagreement_score":0.4775183,"about_ca_system_score_codex":0.000031733445,"about_ca_system_score_gemma":0.0000134329175,"threshold_uncertainty_score":0.8830446},"labels":[],"label_agreement":null},{"id":"W2991158361","doi":"10.1109/sielmen.2019.8905907","title":"CSAP and TFSG – Circuit Symbolic Analysis Programs","year":2019,"lang":"en","type":"article","venue":"2019 International Conference on Electromechanical and Energy Systems (SIELMEN)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Northern Alberta Institute of Technology","funders":"","keywords":"Computer science; Symbolic data analysis; Symbolic execution; Programming language; Theoretical computer science; Software","score_opus":0.014086375612271862,"score_gpt":0.21009545366806476,"score_spread":0.1960090780557929,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2991158361","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.63222855,0.0027476042,0.14341459,0.00064382405,0.0026986564,0.00093357364,0.00010057463,0.0024465502,0.21478608],"genre_scores_gemma":[0.9944597,0.0006838321,0.000052185726,0.000066415036,0.00009879968,0.00007250105,0.000070727554,0.000024649136,0.004471217],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99870414,0.000039751587,0.00029363926,0.00036457874,0.00028802108,0.00030986153],"domain_scores_gemma":[0.99948406,0.000036627072,0.000056831785,0.00020691058,0.0000854398,0.00013012945],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015522346,0.00023377548,0.00037689134,0.00026766388,0.000036361074,0.00017753229,0.00022395213,0.00017523835,0.00014363624],"category_scores_gemma":[0.000005466262,0.00020765026,0.00008090823,0.00022696737,0.000022497194,0.00014865976,0.00004034126,0.00018626284,0.000034746336],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022191825,0.000059434282,0.00047487929,0.00004907688,0.00089159096,0.00000669143,0.000053551565,0.00014774529,0.04092712,0.9303094,0.00028541696,0.02677291],"study_design_scores_gemma":[0.0012915296,0.0017877517,0.0012055999,0.00039664196,0.00037155132,0.00013151075,0.00020062485,0.92914206,0.008437394,0.024899527,0.030418208,0.0017175988],"about_ca_topic_score_codex":0.0002112512,"about_ca_topic_score_gemma":0.00002733851,"teacher_disagreement_score":0.9289943,"about_ca_system_score_codex":0.00006423895,"about_ca_system_score_gemma":0.000016658745,"threshold_uncertainty_score":0.84677315},"labels":[],"label_agreement":null},{"id":"W2997995007","doi":"10.48550/arxiv.1912.09232","title":"Improving Clique Decompositions of Semidefinite Relaxations for Optimal\\n Power Flow Problems","year":2019,"lang":"","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Semidefinite programming; Clique; Mathematics; Chordal graph; Mathematical optimization; Decomposition; Power flow; Clique problem; Extension (predicate logic); Flow (mathematics); Power (physics); Computer science; Combinatorics; Electric power system; Graph","score_opus":0.04127062701432777,"score_gpt":0.1787413784370388,"score_spread":0.13747075142271103,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2997995007","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06481231,0.00020161289,0.9259323,0.000027276652,0.00064705394,0.002615553,0.0006998963,0.0005413144,0.0045227204],"genre_scores_gemma":[0.949558,0.0008704941,0.047810785,0.000022801085,0.000066835135,0.000029879782,0.00024054798,0.00015738323,0.0012432531],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99690545,0.00012480299,0.0008738196,0.0012461569,0.00011486596,0.0007348995],"domain_scores_gemma":[0.99638885,0.0005238636,0.00073911546,0.0014727124,0.0006323218,0.00024311685],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00046605212,0.0007594721,0.00096021715,0.00076539244,0.0002799934,0.00008603005,0.00096855784,0.0010756091,0.00017562605],"category_scores_gemma":[0.0001001886,0.0010162693,0.0008794332,0.00071826525,0.00017609532,0.00051997125,0.0005540622,0.0010688755,0.000075366625],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007369065,0.00019086045,0.00053576904,0.0013629014,0.00042692162,0.000015520745,0.0004736917,0.9602665,0.008938651,0.026950859,0.00037240004,0.00039224196],"study_design_scores_gemma":[0.0010259672,0.00042256224,0.00015930041,0.0009962695,0.0006414061,0.0000095748555,0.00019068945,0.97831076,0.007444627,0.008712365,0.00092915504,0.0011573308],"about_ca_topic_score_codex":0.00014841568,"about_ca_topic_score_gemma":0.000025608335,"teacher_disagreement_score":0.8847457,"about_ca_system_score_codex":0.0005330772,"about_ca_system_score_gemma":0.00032144933,"threshold_uncertainty_score":0.9992288},"labels":[],"label_agreement":null},{"id":"W3003197669","doi":"10.1109/icfpt47387.2019.00025","title":"Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Systolic array; Field-programmable gate array; Computer science; Parallel computing; Partition (number theory); Latency (audio); Throughput; Algorithm; Computer hardware; Embedded system; Very-large-scale integration; Mathematics","score_opus":0.009325196011428774,"score_gpt":0.20386849833754533,"score_spread":0.19454330232611655,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3003197669","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10130367,0.0002743168,0.8622015,0.00005846481,0.00016838014,0.00097596314,0.0000069646485,0.0015995782,0.033411127],"genre_scores_gemma":[0.9570535,0.000034149325,0.041261632,0.00004654979,0.00004364565,0.00016157271,0.000006816153,0.000025033796,0.0013671451],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996035,0.0000046689574,0.00010266325,0.00009873485,0.00004093891,0.000149505],"domain_scores_gemma":[0.9997972,0.00003443845,0.000010304772,0.00010548656,0.000016760125,0.00003577879],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000082697814,0.00008378079,0.0001307238,0.000040390452,0.000026523125,0.000031049112,0.000040227205,0.000052359144,0.00012427448],"category_scores_gemma":[0.000005940843,0.0000724791,0.000030071864,0.00004020512,0.000007611662,0.00009411958,0.000007737587,0.000044320524,0.000035617846],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00021989457,0.00008889587,0.013027107,0.005861775,0.00065178296,0.000012225678,0.0025107737,0.03694016,0.53984934,0.18554842,0.12549676,0.08979288],"study_design_scores_gemma":[0.0024756552,0.0002759277,0.00081215985,0.00022233147,0.00006287844,0.000030551713,0.00025324748,0.6547359,0.31995177,0.0044642696,0.015803913,0.0009113768],"about_ca_topic_score_codex":0.0000037519294,"about_ca_topic_score_gemma":0.0000010306183,"teacher_disagreement_score":0.8557498,"about_ca_system_score_codex":0.000013548662,"about_ca_system_score_gemma":0.0000034504299,"threshold_uncertainty_score":0.29556122},"labels":[],"label_agreement":null},{"id":"W3006437160","doi":"10.48550/arxiv.2002.06998","title":"RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays using Evolutionary Algorithms","year":2020,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"University of Waterloo; Natural Sciences and Engineering Research Council of Canada; Mitacs; Sun Yat-sen University; CMC Microsystems","keywords":"Field-programmable gate array; Computer science; Parallel computing; Systolic array; Placement; Algorithm; Minimum bounding box; Block (permutation group theory); Routing (electronic design automation); Simulated annealing; Floorplan; Computer hardware; Embedded system; Very-large-scale integration; Physical design; Circuit design; Mathematics; Artificial intelligence","score_opus":0.07501290098818877,"score_gpt":0.18550282673030283,"score_spread":0.11048992574211405,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3006437160","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08443872,0.0004139052,0.91074365,0.00001740118,0.0005190161,0.00072525395,0.00019757157,0.0011188061,0.0018256898],"genre_scores_gemma":[0.98094493,0.0005066315,0.01801654,0.000021294396,0.00014139386,0.0000033363654,0.0000658045,0.00008172083,0.00021833886],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982867,0.00009296845,0.00040279597,0.0006853147,0.000143246,0.00038895212],"domain_scores_gemma":[0.99873,0.000048910973,0.00021215845,0.00067825103,0.00013130502,0.00019935162],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00013525988,0.00049223524,0.00072916725,0.00036498444,0.00008831899,0.000026719546,0.0006342476,0.0004271478,0.000075335076],"category_scores_gemma":[0.000015175258,0.0006219066,0.00036105455,0.0004318564,0.00011056298,0.00013616776,0.00048502907,0.00066649425,0.000026029384],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005991684,0.00005174072,0.00013100004,0.0005153763,0.00036887033,0.000129144,0.00020358573,0.9932402,0.0036152129,0.0005522225,0.0010383956,0.00009434581],"study_design_scores_gemma":[0.00071140664,0.00005602615,0.000091250695,0.0003455855,0.00030606487,0.000008650806,0.00018227015,0.9922459,0.00439624,0.00084584433,0.00018814854,0.0006226105],"about_ca_topic_score_codex":0.000091620335,"about_ca_topic_score_gemma":0.0000017054001,"teacher_disagreement_score":0.8965062,"about_ca_system_score_codex":0.00050565053,"about_ca_system_score_gemma":0.00012512789,"threshold_uncertainty_score":0.99962324},"labels":[],"label_agreement":null},{"id":"W3009193187","doi":"10.1109/tcad.2020.2977605","title":"An Automated Topology Synthesis Framework for Analog Integrated Circuits","year":2020,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Research and Development Corporation of Newfoundland and Labrador; Canada Foundation for Innovation","keywords":"Network topology; Topology (electrical circuits); Computer science; Algorithm; Tree (set theory); Mathematics; Engineering; Electrical engineering","score_opus":0.04061444235109959,"score_gpt":0.2629130206829645,"score_spread":0.22229857833186492,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3009193187","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0064004743,0.00026982705,0.9875935,0.00004483007,0.00095798617,0.0012196432,0.00034963706,0.003109629,0.000054497898],"genre_scores_gemma":[0.9863406,0.00013111561,0.01281748,0.00012251892,0.00012354423,0.0003251296,0.000022612872,0.00010955657,0.0000074595873],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99743426,0.00035300537,0.0009182601,0.0005869779,0.00022735691,0.00048012426],"domain_scores_gemma":[0.9978903,0.0008658428,0.0001610906,0.00041998227,0.00033580433,0.00032696174],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000389371,0.0005369157,0.0009812936,0.00041540703,0.00017092688,0.00015297388,0.00041962316,0.00059077906,0.000033670585],"category_scores_gemma":[0.000035656198,0.00048711232,0.00017715555,0.0007400445,0.000119181925,0.00023690047,0.0000012831224,0.0005318424,0.000008862367],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014206143,0.00042367209,0.000020119363,0.0010531727,0.0011883678,0.000049315084,0.001854221,0.53094,0.19076972,0.0028198725,0.0032115865,0.2675279],"study_design_scores_gemma":[0.000381394,0.0013678393,0.000012431512,0.00048219814,0.00012401873,0.00004876713,0.00031002384,0.91030526,0.08608676,0.00022515342,0.00016958646,0.00048655868],"about_ca_topic_score_codex":0.0001145162,"about_ca_topic_score_gemma":0.0000040761265,"teacher_disagreement_score":0.9799401,"about_ca_system_score_codex":0.00011501634,"about_ca_system_score_gemma":0.000096432785,"threshold_uncertainty_score":0.99975806},"labels":[],"label_agreement":null},{"id":"W3009491659","doi":"10.1137/1.9781611976229.10","title":"Generalized Gains for Hybrid Vertex Separator Algorithms","year":2020,"lang":"en","type":"book-chapter","venue":"Society for Industrial and Applied Mathematics eBooks","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Vertex (graph theory); Computer science; Separator (oil production); Reuse; Algorithm; Graph; Theoretical computer science; Engineering","score_opus":0.07819017564935744,"score_gpt":0.2533407399016599,"score_spread":0.17515056425230247,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3009491659","genre_codex":"other","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00020381468,0.00065752544,0.4098862,0.000118220785,0.0010977086,0.013290638,0.004640181,0.0030180984,0.5670876],"genre_scores_gemma":[0.0026604137,0.00059664843,0.7091999,0.0012465832,0.00892004,0.0059323506,0.0017590391,0.0019777624,0.26770723],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"not_applicable","domain_scores_codex":[0.99859494,0.0000014112942,0.0005311659,0.00036022256,0.0001827826,0.00032945984],"domain_scores_gemma":[0.9992428,0.00016198898,0.00015110831,0.0002344446,0.000045640543,0.0001640408],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00018979538,0.0005488416,0.00083750393,0.000032717868,0.00015755967,0.00008540015,0.00019746357,0.0007667718,0.000013877983],"category_scores_gemma":[0.0000093101735,0.00053337216,0.0006824787,0.00001118836,0.000091722475,0.000018715857,0.000056443238,0.0004334839,0.000006136658],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000038810784,0.000015418278,1.0420629e-8,0.0013757243,0.0009960436,0.0000012705312,0.0006953551,0.000014120911,0.00399524,0.66958594,0.2849154,0.038366657],"study_design_scores_gemma":[0.002824551,0.00016862617,3.1464646e-9,0.0002167835,0.0006545755,0.000006387495,0.0000847062,0.015735742,0.023113111,0.44432837,0.5117443,0.0011228318],"about_ca_topic_score_codex":3.4938188e-7,"about_ca_topic_score_gemma":1.9782553e-7,"teacher_disagreement_score":0.29938036,"about_ca_system_score_codex":0.00006986488,"about_ca_system_score_gemma":0.000060708742,"threshold_uncertainty_score":0.9997118},"labels":[],"label_agreement":null},{"id":"W3010080362","doi":"","title":"Minimum length disjoint paths and Capacitated (rooted) Steiner Tree","year":2018,"lang":"en","type":"preprint","venue":"HAL (Le Centre pour la Communication Scientifique Directe)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Group for Research in Decision Analysis; HEC Montréal","funders":"","keywords":"Steiner tree problem; Disjoint sets; Combinatorics; Computer science; Tree (set theory); Mathematics","score_opus":0.012510111540356373,"score_gpt":0.20264043120676392,"score_spread":0.19013031966640756,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3010080362","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.41410026,0.0046227523,0.42863223,0.0020534291,0.0006907616,0.0012590595,0.0002807536,0.0035728428,0.14478791],"genre_scores_gemma":[0.95096445,0.0016265543,0.04301034,0.000041873718,0.000057625068,0.00012121629,0.00038467947,0.00012701462,0.0036662263],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9968194,0.0013116617,0.0005285613,0.0006366196,0.00029775634,0.00040601555],"domain_scores_gemma":[0.9965392,0.00047288282,0.0001870771,0.0017020635,0.00088922033,0.00020960123],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0021970663,0.00046000458,0.00045643075,0.00023579404,0.00017689208,0.0003060422,0.0007270024,0.0004515089,0.000101994934],"category_scores_gemma":[0.0004257497,0.00047771895,0.00015164088,0.00023683184,0.00029321472,0.00012640041,0.0006623861,0.0007015399,0.000037236663],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000056349156,0.0013344077,0.003511528,0.0029991237,0.0011239523,0.00007903277,0.05029992,0.00033083896,0.12544484,0.03806124,0.09011169,0.68664706],"study_design_scores_gemma":[0.0019775436,0.000005452592,0.009384502,0.008174546,0.00032985906,0.00007096804,0.00040771862,0.37102455,0.5173366,0.021719461,0.06586139,0.0037074015],"about_ca_topic_score_codex":0.0003239646,"about_ca_topic_score_gemma":0.00068930926,"teacher_disagreement_score":0.68293965,"about_ca_system_score_codex":0.00011008326,"about_ca_system_score_gemma":0.000070834576,"threshold_uncertainty_score":0.9997674},"labels":[],"label_agreement":null},{"id":"W3011140373","doi":"10.1109/icm48031.2019.9021943","title":"Enhancing the Performance of FPGA Congestion Management via Supervised Learning","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Lookup table; Key (lock); Computer architecture; Embedded system; Placement; Computer engineering; Physical design; Circuit design; Operating system","score_opus":0.004616403771878333,"score_gpt":0.17836288244459259,"score_spread":0.17374647867271426,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3011140373","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9323347,0.00009207069,0.038055345,0.000011038087,0.00008416706,0.00021093144,1.1659806e-7,0.00036526128,0.028846357],"genre_scores_gemma":[0.99763453,0.00012336983,0.0014563829,0.000014402193,0.00001240837,0.000011953208,0.0000014710438,0.000012449703,0.0007330563],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996192,0.000011148117,0.0001211713,0.00006182404,0.00008350226,0.00010314062],"domain_scores_gemma":[0.99980927,0.000021334323,0.000013306192,0.00012977514,0.000014777255,0.00001156398],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016376938,0.00006436493,0.00007679088,0.00003762529,0.000023402205,0.000010149847,0.000090422414,0.000029099316,0.00018113319],"category_scores_gemma":[0.0000012982994,0.000046148274,0.00002287588,0.000075695694,0.000008598418,0.000078197874,0.000019302362,0.00009123366,0.00007314179],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015866479,0.000021939784,0.009757165,0.0008520962,0.00014151716,0.000001796603,0.00084402255,0.061465822,0.6948844,0.0019250917,0.0003992917,0.22969094],"study_design_scores_gemma":[0.00016588796,0.00009619634,0.0057697673,0.00008290271,0.00001853766,0.0000023518353,0.00019001482,0.21656169,0.7753682,0.000032414606,0.0015712443,0.00014076635],"about_ca_topic_score_codex":0.0000049961754,"about_ca_topic_score_gemma":0.0000010103366,"teacher_disagreement_score":0.22955018,"about_ca_system_score_codex":0.000013536312,"about_ca_system_score_gemma":0.0000013982194,"threshold_uncertainty_score":0.19832814},"labels":[],"label_agreement":null},{"id":"W3011353849","doi":"10.1137/20m1330762","title":"A Spectral Approach to Network Design","year":2022,"lang":"en","type":"article","venue":"SIAM Journal on Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Mathematics; Theoretical computer science","score_opus":0.024522106779222865,"score_gpt":0.22343676694356532,"score_spread":0.19891466016434245,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3011353849","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007109428,0.00021624741,0.97885144,0.00006195024,0.0006274653,0.00017167578,8.7142547e-7,0.0004725992,0.012488324],"genre_scores_gemma":[0.8401999,0.0000058234905,0.15839607,0.00031387707,0.0009968806,0.000006348522,9.684514e-7,0.000040714243,0.000039422524],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988491,0.00012125009,0.0002382473,0.00012689397,0.00025670545,0.00040783067],"domain_scores_gemma":[0.99962384,0.000069846166,0.000042151052,0.00011876004,0.000012245837,0.00013315273],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0008757351,0.00013690225,0.00016745696,0.0001275302,0.00043552465,0.00008365234,0.00027882415,0.000025710286,0.000044618457],"category_scores_gemma":[0.000009204793,0.00013951471,0.00007933591,0.00034259396,0.0000054864963,0.000039429287,0.000068910595,0.00074695324,0.000014372202],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010522457,0.000023616823,0.000025999048,0.000004640476,0.000020910647,0.000034208286,0.00024919503,0.9579285,0.00037698826,0.00089519826,0.02861437,0.011815901],"study_design_scores_gemma":[0.00031030586,0.00061759097,0.00024443105,0.000055658777,0.000012868632,0.0011412663,0.00012773591,0.97139263,0.0008955316,0.0031668216,0.021585768,0.00044936626],"about_ca_topic_score_codex":5.425691e-7,"about_ca_topic_score_gemma":3.0221074e-8,"teacher_disagreement_score":0.8330905,"about_ca_system_score_codex":0.00019063291,"about_ca_system_score_gemma":0.000018647213,"threshold_uncertainty_score":0.5689245},"labels":[],"label_agreement":null},{"id":"W3011875640","doi":"10.1145/3337792","title":"Algorithm 1003","year":2020,"lang":"en","type":"article","venue":"ACM Transactions on Mathematical Software","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Division of Civil, Mechanical and Manufacturing Innovation; Office of Naval Research; National Science Foundation","keywords":"Computer science; Graph partition; Theoretical computer science; Parallel computing; Mathematical optimization; Algorithm; Graph; Mathematics","score_opus":0.023439222531116806,"score_gpt":0.22771702112117392,"score_spread":0.20427779859005712,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3011875640","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00019907817,0.000036848105,0.9962664,0.00039362907,0.000044476034,0.00015886972,0.000028808907,0.0025711658,0.0003006993],"genre_scores_gemma":[0.030285472,0.000033181434,0.9689809,0.00043542482,0.000050332663,0.00007119907,0.0000038668622,0.000057908903,0.00008168253],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.99931526,0.000011421492,0.00018375985,0.00014382538,0.00015708758,0.00018864652],"domain_scores_gemma":[0.99939543,0.00013587889,0.000009365257,0.00028088185,0.000018084393,0.00016037244],"candidate_categories":["insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.00004061313,0.00015091182,0.00017966736,0.00003612231,0.000061182414,0.000026852906,0.0002307665,0.00010080703,0.0010461009],"category_scores_gemma":[0.0000615838,0.0001385688,0.00009831117,0.00018044945,0.00002677984,0.0000847848,0.0000031887355,0.00025100744,0.0008113807],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000026637613,0.000053657604,0.000001458717,0.0001456835,0.000040185325,0.000009971264,0.00028005423,0.0007956332,0.00034062966,0.00006861285,0.00039903095,0.9978624],"study_design_scores_gemma":[0.0010550313,0.00069699134,0.000059711303,0.0002911343,0.00022291283,0.000072354575,0.00027090948,0.06565605,0.09553608,0.81100744,0.023512317,0.0016190346],"about_ca_topic_score_codex":4.072395e-7,"about_ca_topic_score_gemma":1.2339886e-7,"teacher_disagreement_score":0.99624336,"about_ca_system_score_codex":0.000025026817,"about_ca_system_score_gemma":0.000005994097,"threshold_uncertainty_score":0.9999666},"labels":[],"label_agreement":null},{"id":"W3013345876","doi":"10.1109/asp-dac47756.2020.9045588","title":"Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"University of Illinois at Urbana-Champaign","keywords":"Graph partition; Computer science; Parallel computing; Speedup; Graph bandwidth; Graph; Strength of a graph; Computation; Theoretical computer science; Algorithm; Voltage graph; Line graph","score_opus":0.01931914162918906,"score_gpt":0.24962297289973262,"score_spread":0.23030383127054355,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3013345876","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.59070647,0.00003929804,0.4053155,0.000042970863,0.00009072082,0.0001075992,0.000006592806,0.0014201289,0.0022706909],"genre_scores_gemma":[0.9778094,0.000018919807,0.02155403,0.00041846035,0.0001086251,0.000019044734,0.0000279326,0.000033216467,0.00001032206],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992666,0.000013309219,0.00020265373,0.00016588699,0.00012391701,0.00022761324],"domain_scores_gemma":[0.99970996,0.000017128807,0.000025269099,0.00012801179,0.000034108685,0.00008551256],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006242533,0.00014651025,0.0001464853,0.0000771561,0.000105854,0.00008638678,0.00010456466,0.00007974103,0.0002525997],"category_scores_gemma":[0.0000042969573,0.00014959433,0.00004662669,0.00030779655,0.00002649743,0.0003306073,0.000013283257,0.00013082061,0.00003696639],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025508974,0.0000214116,0.010969299,0.00021076291,0.000030609463,0.000007598334,0.00009142059,0.27888244,0.7060675,0.0004921382,0.0012910087,0.0019103213],"study_design_scores_gemma":[0.00022383149,0.00004934085,0.003724902,0.00004219025,0.000007956101,0.0000017341796,0.0000045629113,0.55938774,0.43613353,0.00008934989,0.00015045273,0.00018439417],"about_ca_topic_score_codex":0.000010139826,"about_ca_topic_score_gemma":7.8350473e-7,"teacher_disagreement_score":0.38710296,"about_ca_system_score_codex":0.000037663383,"about_ca_system_score_gemma":0.000009786367,"threshold_uncertainty_score":0.61002797},"labels":[],"label_agreement":null},{"id":"W3013952364","doi":"10.1109/asp-dac47756.2020.9045175","title":"AIR: A Fast but Lazy Timing-Driven FPGA Router","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":43,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Router; Computer science; Routing (electronic design automation); Field-programmable gate array; Path (computing); Key (lock); One-armed router; Process (computing); Metrics; Static routing; Static timing analysis; Network routing; Embedded system; Distributed computing; Computer network; Parallel computing; Routing protocol; Operating system","score_opus":0.021713728271957163,"score_gpt":0.20615991764317024,"score_spread":0.18444618937121307,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3013952364","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016368976,0.00010239811,0.8318868,0.0012593117,0.00013160796,0.00025603798,0.000015018437,0.005879858,0.14409998],"genre_scores_gemma":[0.98616403,0.000016699682,0.011882019,0.0009954738,0.00015533628,0.000016366468,0.000004814925,0.000033658853,0.0007315742],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995087,0.0000062373,0.0001163724,0.000120568424,0.00008005203,0.00016806998],"domain_scores_gemma":[0.9997548,0.00001054282,0.000007693946,0.000119349184,0.000012852592,0.000094774274],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000021049851,0.00011234757,0.00012060231,0.000027641074,0.000019296389,0.000021083144,0.00013165035,0.00006550119,0.00034438435],"category_scores_gemma":[0.000005412931,0.00010201093,0.000054306853,0.000085221865,0.000010823287,0.000095505646,0.00003184664,0.000113718284,0.0003922202],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025025429,0.00007036895,0.0020704868,0.0003966977,0.00026502,0.00019887755,0.0042146137,0.013581645,0.22503938,0.0037198162,0.6178039,0.13261417],"study_design_scores_gemma":[0.0006378241,0.00025621735,0.0009150129,0.000056327044,0.000046979156,0.000022393391,0.00024887995,0.37768695,0.44080934,0.00036617412,0.17791705,0.0010368763],"about_ca_topic_score_codex":0.0000089840005,"about_ca_topic_score_gemma":0.0000028119841,"teacher_disagreement_score":0.9697951,"about_ca_system_score_codex":0.000017210901,"about_ca_system_score_gemma":0.0000046113964,"threshold_uncertainty_score":0.50413275},"labels":[],"label_agreement":null},{"id":"W3023260388","doi":"10.1109/tvlsi.2004.831478","title":"Power estimation techniques for FPGAs","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Delay calculation; Field-programmable gate array; Computer science; Routing (electronic design automation); Capacitance; Noise (video); Electronic engineering; Logic gate; Logic synthesis; Interconnection; Dynamic demand; Gate array; Minimum bounding box; CMOS; Programmable logic array; Power (physics); Algorithm; Embedded system; Engineering; Artificial intelligence; Telecommunications","score_opus":0.009093474468148337,"score_gpt":0.23481335160568928,"score_spread":0.22571987713754094,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3023260388","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0045166,0.00009725937,0.98788846,0.000066115106,0.0014269619,0.0013556753,0.00021830821,0.0024999906,0.0019306622],"genre_scores_gemma":[0.98333925,0.000047559748,0.014716208,0.000053703265,0.00009563995,0.0012123405,0.00004135522,0.000084903375,0.0004090271],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9984892,0.000042802887,0.0005364986,0.0003076032,0.00027219026,0.00035172587],"domain_scores_gemma":[0.9992194,0.000066413806,0.0000706765,0.00036804687,0.00017544931,0.00009999764],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00034165048,0.0003219962,0.000317281,0.00035818468,0.00022555023,0.00014328783,0.00017052828,0.00031676344,0.000043488682],"category_scores_gemma":[0.000008051995,0.00030938556,0.00021307133,0.00029322394,0.000032642267,0.00053470006,6.518271e-7,0.0003022091,0.000073101255],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00023380725,0.0012414008,0.0000088124325,0.00093646185,0.00039288943,0.000015722018,0.0044013797,0.68509215,0.20466758,0.007857641,0.012723217,0.082428955],"study_design_scores_gemma":[0.0007192402,0.00036727186,0.00000845612,0.0005815331,0.00005514439,0.00004122669,0.00045996622,0.16612172,0.82431394,0.000889099,0.0058773607,0.0005650276],"about_ca_topic_score_codex":0.0000399718,"about_ca_topic_score_gemma":0.00007076315,"teacher_disagreement_score":0.97882265,"about_ca_system_score_codex":0.0003940963,"about_ca_system_score_gemma":0.000037312046,"threshold_uncertainty_score":0.9999358},"labels":[],"label_agreement":null},{"id":"W3033033241","doi":"10.1145/3388617","title":"VTR 8","year":2020,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":293,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Toronto","funders":"New Brunswick Innovation Foundation; Semiconductor Research Corporation","keywords":"Computer science; Field-programmable gate array; Verilog; Routing (electronic design automation); Embedded system; Computer architecture; Process (computing); Footprint; Implementation; Design flow; Memory footprint; CAD; Electronic design automation; Computer hardware; Operating system; Software engineering","score_opus":0.02123967216127599,"score_gpt":0.20983675866673177,"score_spread":0.18859708650545579,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3033033241","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06466382,0.006737002,0.8749754,0.0061577763,0.0009886749,0.0010923425,0.000071210554,0.013566067,0.031747732],"genre_scores_gemma":[0.9985615,0.00046004867,0.00048546077,0.000097988726,0.000022885744,0.00010800784,0.0000013869751,0.00002516547,0.00023752855],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993493,0.000014631478,0.00019629393,0.00019085313,0.000055603894,0.00019334919],"domain_scores_gemma":[0.99955994,0.000038886086,0.00001823093,0.0002898506,0.000019711615,0.00007336726],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00006412454,0.00014408628,0.00021734687,0.00023429998,0.00010234907,0.000027430217,0.00020647381,0.00028808037,0.00007996885],"category_scores_gemma":[0.00001273083,0.00014086087,0.000034000124,0.000386439,0.000057937636,0.00007970641,0.000001300852,0.00034695724,0.0000967754],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006323887,0.00010668757,0.0004956776,0.000983078,0.0005884796,0.00009189886,0.00078078447,0.011345228,0.121642455,0.016439227,0.010759367,0.8367039],"study_design_scores_gemma":[0.0018584819,0.0015616528,0.00013407171,0.00043314308,0.00017541436,0.0006082713,0.002956776,0.091376975,0.6512625,0.011770596,0.23582907,0.0020329999],"about_ca_topic_score_codex":0.0000059984004,"about_ca_topic_score_gemma":0.000001482918,"teacher_disagreement_score":0.93389773,"about_ca_system_score_codex":0.000016641405,"about_ca_system_score_gemma":0.000006488265,"threshold_uncertainty_score":0.57441396},"labels":[],"label_agreement":null},{"id":"W3041521987","doi":"10.1145/3373269","title":"Machine Learning for Congestion Management and Routability Prediction within FPGA Placement","year":2020,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":21,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Router; Convolutional neural network; Computer engineering; Deep learning; Gate array; Parallel computing; Embedded system; Algorithm; Artificial intelligence; Computer network","score_opus":0.020984262073361945,"score_gpt":0.22161650259867668,"score_spread":0.20063224052531475,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3041521987","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0031368337,0.0005283433,0.9936058,0.00007729208,0.00010954563,0.0015362998,0.000018996821,0.00091270235,0.000074210446],"genre_scores_gemma":[0.99207157,0.0002357222,0.007046757,0.000011364091,0.000021648695,0.00050001935,0.000023375034,0.000028999732,0.000060549282],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99889696,0.00010628295,0.000414233,0.00021329962,0.00017525877,0.00019398742],"domain_scores_gemma":[0.9994948,0.00013561932,0.00009130056,0.00017247305,0.000049113936,0.000056713812],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00046313653,0.00016005356,0.00020799355,0.00011703564,0.00009680413,0.000030172165,0.000099649646,0.000093005925,0.000013029565],"category_scores_gemma":[0.00002549172,0.00016761741,0.00004770682,0.0001704859,0.000018966588,0.00015129035,0.0000021270375,0.0001718895,0.0000033036386],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001077314,0.000038883056,0.000026533045,0.00064236985,0.00017284765,2.4640622e-7,0.00048586604,0.973732,0.005553925,0.00071824144,0.000095497315,0.018425852],"study_design_scores_gemma":[0.0006589204,0.0009034951,0.000089675144,0.00009068402,0.00008860053,0.0000051086354,0.00014329088,0.9763062,0.020694798,0.0003060465,0.00057333,0.00013984517],"about_ca_topic_score_codex":0.0000063551133,"about_ca_topic_score_gemma":0.0000013106734,"teacher_disagreement_score":0.98893476,"about_ca_system_score_codex":0.00018354462,"about_ca_system_score_gemma":0.000016383785,"threshold_uncertainty_score":0.68352395},"labels":[],"label_agreement":null},{"id":"W3043169486","doi":"10.1109/mlcad48534.2019.9142079","title":"Adaptive FPGA Placement Optimization via Reinforcement Learning","year":2019,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":22,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Engineering and Physical Sciences Research Council","keywords":"Heuristics; Reinforcement learning; Computer science; Field-programmable gate array; Process (computing); Computer engineering; Computer architecture; Artificial intelligence; Embedded system; Programming language","score_opus":0.007523945024058885,"score_gpt":0.19182230452809534,"score_spread":0.18429835950403645,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3043169486","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0006297117,0.000038829097,0.8784247,0.0000059483978,0.000080806465,0.00023524895,1.3151282e-7,0.000769041,0.11981555],"genre_scores_gemma":[0.9818306,0.00004566118,0.015113516,0.000035595418,0.000022622819,0.000025050524,0.00001245817,0.000022102065,0.0028924],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995169,0.000008758806,0.00012780166,0.00009253129,0.000109396846,0.00014462805],"domain_scores_gemma":[0.99981344,0.000012096972,0.000016271417,0.00010490507,0.000021296348,0.000031976055],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00007653405,0.00009532585,0.00008639755,0.000056987545,0.000023455035,0.00001660756,0.000057542235,0.000048408005,0.0015289597],"category_scores_gemma":[0.0000020327493,0.000090381036,0.000025580828,0.00007069071,0.0000044503195,0.00011504338,0.000018797904,0.0000946955,0.00022480403],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000043455566,0.000003021796,0.000045521305,0.0000080969585,0.00001950914,4.2359778e-7,0.000065960696,0.9947415,0.0013873088,0.00025322728,0.000717571,0.00275349],"study_design_scores_gemma":[0.00015001884,0.00013035578,0.0000105359695,0.000012552339,0.0000059531867,9.94237e-7,0.00007303125,0.97435117,0.023463009,0.000019272817,0.001650882,0.00013220281],"about_ca_topic_score_codex":0.000007216791,"about_ca_topic_score_gemma":4.5937134e-7,"teacher_disagreement_score":0.9812009,"about_ca_system_score_codex":0.00006295802,"about_ca_system_score_gemma":0.0000040882433,"threshold_uncertainty_score":0.9993838},"labels":[],"label_agreement":null},{"id":"W3046189630","doi":"","title":"Enhancing the Performance of FPGA Congestion Management via Supervised Learning","year":2019,"lang":"en","type":"article","venue":"IEEE Conference Proceedings","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Lookup table; Computer science; Key (lock); Computer engineering; Embedded system; Computer architecture; Artificial intelligence; Machine learning; Operating system","score_opus":0.009717276824317627,"score_gpt":0.19596620584663324,"score_spread":0.1862489290223156,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3046189630","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9794753,0.00004742589,0.008408962,0.000022450971,0.00015944222,0.00033344646,3.9388485e-7,0.0003735236,0.011179012],"genre_scores_gemma":[0.9986002,0.0002257643,0.0006584557,0.000016608179,0.000032237454,0.00004610389,0.0000011935618,0.000022174081,0.00039730614],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9992419,0.000004611552,0.00021930865,0.0001491603,0.00017358402,0.00021146853],"domain_scores_gemma":[0.9996799,0.000019279772,0.000051571784,0.00009165311,0.00012750343,0.00003004732],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00025293318,0.00013995745,0.00016228705,0.00007745094,0.000050898037,0.000052807398,0.0002323956,0.00006796599,0.00007747501],"category_scores_gemma":[0.000005414985,0.000113114285,0.000034639834,0.00015758662,0.000033632918,0.00024511613,0.000025993177,0.0002263456,0.000059500107],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016055486,0.000012164471,0.008265847,0.0010347324,0.00004541023,5.629676e-7,0.0019470688,0.0007193728,0.9513571,0.0010460411,0.00016250511,0.035393097],"study_design_scores_gemma":[0.00022847154,0.00015601212,0.0033584943,0.0003771411,0.000026063415,0.0000060367593,0.0005978178,0.13270019,0.861411,0.00014567691,0.0007542672,0.00023882932],"about_ca_topic_score_codex":0.000004205564,"about_ca_topic_score_gemma":4.632365e-7,"teacher_disagreement_score":0.13198082,"about_ca_system_score_codex":0.000030276504,"about_ca_system_score_gemma":0.000007527221,"threshold_uncertainty_score":0.46126667},"labels":[],"label_agreement":null},{"id":"W3080620120","doi":"10.1109/cjece.2019.2962147","title":"Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm","year":2020,"lang":"en","type":"article","venue":"Canadian Journal of Electrical and Computer Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Floorplan; Control reconfiguration; Field-programmable gate array; Simulated annealing; Gate array; Computer science; Benchmark (surveying); Genetic algorithm; Embedded system; Parallel computing; Algorithm; Computer architecture; Computer engineering","score_opus":0.0035351054875988573,"score_gpt":0.1607900000625606,"score_spread":0.15725489457496175,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3080620120","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20907429,0.00050028117,0.79015636,0.00010024315,0.000032028638,0.000089305955,8.904067e-7,0.000037916037,0.000008695701],"genre_scores_gemma":[0.9704361,0.000028128417,0.02937545,0.00009557552,0.000048545848,0.000002730692,7.5208544e-7,0.000012131146,5.9618225e-7],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995082,0.0000071268387,0.00016322159,0.0000845061,0.00005362843,0.00018332148],"domain_scores_gemma":[0.9995924,0.00007834835,0.000020561942,0.000028744782,0.000013304438,0.00026660925],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0000435317,0.00010486283,0.00015155243,0.0001380451,0.000023075132,0.00006250951,0.000036500598,0.00004214005,0.0000032902715],"category_scores_gemma":[0.000012584046,0.00009516205,0.000010963817,0.000115744326,0.00000634374,0.000043817443,0.0000022281351,0.00019166993,1.4694984e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008133225,0.0000029708183,0.00017876648,0.00005581207,0.000017526778,0.00038905744,0.00017889423,0.6452933,0.00015534929,0.0000052143923,0.000024543797,0.35369045],"study_design_scores_gemma":[0.0003092498,0.0007403114,0.00041597168,0.00010267776,0.000009355091,0.00012122548,0.000003538644,0.99768746,0.0003494699,0.000006699022,0.00013987755,0.00011416077],"about_ca_topic_score_codex":0.000028952989,"about_ca_topic_score_gemma":0.000033932178,"teacher_disagreement_score":0.7613618,"about_ca_system_score_codex":0.000038232345,"about_ca_system_score_gemma":0.00003289756,"threshold_uncertainty_score":0.3880596},"labels":[],"label_agreement":null},{"id":"W3087976346","doi":"10.1109/tcad.2020.3025068","title":"An LDE-Aware <i>g</i> <sub> <i>m</i> </sub>/<i>I</i> <sub> <i>D</i> </sub>-Based Hybrid Sizing Method for Analog Integrated Circuits","year":2020,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Research and Development Corporation of Newfoundland and Labrador; Canada Foundation for Innovation","keywords":"Sizing; Sensitivity (control systems); Computer science; Algorithm; Computation; Electronic circuit; Topology (electrical circuits); Mathematics; Electronic engineering; Engineering; Electrical engineering; Combinatorics","score_opus":0.0300492102004446,"score_gpt":0.23417788038704782,"score_spread":0.20412867018660322,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3087976346","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.02463025,0.0005837673,0.96756727,0.000054060216,0.0012924072,0.0025450492,0.0009836449,0.0023082,0.00003532976],"genre_scores_gemma":[0.99085325,0.00032279667,0.0067092925,0.0008229272,0.0002780733,0.0005534137,0.00015827562,0.000299699,0.0000022609374],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9946567,0.0007698164,0.0017282182,0.0012619437,0.0006030596,0.0009802657],"domain_scores_gemma":[0.99639565,0.00097654015,0.0003943685,0.00077291485,0.0007486176,0.00071192294],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0010790607,0.0011783938,0.0017055642,0.00066970906,0.00038440028,0.00039043606,0.00071085495,0.0005689189,0.0000035250948],"category_scores_gemma":[0.000023802912,0.0011466264,0.0004852855,0.0012277012,0.0001469561,0.0006982582,0.0000041264884,0.0010646121,0.000012160049],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006784625,0.00017194227,0.0000026258178,0.0005406584,0.00026312424,0.000033277967,0.00018716509,0.22368625,0.61882347,0.000046479807,0.0014991929,0.15467799],"study_design_scores_gemma":[0.00093888637,0.0010819284,0.000001514748,0.00051321276,0.00015932372,0.000056404326,0.00009183791,0.47928494,0.5170012,0.0000471872,0.00018998681,0.00063357886],"about_ca_topic_score_codex":0.00008449957,"about_ca_topic_score_gemma":0.000012471649,"teacher_disagreement_score":0.966223,"about_ca_system_score_codex":0.0002750417,"about_ca_system_score_gemma":0.00032838638,"threshold_uncertainty_score":0.99909836},"labels":[],"label_agreement":null},{"id":"W3089997764","doi":"10.1109/iscas45731.2020.9181149","title":"Deep Reinforcement Learning for Analog Circuit Sizing","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":47,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Computer science; Reinforcement learning; Sizing; Task (project management); Filter (signal processing); Reliability (semiconductor); Artificial intelligence; Computer engineering; Deep learning; Polynomial; Machine learning; Engineering; Mathematics","score_opus":0.02906838200091587,"score_gpt":0.2217929692400638,"score_spread":0.19272458723914793,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3089997764","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00027428646,0.00011473752,0.9542472,0.00006373885,0.000028904286,0.00016035598,1.1028647e-7,0.0011931292,0.04391759],"genre_scores_gemma":[0.99532986,0.000032124946,0.003952845,0.0002970927,0.00009010367,0.000035334124,0.000007743025,0.000023320701,0.00023156313],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995662,0.0000037278314,0.00012318233,0.0000884909,0.00005852215,0.00015987981],"domain_scores_gemma":[0.9998272,0.000027355489,0.00001057617,0.00005621555,0.000015456222,0.000063201],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000051662308,0.00007894485,0.00009488063,0.00002597788,0.000039233208,0.000022906397,0.000074001735,0.00004060634,0.00013697866],"category_scores_gemma":[0.000028791628,0.00007852165,0.000046951547,0.00007689621,0.000004793802,0.00006697528,0.000012014163,0.0000860085,0.00002623253],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008943939,0.00000574548,0.00044655267,0.000321976,0.00009832291,0.000006651336,0.0015560746,0.79117596,0.08280159,0.017784191,0.008726686,0.09706732],"study_design_scores_gemma":[0.00013694813,0.00009876161,0.000022686916,0.0000073584347,0.000009135445,7.7018177e-7,0.00008702465,0.9389051,0.031098723,0.00026093805,0.029222533,0.00015000105],"about_ca_topic_score_codex":0.0000022712861,"about_ca_topic_score_gemma":8.211288e-7,"teacher_disagreement_score":0.9950556,"about_ca_system_score_codex":0.000021185571,"about_ca_system_score_gemma":0.0000032405896,"threshold_uncertainty_score":0.32020196},"labels":[],"label_agreement":null},{"id":"W3091003631","doi":"10.1109/iscas45731.2020.9181150","title":"Fast Analog Layout Retargeting with Device Abstraction","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Retargeting; Computer science; Process (computing); Abstraction; Graph; Constraint (computer-aided design); IC layout editor; Integrated circuit layout; Computer hardware; Scheme (mathematics); Page layout; Artificial intelligence; Integrated circuit; Circuit extraction; Theoretical computer science; Engineering; Electrical engineering","score_opus":0.015087580075322451,"score_gpt":0.18936132194819025,"score_spread":0.1742737418728678,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3091003631","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14297658,0.00014925636,0.5882245,0.0005041525,0.00006120649,0.00020550277,0.000003645723,0.004501297,0.26337388],"genre_scores_gemma":[0.98806506,0.00000920363,0.01155454,0.00021306376,0.00007490529,0.000004577231,0.0000042718516,0.000018348674,0.000056001754],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996544,0.0000042827887,0.00008468102,0.000086011365,0.00006597619,0.000104649705],"domain_scores_gemma":[0.9998506,0.000009978302,0.000011025166,0.000058898717,0.000015790396,0.000053731645],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00003492026,0.00007359357,0.00007362152,0.000018619907,0.00002142002,0.000020726018,0.00004971128,0.00003748057,0.00012556868],"category_scores_gemma":[0.000005146317,0.000060064423,0.000015829866,0.00010499848,0.0000058226246,0.00011129528,0.00000538354,0.00010860882,0.00006886155],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000102482016,0.00007076233,0.03430705,0.0009327688,0.00040222408,0.0002183895,0.0043807817,0.101783335,0.59655064,0.002635068,0.08111997,0.17749654],"study_design_scores_gemma":[0.000676355,0.00046095962,0.01625646,0.00010941301,0.00008575142,0.00004851304,0.0012705426,0.4034894,0.52210677,0.00018588516,0.054020073,0.0012898946],"about_ca_topic_score_codex":0.000016385588,"about_ca_topic_score_gemma":0.000012453391,"teacher_disagreement_score":0.8450885,"about_ca_system_score_codex":0.0000121115945,"about_ca_system_score_gemma":0.0000035318214,"threshold_uncertainty_score":0.24493562},"labels":[],"label_agreement":null},{"id":"W3091973109","doi":"10.1109/iemtronics51293.2020.9216458","title":"The Use of Agile Methodology for Porting Analog and Mixed-Signal Circuits Between Different Technology Nodes","year":2020,"lang":"en","type":"article","venue":"2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université du Québec en Outaouais","funders":"","keywords":"Porting; Agile software development; Computer science; Electronic design automation; Time to market; Mixed-signal integrated circuit; Integrated circuit; Integrated circuit design; Process (computing); Automation; Design flow; Electronic circuit; Embedded system; Computer engineering; Software engineering; Engineering; Electrical engineering","score_opus":0.1116785171635695,"score_gpt":0.2934335369577546,"score_spread":0.1817550197941851,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3091973109","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.37223727,0.0063053425,0.61694837,0.0029009802,0.00032359647,0.0006706368,0.00021747188,0.0003162447,0.00008012998],"genre_scores_gemma":[0.98760426,0.007119349,0.0047781444,0.000088766894,0.00016028452,0.00009991703,0.000056829234,0.00005544846,0.000036975005],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99787176,0.00007588952,0.00067200616,0.00047189932,0.0002494631,0.00065901113],"domain_scores_gemma":[0.9984173,0.00069147063,0.0002536384,0.00022787068,0.00026252645,0.00014715323],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004327133,0.0003513149,0.0005564295,0.00014131743,0.00016948809,0.0001362957,0.0005135993,0.0002927428,0.000015331017],"category_scores_gemma":[0.00019398535,0.00030389224,0.00012910519,0.00017139413,0.0001677496,0.00014662863,0.00013638404,0.0006154007,0.0000013565133],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008624512,0.00004633158,0.0021195475,0.00018475547,0.0011641913,0.0000050229037,0.0003562878,0.0016016434,0.18885706,0.4457791,0.0013436956,0.35845613],"study_design_scores_gemma":[0.0017404528,0.0014351065,0.0003758292,0.00013555634,0.000365591,0.00004161706,0.00034455047,0.48502475,0.3238432,0.09162522,0.09394691,0.001121206],"about_ca_topic_score_codex":0.000009868463,"about_ca_topic_score_gemma":0.00006957193,"teacher_disagreement_score":0.61536705,"about_ca_system_score_codex":0.0001373487,"about_ca_system_score_gemma":0.00016168508,"threshold_uncertainty_score":0.9999413},"labels":[],"label_agreement":null},{"id":"W3091995083","doi":"10.1109/dsd51259.2020.00018","title":"Hard and Soft Logic Trade-offs for Multipliers in VTR","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Verilog; Field-programmable gate array; Granularity; Computer science; Routing (electronic design automation); Programmable Array Logic; Electronic circuit; Computer architecture; Reduction (mathematics); Embedded system; Logic gate; Computer hardware; Logic synthesis; Logic family; Engineering; Electrical engineering","score_opus":0.03231239154869903,"score_gpt":0.22470645788283514,"score_spread":0.1923940663341361,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3091995083","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.034892514,0.0005345832,0.9542365,0.0019569593,0.000070225185,0.00068616687,0.00001349815,0.0017177446,0.00589178],"genre_scores_gemma":[0.9736124,0.000043749573,0.025697803,0.00051824376,0.000031473017,0.00003456576,0.0000024429085,0.000015615944,0.000043649376],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996745,0.0000030393885,0.00008599913,0.00009475588,0.000027394413,0.00011434137],"domain_scores_gemma":[0.9998711,0.000030003306,0.0000042640713,0.000042602358,0.0000023105708,0.00004972575],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000037014055,0.00006867265,0.00009611181,0.000025009367,0.000010277353,0.0000119639835,0.000045093966,0.000053133856,0.000016367445],"category_scores_gemma":[0.00001654417,0.000062321385,0.000020725589,0.00005089051,0.000010140256,0.000046721987,0.000007101309,0.000059245805,0.0000034035618],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008584142,0.000066515364,0.008930912,0.001087483,0.00009023969,0.000034991263,0.005082294,0.0038690174,0.48044536,0.011016178,0.12506053,0.36423066],"study_design_scores_gemma":[0.0018628275,0.00034342502,0.008173079,0.000037536225,0.000020196028,0.0000059819413,0.00045963132,0.8151043,0.123731695,0.0052137487,0.04426581,0.00078178226],"about_ca_topic_score_codex":0.0000029940022,"about_ca_topic_score_gemma":0.000002971025,"teacher_disagreement_score":0.9387199,"about_ca_system_score_codex":0.000009497426,"about_ca_system_score_gemma":0.000002334058,"threshold_uncertainty_score":0.25413924},"labels":[],"label_agreement":null},{"id":"W3093817935","doi":"10.1109/fpl50879.2020.00043","title":"Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Computer science; Field-programmable gate array; Process (computing); Work (physics); Estimation; Multiplexer; Embedded system; Engineering; Telecommunications; Multiplexing","score_opus":0.05364929105235554,"score_gpt":0.22556006750814947,"score_spread":0.17191077645579395,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3093817935","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18701212,0.000095695206,0.80969244,0.00042322258,0.000010587401,0.00020326392,0.0000046802734,0.0003920227,0.002165952],"genre_scores_gemma":[0.99027306,0.000012093981,0.009639369,0.0000345351,0.0000039190386,0.000021415522,0.0000022296601,0.0000117072095,0.0000016442801],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995033,0.000009738869,0.00023177516,0.00007309023,0.00008875871,0.0000933283],"domain_scores_gemma":[0.9996947,0.000059324386,0.00003969308,0.00015903193,0.00003202318,0.000015209098],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000092076174,0.000076606804,0.00015112612,0.000110840825,0.000008206183,0.0000038947705,0.00016614025,0.0000781566,0.00002068695],"category_scores_gemma":[0.00009770099,0.00005862049,0.000029636909,0.00028842431,0.000027766808,0.00008686716,0.000020083298,0.00010936456,0.000001920181],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000049244068,0.000013053964,0.00031326056,0.00010317366,0.0000075703397,9.562784e-7,0.0002621941,0.9594251,0.027266327,0.0020925181,0.00010932356,0.010401594],"study_design_scores_gemma":[0.00010273563,0.00002052216,0.00007252813,0.000033597506,0.0000036911672,3.3013362e-7,0.000025895066,0.71505386,0.28222358,0.0024062889,0.000013309426,0.000043657004],"about_ca_topic_score_codex":0.000017363078,"about_ca_topic_score_gemma":0.000007935785,"teacher_disagreement_score":0.803261,"about_ca_system_score_codex":0.00001519925,"about_ca_system_score_gemma":0.000015438256,"threshold_uncertainty_score":0.23904742},"labels":[],"label_agreement":null},{"id":"W3094241140","doi":"10.1109/epeps48591.2020.9231491","title":"An Efficient and Parallel Electromagnetic Solver for Complex Interconnects in Layered Media","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Solver; Computer science; Scalability; Computation; Computational science; Parallel computing; Workload; Transmission-line matrix method; Computational electromagnetics; Electronic engineering; Algorithm; Electromagnetic field; Engineering; Physics","score_opus":0.02807108252980117,"score_gpt":0.23248033030003318,"score_spread":0.204409247770232,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3094241140","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5584733,0.00022796947,0.43755686,0.00031005914,0.000035102203,0.00051919464,0.0000073405236,0.00082912156,0.002041087],"genre_scores_gemma":[0.97283363,0.000016788254,0.026802652,0.0002510396,0.00002914767,0.00003602072,0.00000923638,0.000017578723,0.0000039304027],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995417,0.000008982698,0.00011430909,0.00012567671,0.000041169907,0.00016813392],"domain_scores_gemma":[0.99978954,0.00004657894,0.0000060238085,0.00006858105,0.000008966419,0.00008030254],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00004706695,0.00008837143,0.00012487404,0.00003965432,0.000010832028,0.000019663396,0.00007541348,0.000042552892,0.000060826067],"category_scores_gemma":[0.000014961486,0.00008268475,0.00001735267,0.000065613414,0.000011883744,0.000034453624,0.000010165003,0.000058676538,0.000003439263],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000074376905,0.00007673313,0.00026970115,0.00020445585,0.000023569944,0.000012835698,0.003883098,0.009486178,0.9557003,0.004894396,0.011489182,0.013885171],"study_design_scores_gemma":[0.0005395949,0.00035347138,0.0015921576,0.000007991877,0.00000425794,0.0000019668992,0.00009283253,0.98202634,0.014191203,0.00045001454,0.0005765361,0.00016365865],"about_ca_topic_score_codex":0.000006715727,"about_ca_topic_score_gemma":0.00003762332,"teacher_disagreement_score":0.97254014,"about_ca_system_score_codex":0.000011965729,"about_ca_system_score_gemma":0.0000034908103,"threshold_uncertainty_score":0.33717862},"labels":[],"label_agreement":null},{"id":"W3097021646","doi":"10.1145/3416946","title":"Efficient Parasitic-aware <i> g <sup>m</sup> </i> / <i> I <sup>D</sup> - </i> based Hybrid Sizing Methodology for Analog and RF Integrated Circuits","year":2020,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Floorplan; Parasitic extraction; Sizing; Computer science; Integrated circuit; Piecewise; Electronic engineering; Analogue electronics; Nonlinear programming; Electronic circuit; Mathematical optimization; Algorithm; Nonlinear system; Electrical engineering; Mathematics; Embedded system; Engineering; Physics","score_opus":0.043965003161724595,"score_gpt":0.2605274146914718,"score_spread":0.2165624115297472,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3097021646","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016422737,0.00083910173,0.9790002,0.00020515571,0.000086876986,0.0018026148,0.00013418087,0.0014595784,0.00004951534],"genre_scores_gemma":[0.98380375,0.00006395198,0.015118935,0.00016864274,0.00006258679,0.00059512554,0.00006465203,0.00010225507,0.00002012601],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99705803,0.0005317142,0.0008741976,0.0005326719,0.00031738429,0.0006859885],"domain_scores_gemma":[0.9973181,0.0016152874,0.00017335915,0.0004977755,0.00020956446,0.0001858953],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001070119,0.00045563094,0.00075407856,0.0003897326,0.00019669776,0.00007742274,0.00038231586,0.00026727575,0.000033167093],"category_scores_gemma":[0.00018307353,0.00047331006,0.00020323595,0.00064693356,0.00007371627,0.0001455093,0.000003572149,0.00043097528,0.000013053278],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000619374,0.000069797745,0.000004426479,0.00048075817,0.00020149461,0.00000318196,0.0005636985,0.9607652,0.02504845,0.00018134143,0.0005702391,0.012049514],"study_design_scores_gemma":[0.0009390696,0.0008273212,0.0000037404513,0.00017879167,0.00017181566,0.000042427757,0.00032132308,0.8931054,0.1033599,0.00016126751,0.00051789253,0.0003710543],"about_ca_topic_score_codex":0.00003177932,"about_ca_topic_score_gemma":0.0000014368622,"teacher_disagreement_score":0.967381,"about_ca_system_score_codex":0.00031783184,"about_ca_system_score_gemma":0.00019834959,"threshold_uncertainty_score":0.99977183},"labels":[],"label_agreement":null},{"id":"W3098798579","doi":"10.1109/southeastcon44009.2020.9249694","title":"An Investigation of the Accuracy of the VPR and COFFE Area Models in Predicting the Layout Area of FPGA Lookup Tables","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Field-programmable gate array; Routing (electronic design automation); Lookup table; Computer science; Benchmark (surveying); Block (permutation group theory); Embedded system; Mathematics; Geometry","score_opus":0.03398046109264609,"score_gpt":0.21176110220676217,"score_spread":0.17778064111411607,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3098798579","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.98895204,0.00018200072,0.008973395,0.00027350988,0.000020073065,0.00032339478,0.000022499966,0.00007066722,0.0011824378],"genre_scores_gemma":[0.9994365,0.00004277595,0.000393452,0.000086405096,0.00001127363,0.000009727075,0.0000017434941,0.000011263756,0.000006867398],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993839,0.0000536842,0.0002625936,0.00008218326,0.00013339752,0.00008421254],"domain_scores_gemma":[0.99947846,0.00013288668,0.00008889859,0.00023892376,0.000036243193,0.00002455992],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019548817,0.000084744664,0.00014380367,0.00002262363,0.000026709771,0.000009328359,0.00025644933,0.000052239386,0.0000074454424],"category_scores_gemma":[0.000082897226,0.00004262959,0.000032110165,0.00021617257,0.000099156015,0.00017079238,0.000059502414,0.00012241869,4.7491554e-8],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022149079,0.000036083104,0.2097159,0.0006691886,0.00007057176,4.1241663e-7,0.024875207,0.21938053,0.5357605,0.0036256604,0.0013311714,0.004512592],"study_design_scores_gemma":[0.00011289699,0.000029016337,0.011157793,0.00013906557,0.000016261773,7.628446e-7,0.00072772976,0.5971265,0.38791916,0.0027097382,0.0000064416763,0.000054651686],"about_ca_topic_score_codex":0.00015947346,"about_ca_topic_score_gemma":0.00005809118,"teacher_disagreement_score":0.37774596,"about_ca_system_score_codex":0.000008265394,"about_ca_system_score_gemma":0.000020856598,"threshold_uncertainty_score":0.17383842},"labels":[],"label_agreement":null},{"id":"W3101215367","doi":"","title":"A NEW AND FLEXIBLE METHOD FOR CONSTRUCTING DESIGNS FOR COMPUTER EXPERIMENTS","year":2016,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":92,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Queen's University; Simon Fraser University","funders":"","keywords":"Latin hypercube sampling; Hypercube; Orthogonal array; Construct (python library); Computer experiment; Mathematics; Feature (linguistics); Power of two; Computer science; Theoretical computer science; Algorithm; Mathematical optimization; Discrete mathematics; Statistics; Monte Carlo method; Programming language","score_opus":0.05746213606325693,"score_gpt":0.3228053845310089,"score_spread":0.2653432484677519,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3101215367","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00033457673,0.0000783029,0.9976088,0.000035775913,0.00009877111,0.00041031383,0.0000053141766,0.00055118167,0.00087696844],"genre_scores_gemma":[0.012978336,0.0000069892617,0.9861914,0.00004944106,0.000115152005,0.00008659947,7.047916e-7,0.000023314447,0.00054805493],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995868,0.0000056627346,0.00010683857,0.000114848815,0.000028369383,0.00015746523],"domain_scores_gemma":[0.99963033,0.00021014088,0.000011385179,0.00007410304,0.000017552207,0.00005646905],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010384654,0.00008691129,0.00011598264,0.000037996793,0.000027549664,0.000022354232,0.000047480073,0.00004849731,0.00002955053],"category_scores_gemma":[0.000007941351,0.000060557966,0.000032828553,0.00002208278,0.0000081510325,0.000084345505,0.000012121999,0.000014284761,0.0000012932795],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000009744667,0.00000273422,0.000045229666,0.000036107613,0.00003257701,1.4905645e-7,0.00009025548,0.0000075134744,0.32547107,0.007911488,0.02069391,0.6456992],"study_design_scores_gemma":[0.0007489706,0.000102994825,0.0000050865992,0.000033568493,0.000009257873,0.000007862183,0.000024724868,0.012511928,0.970414,0.00583829,0.010150957,0.00015240168],"about_ca_topic_score_codex":0.000003907021,"about_ca_topic_score_gemma":5.1237083e-7,"teacher_disagreement_score":0.64554685,"about_ca_system_score_codex":0.00001740252,"about_ca_system_score_gemma":0.00000765981,"threshold_uncertainty_score":0.24694823},"labels":[],"label_agreement":null},{"id":"W3107133478","doi":"10.1145/3380446.3430618","title":"An Adaptive Analytic FPGA Placement Framework based on Deep-Learning","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Encoder; Quality (philosophy); Placer mining; Deep learning; Parallel computing; Computer engineering; Artificial intelligence; Embedded system; Operating system","score_opus":0.016703661068808717,"score_gpt":0.23276744533996496,"score_spread":0.21606378427115625,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3107133478","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0018552092,0.000041092422,0.9757195,0.000113274444,0.000031206066,0.00014050395,0.0000011668025,0.0017551228,0.02034294],"genre_scores_gemma":[0.96824026,0.000007299369,0.030728264,0.0008621216,0.00008177381,0.000017698418,0.000006057965,0.00003369446,0.000022848451],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99934304,0.00003122612,0.0001228912,0.00017386799,0.00014684151,0.00018215962],"domain_scores_gemma":[0.99960846,0.00007013154,0.0000139720505,0.000149422,0.000015975496,0.0001420535],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007454774,0.00013856591,0.00013478176,0.00005567282,0.000039621325,0.000033152744,0.00012121918,0.000088785535,0.0007954095],"category_scores_gemma":[0.000028465913,0.0001298799,0.000044108318,0.00018260373,0.000009694967,0.000065744905,0.000008614154,0.0003096663,0.00010346824],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006318407,0.00004110695,0.0003489239,0.00002784638,0.000053642223,0.000021436817,0.00043254127,0.9682662,0.0018435061,0.0019577208,0.0018032849,0.025140606],"study_design_scores_gemma":[0.00010233127,0.0006923434,0.00012493058,0.000024257604,0.000015639458,1.9369874e-7,0.00013429185,0.9847881,0.0128506,0.00015195386,0.00093522266,0.00018013587],"about_ca_topic_score_codex":0.0000029327543,"about_ca_topic_score_gemma":0.000001076253,"teacher_disagreement_score":0.966385,"about_ca_system_score_codex":0.00004064346,"about_ca_system_score_gemma":0.0000064751125,"threshold_uncertainty_score":0.87091756},"labels":[],"label_agreement":null},{"id":"W3107926654","doi":"10.1109/ccece47787.2020.9255695","title":"Placement with Sequence-Pair-Driven TCG for Advanced Analog Constraints","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Transitive closure; Computer science; Analogue electronics; Analog computer; Graph; Sequence (biology); Transitive reduction; Electronic design automation; Computer engineering; Electronic circuit; Theoretical computer science; Engineering; Embedded system; Mathematics; Electrical engineering","score_opus":0.031242928009064422,"score_gpt":0.2395470291519036,"score_spread":0.20830410114283918,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3107926654","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008316847,0.00003178714,0.97273666,0.00032814546,0.00002933618,0.00054377806,0.000034674016,0.0012943813,0.01668438],"genre_scores_gemma":[0.90864164,0.000012394828,0.09076216,0.00034944745,0.00003191553,0.00009072487,0.000016294714,0.00002191699,0.000073490715],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999509,0.000004272335,0.00010964504,0.00013266316,0.00007287338,0.00017158216],"domain_scores_gemma":[0.9997674,0.00002279629,0.000012782269,0.00008463471,0.000025892816,0.00008647415],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000028010045,0.00011075505,0.00012700392,0.00002164759,0.000023557728,0.000013548781,0.00008426522,0.00003857374,0.00015515012],"category_scores_gemma":[0.0000067768206,0.00009024707,0.000029596613,0.00007848328,0.00003818038,0.00007302106,0.000008229931,0.000061468134,0.000013619403],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00028629266,0.00007430196,0.0022248963,0.000815568,0.0004970954,0.000091822745,0.0019333926,0.09246762,0.6144523,0.019653851,0.08916298,0.17833987],"study_design_scores_gemma":[0.0033600058,0.0023003616,0.000103310274,0.00014933532,0.000079543155,0.000026059093,0.0010885553,0.31185436,0.6200642,0.00065969507,0.059051886,0.0012627043],"about_ca_topic_score_codex":0.0000010611232,"about_ca_topic_score_gemma":0.0000030918109,"teacher_disagreement_score":0.9003248,"about_ca_system_score_codex":0.000029172881,"about_ca_system_score_gemma":0.000014458299,"threshold_uncertainty_score":0.36801687},"labels":[],"label_agreement":null},{"id":"W3114620271","doi":"","title":"ALGORITMO DIVISÃO UTILIZANDO A META-HEURÍSTICA SIMULATED ANNEALING APLICADO NA OTIMIZAÇÃO DE CIRCUITOS REVERSÍVEIS","year":2019,"lang":"pt","type":"article","venue":"Congresso Brasileiro de Automática - CBA","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Physics; Simulated annealing; Computer science; Algorithm","score_opus":0.03567885243618515,"score_gpt":0.27381505206462226,"score_spread":0.2381361996284371,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3114620271","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.48210573,0.025947683,0.44778442,0.0011045096,0.004987069,0.0090500945,0.0017543162,0.014207696,0.013058483],"genre_scores_gemma":[0.989679,0.0007239356,0.004884939,0.000852683,0.00030653426,0.00016390372,0.00010827819,0.00054514117,0.0027355792],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99207854,0.0006484224,0.0016836483,0.0017233634,0.000951249,0.0029147663],"domain_scores_gemma":[0.99417734,0.0014257947,0.00046030537,0.0023710178,0.0003816848,0.0011838739],"candidate_categories":["metaepi_narrow","research_integrity","insufficient_payload"],"consensus_categories":["metaepi_narrow","insufficient_payload"],"category_scores_codex":[0.0015191701,0.0016580505,0.002601723,0.00065532385,0.00040476915,0.00062663155,0.0016988593,0.0016037986,0.004009314],"category_scores_gemma":[0.0009667046,0.0017605977,0.0012513379,0.0012395821,0.00032598025,0.0006548334,0.00044435376,0.002025521,0.001048248],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0014400382,0.0041880067,0.13336833,0.016430821,0.05806344,0.0073228814,0.023227101,0.26972345,0.23236121,0.010630808,0.09042302,0.15282091],"study_design_scores_gemma":[0.0027705142,0.00043220064,0.010037082,0.0008491166,0.005064029,0.00022854476,0.00022206784,0.952921,0.019726504,0.0005296013,0.0047872267,0.0024321373],"about_ca_topic_score_codex":0.00024769307,"about_ca_topic_score_gemma":0.000007722122,"teacher_disagreement_score":0.68319756,"about_ca_system_score_codex":0.0007003415,"about_ca_system_score_gemma":0.00040224704,"threshold_uncertainty_score":0.9997296},"labels":[],"label_agreement":null},{"id":"W3116009344","doi":"10.1109/icecs49266.2020.9294968","title":"Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design","year":2020,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Grain Research and Development Corporation","keywords":"Computer science; Transitive closure; Redundancy (engineering); Network topology; Graph; Representation (politics); Analogue electronics; Computation; Flexibility (engineering); Automation; Electronic design automation; Theoretical computer science; Computer engineering; Distributed computing; Electronic circuit; Algorithm; Embedded system; Mathematics; Engineering","score_opus":0.04488228364013116,"score_gpt":0.2601018625108018,"score_spread":0.21521957887067064,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3116009344","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0019270697,0.000068285895,0.9939711,0.00031321464,0.000039199615,0.000785644,0.00001937146,0.0010529575,0.0018231313],"genre_scores_gemma":[0.88189363,0.000013694769,0.11726305,0.00046491445,0.000040008003,0.00021868527,0.000042827727,0.00003193464,0.00003126553],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993475,0.000025593494,0.00017577424,0.0001806112,0.00010119092,0.00016932169],"domain_scores_gemma":[0.99967146,0.000089093766,0.000016986533,0.000105942796,0.000038476748,0.00007802338],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009152574,0.00012759313,0.00014970622,0.00005528438,0.000034276178,0.000018608162,0.00007817999,0.00005513944,0.00006814691],"category_scores_gemma":[0.00001920002,0.00012495567,0.00008621171,0.00017840773,0.000013043744,0.00009595498,0.000002793906,0.00005919905,0.000007468544],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00047040154,0.000055261065,0.00027778337,0.00024175367,0.00013527578,0.0000105572235,0.001156081,0.58918726,0.36118153,0.0008037701,0.026901986,0.01957833],"study_design_scores_gemma":[0.0010382115,0.0003567652,0.00009974986,0.000014727884,0.00002974475,3.7124585e-7,0.0001170308,0.39014843,0.60631645,0.0003644453,0.0012855765,0.00022850776],"about_ca_topic_score_codex":0.0000024243132,"about_ca_topic_score_gemma":0.000001929909,"teacher_disagreement_score":0.87996656,"about_ca_system_score_codex":0.000021681899,"about_ca_system_score_gemma":0.000011404087,"threshold_uncertainty_score":0.50955445},"labels":[],"label_agreement":null},{"id":"W3141105696","doi":"10.1109/date.2009.5090829","title":"Finite Precision bit-width allocation using SAT-Modulo Theory","year":2009,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Modulo; Bit (key); Context (archaeology); Computer science; Finite field; Arithmetic; Division (mathematics); Algorithm; Mathematics; Theoretical computer science; Discrete mathematics","score_opus":0.01561764808198758,"score_gpt":0.2397121338565358,"score_spread":0.22409448577454824,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3141105696","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.033708904,0.00022412784,0.9457188,0.000028249058,0.00008826541,0.0001452954,0.0000012955384,0.0011445031,0.018940514],"genre_scores_gemma":[0.9659906,0.00005919821,0.03346742,0.0001420006,0.000067043635,0.000003079261,0.000008826719,0.000017075017,0.00024477002],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99946344,0.00002291123,0.00014987092,0.00011356617,0.00010059396,0.00014962436],"domain_scores_gemma":[0.9996642,0.000056007157,0.000014523119,0.00020110702,0.000025016212,0.00003916238],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021399667,0.000107665364,0.000095443094,0.00010160293,0.000037470254,0.00003125579,0.00009527318,0.000084254076,0.00010212966],"category_scores_gemma":[0.000026840948,0.000095157375,0.000037242477,0.00014168854,0.000008448529,0.00016923201,0.000008467067,0.00008257206,0.000045699213],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015972482,0.000046738063,0.00008949434,0.000022340311,0.000020120351,0.0000046400546,0.00031665986,0.029428406,0.27416298,0.0118041625,0.0028745283,0.681214],"study_design_scores_gemma":[0.00026742712,0.00015394621,0.0026042045,0.00010481584,0.000027735112,0.0000112452135,0.000041334457,0.6191116,0.26714334,0.106428675,0.0035845335,0.0005211766],"about_ca_topic_score_codex":0.0000037813543,"about_ca_topic_score_gemma":0.0000010411161,"teacher_disagreement_score":0.9322817,"about_ca_system_score_codex":0.000042993102,"about_ca_system_score_gemma":0.000005658794,"threshold_uncertainty_score":0.3880405},"labels":[],"label_agreement":null},{"id":"W3141147179","doi":"10.1109/iccad.2006.320013","title":"Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs","year":2006,"lang":"en","type":"article","venue":"Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Interconnection; Benchmark (surveying); Field-programmable gate array; Routing (electronic design automation); Computer science; Place and route; Electronic circuit; Electronic design automation; Logic synthesis; Design flow; Physical design; Embedded system; Electronic engineering; Logic gate; Circuit design; Engineering; Electrical engineering; Algorithm; Telecommunications","score_opus":0.0359316740128897,"score_gpt":0.26682030673019463,"score_spread":0.23088863271730492,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3141147179","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014655696,0.0000798744,0.88567054,0.00045873356,0.0009861595,0.004371795,0.0005016022,0.0024553696,0.09082025],"genre_scores_gemma":[0.95502824,0.000071005634,0.043896873,0.00008996291,0.00022429465,0.00039563957,0.00011093314,0.00014130166,0.000041749878],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99513197,0.00018811425,0.0018979039,0.0009455446,0.0010983861,0.0007380917],"domain_scores_gemma":[0.99546385,0.0016817222,0.00078605866,0.0012476259,0.00061954575,0.00020117337],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0010597853,0.00085674244,0.0013745319,0.0006506206,0.00012610848,0.00008711168,0.0020029016,0.0006391083,0.000081505066],"category_scores_gemma":[0.00030940984,0.0007614437,0.0004985287,0.00050171744,0.00033194994,0.0002750337,0.00020607692,0.0007096672,0.000009362278],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0012472072,0.0010986751,0.00015900383,0.000623566,0.00028413287,0.00003532753,0.00005327535,0.03668438,0.8981427,0.058004703,0.00081679405,0.0028502194],"study_design_scores_gemma":[0.008962897,0.012534451,0.018572127,0.013386396,0.00051610015,0.00023105474,0.00018348866,0.06592614,0.8702517,0.0044697607,0.0012558979,0.003709983],"about_ca_topic_score_codex":0.00005727621,"about_ca_topic_score_gemma":0.000055469915,"teacher_disagreement_score":0.9403725,"about_ca_system_score_codex":0.0005416462,"about_ca_system_score_gemma":0.0001405233,"threshold_uncertainty_score":0.99948364},"labels":[],"label_agreement":null},{"id":"W3143008962","doi":"10.1109/aspdac.2011.5722215","title":"Area-efficient FPGA logic elements: Architecture and synthesis","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Logic optimization; Logic synthesis; Lookup table; Logic block; Logic family; Programmable logic array; Functional decomposition; Field-programmable gate array; Logic gate; Trimming; Sequential logic; Programmable logic device; Parallel computing; Leverage (statistics); Computer architecture; Algorithm; Embedded system; Artificial intelligence","score_opus":0.02449781595460505,"score_gpt":0.1957363852504816,"score_spread":0.17123856929587655,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3143008962","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1258838,0.00053937826,0.643262,0.00003921462,0.00010661804,0.0003600772,0.000010905247,0.002364976,0.22743303],"genre_scores_gemma":[0.97866493,0.00004960404,0.021062704,0.00006301644,0.000013732907,0.000035115987,6.566851e-7,0.000016002205,0.000094212715],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99954957,0.000008591144,0.00011014051,0.000108901375,0.00006137122,0.00016142236],"domain_scores_gemma":[0.9997709,0.000023442457,0.000009347749,0.00013661988,0.000009090033,0.00005060506],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000074489035,0.0001064714,0.000097421915,0.00006700041,0.000024399345,0.000011451481,0.000078142264,0.000050762013,0.0005238339],"category_scores_gemma":[0.00001276763,0.00008145691,0.000024064328,0.00005769482,0.00002150859,0.000019537025,0.00002174032,0.00007038337,0.000018420991],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003601718,0.0004488225,0.0026810113,0.00036502432,0.00030664992,0.000094699746,0.0036067246,0.0014768034,0.06153867,0.012676348,0.017830739,0.8989385],"study_design_scores_gemma":[0.00039431345,0.0002194312,0.005741203,0.0001178292,0.00008703089,0.00006837959,0.00033139612,0.019729743,0.9506862,0.0121609,0.009398729,0.0010648217],"about_ca_topic_score_codex":0.000010249819,"about_ca_topic_score_gemma":0.000004287621,"teacher_disagreement_score":0.89787364,"about_ca_system_score_codex":0.000012726853,"about_ca_system_score_gemma":0.0000019562535,"threshold_uncertainty_score":0.5735614},"labels":[],"label_agreement":null},{"id":"W3143897082","doi":"10.1007/s10878-021-00757-7","title":"The Steiner cycle and path cover problem on interval graphs","year":2021,"lang":"en","type":"article","venue":"Journal of Combinatorial Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Surrey Memorial Hospital; Simon Fraser University; Fraser Health","funders":"Austrian Science Fund; TU Graz, Internationale Beziehungen und Mobilitätsprogramme","keywords":"Steiner tree problem; Combinatorics; Mathematics; Hamiltonian path; Path (computing); Cover (algebra); Longest path problem; Discrete mathematics; Set cover problem; Dominating set; Graph; Shortest path problem; Computer science; Set (abstract data type); Vertex (graph theory)","score_opus":0.004398170932766899,"score_gpt":0.19789507340397589,"score_spread":0.193496902471209,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3143897082","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11758691,0.0053205383,0.82980585,0.002071121,0.018810406,0.0008240671,0.000013200882,0.00052248203,0.025045412],"genre_scores_gemma":[0.98742807,0.0011988942,0.011005038,0.000049024526,0.00023388563,0.0000030940603,0.0000022503002,0.00002524962,0.000054485132],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993974,0.00004823038,0.00025068386,0.00004900559,0.00016817995,0.00008647823],"domain_scores_gemma":[0.99953556,0.00006758835,0.00008659248,0.00007837353,0.00017906495,0.000052821528],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00022899693,0.000076939825,0.000123632,0.000044772576,0.00006105569,0.0000944564,0.00007081233,0.00005775041,0.00001148277],"category_scores_gemma":[0.0000673608,0.000054891745,0.000050440118,0.00011796251,0.000016585409,0.00016132309,0.000014112936,0.00016277331,9.1638793e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017816559,0.00017532741,0.0002699506,0.000065869004,0.00020407618,0.00007238765,0.00041849937,0.88136566,0.0030215157,0.07648116,0.026558336,0.011189068],"study_design_scores_gemma":[0.008316739,0.002944125,0.00055630546,0.0009013647,0.00025719733,0.00040926697,0.00027639323,0.61259454,0.047484163,0.28176847,0.043474592,0.0010168387],"about_ca_topic_score_codex":3.815476e-7,"about_ca_topic_score_gemma":6.040919e-8,"teacher_disagreement_score":0.86984116,"about_ca_system_score_codex":0.00003422474,"about_ca_system_score_gemma":0.000027665938,"threshold_uncertainty_score":0.22384204},"labels":[],"label_agreement":null},{"id":"W3150149142","doi":"10.1109/aspdac.2011.5722305","title":"An integer programming placement approach to FPGA clock power reduction","year":2011,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Clock skew; Digital clock manager; Clock network; Clock gating; CPU multiplier; Computer science; Field-programmable gate array; Integer programming; Synchronous circuit; Reduction (mathematics); Static timing analysis; Skew; Routing (electronic design automation); Dynamic demand; Clock rate; Electronic engineering; Embedded system; Power (physics); Clock signal; Engineering; Mathematics; Algorithm; Jitter; Telecommunications; Chip","score_opus":0.026024550565928735,"score_gpt":0.22797989032749408,"score_spread":0.20195533976156535,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3150149142","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022137947,0.000028164113,0.8131089,0.0000057495267,0.0001714972,0.0004617069,6.1779986e-7,0.0019250601,0.16216035],"genre_scores_gemma":[0.85421866,0.0000026292173,0.14523701,0.000021086902,0.00004196938,0.0001215068,0.000004305569,0.000027332633,0.000325505],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9993934,0.000011175754,0.00013729741,0.00016363838,0.00008908153,0.00020542582],"domain_scores_gemma":[0.99963427,0.0000015882572,0.0000090461945,0.0002293311,0.000025256135,0.000100490935],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012997333,0.000117682896,0.00009009539,0.000094297786,0.000026511732,0.000026922862,0.00011681813,0.00006758968,0.00015068964],"category_scores_gemma":[0.0000024375986,0.00010391966,0.00002787245,0.00012607248,0.000009846176,0.00015131867,0.000014988486,0.00009372384,0.000047551086],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015686845,0.0020197516,0.00050797244,0.00025509737,0.00028239482,0.000011967733,0.03995875,0.004522844,0.16570863,0.037298393,0.08479188,0.66448545],"study_design_scores_gemma":[0.00046260853,0.0014837182,0.00081568497,0.000062083884,0.000045613437,0.000081878476,0.005611286,0.015844522,0.9074011,0.00070039724,0.066013224,0.0014779173],"about_ca_topic_score_codex":0.000025646548,"about_ca_topic_score_gemma":0.0000010487356,"teacher_disagreement_score":0.8320807,"about_ca_system_score_codex":0.000048649174,"about_ca_system_score_gemma":0.0000039394486,"threshold_uncertainty_score":0.42377207},"labels":[],"label_agreement":null},{"id":"W3159717212","doi":"10.1109/iscas51556.2021.9401562","title":"Analog Layout Placement for FinFET Technology Using Reinforcement Learning","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Leverage (statistics); Computer science; Reinforcement learning; Analog multiplier; Analogue electronics; Page layout; Process (computing); Computer engineering; Computer architecture; Artificial intelligence; Engineering; Computer hardware; Analog signal; Electrical engineering; Electronic circuit","score_opus":0.019697238196305606,"score_gpt":0.25247244360131227,"score_spread":0.23277520540500665,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3159717212","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011815253,0.00042486636,0.976986,0.000047726604,0.000088607034,0.00019729973,0.0000014215354,0.0010722611,0.009366561],"genre_scores_gemma":[0.95128405,0.000056774457,0.047694772,0.0000796093,0.000041209154,0.000059548187,0.00002083662,0.000028981733,0.000734207],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993896,0.0000059371428,0.00017674419,0.00012689999,0.000069055124,0.00023177138],"domain_scores_gemma":[0.99973613,0.00001674981,0.000017901119,0.00014741249,0.000054873628,0.000026904796],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000085820255,0.00010737545,0.00013504646,0.000117341726,0.00006398478,0.000022087255,0.00006767394,0.00010296721,0.00017209345],"category_scores_gemma":[0.000026745107,0.000110547844,0.000046242152,0.00017699684,0.00001247093,0.000051898394,0.00003835632,0.00011295912,0.000009040678],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007042436,0.000025408946,0.00095479755,0.00014228937,0.00020121009,0.00002712577,0.00013323329,0.74751866,0.19713297,0.022575254,0.0038280026,0.027454024],"study_design_scores_gemma":[0.0003392097,0.00009597478,0.000012654036,0.00003586035,0.000033647317,0.000018114106,0.00020060778,0.55974156,0.40116572,0.0011531706,0.03694295,0.00026054026],"about_ca_topic_score_codex":0.000002067431,"about_ca_topic_score_gemma":0.000004447967,"teacher_disagreement_score":0.9394688,"about_ca_system_score_codex":0.00006819837,"about_ca_system_score_gemma":0.000020615887,"threshold_uncertainty_score":0.450801},"labels":[],"label_agreement":null},{"id":"W3166559827","doi":"10.1109/mcas.2021.3071607","title":"FPGA Architecture: Principles and Progression","year":2021,"lang":"en","type":"article","venue":"IEEE Circuits and Systems Magazine","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":189,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Vector Institute; University of Toronto","funders":"Vector Institute","keywords":"Reconfigurability; Field-programmable gate array; Computer architecture; Reconfigurable computing; Embedded system; Computer science; Architecture; Key (lock); Process (computing); Telecommunications; Operating system","score_opus":0.02337800119548627,"score_gpt":0.23485294282619915,"score_spread":0.21147494163071287,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3166559827","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7394922,0.07114468,0.13345753,0.00019660384,0.0021337022,0.0012654441,0.00006712366,0.002416207,0.04982655],"genre_scores_gemma":[0.99824405,0.00052319583,0.00018441203,0.000017783517,0.00018605599,0.00003790695,0.000006514831,0.000030579125,0.00076948875],"study_design_codex":"bench_or_experimental","study_design_gemma":"not_applicable","domain_scores_codex":[0.9992262,0.00003527014,0.00020797581,0.00020835272,0.00012438183,0.00019780206],"domain_scores_gemma":[0.9996157,0.000031185275,0.000027065096,0.00018104793,0.000042715117,0.00010223156],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00014410546,0.00015323861,0.00022735485,0.000059424885,0.000057274112,0.0001115624,0.00004991549,0.00009708544,0.0000069501934],"category_scores_gemma":[0.000013993741,0.00012919282,0.000023405259,0.00010344439,0.000033486882,0.000062812294,0.000019520001,0.00013015997,0.000007927736],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004070387,0.00005338854,0.0029530958,0.0024742652,0.0001139077,0.0003597046,0.00085721165,0.0013557614,0.5781508,0.0020815993,0.0060796672,0.4055165],"study_design_scores_gemma":[0.0027551907,0.0005036798,0.03644855,0.0035512203,0.00018832299,0.0055898787,0.00030611284,0.06439535,0.23421898,0.0019378818,0.6472826,0.0028222227],"about_ca_topic_score_codex":0.0000020222308,"about_ca_topic_score_gemma":0.00000488561,"teacher_disagreement_score":0.6412029,"about_ca_system_score_codex":0.00001367112,"about_ca_system_score_gemma":0.000011819188,"threshold_uncertainty_score":0.52683306},"labels":[],"label_agreement":null},{"id":"W3168334689","doi":"10.1186/s42774-021-00074-x","title":"A new multi-level algorithm for balanced partition problem on large scale directed graphs","year":2021,"lang":"en","type":"article","venue":"Advances in Aerodynamics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"China Aerodynamics Research and Development Center; National Natural Science Foundation of China","keywords":"Graph partition; Partition (number theory); Partition problem; Cluster analysis; Computer science; Algorithm; Frequency partition of a graph; Theoretical computer science; Graph; Mathematics; Mathematical optimization; Combinatorics; Line graph; Artificial intelligence","score_opus":0.010618390845147357,"score_gpt":0.2563474883941447,"score_spread":0.24572909754899733,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3168334689","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0024805737,0.0011905804,0.9939468,0.000023427367,0.00029291405,0.00037978392,0.00018958413,0.000763038,0.0007333297],"genre_scores_gemma":[0.0674543,0.00244401,0.9290613,0.000072593946,0.00005652824,0.00023713306,0.00028068564,0.00006236019,0.0003311055],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999045,0.000021101589,0.0002374183,0.00025761168,0.00010524687,0.0003335815],"domain_scores_gemma":[0.9995835,0.000062279956,0.000033742042,0.00020355213,0.000055915298,0.00006104149],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000099295125,0.00017353347,0.00021470533,0.00008093576,0.000042662596,0.000022337183,0.000104315484,0.00010554183,0.000010720102],"category_scores_gemma":[0.000023562623,0.00018829569,0.00006642861,0.00034523616,0.000013062644,0.00024028086,0.000017310413,0.00015571067,0.0000048121083],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018387176,0.00021047576,0.0008107787,0.00017271168,0.000027822134,0.000019623601,0.00023487212,0.010935775,0.0065118345,0.002900675,0.00067198405,0.97748506],"study_design_scores_gemma":[0.0016173405,0.0000916269,0.0018261974,0.00023980644,0.000014008747,0.0000062106756,0.0000586723,0.95950186,0.012910653,0.013017051,0.010260598,0.00045598295],"about_ca_topic_score_codex":0.0000035296346,"about_ca_topic_score_gemma":0.0008081854,"teacher_disagreement_score":0.9770291,"about_ca_system_score_codex":0.0000915256,"about_ca_system_score_gemma":0.000021774513,"threshold_uncertainty_score":0.76784754},"labels":[],"label_agreement":null},{"id":"W317001884","doi":"","title":"Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 03, 2009","year":2009,"lang":"en","type":"article","venue":"Symposium on Integrated Circuits and Systems Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Chip; System on a chip; Engineering; Telecommunications; Embedded system","score_opus":0.019313384306271133,"score_gpt":0.219492695547199,"score_spread":0.20017931124092786,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W317001884","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.58428806,0.021885954,0.042579964,0.0026426874,0.012214488,0.04257153,0.003917215,0.009815051,0.28008506],"genre_scores_gemma":[0.99524,0.00050685473,0.00001985482,0.0003357179,0.00028955785,0.00039051686,0.000031062576,0.00018855395,0.002997898],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9949175,0.00053354807,0.0014301053,0.0010874702,0.0009626364,0.0010687128],"domain_scores_gemma":[0.9970366,0.0006000216,0.0005165045,0.0008176327,0.0006718023,0.0003574362],"candidate_categories":["metaepi_narrow"],"consensus_categories":["metaepi_narrow"],"category_scores_codex":[0.0019766302,0.0012849192,0.001291199,0.0005807549,0.0005457151,0.0008048714,0.0009697341,0.00087686523,0.0000210114],"category_scores_gemma":[0.000120313394,0.00078250834,0.00022893156,0.0013172773,0.00027981083,0.00048838666,0.000041129675,0.0014163704,0.000052937074],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00029161508,0.0005614398,0.0003771174,0.0010876437,0.0007108669,0.000060386985,0.0026870146,0.01118733,0.589495,0.025447756,0.36594072,0.002153105],"study_design_scores_gemma":[0.009148396,0.022747038,0.0051900037,0.03752806,0.0017260443,0.0030382883,0.01608595,0.18268247,0.64562315,0.0015230369,0.06359031,0.011117241],"about_ca_topic_score_codex":0.00021472418,"about_ca_topic_score_gemma":0.0000047024123,"teacher_disagreement_score":0.4109519,"about_ca_system_score_codex":0.0003067512,"about_ca_system_score_gemma":0.00017265047,"threshold_uncertainty_score":0.9999903},"labels":[],"label_agreement":null},{"id":"W3182769310","doi":"10.1109/rtas52030.2021.00061","title":"Work in Progress: Path-based Graph Partition for Parallel Hardware-accelerated Functional Verification","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Research and Development","keywords":"Computer science; Parallel computing; Graph partition; Partition (number theory); Directed acyclic graph; Scheduling (production processes); Partition problem; Very-large-scale integration; Critical path method; Graph; Theoretical computer science; Algorithm; Embedded system; Mathematics; Mathematical optimization","score_opus":0.03826321316868462,"score_gpt":0.2383112089487506,"score_spread":0.200047995780066,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3182769310","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.023449987,0.00041103325,0.9733734,0.00023570683,0.0001798257,0.00047220336,0.000013122606,0.001003494,0.0008612162],"genre_scores_gemma":[0.96177495,0.000032580287,0.036561288,0.000083473606,0.000047383477,0.0009057693,0.00044767937,0.000023650393,0.00012320242],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994044,0.00001746013,0.00018117037,0.00015467782,0.00008354568,0.00015874804],"domain_scores_gemma":[0.9997116,0.000025636784,0.000016503585,0.00013069308,0.00008395645,0.000031627133],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000090630834,0.00009934172,0.00010245767,0.00007040928,0.000032295175,0.000041017745,0.000039421917,0.000086286665,0.0001577124],"category_scores_gemma":[0.000012794717,0.000099588324,0.0000506311,0.0003509238,0.000014607416,0.00010265591,0.000003521986,0.00006888788,0.000011129531],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.001118763,0.001789551,0.06556224,0.0014044796,0.00030746058,0.00010239821,0.00055600086,0.17884277,0.17957851,0.031907033,0.34453928,0.19429149],"study_design_scores_gemma":[0.0041147526,0.0002528963,0.16341382,0.00042014514,0.00006188563,0.000006470811,0.00017911015,0.2619487,0.50711614,0.0106825065,0.050328553,0.0014750336],"about_ca_topic_score_codex":0.000001654537,"about_ca_topic_score_gemma":0.0000065211593,"teacher_disagreement_score":0.938325,"about_ca_system_score_codex":0.00004123282,"about_ca_system_score_gemma":0.00002680778,"threshold_uncertainty_score":0.4061094},"labels":[],"label_agreement":null},{"id":"W3187519750","doi":"10.1016/j.disopt.2021.100657","title":"The Bipartite Boolean Quadric Polytope","year":2021,"lang":"en","type":"article","venue":"Discrete Optimization","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Polytope; Mathematics; Quadric; Combinatorics; Discrete mathematics; Bipartite graph; Clique; Duality (order theory); Graph","score_opus":0.004837548440651212,"score_gpt":0.1978723109585278,"score_spread":0.1930347625178766,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3187519750","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0009865656,0.001536586,0.9722475,0.0002724307,0.00022116821,0.000105323605,0.0000057139305,0.00063875475,0.023985991],"genre_scores_gemma":[0.9662557,0.002976264,0.02782762,0.00014772112,0.00016912402,0.000055529144,0.00014120908,0.000077522665,0.0023492565],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995132,0.000024258672,0.000128035,0.000095511205,0.0000884345,0.00015057476],"domain_scores_gemma":[0.9996733,0.000023964098,0.000016028423,0.00021135787,0.000040535924,0.00003480706],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007215102,0.0000818691,0.00006620461,0.00002384732,0.00011674845,0.000100929305,0.00008282963,0.000045322115,0.00007442736],"category_scores_gemma":[0.000025308904,0.00006420299,0.0000374161,0.0002158819,0.000018434235,0.00011812435,0.000017782217,0.00006958542,0.000021617496],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004135953,0.000008419239,0.00026414002,0.000018834848,0.000035578803,0.000009897046,0.00016877458,0.96709466,0.0038651484,0.0043621175,0.007710049,0.016458252],"study_design_scores_gemma":[0.00009938059,0.000013279525,0.00021809379,0.000018574516,0.000014712316,0.000006557165,0.000070482936,0.95805776,0.023984218,0.00028858695,0.017052658,0.00017566959],"about_ca_topic_score_codex":0.0000032243418,"about_ca_topic_score_gemma":0.0000077728155,"teacher_disagreement_score":0.9652692,"about_ca_system_score_codex":0.000021822205,"about_ca_system_score_gemma":0.000010658434,"threshold_uncertainty_score":0.2618122},"labels":[],"label_agreement":null},{"id":"W3193692689","doi":"10.1145/3465373","title":"A Deep Learning Framework to Predict Routability for FPGA Circuit Placement","year":2021,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":21,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Field-programmable gate array; Overfitting; Convolutional neural network; Deep learning; Process (computing); Computer engineering; Artificial intelligence; Placement; Netlist; Computer architecture; Artificial neural network; Parallel computing; Algorithm; Machine learning; Embedded system; Circuit design; Physical design","score_opus":0.01829405432440499,"score_gpt":0.23635761236458508,"score_spread":0.2180635580401801,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3193692689","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017717274,0.0013507067,0.97643846,0.00031597607,0.0004531398,0.00075462443,0.000024869743,0.0017449559,0.0011999633],"genre_scores_gemma":[0.99402565,0.000234174,0.0039656893,0.000036870853,0.000028250595,0.0011158471,0.0000067499077,0.00003685789,0.00054993865],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99883413,0.000043486034,0.00032799607,0.00036402667,0.000090136615,0.00034020017],"domain_scores_gemma":[0.9989881,0.00026393204,0.0000306495,0.0005429611,0.00008731862,0.000087064844],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00027825419,0.00019785455,0.00033492636,0.00032167195,0.00024643872,0.00005485135,0.00019246369,0.00048788593,0.00009100441],"category_scores_gemma":[0.00014508289,0.00021162555,0.00006948486,0.00048248706,0.000041774096,0.00007105802,0.0000033540418,0.00052973017,0.000019186853],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011671985,0.00032161755,0.0016258346,0.0016864782,0.00088227546,0.000040943414,0.0014863486,0.19041385,0.031173412,0.012714736,0.00063824304,0.75889957],"study_design_scores_gemma":[0.0030137259,0.0033626913,0.00059679366,0.0024408277,0.000497814,0.00088747026,0.014209686,0.13849913,0.621602,0.075279064,0.13652024,0.0030905476],"about_ca_topic_score_codex":0.0000069392386,"about_ca_topic_score_gemma":0.000013595029,"teacher_disagreement_score":0.97630835,"about_ca_system_score_codex":0.00009313539,"about_ca_system_score_gemma":0.000020387648,"threshold_uncertainty_score":0.86298394},"labels":[],"label_agreement":null},{"id":"W3196467229","doi":"10.1109/tvlsi.2021.3107404","title":"Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":30,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Newfoundland and Labrador; Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Foundation for Innovation","keywords":"Netlist; Computer science; Circuit extraction; Electronic engineering; Network topology; CMOS; Equivalent circuit; Transistor; Topology (electrical circuits); Computer engineering; Algorithm; Computer hardware; Engineering; Electrical engineering; Voltage","score_opus":0.019417589222570582,"score_gpt":0.2264605211824901,"score_spread":0.20704293195991952,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3196467229","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08769491,0.000184046,0.90675294,0.000015393243,0.0014351216,0.0005794953,0.0002651937,0.002368714,0.00070419704],"genre_scores_gemma":[0.99742466,0.00008186207,0.0011509571,0.000023554847,0.00009394317,0.00083631644,0.000032136966,0.000075127755,0.0002814655],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982502,0.0000826251,0.00058508397,0.0003705731,0.00030066556,0.00041088977],"domain_scores_gemma":[0.99901336,0.00013402793,0.000055335582,0.00040657318,0.0002845942,0.0001061299],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00036688312,0.0003056928,0.00038638528,0.00027518434,0.00030840203,0.0001416604,0.00015719996,0.00025993364,0.00005068749],"category_scores_gemma":[0.000013610853,0.00030459109,0.00023315339,0.0004400757,0.0000191367,0.00017895477,9.473331e-7,0.00028112347,0.00005502458],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015521578,0.00012991382,0.0000038510075,0.00024042556,0.00008053182,0.0000034747713,0.00032258438,0.96844596,0.02553694,0.000060718165,0.00037662,0.004783454],"study_design_scores_gemma":[0.00021701586,0.000045167166,0.0000048410675,0.00036754092,0.00006300921,0.000026938465,0.00042706545,0.8409705,0.1573807,0.0000065826125,0.00021396684,0.00027664294],"about_ca_topic_score_codex":0.000021290027,"about_ca_topic_score_gemma":0.000049703744,"teacher_disagreement_score":0.9097297,"about_ca_system_score_codex":0.00029101377,"about_ca_system_score_gemma":0.00005954251,"threshold_uncertainty_score":0.99994063},"labels":[],"label_agreement":null},{"id":"W3197603378","doi":"10.1109/tcad.2021.3109863","title":"RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":43,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Vector Institute; University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; Huawei Technologies; VMware; Google","keywords":"Field-programmable gate array; Computer science; Reinforcement learning; Simulated annealing; Quality (philosophy); Parallel computing; Algorithm; Artificial intelligence; Embedded system","score_opus":0.03147460674607729,"score_gpt":0.23712456196530796,"score_spread":0.20564995521923066,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3197603378","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010443936,0.00043406803,0.9874515,0.000012355894,0.00054929045,0.0005752596,0.000015218274,0.00029777712,0.00022058077],"genre_scores_gemma":[0.9876384,0.00025738255,0.011595809,0.000041148698,0.000035935955,0.00007516749,0.000006910805,0.00004348657,0.00030572814],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984989,0.00016136852,0.00054069015,0.00031591966,0.00022044833,0.00026267784],"domain_scores_gemma":[0.9991682,0.00019242699,0.00006776851,0.00019610475,0.00022253899,0.00015292007],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00029488254,0.00028486963,0.00042402162,0.00029651698,0.00019227587,0.00014968547,0.000083194784,0.00014544508,0.000027356971],"category_scores_gemma":[0.00000712187,0.00027623444,0.000063506086,0.00036250384,0.000032684922,0.00012844114,0.0000025818129,0.00029393824,0.0000031224856],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013491135,0.000036030542,0.000004672818,0.00011586734,0.00014432409,0.000010803489,0.00048422557,0.9257905,0.06084139,0.000049230028,0.00019933468,0.012310137],"study_design_scores_gemma":[0.00045137457,0.00038908655,0.0000042950505,0.0005510554,0.00006127171,0.0001102653,0.00047138784,0.93246055,0.06470725,0.0000066044845,0.0004929054,0.00029394653],"about_ca_topic_score_codex":0.00007140919,"about_ca_topic_score_gemma":0.0000029309751,"teacher_disagreement_score":0.9771945,"about_ca_system_score_codex":0.00014939337,"about_ca_system_score_gemma":0.000070607195,"threshold_uncertainty_score":0.999969},"labels":[],"label_agreement":null},{"id":"W3199073795","doi":"10.1109/mlcad52597.2021.9531243","title":"Effective Machine-Learning Models for Predicting Routability During FPGA Placement","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Boosting (machine learning); Computer science; Routing (electronic design automation); Field-programmable gate array; Simple (philosophy); Stack (abstract data type); Algorithm; Machine learning; Parallel computing; Artificial intelligence; Computer engineering; Embedded system","score_opus":0.011180650174050306,"score_gpt":0.2180569008370414,"score_spread":0.2068762506629911,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3199073795","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.23759528,0.00030271534,0.7499256,0.000014309146,0.000104911196,0.00059024076,0.000013860146,0.0017494708,0.009703629],"genre_scores_gemma":[0.9892246,0.000027740127,0.009983754,0.000011229273,0.00006973518,0.00029675086,0.000018265318,0.00004071528,0.00032718392],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99915665,0.000040501345,0.00019666007,0.00023162559,0.000107142194,0.00026739386],"domain_scores_gemma":[0.99954414,0.00015220646,0.000018915378,0.00016534948,0.000060871324,0.00005853525],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023669402,0.00015201679,0.00018142718,0.00004070341,0.00011598761,0.000040508206,0.00006783532,0.00007719737,0.000061670726],"category_scores_gemma":[0.000075143216,0.00015213012,0.000075062,0.000096339645,0.000009157696,0.00017024271,0.000048724425,0.00019742211,0.0000030826093],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000052523144,0.00007793765,0.0060241837,0.0009846614,0.00020955662,0.00001623596,0.0013828796,0.8504633,0.12275266,0.00091668044,0.0001699634,0.016949477],"study_design_scores_gemma":[0.00033101023,0.000046990936,0.00033541356,0.000032854055,0.000015691674,0.0000066373104,0.00011289453,0.6772294,0.3207481,0.00082080526,0.00015933652,0.00016083138],"about_ca_topic_score_codex":0.000013471028,"about_ca_topic_score_gemma":0.00001567498,"teacher_disagreement_score":0.75162935,"about_ca_system_score_codex":0.00013434261,"about_ca_system_score_gemma":0.000010128092,"threshold_uncertainty_score":0.6203686},"labels":[],"label_agreement":null},{"id":"W3204115212","doi":"10.1109/tvlsi.2021.3109560","title":"Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Alberta Innovates; Natural Sciences and Engineering Research Council of Canada; Canada Research Chairs","keywords":"Computer science; Analogue electronics; Electronic engineering; Electronic circuit; Representation (politics); Parasitic extraction; Circuit design; Computer engineering; Algorithm; Engineering; Electrical engineering","score_opus":0.044292664488729004,"score_gpt":0.24585190853968122,"score_spread":0.2015592440509522,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3204115212","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.030743599,0.00046871483,0.9640406,0.000009741323,0.0013831075,0.00058687216,0.00022680435,0.0011470751,0.0013935195],"genre_scores_gemma":[0.9942395,0.0001797001,0.0046340004,0.000042579417,0.00014289415,0.00020575878,0.000033511176,0.00008521482,0.00043685103],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976764,0.00031058642,0.0006834466,0.00046149985,0.00038680018,0.0004812833],"domain_scores_gemma":[0.9988163,0.00019548442,0.00009130605,0.0004914584,0.00025138192,0.00015404313],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00040759216,0.00042598837,0.0005114974,0.00034312336,0.00033631668,0.0002785588,0.00019358398,0.0003426115,0.00011053955],"category_scores_gemma":[0.000011556396,0.00042402523,0.00023857476,0.0006729516,0.000057246918,0.00057007273,0.0000014435118,0.00050588103,0.00007738093],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000524366,0.0004968291,0.000052518997,0.00039459084,0.0006166887,0.0001420761,0.0048052026,0.49119216,0.4819055,0.0033579224,0.0016202084,0.015363874],"study_design_scores_gemma":[0.00045867142,0.0001245689,0.000044850218,0.0006092167,0.00014805127,0.0002626537,0.0033832963,0.6021625,0.39120635,0.00025335114,0.00065929454,0.00068719254],"about_ca_topic_score_codex":0.00010203955,"about_ca_topic_score_gemma":0.0001917537,"teacher_disagreement_score":0.9634959,"about_ca_system_score_codex":0.0004695178,"about_ca_system_score_gemma":0.0001645786,"threshold_uncertainty_score":0.9998212},"labels":[],"label_agreement":null},{"id":"W3211377203","doi":"10.1016/j.orl.2021.10.005","title":"The pairwise flowtime network construction problem","year":2021,"lang":"en","type":"article","venue":"Operations Research Letters","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"The Scarborough Hospital; University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Pairwise comparison; Connection (principal bundle); Mathematics; Combinatorics; Time complexity; Discrete mathematics; Computer science; Mathematical optimization; Algorithm","score_opus":0.024144724458390502,"score_gpt":0.2807077763147023,"score_spread":0.2565630518563118,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3211377203","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.26053438,0.007452629,0.56074893,0.091685034,0.002208755,0.0037173762,0.00005116888,0.0039997855,0.069601946],"genre_scores_gemma":[0.8150625,0.0029534346,0.17362578,0.001162843,0.0019061096,0.0013018798,0.00013388811,0.0001440024,0.0037095319],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9989251,0.000188935,0.00014303152,0.0001300389,0.00025517223,0.0003577192],"domain_scores_gemma":[0.9993497,0.00015070035,0.0000028389518,0.00028427917,0.00015669335,0.00005579118],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0006143536,0.00007206574,0.00006491324,0.000047113466,0.0007309475,0.0003418637,0.00014231539,0.00004354251,0.0000945453],"category_scores_gemma":[0.00007224134,0.0000574708,0.000033791264,0.000475668,0.0001316365,0.00014675148,0.00003979161,0.0003563418,0.0001011946],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004096985,0.000015579846,0.000167355,0.000027792068,0.000072273724,0.00004602597,0.00023026604,0.2522139,0.22956468,0.013145197,0.45648423,0.048028603],"study_design_scores_gemma":[0.00045924017,0.0000742218,0.0004464143,0.00015049966,0.0000172981,0.00017412356,0.00048371335,0.33984542,0.09270937,0.0022277813,0.56281644,0.00059549295],"about_ca_topic_score_codex":0.000015038565,"about_ca_topic_score_gemma":0.00009569422,"teacher_disagreement_score":0.5545281,"about_ca_system_score_codex":0.00008262069,"about_ca_system_score_gemma":0.00005356549,"threshold_uncertainty_score":0.5621931},"labels":[],"label_agreement":null},{"id":"W3215814272","doi":"10.32920/ryerson.14647368.v1","title":"Parallel Implementation of Non-slicing Floorplans with MPI and OpenMP","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Parallel computing; Computer science; Floorplan; Benchmark (surveying); Multiprocessing; Very-large-scale integration; Slicing; Computation; Tree (set theory); Computer architecture; Embedded system; Algorithm","score_opus":0.010706930939589066,"score_gpt":0.259707047487965,"score_spread":0.24900011654837595,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3215814272","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4028732,0.00022323221,0.59005404,0.000022477196,0.000061966435,0.0004389082,0.000020171605,0.0002618577,0.0060441964],"genre_scores_gemma":[0.93623596,0.0003815775,0.06312427,0.000018703038,0.000024400568,0.000056440178,0.00008181323,0.000029147785,0.000047704918],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994,0.000009562243,0.00020342493,0.00017251057,0.000095294025,0.000119169876],"domain_scores_gemma":[0.9996751,0.000012447771,0.000039555096,0.00020301854,0.000036419435,0.000033467888],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000079108795,0.00016009818,0.00025368104,0.00007031418,0.000014713018,0.000047883364,0.000088309636,0.00010687545,0.00012089645],"category_scores_gemma":[8.769269e-7,0.00013999217,0.000028346154,0.00004794261,0.000013264532,0.00006506019,0.00011022229,0.00017305155,7.326673e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001049391,0.0002105228,0.11373119,0.017506234,0.0037813475,0.00029561933,0.029868152,0.12576403,0.3144097,0.0024899088,0.02326562,0.36857274],"study_design_scores_gemma":[0.002340202,0.00043281403,0.072398715,0.002003509,0.0004180039,0.0000860083,0.0098429285,0.07170837,0.8372565,0.0006634175,0.00060706795,0.0022424958],"about_ca_topic_score_codex":0.00068245817,"about_ca_topic_score_gemma":0.00043584267,"teacher_disagreement_score":0.53336275,"about_ca_system_score_codex":0.000021608503,"about_ca_system_score_gemma":0.000029057332,"threshold_uncertainty_score":0.57087153},"labels":[],"label_agreement":null},{"id":"W3216491306","doi":"10.1109/tvlsi.2021.3102088","title":"High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Foundation for Innovation","keywords":"Sizing; Bayesian optimization; Computer science; Dimension (graph theory); Mathematical optimization; Computer engineering; Electronic engineering; Engineering; Artificial intelligence; Mathematics","score_opus":0.00880592322359947,"score_gpt":0.21828826331407286,"score_spread":0.2094823400904734,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3216491306","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0033922414,0.0002284727,0.99124396,0.000057532037,0.0025418599,0.0007870815,0.0005206762,0.00093741645,0.00029073318],"genre_scores_gemma":[0.9872806,0.00007118516,0.010821857,0.00006893332,0.00020321408,0.0005449074,0.00026378906,0.00009612056,0.000649375],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9980554,0.00013798557,0.0005984946,0.00046759337,0.0003411922,0.00039934856],"domain_scores_gemma":[0.9988317,0.00015662856,0.000089860834,0.00037267516,0.00042168557,0.00012748627],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00028333472,0.00036274307,0.00042982187,0.0003400471,0.0003638031,0.0001658466,0.00013376908,0.00033562313,0.00017555912],"category_scores_gemma":[0.000011369822,0.00037273634,0.00025817862,0.0005103777,0.00002917221,0.00048993283,0.0000015616695,0.000370919,0.00002801162],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005041392,0.00019044951,0.0000079227475,0.00017690478,0.00016975806,0.000013753551,0.00037376743,0.9765457,0.015837686,0.00039632447,0.0015582932,0.004679035],"study_design_scores_gemma":[0.0005765073,0.00011614507,0.000014272747,0.0003207839,0.000080322396,0.000040716877,0.0006551737,0.8265214,0.17094351,0.00007700665,0.00027657184,0.0003775674],"about_ca_topic_score_codex":0.000058812184,"about_ca_topic_score_gemma":0.0002187245,"teacher_disagreement_score":0.9838884,"about_ca_system_score_codex":0.00038114938,"about_ca_system_score_gemma":0.00007916725,"threshold_uncertainty_score":0.99987245},"labels":[],"label_agreement":null},{"id":"W4200335229","doi":"10.32920/17303846","title":"Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University; McGill University","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Lookup table; Computer science; Block (permutation group theory); Benchmark (surveying); Embedded system; Mathematics; Geometry; Geography","score_opus":0.029610208371433935,"score_gpt":0.21355779931383623,"score_spread":0.1839475909424023,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4200335229","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9361254,0.003531043,0.048164666,0.0001546295,0.00016839281,0.0008670011,0.000045246656,0.00020205883,0.010741561],"genre_scores_gemma":[0.9981586,0.00029784613,0.0013133436,0.000045035446,0.000026261408,0.00006994142,0.0000067180913,0.000032636955,0.00004963223],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985233,0.00012305395,0.00057563407,0.00025150427,0.00029261125,0.00023392666],"domain_scores_gemma":[0.9985949,0.0003856677,0.00018613941,0.00071896816,0.000082889914,0.00003144424],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0008250381,0.0002628702,0.00040204925,0.00007059677,0.0000838779,0.000064235304,0.0006491684,0.0002137439,0.0000140478905],"category_scores_gemma":[0.00019204638,0.00013364702,0.000108054,0.00027050238,0.00025215925,0.00007347526,0.00072313054,0.00077300874,7.2458135e-8],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000028162642,0.00005423437,0.020340722,0.0016586323,0.00014778989,0.000002373245,0.017008772,0.93460166,0.02061191,0.0015393416,0.000501306,0.003530437],"study_design_scores_gemma":[0.00010737382,0.000013657263,0.0014094223,0.0017317496,0.00005429162,0.000006463872,0.0024746994,0.91234004,0.076449595,0.0052059353,0.000007893913,0.00019887032],"about_ca_topic_score_codex":0.0005685008,"about_ca_topic_score_gemma":0.00018918699,"teacher_disagreement_score":0.062033184,"about_ca_system_score_codex":0.000035389432,"about_ca_system_score_gemma":0.00009066891,"threshold_uncertainty_score":0.54499674},"labels":[],"label_agreement":null},{"id":"W4200447807","doi":"10.32920/17303846.v1","title":"Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University; McGill University","funders":"","keywords":"Field-programmable gate array; Routing (electronic design automation); Lookup table; Computer science; Block (permutation group theory); Benchmark (surveying); Embedded system; Mathematics; Geometry; Geography","score_opus":0.029610208371433935,"score_gpt":0.21355779931383623,"score_spread":0.1839475909424023,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4200447807","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9361254,0.003531043,0.048164666,0.0001546295,0.00016839281,0.0008670011,0.000045246656,0.00020205883,0.010741561],"genre_scores_gemma":[0.9981586,0.00029784613,0.0013133436,0.000045035446,0.000026261408,0.00006994142,0.0000067180913,0.000032636955,0.00004963223],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985233,0.00012305395,0.00057563407,0.00025150427,0.00029261125,0.00023392666],"domain_scores_gemma":[0.9985949,0.0003856677,0.00018613941,0.00071896816,0.000082889914,0.00003144424],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0008250381,0.0002628702,0.00040204925,0.00007059677,0.0000838779,0.000064235304,0.0006491684,0.0002137439,0.0000140478905],"category_scores_gemma":[0.00019204638,0.00013364702,0.000108054,0.00027050238,0.00025215925,0.00007347526,0.00072313054,0.00077300874,7.2458135e-8],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000028162642,0.00005423437,0.020340722,0.0016586323,0.00014778989,0.000002373245,0.017008772,0.93460166,0.02061191,0.0015393416,0.000501306,0.003530437],"study_design_scores_gemma":[0.00010737382,0.000013657263,0.0014094223,0.0017317496,0.00005429162,0.000006463872,0.0024746994,0.91234004,0.076449595,0.0052059353,0.000007893913,0.00019887032],"about_ca_topic_score_codex":0.0005685008,"about_ca_topic_score_gemma":0.00018918699,"teacher_disagreement_score":0.062033184,"about_ca_system_score_codex":0.000035389432,"about_ca_system_score_gemma":0.00009066891,"threshold_uncertainty_score":0.54499674},"labels":[],"label_agreement":null},{"id":"W4206801664","doi":"10.1109/icm52667.2021.9664954","title":"Using Machine Learning to Predict Operating Frequency During Placement in FPGA Designs","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Netlist; Computer science; Field-programmable gate array; Machine learning; Design flow; Regression; Artificial intelligence; Computer engineering; Computer hardware; Embedded system; Mathematics","score_opus":0.032476833279040794,"score_gpt":0.2565671384650938,"score_spread":0.22409030518605302,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4206801664","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.80901664,0.00038571755,0.18113124,0.00002163124,0.00008524501,0.0002321742,0.0000028454258,0.00082409853,0.008300418],"genre_scores_gemma":[0.90889674,0.000035394623,0.09059413,0.000036615264,0.000049689217,0.00002698945,0.0000063293874,0.000042086598,0.0003119982],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9989923,0.000051354866,0.0002837936,0.00021372086,0.0001362024,0.00032262574],"domain_scores_gemma":[0.9996944,0.000026297692,0.000013018733,0.00015191035,0.000029948638,0.00008440377],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019151164,0.00016146232,0.00017823394,0.00014390002,0.00008398986,0.000065056134,0.000091586284,0.000067074616,0.00036228605],"category_scores_gemma":[0.00005954571,0.00017175151,0.000033160344,0.00032563636,0.0000053510357,0.00014732103,0.00006221307,0.00025895526,0.0000127544245],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000001578213,0.000014164524,0.015814343,0.000055447923,0.000013716472,0.00009575629,0.00046096553,0.20556392,0.77735,0.000051071438,0.000026322517,0.0005526991],"study_design_scores_gemma":[0.0003007096,0.000041265663,0.0013364786,0.00017861825,0.0000074407426,0.0000383075,0.00028424925,0.24850726,0.74886525,0.00004225562,0.00009028721,0.00030785275],"about_ca_topic_score_codex":0.000117512485,"about_ca_topic_score_gemma":0.000116563795,"teacher_disagreement_score":0.099880144,"about_ca_system_score_codex":0.00019993122,"about_ca_system_score_gemma":0.000026433328,"threshold_uncertainty_score":0.70038235},"labels":[],"label_agreement":null},{"id":"W4211258324","doi":"10.1145/611835.611838","title":"Using logic duplication to improve performance in FPGAs","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Path (computing); Computer science; Critical path method; Programmable logic device; Logic synthesis; Logic optimization; Data deduplication; Logic gate; Parallel computing; Gene duplication; Algorithm; Embedded system; Engineering; Programming language","score_opus":0.025479367273861124,"score_gpt":0.2480734802009621,"score_spread":0.22259411292710096,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4211258324","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.49317488,0.000047850695,0.45122525,0.000014076534,0.00006537765,0.00022046792,3.6271402e-7,0.0003963777,0.054855354],"genre_scores_gemma":[0.9667802,0.00001572174,0.03299743,0.000064365544,0.000009791582,0.000019805182,3.6357082e-7,0.000009689059,0.00010267582],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99967784,0.0000047456447,0.00008921969,0.00007514369,0.00003526148,0.000117777796],"domain_scores_gemma":[0.9998465,0.0000047244857,0.0000049374266,0.00010925999,0.000009467733,0.000025111676],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008352053,0.000055750723,0.000055009965,0.00006776468,0.000011566293,0.000009290374,0.0000431297,0.000037479807,0.000035752248],"category_scores_gemma":[0.000007823649,0.000052820436,0.000009395108,0.00014899278,0.0000030641863,0.00007597648,0.000004590665,0.000048805745,0.00003486823],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000028892237,0.000029197812,0.005448648,0.0000727355,0.000005611234,0.0000021701712,0.0001979168,0.035857733,0.9094557,0.013440227,0.000471199,0.03501596],"study_design_scores_gemma":[0.00013123339,0.00005429595,0.0034531043,0.000021784464,0.0000027022254,0.000006368708,0.000025280551,0.17376955,0.8171729,0.0011020019,0.004007265,0.00025352425],"about_ca_topic_score_codex":0.0000073534093,"about_ca_topic_score_gemma":0.0000036349315,"teacher_disagreement_score":0.47360528,"about_ca_system_score_codex":0.000055666645,"about_ca_system_score_gemma":0.0000043023665,"threshold_uncertainty_score":0.2153955},"labels":[],"label_agreement":null},{"id":"W4213131631","doi":"10.1145/3501803","title":"RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm","year":2022,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"National Key Research and Development Program of China; University of Waterloo; Mitacs; Sun Yat-sen University","keywords":"Computer science; Algorithm; Placement; Parallel computing; Field-programmable gate array; Block (permutation group theory); Simulated annealing; Routing (electronic design automation); Minimum bounding box; Bootstrapping (finance); Computer hardware; Embedded system; Circuit design; Physical design; Mathematics","score_opus":0.018276673021964496,"score_gpt":0.21781229927105503,"score_spread":0.19953562624909052,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4213131631","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.047548898,0.0054784142,0.94057906,0.00018221857,0.0011992845,0.0012796443,0.00037417945,0.0021354982,0.001222817],"genre_scores_gemma":[0.9879241,0.0003274376,0.010648856,0.000014757903,0.000018861878,0.00051185006,0.000010882944,0.000046218825,0.0004970202],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985908,0.00008788711,0.0005038611,0.0003015381,0.00019117896,0.00032471106],"domain_scores_gemma":[0.9991431,0.000072161696,0.000104072606,0.0005704279,0.000053798532,0.000056433313],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00028174018,0.00024333235,0.00047994862,0.00096422865,0.00042913092,0.000016462252,0.00032878923,0.00023867779,0.00015551223],"category_scores_gemma":[0.0000071722666,0.000266409,0.000092667375,0.00064817106,0.0001078933,0.000090030095,0.000008926623,0.00054240384,0.0000054700718],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009746489,0.00029008187,0.0000682164,0.00050264964,0.00077339535,0.000034078872,0.0004130832,0.88690335,0.05643852,0.00062030286,0.0010643066,0.05279458],"study_design_scores_gemma":[0.002439111,0.0009243487,0.000030052259,0.00037347517,0.00027640292,0.0015261398,0.006707646,0.89052117,0.0885812,0.0008382905,0.00672902,0.0010531283],"about_ca_topic_score_codex":0.000058396432,"about_ca_topic_score_gemma":0.0000011093572,"teacher_disagreement_score":0.9403752,"about_ca_system_score_codex":0.00019598982,"about_ca_system_score_gemma":0.000037135236,"threshold_uncertainty_score":0.99997884},"labels":[],"label_agreement":null},{"id":"W4213423202","doi":"10.1109/tcad.2022.3153437","title":"Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning","year":2022,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":48,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Newfoundland and Labrador; Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Foundation for Innovation","keywords":"Network topology; Computer science; Reinforcement learning; Operational amplifier; Topology (electrical circuits); Circuit design; Computer engineering; Physical design; Electronic engineering; Computer architecture; Amplifier; Artificial intelligence; Engineering; Electrical engineering; CMOS; Embedded system","score_opus":0.021714337896414457,"score_gpt":0.20268336025317465,"score_spread":0.1809690223567602,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4213423202","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0063055386,0.0002883101,0.9907889,0.000008008887,0.00060244737,0.0007005233,0.000026466269,0.0007184723,0.0005613592],"genre_scores_gemma":[0.99839854,0.0001569627,0.0007105783,0.00002716722,0.00003005746,0.00045822887,0.000014123877,0.00007203033,0.00013232011],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976722,0.00046375825,0.0006904596,0.0004060343,0.00036075394,0.0004067744],"domain_scores_gemma":[0.9988242,0.00038446212,0.00015769167,0.0003281143,0.00017361899,0.00013191343],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005286605,0.00041243268,0.00067492644,0.0006367221,0.00036470278,0.00008001992,0.00029170245,0.00015724123,0.00015760446],"category_scores_gemma":[0.0000058031073,0.0003586059,0.000104139435,0.00071039435,0.00010104263,0.00015426459,0.0000029942364,0.00079667073,0.0000047190088],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000047177968,0.000075923555,0.00001437548,0.00010025213,0.0003433468,0.000036895522,0.0004707494,0.9381946,0.010585744,0.0003311753,0.00014790079,0.04965186],"study_design_scores_gemma":[0.00053391646,0.002063817,0.000010466564,0.00025399792,0.00012256605,0.00033580398,0.0012144587,0.97009516,0.024222212,0.00003467198,0.0006004804,0.0005124755],"about_ca_topic_score_codex":0.00033304677,"about_ca_topic_score_gemma":0.000009423682,"teacher_disagreement_score":0.99209297,"about_ca_system_score_codex":0.00029460192,"about_ca_system_score_gemma":0.000086309105,"threshold_uncertainty_score":0.9998866},"labels":[],"label_agreement":null},{"id":"W4220782754","doi":"10.1186/s13059-022-02645-7","title":"Author Correction: Benchmarking transposable element annotation methods for creation of a streamlined, comprehensive pipeline","year":2022,"lang":"en","type":"erratum","venue":"Genome biology","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Transposable element; Benchmarking; Pipeline (software); Biology; Computational biology; Annotation; Human genetics; Genome; Genetics; Data science; Computer science; Gene; Programming language","score_opus":0.02890398508704715,"score_gpt":0.3353251674681216,"score_spread":0.3064211823810744,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4220782754","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000043118715,0.0059715114,0.9677306,0.000043668693,0.020711198,0.0010660951,0.00070673786,0.00033424987,0.003392822],"genre_scores_gemma":[0.010095943,0.008570376,0.7559978,0.00026310445,0.009187111,0.0049649524,0.11533505,0.0005729329,0.09501273],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99850297,0.0001772292,0.000611771,0.0003410398,0.000076300516,0.00029071653],"domain_scores_gemma":[0.99908423,0.00021249878,0.0002170188,0.0002527847,0.00019210533,0.000041382747],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00037661687,0.00029737395,0.0006085967,0.00033551367,0.00009847503,0.000009568373,0.00018956042,0.0004604931,0.0005086298],"category_scores_gemma":[0.000028356406,0.0003230111,0.00017984577,0.0002309345,0.000042685217,0.000036346373,0.000026970409,0.00039679778,0.0000012784309],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00013224366,0.00007809472,0.000026981867,0.0010649198,0.00039999562,0.0000017336093,0.0007496639,0.0076372335,0.059860136,0.00032716402,0.5541465,0.37557527],"study_design_scores_gemma":[0.00024089987,0.0005827963,0.00004884597,0.00003407993,0.00012728365,0.0000058879723,0.000087203436,0.062201753,0.0024148906,0.0005357585,0.933426,0.0002945802],"about_ca_topic_score_codex":0.00003613071,"about_ca_topic_score_gemma":0.000014283114,"teacher_disagreement_score":0.37927946,"about_ca_system_score_codex":0.00020891466,"about_ca_system_score_gemma":0.00007097619,"threshold_uncertainty_score":0.9999222},"labels":[],"label_agreement":null},{"id":"W4226144797","doi":"10.1007/978-3-030-98832-6_49","title":"Quantitative Analysis of Informational Significance of SWEBOK Knowledge Areas in IEEE/ACM Curriculum Guidelines","year":2022,"lang":"en","type":"book-chapter","venue":"Lecture notes in networks and systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"École de Technologie Supérieure","funders":"","keywords":"Curriculum; Computer science; Psychology; Pedagogy","score_opus":0.03136443883641031,"score_gpt":0.2783706916736247,"score_spread":0.2470062528372144,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4226144797","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0059136306,0.15213835,0.78079414,0.000037559053,0.0020423897,0.0025488178,0.00057493564,0.00030952765,0.05564064],"genre_scores_gemma":[0.99601,0.002548479,0.00073269586,0.000010593208,0.00013820648,0.000084421314,0.00018926612,0.000043035943,0.00024330485],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982689,0.000045822348,0.0011034169,0.00020003431,0.00020851422,0.00017330854],"domain_scores_gemma":[0.99872243,0.000468575,0.00030626197,0.000296775,0.00017335652,0.000032614676],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004616898,0.00029303663,0.0009994938,0.0008132667,0.000021397847,0.000015659976,0.00022914716,0.00034465836,0.00004469875],"category_scores_gemma":[0.000083068815,0.00027020343,0.00015528454,0.00046224543,0.000055477594,0.00006923793,0.000047428308,0.0004392195,3.6483834e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000009475385,0.000010184956,0.0012151701,0.00041320798,0.0003561754,0.0000037229381,0.0003850872,0.9882251,0.000028962106,0.0060714344,0.00044812,0.0028333643],"study_design_scores_gemma":[0.00013122415,0.00006871455,0.000151106,0.0007280991,0.00017115883,0.000002524173,0.00002776868,0.9937051,0.000021251028,0.0010626906,0.0036208667,0.0003094822],"about_ca_topic_score_codex":0.00024370596,"about_ca_topic_score_gemma":0.0006043388,"teacher_disagreement_score":0.9900964,"about_ca_system_score_codex":0.000094122486,"about_ca_system_score_gemma":0.000031811956,"threshold_uncertainty_score":0.999975},"labels":[],"label_agreement":null},{"id":"W4229764280","doi":"10.1109/eurdac.1992.246233","title":"Efficient constrained encoding for VLSI sequential logic synthesis","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Encoding (memory); Heuristic; Computer science; Asynchronous communication; Sequential logic; Variety (cybernetics); Algorithm; State (computer science); Theoretical computer science; Parallel computing; Arithmetic; Logic gate; Artificial intelligence; Mathematics","score_opus":0.05243470574356956,"score_gpt":0.24200893338452087,"score_spread":0.1895742276409513,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4229764280","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011416179,0.00007436498,0.87875605,0.000060833365,0.00027038032,0.0012087879,0.000020794423,0.0035448913,0.104647726],"genre_scores_gemma":[0.9393107,0.000042094103,0.059999764,0.00008691075,0.00009962438,0.00017309698,0.0000071683676,0.00013170645,0.00014890594],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976103,0.00015198007,0.00069057214,0.0005716435,0.00034554765,0.0006299796],"domain_scores_gemma":[0.9986477,0.00028818168,0.00021936167,0.00020380325,0.00044890287,0.00019206291],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0016130845,0.00048301963,0.00039771863,0.0003200073,0.00026119783,0.00041860272,0.00044480275,0.0001206232,0.00019049496],"category_scores_gemma":[0.0011313765,0.000499812,0.00014163768,0.0003899197,0.00012340004,0.00024625813,0.000041370142,0.00025268923,0.0001577399],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000036576625,0.00011056546,0.000081387654,0.0005913998,0.000104956795,0.00002564911,0.00125629,0.005774688,0.88442534,0.084822364,0.006158582,0.016612213],"study_design_scores_gemma":[0.0007462182,0.00022733335,0.00019370789,0.00038396148,0.00013380719,0.00011300699,0.00025439134,0.51364875,0.47691008,0.0023272408,0.003911695,0.0011498167],"about_ca_topic_score_codex":6.731334e-7,"about_ca_topic_score_gemma":7.8627565e-8,"teacher_disagreement_score":0.92789453,"about_ca_system_score_codex":0.00012339394,"about_ca_system_score_gemma":0.00007377194,"threshold_uncertainty_score":0.99974537},"labels":[],"label_agreement":null},{"id":"W4230336076","doi":"10.1109/date.2010.5457151","title":"A power optimization method for CMOS Op-Amps using sub-space based geometric programming","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"York University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Geometric programming; Monomial; CMOS; Convex optimization; Mathematical optimization; Transistor; Space (punctuation); Computer science; Regular polygon; Constraint (computer-aided design); Power (physics); Voltage; Electronic engineering; Topology (electrical circuits); Mathematics; Engineering; Electrical engineering; Discrete mathematics","score_opus":0.014328292748706504,"score_gpt":0.2706430490692564,"score_spread":0.2563147563205499,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4230336076","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0033973418,0.00004064705,0.99353975,0.000028632852,0.00020324673,0.0006549793,0.000003887885,0.0011913097,0.0009402141],"genre_scores_gemma":[0.18406516,0.0000026364942,0.81566465,0.000034788874,0.00004678428,0.00008313666,0.000009386728,0.000053042244,0.000040411414],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992227,0.000014871822,0.00018014708,0.00017708576,0.00011759855,0.00028757512],"domain_scores_gemma":[0.9994544,0.00013551455,0.000032151485,0.0002105639,0.00009258442,0.00007478384],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00041949507,0.00015605576,0.00016625188,0.00037419362,0.00006678601,0.00008517073,0.00011424197,0.00016252602,0.00011948992],"category_scores_gemma":[0.000120014185,0.00014950475,0.00007940082,0.00065924745,0.000011539553,0.00016090847,0.000013178674,0.00015887413,0.0000024153908],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000018193892,0.00009318247,0.00023724216,0.00019259148,0.000059088965,0.0000037025775,0.000099924124,0.48075762,0.41913822,0.0011665946,0.0018502532,0.09638339],"study_design_scores_gemma":[0.00019468361,0.000037589987,0.000009683591,0.000008500548,0.000015210115,0.0000039464926,0.000011421763,0.7880636,0.20757484,0.000043701162,0.0038534782,0.00018333204],"about_ca_topic_score_codex":0.000017024939,"about_ca_topic_score_gemma":0.000005222049,"teacher_disagreement_score":0.307306,"about_ca_system_score_codex":0.000037693193,"about_ca_system_score_gemma":0.000020569863,"threshold_uncertainty_score":0.60966265},"labels":[],"label_agreement":null},{"id":"W4230667489","doi":"10.1109/wsc.2007.4419650","title":"Optimizing time warp simulation with reinforcement learning techniques","year":2007,"lang":"en","type":"article","venue":"2007 Winter Simulation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Reinforcement learning; Computer science; Benchmark (surveying); Bellman equation; Dynamic programming; Function (biology); Bounded function; State (computer science); Optimal control; Artificial intelligence; Mathematical optimization; Algorithm; Mathematics","score_opus":0.01691587200443344,"score_gpt":0.2577633236223327,"score_spread":0.24084745161789922,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4230667489","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007293009,0.000024592911,0.963795,0.000008311861,0.000055723678,0.00031106375,7.034507e-7,0.0016960513,0.026815549],"genre_scores_gemma":[0.9783402,0.000006898003,0.0205341,0.000050442923,0.000111900066,0.000010335426,0.000027304826,0.000043203192,0.00087562855],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99887836,0.000019709689,0.00035162712,0.00020575206,0.00023410324,0.00031046505],"domain_scores_gemma":[0.99930036,0.00014991638,0.00007508157,0.00020013575,0.00019487974,0.000079654645],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00033716497,0.00021943566,0.00018143418,0.00020270192,0.00008248282,0.00008070598,0.00012963095,0.00012927568,0.00047622624],"category_scores_gemma":[0.000027093796,0.00020731475,0.000041699273,0.00016474638,0.000032779193,0.0003823762,0.000025885845,0.0002450018,0.00008324596],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000034953842,0.000007094196,0.00021477004,0.000017989356,0.000018563478,0.00000501043,0.00046482583,0.9750378,0.0044050287,0.000074529125,0.00005526495,0.019664159],"study_design_scores_gemma":[0.0001755826,0.00013919371,0.00018358396,0.00012809427,0.000012790132,0.0000018296749,0.000037911093,0.9577306,0.034880783,0.000048866637,0.006379082,0.00028168436],"about_ca_topic_score_codex":0.000004599607,"about_ca_topic_score_gemma":0.0000023050443,"teacher_disagreement_score":0.97104716,"about_ca_system_score_codex":0.000107589854,"about_ca_system_score_gemma":0.000013863864,"threshold_uncertainty_score":0.84540504},"labels":[],"label_agreement":null},{"id":"W4232625310","doi":"10.1145/503057.503059","title":"Integrated retiming and placement for field programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Retiming; Computer science; Field-programmable gate array; Gate array; Routing (electronic design automation); Parallel computing; Combinational logic; Algorithm; Electronic circuit; Logic gate; Embedded system; Engineering","score_opus":0.021977691626485916,"score_gpt":0.21168669329966935,"score_spread":0.18970900167318344,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4232625310","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008839051,0.0003465276,0.95497996,0.00015233195,0.000074500356,0.000562369,0.0000027537885,0.0013181054,0.033724397],"genre_scores_gemma":[0.8815672,0.00022501532,0.114392504,0.00014427057,0.000042575204,0.00022070318,0.0000060606776,0.00003077529,0.0033709009],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996356,0.0000029789412,0.0000916886,0.00008332363,0.000034506134,0.0001519525],"domain_scores_gemma":[0.9998387,0.000030233328,0.0000067932515,0.00007565362,0.000014387763,0.000034243167],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000057395257,0.00007792269,0.00007788369,0.000032358403,0.000030063286,0.00003319318,0.000038058457,0.00004897752,0.0001989768],"category_scores_gemma":[0.00001110949,0.00006620973,0.000018630988,0.000048721715,0.000006386787,0.000053554275,0.0000067936885,0.00005532327,0.0000050591552],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000028949826,0.00007199936,0.00024595414,0.00043309975,0.00011521245,0.000008208977,0.0011897488,0.0012212419,0.04197097,0.0030515385,0.2964395,0.65522355],"study_design_scores_gemma":[0.00035336614,0.00029145408,0.0000037033433,0.00005411644,0.000015284895,0.000005920946,0.00015628118,0.6980168,0.20891552,0.0006408843,0.091287956,0.00025868465],"about_ca_topic_score_codex":0.0000068507047,"about_ca_topic_score_gemma":0.0000050427698,"teacher_disagreement_score":0.87272817,"about_ca_system_score_codex":0.00001321837,"about_ca_system_score_gemma":8.961135e-7,"threshold_uncertainty_score":0.26999542},"labels":[],"label_agreement":null},{"id":"W4232809888","doi":"10.1007/978-0-387-30162-4_69","title":"Circuit Placement","year":2008,"lang":"en","type":"book-chapter","venue":"Encyclopedia of Algorithms","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Computer science","score_opus":0.015496608379691827,"score_gpt":0.20329742567141884,"score_spread":0.187800817291727,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4232809888","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0000074886507,0.0042863563,0.011306626,0.00000461683,0.000631062,0.00032334536,0.00009227061,0.000654473,0.98269373],"genre_scores_gemma":[0.0005355812,0.1081859,0.010101606,0.00003735151,0.001276574,0.00006601856,0.00016240652,0.00038090046,0.8792537],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9986124,0.0000048906877,0.0004909983,0.00026052113,0.0003698952,0.00026128627],"domain_scores_gemma":[0.9992634,0.000042364587,0.00010231556,0.00043148873,0.000058798996,0.0001016328],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000075788026,0.0004179412,0.0005242098,0.00022120414,0.00003207384,0.000007137873,0.0002848594,0.00043235387,0.0007150683],"category_scores_gemma":[0.0000058188407,0.0004479733,0.00019239295,0.00003289978,0.00007845914,0.00006510164,0.00004502172,0.0004135674,0.00018481008],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000827274,0.000053334796,0.000011691971,0.0005811975,0.00057253434,0.00031560045,0.0011036294,0.00041393697,0.00015452103,0.009404331,0.5782399,0.409141],"study_design_scores_gemma":[0.0001643047,0.000099767894,0.000009708027,0.00016193991,0.000051727246,0.000029703833,0.000004594892,0.00030500971,0.00056727714,0.002629483,0.9954193,0.00055714085],"about_ca_topic_score_codex":0.000004569761,"about_ca_topic_score_gemma":0.0000010182085,"teacher_disagreement_score":0.4171794,"about_ca_system_score_codex":0.00009805994,"about_ca_system_score_gemma":0.000046374607,"threshold_uncertainty_score":0.9997972},"labels":[],"label_agreement":null},{"id":"W4234183293","doi":"10.1109/aspdac.2002.994967","title":"Probabilistic analysis of rectilinear Steiner trees","year":2003,"lang":"en","type":"article","venue":"Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Probabilistic logic; Very-large-scale integration; Computer science; Set (abstract data type); Interconnection; Tree (set theory); Statistical model; Algorithm; Probabilistic analysis of algorithms; Theoretical computer science; Mathematical optimization; Mathematics; Artificial intelligence; Combinatorics; Programming language","score_opus":0.05023175393092778,"score_gpt":0.25355997425688653,"score_spread":0.20332822032595876,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4234183293","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024505433,0.0002486225,0.9439369,0.00012099407,0.00024360545,0.001875012,0.00010129154,0.0006780458,0.028290093],"genre_scores_gemma":[0.9619921,0.00057300396,0.03638342,0.00002322101,0.000039306127,0.0002060171,0.000024746087,0.00006235143,0.000695821],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9963441,0.00019831596,0.0012630705,0.00081351364,0.0008466674,0.00053435925],"domain_scores_gemma":[0.997016,0.00048999157,0.00060781493,0.00027290793,0.0013401877,0.00027308543],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017317822,0.00069681305,0.0011099216,0.001414784,0.00015762332,0.00035514924,0.00048555023,0.00041009922,0.0004762066],"category_scores_gemma":[0.0005770826,0.00065760594,0.00019271445,0.0009682962,0.00033864478,0.00069958635,0.000038902825,0.0003937766,0.000016021037],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0018205007,0.0014340417,0.005332129,0.0016900591,0.008139989,0.000041209096,0.02639748,0.032404326,0.41274425,0.41042727,0.009952428,0.0896163],"study_design_scores_gemma":[0.0013316475,0.0012472911,0.0015954823,0.0005400614,0.0009347441,0.000029739229,0.003945131,0.88873845,0.09296087,0.007244798,0.00027009865,0.0011616627],"about_ca_topic_score_codex":0.00000880591,"about_ca_topic_score_gemma":0.000001308621,"teacher_disagreement_score":0.9374867,"about_ca_system_score_codex":0.000091169095,"about_ca_system_score_gemma":0.00018833998,"threshold_uncertainty_score":0.99958754},"labels":[],"label_agreement":null},{"id":"W4234246562","doi":"10.1109/iccad.2005.1560189","title":"Mixed-size placement via line search","year":2005,"lang":"en","type":"article","venue":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Scaling; Computer science; Simple (philosophy); Line (geometry); Sampling (signal processing); Algorithm; Line search; Function (biology); Mathematical optimization; Mathematics; Geometry","score_opus":0.07272725290455787,"score_gpt":0.2939019442810032,"score_spread":0.22117469137644533,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4234246562","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007879225,0.00018006272,0.9772347,0.002092146,0.0024274883,0.0009155129,0.00009048431,0.0016358208,0.007544525],"genre_scores_gemma":[0.83406895,0.0007476214,0.15669584,0.0010409631,0.0028845486,0.00019094505,0.000100841724,0.00017316069,0.004097107],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9953952,0.00022740428,0.0010417436,0.00088266947,0.0012248699,0.0012281068],"domain_scores_gemma":[0.9973956,0.00057063164,0.00016900568,0.0010098561,0.00036056366,0.0004943661],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.001017262,0.00079778506,0.0006341911,0.00058435724,0.00017354982,0.00039009284,0.0019595565,0.00038552974,0.002638435],"category_scores_gemma":[0.000057099536,0.0008277765,0.00024620455,0.00019400117,0.00012671844,0.00056054915,0.00022104614,0.0009082538,0.001593594],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005462776,0.0012493312,0.00011235776,0.00014110692,0.0010094399,0.0002412536,0.0005779826,0.3408851,0.110760294,0.01444394,0.30554342,0.22448948],"study_design_scores_gemma":[0.0014869585,0.00043928134,0.0001728718,0.00027551,0.00003435341,0.00008663135,0.00002693868,0.8037604,0.14658648,0.0019167832,0.04412693,0.0010868674],"about_ca_topic_score_codex":0.0000370961,"about_ca_topic_score_gemma":0.0000735362,"teacher_disagreement_score":0.82618976,"about_ca_system_score_codex":0.0008312954,"about_ca_system_score_gemma":0.00020532378,"threshold_uncertainty_score":0.9994173},"labels":[],"label_agreement":null},{"id":"W4234875748","doi":"10.1109/dac.1992.227777","title":"TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections","year":2003,"lang":"en","type":"article","venue":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Netlist; Field-programmable gate array; Computer science; Set (abstract data type); Parallel computing; Embedded system","score_opus":0.07288281590620302,"score_gpt":0.2520814451196865,"score_spread":0.17919862921348348,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4234875748","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017692681,0.00010353693,0.97712463,0.00046330792,0.00012789134,0.001744291,0.000013239186,0.001789443,0.00094096235],"genre_scores_gemma":[0.90863425,0.00004513793,0.08990946,0.000035868612,0.000043078107,0.0012345455,0.000006151847,0.000053212818,0.000038329355],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99851334,0.000026053094,0.0005038223,0.00033310984,0.0002580926,0.0003655685],"domain_scores_gemma":[0.9986299,0.00031139495,0.00024389486,0.00030468803,0.00044817504,0.0000619312],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00053630193,0.00031519466,0.00033762274,0.0004677339,0.00027370182,0.00013537545,0.00044864215,0.0002266648,0.000024982692],"category_scores_gemma":[0.00047376912,0.00024688605,0.000066399014,0.00064462755,0.00015764392,0.0004311281,0.000018151271,0.00022857798,0.000005407544],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000107153,0.00011291798,0.00045722182,0.0008947498,0.00036320303,0.000001871162,0.0053034592,0.012208618,0.82158035,0.102905564,0.0061497027,0.049915187],"study_design_scores_gemma":[0.00069961365,0.0003706783,0.00022226422,0.00029460483,0.00008404286,0.000048067115,0.0014620945,0.12970708,0.82269186,0.041579865,0.0023376949,0.0005021221],"about_ca_topic_score_codex":0.0000071907757,"about_ca_topic_score_gemma":0.00000669324,"teacher_disagreement_score":0.89094156,"about_ca_system_score_codex":0.0000726173,"about_ca_system_score_gemma":0.000112510585,"threshold_uncertainty_score":0.99999833},"labels":[],"label_agreement":null},{"id":"W4235520433","doi":"10.1109/aspdac.2004.1337565","title":"An approach for reducing dynamic power consumption in synchronous sequential digital designs","year":2004,"lang":"en","type":"article","venue":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Retiming; Dynamic voltage scaling; Computer science; Benchmark (surveying); Scaling; Sequential logic; Dynamic demand; Combinational logic; Power (physics); Digital electronics; Voltage; Parallel computing; Algorithm; Electronic circuit; Logic gate; Mathematics; Engineering","score_opus":0.030050040300585872,"score_gpt":0.25423693336913966,"score_spread":0.2241868930685538,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4235520433","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13243487,0.0001497882,0.8627335,0.00001806572,0.00035518766,0.0016676767,0.00013465273,0.0012631585,0.0012430939],"genre_scores_gemma":[0.9288893,0.000060594975,0.069987565,0.000017182188,0.000076944256,0.00039060545,0.0003342037,0.00011018956,0.00013344361],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99706,0.00013562986,0.00083327934,0.00080488756,0.00035455846,0.00081167364],"domain_scores_gemma":[0.9986644,0.00008273079,0.0001994772,0.00055131543,0.00021357276,0.00028853503],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006287147,0.0006268504,0.00060437067,0.0005171618,0.00023103514,0.0005530262,0.00033052388,0.00051587314,0.00005447747],"category_scores_gemma":[0.00007151787,0.0006787948,0.00013413488,0.0003234599,0.00019557896,0.0011946367,0.000017501665,0.0003314189,0.000093235634],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00042525824,0.0012717637,0.0021741907,0.0016985832,0.0004612546,0.00011321995,0.032288294,0.40439698,0.50054055,0.0028975818,0.0016900661,0.05204226],"study_design_scores_gemma":[0.002733681,0.0006159886,0.0016219487,0.00040131828,0.00010016495,0.00011743505,0.0024987757,0.9770378,0.011209817,0.0020601626,0.000044056327,0.0015588596],"about_ca_topic_score_codex":0.00002314887,"about_ca_topic_score_gemma":0.000003499612,"teacher_disagreement_score":0.79645437,"about_ca_system_score_codex":0.0005386821,"about_ca_system_score_gemma":0.0003123574,"threshold_uncertainty_score":0.9995663},"labels":[],"label_agreement":null},{"id":"W4236097829","doi":"10.1109/iccad.2006.320150","title":"Timing Model Reduction for Hierarchical Timing Analysis","year":2006,"lang":"en","type":"article","venue":"Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Alterra Power (Canada)","funders":"","keywords":"Static timing analysis; Reduction (mathematics); Computer science; Algorithm; Block (permutation group theory); Hierarchical database model; Star (game theory); Mathematics; Data mining","score_opus":0.061136294365063154,"score_gpt":0.29371543404476447,"score_spread":0.2325791396797013,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4236097829","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.015619888,0.00011669379,0.8531741,0.0010600076,0.0008423621,0.0023099293,0.00026916043,0.0030018338,0.123606026],"genre_scores_gemma":[0.8778014,0.0001400532,0.12108527,0.00007037172,0.00027262294,0.0002390195,0.00014763858,0.00009624313,0.00014734267],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99532306,0.00011157984,0.0017584604,0.0010081531,0.0010915243,0.00070721825],"domain_scores_gemma":[0.9967734,0.0008840304,0.00048221392,0.0011467977,0.00048697492,0.00022654183],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00078541244,0.0007494728,0.0013012047,0.0010124065,0.000154602,0.000104806604,0.0019500724,0.0007206567,0.00008475974],"category_scores_gemma":[0.00026177632,0.0007337077,0.0009332775,0.0008418781,0.0004787671,0.00029395777,0.00021560708,0.000843425,0.0000072166026],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00025178213,0.00048076946,0.000077185956,0.000089034365,0.0003408943,0.000009101479,0.000020602747,0.17538664,0.79253566,0.025436955,0.0015182336,0.0038531083],"study_design_scores_gemma":[0.0032172545,0.0034064068,0.00716336,0.0016859875,0.0014719585,0.00013759806,0.0000534515,0.55457675,0.39437404,0.02915547,0.0013198432,0.0034378846],"about_ca_topic_score_codex":0.000043723463,"about_ca_topic_score_gemma":0.000020283123,"teacher_disagreement_score":0.86218154,"about_ca_system_score_codex":0.00045245982,"about_ca_system_score_gemma":0.00013576284,"threshold_uncertainty_score":0.9995114},"labels":[],"label_agreement":null},{"id":"W4236875804","doi":"10.1109/iccad.1996.571342","title":"Directional bias and non-uniformity in FPGA global routing architectures","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":43,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Placement; Computer science; Channel (broadcasting); Key (lock); Field-programmable gate array; Horizontal and vertical; Chip; Topology (electrical circuits); Electronic engineering; Parallel computing; Computer architecture; Electrical engineering; Computer network; Computer hardware; Telecommunications; Embedded system; Engineering; Physical design; Mathematics; Geometry; Circuit design","score_opus":0.01766529659440104,"score_gpt":0.21374269259747017,"score_spread":0.19607739600306912,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4236875804","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.79620194,0.0002423639,0.03432574,0.000052233056,0.00007839289,0.000120674595,0.000006152429,0.0007613194,0.1682112],"genre_scores_gemma":[0.9955844,0.000031734733,0.0041927807,0.000036534042,0.00003883207,0.0000065843255,7.2416356e-7,0.0000070300885,0.00010132329],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995841,0.000007867404,0.0001060193,0.00008965855,0.00006472992,0.00014765325],"domain_scores_gemma":[0.99986273,0.000024405113,0.000007050832,0.00006405523,0.0000055597484,0.000036187612],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007554214,0.00008422736,0.00008580817,0.000046766883,0.000026021184,0.000020997371,0.000044165132,0.000052397296,0.00009641125],"category_scores_gemma":[0.000014836261,0.00007515477,0.000019676487,0.00012552281,0.000015928956,0.000040373532,0.00001698809,0.00009476778,0.000008564112],"study_design_candidate":"observational","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000104957335,0.000108947905,0.41240376,0.00012497157,0.00006193483,0.00004810586,0.0009192599,0.009770287,0.0037828346,0.0022666992,0.009819972,0.5606827],"study_design_scores_gemma":[0.0007205125,0.0000895166,0.4790123,0.00009074243,0.000011226984,0.00015984046,0.000081529535,0.48072895,0.029108211,0.006939114,0.002306156,0.00075189036],"about_ca_topic_score_codex":0.00010530256,"about_ca_topic_score_gemma":0.00016679327,"teacher_disagreement_score":0.55993086,"about_ca_system_score_codex":0.000040023457,"about_ca_system_score_gemma":0.0000014960938,"threshold_uncertainty_score":0.30647227},"labels":[],"label_agreement":null},{"id":"W4237150254","doi":"10.1109/vlsi-soc.2012.7332115","title":"FPGA power reduction by guarded evaluation considering physical information","year":2012,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto; University of Waterloo","funders":"","keywords":"Netlist; Field-programmable gate array; Computer science; Routing (electronic design automation); Reduction (mathematics); Dynamic demand; Power consumption; Resource consumption; Design flow; Embedded system; Power analysis; Power (physics); Flow (mathematics); Cryptography; Algorithm; Mathematics","score_opus":0.012898149793095556,"score_gpt":0.24323604929108653,"score_spread":0.23033789949799097,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4237150254","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.72418547,0.0002251076,0.16175984,0.000065311986,0.00067535305,0.0005330116,0.0000051342945,0.0020321868,0.11051859],"genre_scores_gemma":[0.9985501,0.000007663663,0.0012266764,0.000024158195,0.00008251874,0.000039529325,0.000027641663,0.000009358744,0.000032343385],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995138,0.000015742788,0.00011917471,0.00003782251,0.00016433142,0.00014913875],"domain_scores_gemma":[0.99979174,0.0000095684545,0.000017095606,0.00009597857,0.000044303953,0.00004132745],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021514451,0.00007759599,0.00006812585,0.00005066079,0.000027544556,0.000026099746,0.000029679813,0.000049774,0.0001705752],"category_scores_gemma":[0.000018595203,0.00007444705,0.000025034888,0.00006982425,0.00000973172,0.0011407128,0.0000072258767,0.00006885682,0.00013335358],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007678419,0.00007765757,0.00013944821,0.000053158397,0.000060044742,8.0286725e-8,0.0051485277,0.0017528012,0.5319155,0.0023482027,0.27498162,0.18351533],"study_design_scores_gemma":[0.0002733042,0.00003474714,0.00045231398,0.000012355258,0.000029848192,0.000014469064,0.00038847674,0.0520429,0.9206254,0.0008656505,0.024975948,0.00028460714],"about_ca_topic_score_codex":0.0000044283934,"about_ca_topic_score_gemma":7.624535e-8,"teacher_disagreement_score":0.38870993,"about_ca_system_score_codex":0.00007147339,"about_ca_system_score_gemma":0.0000050469257,"threshold_uncertainty_score":0.30358627},"labels":[],"label_agreement":null},{"id":"W4238119721","doi":"10.32920/ryerson.14648718.v1","title":"Minimizing the layout area of 2-input look up tables","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Multiplexer; Routing (electronic design automation); Block (permutation group theory); Computer science; Router; Field-programmable gate array; Integrated circuit layout; Benchmark (surveying); Place and route; Computer hardware; Multiplexing; Embedded system; Computer network; Integrated circuit; Telecommunications; Mathematics","score_opus":0.02525693990355,"score_gpt":0.2258160281992281,"score_spread":0.20055908829567812,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4238119721","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11103073,0.013118046,0.68477505,0.00022708352,0.0025422052,0.0011558473,0.000113707196,0.0031253602,0.183912],"genre_scores_gemma":[0.98388153,0.0007962429,0.012943806,0.00006409378,0.00011207876,0.000074587886,0.000059050937,0.00006319942,0.0020054092],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9990437,0.000029398967,0.0003307573,0.00021949975,0.00017044786,0.00020617583],"domain_scores_gemma":[0.9990793,0.0000849851,0.00005670422,0.000671039,0.000071258044,0.000036741374],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001857865,0.0002470056,0.00037739085,0.00007669112,0.000028209928,0.000077634635,0.00040776774,0.00028204874,0.00042044328],"category_scores_gemma":[0.000026057858,0.00018009388,0.00017514401,0.00008906058,0.000040482846,0.000045698052,0.000342992,0.0004558338,0.0000058032597],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004137767,0.0003199826,0.0047313115,0.011335172,0.0037335115,0.00021449682,0.017930346,0.17222622,0.1833371,0.010225512,0.43789482,0.15801014],"study_design_scores_gemma":[0.0003219435,0.000041729792,0.00050866586,0.0018095389,0.00027462156,0.00003205864,0.0028543626,0.10529692,0.8670783,0.0029710163,0.017370597,0.0014402121],"about_ca_topic_score_codex":0.00014389414,"about_ca_topic_score_gemma":0.000045655168,"teacher_disagreement_score":0.8728508,"about_ca_system_score_codex":0.000037784124,"about_ca_system_score_gemma":0.000048933925,"threshold_uncertainty_score":0.7344015},"labels":[],"label_agreement":null},{"id":"W4238593108","doi":"10.1109/iccad.2002.1167616","title":"Incremental placement for layout-driven optimizations on FPGAs","year":2003,"lang":"en","type":"article","venue":"IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Netlist; Computer science; Logic optimization; Logic synthesis; Place and route; Restructuring; Field-programmable gate array; Logic block; Placement; Logic gate; Logic family; Parallel computing; Computer architecture; Programmable logic device; Computer engineering; Algorithm; Physical design; Embedded system; Circuit design","score_opus":0.07900521087211489,"score_gpt":0.291412927817465,"score_spread":0.2124077169453501,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4238593108","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0011465818,0.00003291316,0.9687831,0.00023613703,0.0018074843,0.0011021099,0.00015029649,0.0006701841,0.026071219],"genre_scores_gemma":[0.66836596,0.00016693927,0.32601988,0.0013349331,0.0006461013,0.00058141956,0.00012768437,0.00015432468,0.0026027532],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976522,0.00012514918,0.00059577613,0.0005590637,0.00056055054,0.0005073139],"domain_scores_gemma":[0.9985426,0.00028000065,0.00012213275,0.00054838305,0.00032485707,0.00018200191],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0003150097,0.0004953106,0.0003620413,0.00043061157,0.00016000817,0.00024876918,0.0008399518,0.0002027358,0.0015030236],"category_scores_gemma":[0.000069201014,0.00051434385,0.00016308947,0.00018878648,0.000058340323,0.00027243805,0.000048006932,0.00032919427,0.0004183158],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014784475,0.0004096792,0.00005262282,0.000036381545,0.00036230165,0.000025933103,0.00027112383,0.6826408,0.0069082025,0.049314782,0.2546992,0.005131103],"study_design_scores_gemma":[0.0019483601,0.0009790165,0.00006452615,0.00025712224,0.00004083928,0.000027733522,0.000035960515,0.9221646,0.052178644,0.002526063,0.018893294,0.00088384666],"about_ca_topic_score_codex":0.00000711765,"about_ca_topic_score_gemma":0.0000036747892,"teacher_disagreement_score":0.6672194,"about_ca_system_score_codex":0.0003533693,"about_ca_system_score_gemma":0.00008368237,"threshold_uncertainty_score":0.9997308},"labels":[],"label_agreement":null},{"id":"W4239075140","doi":"10.21203/rs.3.rs-359089/v1","title":"A New Multi-level Algorithms for Balanced Partition Problem on Large Scale Directed Graphs","year":2021,"lang":"en","type":"preprint","venue":"Research Square","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"China Aerodynamics Research and Development Center; National Natural Science Foundation of China","keywords":"Partition (number theory); Computer science; Scale (ratio); Algorithm; Mathematics; Combinatorics; Physics","score_opus":0.10681327905304573,"score_gpt":0.3800277494543114,"score_spread":0.2732144704012657,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4239075140","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009247768,0.0020709396,0.97521,0.0002119162,0.00046472705,0.0056384373,0.0016931598,0.0037381714,0.0017248853],"genre_scores_gemma":[0.49338135,0.0024954746,0.48973164,0.00003908365,0.0007027415,0.0069795237,0.0036619948,0.0003953186,0.0026128876],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9972681,0.0001817575,0.00033880174,0.00063821924,0.0006737309,0.00089940836],"domain_scores_gemma":[0.99833924,0.00018643086,0.000040625742,0.0006599347,0.00051211816,0.0002616454],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00087671063,0.00033635602,0.0004406781,0.00044408333,0.00016307665,0.00023660946,0.00037186895,0.000548564,0.000117584714],"category_scores_gemma":[0.00013610857,0.0003443912,0.0002588296,0.0004955194,0.00003074158,0.000093489056,0.00025264305,0.0013285897,0.000024708072],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00041493637,0.0023306683,0.0018805934,0.026324349,0.0012127775,0.00026523753,0.007927241,0.010500661,0.07738631,0.0025071441,0.3491584,0.5200917],"study_design_scores_gemma":[0.0056782197,0.001232655,0.016046008,0.013444301,0.000096970514,0.000012414914,0.0010092435,0.6294724,0.28326932,0.022212995,0.024494397,0.0030310748],"about_ca_topic_score_codex":0.000098764496,"about_ca_topic_score_gemma":0.00019149805,"teacher_disagreement_score":0.61897177,"about_ca_system_score_codex":0.0002704609,"about_ca_system_score_gemma":0.00020018854,"threshold_uncertainty_score":0.9999008},"labels":[],"label_agreement":null},{"id":"W4240011581","doi":"10.1109/aspdac.2010.5419877","title":"Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Transitive closure; Computer science; Representation (politics); Graph; Integrated circuit layout; Time complexity; Algorithm; Symmetry (geometry); Set (abstract data type); Topology (electrical circuits); Computational complexity theory; Theoretical computer science; Mathematics; Discrete mathematics; Integrated circuit; Combinatorics; Geometry","score_opus":0.07553143801172356,"score_gpt":0.2747646273056059,"score_spread":0.19923318929388234,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4240011581","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00123926,0.000014901195,0.9931639,0.000037248385,0.00022138203,0.00094079727,0.00007325071,0.0013476766,0.002961573],"genre_scores_gemma":[0.8529708,0.0000020767218,0.14627323,0.00031887332,0.000053108844,0.000157749,0.00008024907,0.000056403933,0.00008750706],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99884295,0.00002594227,0.00028690632,0.00026506442,0.00015691108,0.00042223794],"domain_scores_gemma":[0.99921,0.00021936852,0.000035043835,0.00031845164,0.00007085683,0.0001462545],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00031052312,0.0002635453,0.0002597896,0.00015982096,0.00008934277,0.00006156735,0.00022894087,0.00019973489,0.00079804525],"category_scores_gemma":[0.000021837704,0.00025094664,0.000106267966,0.00013597535,0.00010018348,0.000077309494,0.000015829533,0.00022918828,0.000038028964],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008665427,0.0006404051,0.0012588868,0.00052786624,0.0004360936,0.000027782991,0.00021329851,0.018374551,0.82719845,0.050933972,0.05688268,0.04341935],"study_design_scores_gemma":[0.004073245,0.00047341728,0.0019118742,0.00006106547,0.00009350318,0.000018382196,0.00024344717,0.8549557,0.13013412,0.0029441698,0.003796909,0.0012941845],"about_ca_topic_score_codex":0.000013401477,"about_ca_topic_score_gemma":0.00006154863,"teacher_disagreement_score":0.85173154,"about_ca_system_score_codex":0.00006464984,"about_ca_system_score_gemma":0.00003153206,"threshold_uncertainty_score":0.9999943},"labels":[],"label_agreement":null},{"id":"W4241249008","doi":"10.1109/iccad.2003.159755","title":"On the interaction between power-aware FPGA CAD Algorithms","year":2003,"lang":"en","type":"article","venue":"ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":71,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Computer science; CAD; Cluster analysis; Routing (electronic design automation); Power analysis; Design flow; Energy consumption; Power (physics); Embedded system; Algorithm; Power optimization; Electronic design automation; Energy (signal processing); FPGA prototype; Reconfigurable computing; Field (mathematics); Power consumption; Artificial intelligence; Engineering; Electrical engineering","score_opus":0.06249537015885398,"score_gpt":0.28237616494298573,"score_spread":0.21988079478413175,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4241249008","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007868177,0.000018832337,0.9610234,0.0003794926,0.006554014,0.0010108504,0.00012808948,0.001021767,0.021995362],"genre_scores_gemma":[0.97210604,0.00012637119,0.023780119,0.0012833549,0.0009483138,0.0002523618,0.0000911442,0.00015279668,0.0012595182],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99652565,0.00035515038,0.0007995083,0.0007696476,0.0008895851,0.0006604755],"domain_scores_gemma":[0.99666834,0.00068801123,0.00021759109,0.0007589929,0.001428495,0.00023856194],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.00069641677,0.00073266897,0.0005315059,0.0004693142,0.00022110081,0.000453565,0.0012024639,0.00035417132,0.00091732066],"category_scores_gemma":[0.00037116683,0.00062403525,0.00016742262,0.000640269,0.000115472765,0.00047556506,0.00006462296,0.00095980125,0.0013587587],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00032981977,0.0008668609,0.0006169373,0.00013648513,0.002002477,0.00027827977,0.0020310981,0.030890834,0.0241266,0.20550312,0.6448852,0.088332295],"study_design_scores_gemma":[0.00113712,0.0013710586,0.00054847077,0.0010482876,0.00008399179,0.00009952549,0.0001337211,0.86131054,0.095963135,0.008167095,0.028182093,0.0019549883],"about_ca_topic_score_codex":0.000036964415,"about_ca_topic_score_gemma":0.000003190566,"teacher_disagreement_score":0.96423787,"about_ca_system_score_codex":0.0005470323,"about_ca_system_score_gemma":0.00022145391,"threshold_uncertainty_score":0.99999595},"labels":[],"label_agreement":null},{"id":"W4241903622","doi":"10.1109/aspdac.2008.4483939","title":"Large-scale fixed-outline floorplanning design using convex optimization techniques","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph; University of Waterloo","funders":"","keywords":"Floorplan; Mathematical optimization; Computer science; Voronoi diagram; Minification; Convex optimization; Regular polygon; Graph; Mathematics; Theoretical computer science","score_opus":0.0293150775017935,"score_gpt":0.23663767064324662,"score_spread":0.20732259314145313,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4241903622","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0043396703,0.00017660168,0.9867352,0.000009679934,0.00007585031,0.00029330453,0.000005208512,0.0037673556,0.0045971004],"genre_scores_gemma":[0.28099403,0.0001633249,0.7183339,0.00008801705,0.000105638625,0.000025908479,0.000017101076,0.00006256413,0.00020949595],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990773,0.00003210866,0.00026241734,0.00017806177,0.00014135936,0.0003087157],"domain_scores_gemma":[0.99959725,0.000031740376,0.000029612678,0.00021020498,0.000059418668,0.00007176056],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020309394,0.00019524634,0.000218414,0.0001585236,0.00014029365,0.000025446912,0.0001309368,0.00016328896,0.00022301156],"category_scores_gemma":[0.000012863778,0.00019272433,0.00005159747,0.00022567468,0.000031056043,0.00024802095,0.000026503772,0.00015164164,0.000014198102],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000020114832,0.000093093695,0.0011115663,0.000079577396,0.000061962455,0.00008928265,0.0014061668,0.86865807,0.106414616,0.00014115545,0.019620731,0.0023036897],"study_design_scores_gemma":[0.0001107474,0.00003319675,0.00001815703,0.000029078383,0.000010050683,0.000063930354,0.000046505127,0.7535102,0.24497548,0.000040149025,0.00093449804,0.00022802378],"about_ca_topic_score_codex":0.00000894748,"about_ca_topic_score_gemma":6.5748935e-7,"teacher_disagreement_score":0.27665436,"about_ca_system_score_codex":0.000062193845,"about_ca_system_score_gemma":0.000018503928,"threshold_uncertainty_score":0.78590703},"labels":[],"label_agreement":null},{"id":"W4242232961","doi":"10.1109/date.2010.5457088","title":"Leveraging dominators for preprocessing QBF","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Preprocessor; Conjunctive normal form; Computer science; Very-large-scale integration; Algorithm; True quantified Boolean formula; Time complexity; Computational complexity theory; Process (computing); Theoretical computer science; Computation; Artificial intelligence; Programming language","score_opus":0.007577734978648513,"score_gpt":0.22073527213707117,"score_spread":0.21315753715842264,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4242232961","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17936267,0.00004461401,0.7817102,0.000025924699,0.0003071329,0.00017924278,9.359342e-7,0.0016216926,0.03674757],"genre_scores_gemma":[0.95547086,0.0000023622542,0.043983195,0.000029593411,0.00007926456,0.000042156804,0.0000011585072,0.000022538332,0.00036885703],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99965835,0.0000013147989,0.000081177815,0.00008791629,0.000038012247,0.00013325056],"domain_scores_gemma":[0.99980044,0.000027524215,0.000007146858,0.00011455381,0.000019152974,0.00003120428],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00010328049,0.00006785562,0.00006611127,0.000041085776,0.00003957651,0.000034269535,0.000077558805,0.000055555323,0.000062561376],"category_scores_gemma":[0.000017439568,0.0000619418,0.000029582996,0.000043898475,0.000009967687,0.00010061358,0.000007715773,0.000094827425,0.0000070082965],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000042259817,0.000015298325,0.00072197546,0.00022025514,0.000021429652,0.0000017077741,0.00061070966,0.00020707796,0.7503162,0.0034570326,0.012530259,0.23189381],"study_design_scores_gemma":[0.00018116542,0.00001199569,0.00016479385,0.000014892674,0.000007743463,0.000006901284,0.000050362432,0.05056227,0.91470957,0.0066637904,0.02740536,0.00022116459],"about_ca_topic_score_codex":0.000002302316,"about_ca_topic_score_gemma":0.000002297505,"teacher_disagreement_score":0.7761082,"about_ca_system_score_codex":0.0000072031266,"about_ca_system_score_gemma":0.0000051165184,"threshold_uncertainty_score":0.25259134},"labels":[],"label_agreement":null},{"id":"W4242254166","doi":"10.1145/611839.611842","title":"Automatic transistor and physical design of FPGA tiles from an architectural specification","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Place and route; Netlist; Schematic; Design layout record; Router; Embedded system; Lookup table; Computer hardware; Process (computing); Integrated circuit layout; Computer architecture; Integrated circuit; Engineering; Electrical engineering; Circuit extraction; Operating system; Voltage","score_opus":0.01827725736220543,"score_gpt":0.2206740602273176,"score_spread":0.20239680286511216,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4242254166","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.58052003,0.000063676176,0.41822785,0.000004725486,0.000014310254,0.000097884644,0.000003162439,0.00029236876,0.00077599485],"genre_scores_gemma":[0.9487943,0.0000073018177,0.051136564,0.0000053315707,0.000018940691,0.000009513202,0.000003410658,0.000013143876,0.000011485559],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996439,0.00003278557,0.00010282078,0.00008575304,0.000059891558,0.00007482373],"domain_scores_gemma":[0.99977607,0.000047738475,0.000011143016,0.00012077508,0.000008364635,0.000035926754],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000045723842,0.00007865513,0.00011879361,0.000036136164,0.000012587457,0.000009178447,0.000045537967,0.000030347062,0.00006693455],"category_scores_gemma":[0.000005523484,0.0000675338,0.00001979992,0.000045265144,0.000026235268,0.00006368795,0.0000012856923,0.000045377048,0.0000034532386],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000067299916,0.000086950255,0.00007294585,0.000069781214,0.00004097239,0.0000014648994,0.003604279,0.0012983662,0.8059718,0.00175931,0.00035557497,0.18673183],"study_design_scores_gemma":[0.00017667796,0.00010404945,0.0040777745,0.000018486484,0.000024512909,0.0000057924626,0.000092638984,0.23428857,0.75435317,0.006557345,0.00011335757,0.00018762381],"about_ca_topic_score_codex":0.000010084357,"about_ca_topic_score_gemma":0.0000019748827,"teacher_disagreement_score":0.36827427,"about_ca_system_score_codex":0.000010090077,"about_ca_system_score_gemma":0.0000039494676,"threshold_uncertainty_score":0.27539483},"labels":[],"label_agreement":null},{"id":"W4243927247","doi":"10.1109/edac.1990.136631","title":"Transistor placement and interconnect algorithms for leaf cell synthesis","year":2002,"lang":"en","type":"article","venue":"Proceedings of the European Design Automation Conference, 1990., EDAC.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Bell (Canada); Carleton University","funders":"","keywords":"Routing (electronic design automation); Chaining; Transistor; Computer science; Algorithm; Interconnection; Placement; Set (abstract data type); Metric (unit); Routing table; Parallel computing; Physical design; Engineering; Embedded system; Electrical engineering; Circuit design; Computer network; Routing protocol; Voltage","score_opus":0.038765431086630074,"score_gpt":0.20607168351157593,"score_spread":0.16730625242494584,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4243927247","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.031190462,0.00081569515,0.8384987,0.0004224097,0.00047289475,0.0028900902,0.00006401429,0.002452315,0.12319341],"genre_scores_gemma":[0.97314346,0.00017247882,0.025905453,0.000030369985,0.00007469312,0.000111379246,0.0000013061483,0.000065375694,0.0004954786],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9988897,0.000040859744,0.00040388753,0.00024214607,0.00018352718,0.00023990216],"domain_scores_gemma":[0.999338,0.00013918508,0.00015176402,0.00012459992,0.00017753187,0.000068974674],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00068749656,0.00024082417,0.00025464216,0.00015267382,0.00011004163,0.00012960783,0.00038842676,0.00006298654,0.000076522156],"category_scores_gemma":[0.0001178291,0.00019891764,0.00009504186,0.00015773982,0.00007337974,0.00029132774,0.000038565136,0.00012151905,0.000014632785],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007480438,0.0003038157,0.00010606193,0.0028038926,0.0002880732,0.0000019661616,0.011038738,0.0008309942,0.47952238,0.0028477134,0.14218761,0.35999396],"study_design_scores_gemma":[0.0007080156,0.000241872,0.0002842482,0.00041491122,0.00015525533,0.00001386162,0.00044671,0.47398433,0.51496553,0.00058962044,0.007623022,0.0005726514],"about_ca_topic_score_codex":0.0000013164072,"about_ca_topic_score_gemma":1.8566264e-7,"teacher_disagreement_score":0.941953,"about_ca_system_score_codex":0.000048162172,"about_ca_system_score_gemma":0.0000072019516,"threshold_uncertainty_score":0.8111626},"labels":[],"label_agreement":null},{"id":"W4244552270","doi":"10.1109/socc52499.2021.9739496","title":"Dynamic Power Analysis of Standard-Cell FPGA Fabrics","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Stratix; Field-programmable gate array; Software portability; Computer science; Embedded system; Application-specific integrated circuit; Power analysis; Standard cell; Dynamic demand; Power (physics); Reconfigurable computing; Computer hardware; Integrated circuit; Operating system; Algorithm","score_opus":0.004115572483494668,"score_gpt":0.20778413610152527,"score_spread":0.2036685636180306,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4244552270","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.097780645,0.0007259274,0.7933524,0.000016634605,0.00006342035,0.00004652913,0.00004991132,0.00048089793,0.10748359],"genre_scores_gemma":[0.98810714,0.00014477508,0.010634774,0.00002177939,0.0000019316797,0.0000021922206,0.000017583909,0.000014230517,0.0010555825],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995046,0.000009391335,0.0001589489,0.00009419675,0.00012153462,0.00011128047],"domain_scores_gemma":[0.99963474,0.000022157705,0.00001411736,0.00022764444,0.0000697695,0.000031591237],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00006500421,0.000076426644,0.0002262491,0.00015746825,0.000009964434,0.000012442086,0.00006825397,0.000056306933,0.0009702721],"category_scores_gemma":[0.00000704901,0.00007377912,0.0001242193,0.00075390027,0.000010271011,0.000039231953,0.000017654458,0.000060744816,0.000006926604],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023462502,0.00029884445,0.0063865846,0.00045504828,0.0049087484,0.00021659699,0.0013667012,0.0649314,0.8405475,0.004612669,0.034109235,0.04214319],"study_design_scores_gemma":[0.00023621418,0.00006136249,0.0025538837,0.000013622658,0.00067211024,0.0000026790806,0.0002566722,0.13974862,0.8480675,0.0004711999,0.0075538903,0.00036223754],"about_ca_topic_score_codex":0.0000051456577,"about_ca_topic_score_gemma":0.000023535455,"teacher_disagreement_score":0.8903265,"about_ca_system_score_codex":0.000036821977,"about_ca_system_score_gemma":0.0000137312745,"threshold_uncertainty_score":0.99994296},"labels":[],"label_agreement":null},{"id":"W4244639180","doi":"10.1145/611823.611824","title":"Hardware-assisted simulated annealing with application for fast FPGA placement","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Netlist; Simulated annealing; Field-programmable gate array; Computer science; Placement; Lookup table; Exploit; Routing (electronic design automation); Parallel computing; Reconfigurable computing; Computer hardware; Embedded system; Physical design; Algorithm; Circuit design","score_opus":0.012069945974130214,"score_gpt":0.22692480863411527,"score_spread":0.21485486265998505,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4244639180","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008558071,0.000045565706,0.97933406,0.000011187702,0.000025029307,0.0006304738,0.0000059416834,0.0010555655,0.010334093],"genre_scores_gemma":[0.97339135,0.000006271499,0.025986856,0.00003825578,0.000014572936,0.00014578046,0.000030833693,0.000034332003,0.0003517562],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994889,0.0000069841117,0.00013283899,0.00012962196,0.00007298862,0.00016864964],"domain_scores_gemma":[0.99970907,0.000026674572,0.00001751176,0.00015600915,0.00004794676,0.000042769487],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008871416,0.00011139633,0.00010438559,0.000047702113,0.000045982673,0.00002131531,0.00005350712,0.000057259884,0.00003117344],"category_scores_gemma":[0.0000059370136,0.00009369475,0.00002492586,0.0001186636,0.000007741932,0.000057163517,0.0000029438609,0.000046188827,0.000008052204],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012966483,0.00018064663,0.001078699,0.00048723817,0.000342784,0.000005402655,0.0005042634,0.668144,0.19468537,0.010827036,0.013364718,0.11025022],"study_design_scores_gemma":[0.0011700179,0.0002089657,0.0001892812,0.000041232655,0.00004272706,0.000008025143,0.00014757266,0.40281314,0.5413576,0.00031241574,0.053230926,0.00047815515],"about_ca_topic_score_codex":0.000005896202,"about_ca_topic_score_gemma":0.0000068844856,"teacher_disagreement_score":0.96483326,"about_ca_system_score_codex":0.00004853555,"about_ca_system_score_gemma":0.000008472288,"threshold_uncertainty_score":0.38207608},"labels":[],"label_agreement":null},{"id":"W4246056576","doi":"10.1109/aspdac.2004.1337686","title":"Interconnect capacitance estimation for FPGAs","year":2005,"lang":"en","type":"article","venue":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Capacitance; Field-programmable gate array; Routing (electronic design automation); Noise (video); Computer science; Dynamic demand; Electronic engineering; CMOS; Bounding overwatch; Interconnection; Power (physics); Embedded system; Engineering; Artificial intelligence; Telecommunications","score_opus":0.025833801124650255,"score_gpt":0.23631121189645632,"score_spread":0.21047741077180607,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4246056576","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019955344,0.00031887222,0.97025454,0.00020274946,0.00061566534,0.0015121746,0.00010741245,0.0019575777,0.0050756843],"genre_scores_gemma":[0.8733476,0.000100865385,0.12452333,0.000077735975,0.00024827072,0.00046526242,0.00009558485,0.00009278658,0.0010485739],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9974059,0.00013574613,0.00080084824,0.00061653054,0.00034361987,0.00069734553],"domain_scores_gemma":[0.99838626,0.00021591186,0.00021869339,0.00053046143,0.00039391406,0.00025476277],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006976083,0.0005946499,0.00057729287,0.00035436504,0.0002605242,0.00030871204,0.00032256826,0.0004191516,0.00016688033],"category_scores_gemma":[0.00020348381,0.0006169266,0.00015333449,0.00030729265,0.0001422488,0.0008599448,0.000012773339,0.0002749666,0.0003958538],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00024622984,0.00036164196,0.00038048482,0.0016784928,0.0005704627,0.00003067535,0.03184591,0.09731288,0.25544563,0.0096548945,0.10707512,0.49539757],"study_design_scores_gemma":[0.0009876029,0.00020455342,0.0001613676,0.00032045314,0.00008833425,0.00003625441,0.000930552,0.95045406,0.041483983,0.0020119117,0.0024007196,0.00092021836],"about_ca_topic_score_codex":0.000010088903,"about_ca_topic_score_gemma":0.000008633577,"teacher_disagreement_score":0.85339224,"about_ca_system_score_codex":0.00025633632,"about_ca_system_score_gemma":0.00015175175,"threshold_uncertainty_score":0.9996282},"labels":[],"label_agreement":null},{"id":"W4246691826","doi":"10.32920/ryerson.14648718","title":"Minimizing the layout area of 2-input look up tables","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Multiplexer; Routing (electronic design automation); Block (permutation group theory); Computer science; Router; Field-programmable gate array; Integrated circuit layout; Benchmark (surveying); Computer hardware; Multiplexing; Embedded system; Computer network; Integrated circuit; Telecommunications; Mathematics","score_opus":0.02525693990355,"score_gpt":0.2258160281992281,"score_spread":0.20055908829567812,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4246691826","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11103073,0.013118046,0.68477505,0.00022708352,0.0025422052,0.0011558473,0.000113707196,0.0031253602,0.183912],"genre_scores_gemma":[0.98388153,0.0007962429,0.012943806,0.00006409378,0.00011207876,0.000074587886,0.000059050937,0.00006319942,0.0020054092],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9990437,0.000029398967,0.0003307573,0.00021949975,0.00017044786,0.00020617583],"domain_scores_gemma":[0.9990793,0.0000849851,0.00005670422,0.000671039,0.000071258044,0.000036741374],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001857865,0.0002470056,0.00037739085,0.00007669112,0.000028209928,0.000077634635,0.00040776774,0.00028204874,0.00042044328],"category_scores_gemma":[0.000026057858,0.00018009388,0.00017514401,0.00008906058,0.000040482846,0.000045698052,0.000342992,0.0004558338,0.0000058032597],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004137767,0.0003199826,0.0047313115,0.011335172,0.0037335115,0.00021449682,0.017930346,0.17222622,0.1833371,0.010225512,0.43789482,0.15801014],"study_design_scores_gemma":[0.0003219435,0.000041729792,0.00050866586,0.0018095389,0.00027462156,0.00003205864,0.0028543626,0.10529692,0.8670783,0.0029710163,0.017370597,0.0014402121],"about_ca_topic_score_codex":0.00014389414,"about_ca_topic_score_gemma":0.000045655168,"teacher_disagreement_score":0.8728508,"about_ca_system_score_codex":0.000037784124,"about_ca_system_score_gemma":0.000048933925,"threshold_uncertainty_score":0.7344015},"labels":[],"label_agreement":null},{"id":"W4246796329","doi":"10.1109/dac.1990.114892","title":"System simulation of printed circuit boards including packages and connectors","year":2002,"lang":"en","type":"article","venue":"27th ACM/IEEE Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Quantic EMC (Canada)","funders":"","keywords":"Printed circuit board; Computer science; Integrated circuit packaging; Circuit extraction; Electronic packaging; Engineering drawing; Electrical engineering; Electronic engineering; Engineering; Integrated circuit; Equivalent circuit; Operating system; Voltage","score_opus":0.10636625896206409,"score_gpt":0.2685288992032618,"score_spread":0.1621626402411977,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4246796329","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11878449,0.00012873921,0.87730736,0.000013632219,0.00014558596,0.00044435315,0.000009921812,0.0015826197,0.0015832888],"genre_scores_gemma":[0.99547285,0.000050420367,0.0043328954,0.000009373499,0.000032517193,0.00004182791,0.0000051610064,0.000030725845,0.000024228188],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.998809,0.00010691299,0.00043480413,0.00021081923,0.00022970092,0.00020879936],"domain_scores_gemma":[0.9989433,0.00034118778,0.00013562826,0.00033124522,0.0001714537,0.000077153156],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000319545,0.0002064692,0.0002954629,0.00021987892,0.00007544811,0.00008348056,0.00020494129,0.00015229234,0.00008623313],"category_scores_gemma":[0.00019289131,0.00021412029,0.000038377322,0.00023513955,0.000050333456,0.00030812953,0.000027204076,0.00012256906,0.000020467061],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000024750778,0.000101525526,0.0021936763,0.002698319,0.00025425415,0.00002270596,0.007217248,0.18299724,0.6469566,0.017915932,0.0018633838,0.13775437],"study_design_scores_gemma":[0.00022197614,0.000055400695,0.0010555292,0.00023621935,0.000022268612,0.000006958368,0.000097862205,0.9047612,0.09280235,0.0004709575,0.000054224547,0.00021507856],"about_ca_topic_score_codex":0.0000072543594,"about_ca_topic_score_gemma":7.906504e-7,"teacher_disagreement_score":0.87668836,"about_ca_system_score_codex":0.00009820629,"about_ca_system_score_gemma":0.0000151749455,"threshold_uncertainty_score":0.8731572},"labels":[],"label_agreement":null},{"id":"W4246960621","doi":"10.1109/iccad.2000.896456","title":"General models for optimum arbitrary-dimension FPGA switch box designs","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Topology (electrical circuits); Network topology; Dimension (graph theory); Path (computing); Mathematics; Combinatorics; Computer network; Embedded system","score_opus":0.048688602633949495,"score_gpt":0.23212504713796064,"score_spread":0.18343644450401114,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4246960621","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007846228,0.0005399788,0.9510179,0.000063420455,0.00012296771,0.0004100713,0.0000067827423,0.0016286834,0.038363926],"genre_scores_gemma":[0.7023117,0.00018490628,0.29398295,0.00025111108,0.0001417362,0.00012517639,0.000009664087,0.00007323656,0.0029195326],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99917275,0.000008877881,0.00019816631,0.00018573034,0.000107110136,0.0003273845],"domain_scores_gemma":[0.9996044,0.00003095269,0.000013774645,0.00022894595,0.00003321689,0.00008871795],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008845192,0.00018075324,0.00017615106,0.00008374939,0.000058313293,0.00003455161,0.00012937325,0.00013461312,0.00025350874],"category_scores_gemma":[0.0000035888404,0.00016696863,0.00009325923,0.000093220406,0.000011959014,0.00023722084,0.000015665975,0.00010452143,0.000042211428],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001897665,0.00013991797,0.000014801558,0.00011267886,0.00011182036,0.000020371064,0.00042110184,0.1884669,0.2625014,0.018248577,0.4797838,0.05015965],"study_design_scores_gemma":[0.00021225003,0.00007085432,0.0000021744586,0.00001036426,0.000011132533,0.0000067371516,0.000005519144,0.8191148,0.17192672,0.006506915,0.0019056051,0.00022694783],"about_ca_topic_score_codex":0.000009190625,"about_ca_topic_score_gemma":0.0000016166784,"teacher_disagreement_score":0.69446546,"about_ca_system_score_codex":0.000038440423,"about_ca_system_score_gemma":0.0000035909695,"threshold_uncertainty_score":0.68087834},"labels":[],"label_agreement":null},{"id":"W4248081385","doi":"10.1109/iccad.1990.129931","title":"A detailed router for field-programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Router; Routing (electronic design automation); Computer science; Interconnection; Routing algorithm; Gate array; Parallel computing; Field (mathematics); Embedded system; Computer network; Routing protocol; Mathematics","score_opus":0.01919086254441044,"score_gpt":0.20655236987145645,"score_spread":0.187361507327046,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4248081385","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003982834,0.00017611307,0.9367209,0.000119074306,0.000105854204,0.00033651871,0.0000018710297,0.0016649468,0.056891907],"genre_scores_gemma":[0.92220813,0.00006884172,0.07136834,0.0002531718,0.00010052047,0.00023414631,0.0000026748562,0.00003418634,0.0057299947],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99955356,0.0000030820472,0.00010346485,0.00008816138,0.00004268049,0.00020904074],"domain_scores_gemma":[0.9997664,0.000029876894,0.0000067052647,0.00014094675,0.000015507172,0.000040528063],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000043369168,0.000087799584,0.00009607242,0.000033639204,0.000026521677,0.000034210403,0.000081557206,0.000066676286,0.00067088235],"category_scores_gemma":[0.0000073902756,0.00007629226,0.000060329832,0.000056043154,0.000004443391,0.00008023212,0.0000067844685,0.000053772732,0.00008308321],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015727834,0.00009538808,0.00074199156,0.0002652441,0.00014912317,0.0000152159655,0.0005949743,0.0010124624,0.028550833,0.0045466293,0.5478176,0.41619483],"study_design_scores_gemma":[0.00065098365,0.0002524884,0.00003197732,0.000025167732,0.000026966773,0.000008834948,0.000030648753,0.54173213,0.25042188,0.0037512865,0.20258132,0.0004863164],"about_ca_topic_score_codex":0.0000029930623,"about_ca_topic_score_gemma":0.00001235271,"teacher_disagreement_score":0.9182253,"about_ca_system_score_codex":0.000011528838,"about_ca_system_score_gemma":7.7757306e-7,"threshold_uncertainty_score":0.73456913},"labels":[],"label_agreement":null},{"id":"W4248168031","doi":"10.1145/611839.611841","title":"Design of FPGA interconnect for multilevel metalization","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Field-programmable gate array; Interconnection; Routing (electronic design automation); Computer science; Exploit; Topology (electrical circuits); Dimension (graph theory); Hierarchy; Scaling; Embedded system; Computer network; Electrical engineering; Engineering; Mathematics","score_opus":0.04161591048762313,"score_gpt":0.24606562240394603,"score_spread":0.20444971191632288,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4248168031","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0004157841,0.00009049108,0.995148,0.0000015434975,0.000057896043,0.00027099825,0.0000020077887,0.000271374,0.003741902],"genre_scores_gemma":[0.81112695,0.000019668241,0.1886,0.00001138261,0.000005249612,0.000047436093,0.0000022141458,0.000016345346,0.00017072927],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996925,0.00001475596,0.00012389812,0.00005636025,0.000032879558,0.00007960402],"domain_scores_gemma":[0.9997939,0.00006505983,0.000011996652,0.00008176968,0.00003207367,0.000015207819],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013998317,0.00006136134,0.000094591596,0.000052314943,0.0000089615605,0.0000050018143,0.00004389319,0.000041354288,0.00007632377],"category_scores_gemma":[0.000051815794,0.000054817378,0.000031126114,0.000047495247,0.000006594352,0.00006137003,0.0000021239227,0.000018013048,0.0000027024953],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019301617,0.00008457867,0.000049480983,0.00036372928,0.0001913598,9.629676e-7,0.00069970416,0.04684823,0.77280265,0.07909931,0.013487904,0.08635281],"study_design_scores_gemma":[0.00013510277,0.0000411754,0.0000048726483,0.000008257904,0.000009825265,0.000001047504,0.00001581243,0.13184017,0.8637488,0.0026725838,0.0014484755,0.00007390571],"about_ca_topic_score_codex":0.0000015396699,"about_ca_topic_score_gemma":4.4939938e-7,"teacher_disagreement_score":0.8107112,"about_ca_system_score_codex":0.000011065688,"about_ca_system_score_gemma":0.0000042911743,"threshold_uncertainty_score":0.22353879},"labels":[],"label_agreement":null},{"id":"W4248286858","doi":"10.1109/n-ssc.2004.6500036","title":"CICC celebrates 26 years of innovation, education, and communication","year":2004,"lang":"en","type":"article","venue":"IEEE Solid-State Circuits Society Newsletter","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Business; Engineering management; Engineering","score_opus":0.011464113626978705,"score_gpt":0.24298867439215224,"score_spread":0.23152456076517353,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4248286858","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9603261,0.0007327944,0.036184847,0.00084572326,0.00022626675,0.0003356052,0.000018189701,0.00061015796,0.00072035985],"genre_scores_gemma":[0.994101,0.00048394146,0.0029486439,0.0021664994,0.00008070092,0.00004375523,0.000027427977,0.000060114973,0.0000879267],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9990598,0.00002016261,0.0004131853,0.00016066879,0.00013812557,0.00020806842],"domain_scores_gemma":[0.9992686,0.00003485087,0.000095604584,0.00035147963,0.00020769796,0.00004177339],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018737055,0.00015240577,0.00018827354,0.00008606053,0.000066535664,0.000046741046,0.0001858659,0.00009803152,0.000013261245],"category_scores_gemma":[0.0000125534925,0.00018139096,0.000056768797,0.0005169205,0.00012165452,0.00025723915,0.000019210147,0.00020949409,0.000016288082],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000014889108,0.00018965093,0.0023859034,0.00038952776,0.00021566084,0.0000017264908,0.017578227,0.0038761501,0.6700446,0.0017549618,0.25219667,0.05136544],"study_design_scores_gemma":[0.0017128745,0.0000861827,0.018241433,0.0004483293,0.00009167928,0.000043563683,0.0010395686,0.0009806418,0.8778252,0.05866174,0.039474346,0.0013944353],"about_ca_topic_score_codex":0.00004480385,"about_ca_topic_score_gemma":0.0000054834154,"teacher_disagreement_score":0.21272232,"about_ca_system_score_codex":0.00008501348,"about_ca_system_score_gemma":0.00007666037,"threshold_uncertainty_score":0.7396909},"labels":[],"label_agreement":null},{"id":"W4249099118","doi":"10.1145/611851.611875","title":"Synthetic circuit generation using clustering and iteration","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Benchmark (surveying); Electronic circuit; Cluster analysis; Computer engineering; Routing (electronic design automation); Path (computing); Netlist; Algorithm; Embedded system; Engineering; Artificial intelligence","score_opus":0.038698831075028556,"score_gpt":0.21956467715342598,"score_spread":0.18086584607839742,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4249099118","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15804212,0.0001322421,0.83349043,0.000001944024,0.00006875187,0.00006229622,2.6294475e-7,0.00023468716,0.007967248],"genre_scores_gemma":[0.9879779,0.00002488081,0.011876078,0.000019481076,0.000030177034,0.0000042502425,0.000001099648,0.000012039316,0.00005408547],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99973637,0.000011344512,0.00007689541,0.00006830181,0.000034714216,0.00007237404],"domain_scores_gemma":[0.9998976,0.0000052749674,0.000005425416,0.00006330406,0.000008503358,0.000019897765],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000069776615,0.000054925218,0.000047034006,0.000040886927,0.000035728986,0.000048452293,0.000013395341,0.00003531499,0.000040175724],"category_scores_gemma":[0.0000063951634,0.000055311826,0.000008578341,0.000037734284,0.0000050671806,0.00011669976,0.0000027530207,0.00002922038,0.0000025240302],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[1.8978176e-7,0.0000035438043,0.00012388595,0.000027400605,0.000006454723,0.0000014808186,0.00016152843,0.008327964,0.97389776,0.0047835377,0.00011328136,0.012552958],"study_design_scores_gemma":[0.000049987768,0.00000838744,0.000026295145,0.000010491795,0.000005659136,0.000032240805,0.00001125696,0.7948695,0.2040077,0.00033661377,0.0005356269,0.00010624404],"about_ca_topic_score_codex":0.0000025313523,"about_ca_topic_score_gemma":0.0000036752908,"teacher_disagreement_score":0.8299358,"about_ca_system_score_codex":0.000021774078,"about_ca_system_score_gemma":0.0000023062005,"threshold_uncertainty_score":0.22555508},"labels":[],"label_agreement":null},{"id":"W4250067423","doi":"10.1145/503049.503052","title":"Circuit design of routing switches","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Computer science; Benchmark (surveying); Very-large-scale integration; Electronic circuit; Transistor; Logic gate; Circuit switching; Logic synthesis; Electronic engineering; Embedded system; Electrical engineering; Computer network; Engineering; Algorithm; Voltage","score_opus":0.053136683840399636,"score_gpt":0.19464615835084725,"score_spread":0.14150947451044762,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4250067423","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030604277,0.00021557022,0.9172256,0.0000049553482,0.000029325727,0.00007447841,4.1873557e-7,0.000866186,0.078523055],"genre_scores_gemma":[0.9916593,0.000052208736,0.007840664,0.00001305073,0.000019651665,0.0000053176973,1.7394238e-7,0.0000142821345,0.0003953841],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99966043,0.000005248271,0.00011776489,0.000052355754,0.000056331442,0.00010788884],"domain_scores_gemma":[0.9998228,0.000030197374,0.000010251694,0.00010526323,0.000010619689,0.00002089351],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000075603806,0.00006013825,0.00008705206,0.000039715487,0.000011150816,0.000006551423,0.00007262981,0.000041652744,0.0004063522],"category_scores_gemma":[0.000009478045,0.000055676224,0.000023771257,0.000079551726,0.000008695925,0.00005301555,0.0000057730917,0.00004599077,0.000038491125],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000013448073,0.000042021322,0.0012330305,0.00012017276,0.000077274,0.000007827735,0.0013274974,0.011549135,0.7846755,0.0074642724,0.034185942,0.15931602],"study_design_scores_gemma":[0.00011022189,0.00004624344,0.00019022722,0.00002994412,0.000009908504,0.0000068902486,0.000049517406,0.30547395,0.6915942,0.0017661292,0.0005181874,0.00020463046],"about_ca_topic_score_codex":0.0000048420993,"about_ca_topic_score_gemma":2.0399884e-7,"teacher_disagreement_score":0.9885988,"about_ca_system_score_codex":0.000016190523,"about_ca_system_score_gemma":0.0000012774016,"threshold_uncertainty_score":0.44492716},"labels":[],"label_agreement":null},{"id":"W4250954305","doi":"10.1109/aspdac.2001.913381","title":"Combinatorial routing analysis and design of universal switch blocks","year":2002,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge; University of Victoria","funders":"","keywords":"Routing (electronic design automation); Block (permutation group theory); Computer science; Set (abstract data type); Decomposition; Dimension (graph theory); Constraint (computer-aided design); Topology (electrical circuits); Parallel computing; Mathematics; Discrete mathematics; Combinatorics; Embedded system","score_opus":0.02423002539524414,"score_gpt":0.2055888944431886,"score_spread":0.18135886904794446,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4250954305","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5620526,0.00015694718,0.412658,0.00020551414,0.000565501,0.0023631712,0.00006672893,0.0013921628,0.020539394],"genre_scores_gemma":[0.97167456,0.00025566947,0.027540525,0.000007714253,0.000062194515,0.000031942112,0.0000044551693,0.000042083997,0.00038085942],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99783504,0.00006599667,0.00070587697,0.00042234184,0.0004570466,0.0005136764],"domain_scores_gemma":[0.9984113,0.00015680096,0.00045882698,0.00024242087,0.0005561665,0.0001744709],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0009393387,0.00041302436,0.0007010357,0.00046659165,0.00019886559,0.00015955158,0.00042824933,0.00030910058,0.00021024449],"category_scores_gemma":[0.00022505035,0.00036330984,0.00014880198,0.0010304577,0.00021186064,0.00044142458,0.00008369166,0.00022281305,0.00001033685],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003314639,0.00059063593,0.042590123,0.0012419093,0.002877196,0.000009857876,0.037938684,0.003676827,0.85572714,0.012239782,0.019972928,0.022803452],"study_design_scores_gemma":[0.00077768817,0.0001967851,0.0024469157,0.00018339866,0.0005815125,0.000012099238,0.0022888589,0.9666524,0.024983935,0.0013472048,0.000043849544,0.00048533396],"about_ca_topic_score_codex":0.00002788285,"about_ca_topic_score_gemma":6.587978e-7,"teacher_disagreement_score":0.96297556,"about_ca_system_score_codex":0.00007633754,"about_ca_system_score_gemma":0.00004649961,"threshold_uncertainty_score":0.99988186},"labels":[],"label_agreement":null},{"id":"W4251343752","doi":"10.1109/eurdac.1992.246230","title":"Routing algorithms for multi-chip modules","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Static routing; Routing (electronic design automation); Link-state routing protocol; Equal-cost multi-path routing; Policy-based routing; Placement; Multipath routing; Dynamic Source Routing; Destination-Sequenced Distance Vector routing; Algorithm; Channel (broadcasting); Distributed computing; Computer network; Physical design; Routing protocol; Embedded system; Circuit design","score_opus":0.09028723337086844,"score_gpt":0.26703503960550923,"score_spread":0.1767478062346408,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4251343752","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004865196,0.00011657502,0.96695733,0.000029567324,0.00022669029,0.0010562787,0.000013648281,0.004125399,0.022609318],"genre_scores_gemma":[0.6970292,0.00006620241,0.30213398,0.0000681003,0.00009829121,0.000099299374,0.000011084635,0.00015274754,0.00034111852],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9977682,0.00010916606,0.0006575508,0.000558199,0.00029278058,0.00061408663],"domain_scores_gemma":[0.9988188,0.00011488458,0.00020547744,0.00021381781,0.00046526603,0.00018176815],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0013830992,0.00047593506,0.0003530021,0.00025194188,0.00025510223,0.00044292372,0.00045510713,0.000112161615,0.000048692014],"category_scores_gemma":[0.0006581701,0.00050351786,0.00011537898,0.00035029426,0.00006469727,0.0006432746,0.00004424214,0.00029335855,0.00015153381],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000054195392,0.00033683635,0.001086227,0.0013370252,0.0002506475,0.00003624826,0.0062260036,0.002768036,0.6313299,0.08424545,0.026333986,0.24599546],"study_design_scores_gemma":[0.00081853283,0.00015366993,0.0012446663,0.00021186241,0.000047058147,0.000039909028,0.00016588293,0.857233,0.13344747,0.001254344,0.004583997,0.0007996366],"about_ca_topic_score_codex":0.0000013204613,"about_ca_topic_score_gemma":1.7167099e-7,"teacher_disagreement_score":0.85446495,"about_ca_system_score_codex":0.00008525833,"about_ca_system_score_gemma":0.000037529004,"threshold_uncertainty_score":0.9997417},"labels":[],"label_agreement":null},{"id":"W4251855355","doi":"10.1109/aspdac.2010.5419880","title":"A performance-constrained template-based layout retargeting algorithm for analog integrated circuits","year":2010,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Retargeting; Parasitic extraction; Computer science; Integrated circuit layout; Algorithm; Set (abstract data type); Analogue electronics; Integer programming; Standard cell; Electronic circuit; IC layout editor; Design layout record; Circuit extraction; Integrated circuit; Electronic engineering; Engineering; Artificial intelligence; Equivalent circuit","score_opus":0.011369565169900932,"score_gpt":0.21241767457492255,"score_spread":0.20104810940502163,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4251855355","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11466255,0.000018403762,0.86649907,0.000025381736,0.00054732437,0.000513709,0.000054757846,0.0025016537,0.015177182],"genre_scores_gemma":[0.87298876,0.000003314316,0.12642974,0.000059455844,0.0001655479,0.00009272451,0.00007838934,0.000043406355,0.00013863221],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99913985,0.000007985053,0.0002505593,0.00017675487,0.000092076196,0.00033275355],"domain_scores_gemma":[0.99953187,0.00006872929,0.000027435663,0.00019518401,0.00009145263,0.000085357606],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00028062327,0.00019358797,0.00019977946,0.00014757698,0.00008180549,0.000044499335,0.00015958589,0.00018568599,0.00022358054],"category_scores_gemma":[0.000033002718,0.00016975288,0.000082222745,0.00018890663,0.000041866482,0.00012484661,0.000007096,0.00030345135,0.000017945515],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000054700417,0.000035457808,0.001735377,0.00013411665,0.00006256681,0.0000052635974,0.000104251696,0.0005277637,0.20380028,0.00018850132,0.007530932,0.78587],"study_design_scores_gemma":[0.0003757953,0.00007462465,0.00018849073,0.000025820074,0.000013832192,0.000007078137,0.000024043393,0.8537536,0.14027685,0.000064901695,0.004930933,0.00026400405],"about_ca_topic_score_codex":0.000014080312,"about_ca_topic_score_gemma":0.000015737687,"teacher_disagreement_score":0.8532259,"about_ca_system_score_codex":0.000024127055,"about_ca_system_score_gemma":0.00003944817,"threshold_uncertainty_score":0.69223213},"labels":[],"label_agreement":null},{"id":"W4254348042","doi":"10.1109/aspdac.2003.1195042","title":"On improving FPGA routability applying multi-level switch boxes","year":2003,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria; University of Lethbridge","funders":"","keywords":"Field-programmable gate array; Routing (electronic design automation); Computer science; Kernel (algebra); Embedded system; Extension (predicate logic); Placement; Parallel computing; Computer hardware; Physical design; Mathematics; Circuit design","score_opus":0.03508341948293945,"score_gpt":0.22141111134759192,"score_spread":0.18632769186465248,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4254348042","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18880154,0.00021026054,0.76831496,0.00004591031,0.0005020704,0.0031837143,0.000052916228,0.0017741633,0.03711444],"genre_scores_gemma":[0.9663461,0.000017986842,0.03302439,0.000014803821,0.00001984334,0.00019791248,0.0000022951026,0.000044321907,0.00033238987],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9983051,0.00004452369,0.0005325043,0.0003846279,0.0003457733,0.00038747347],"domain_scores_gemma":[0.9988968,0.00005804771,0.00024345062,0.00022018579,0.00047075367,0.000110806104],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008900506,0.0003602799,0.0003931412,0.00018456919,0.00024725715,0.00018821377,0.00029433818,0.00023016748,0.00003781411],"category_scores_gemma":[0.0005571555,0.0002866677,0.00007836799,0.0005937643,0.00012301693,0.000347487,0.000036236797,0.00031903526,0.000012435057],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002109701,0.000751811,0.026654368,0.003826692,0.00057119195,0.00000435108,0.04027015,0.0014843774,0.48808083,0.21352059,0.0084797125,0.21614496],"study_design_scores_gemma":[0.0021238427,0.00034787966,0.018534862,0.0007446321,0.00020773831,0.00004042708,0.012331031,0.44535458,0.50445,0.013404959,0.00070110185,0.0017589191],"about_ca_topic_score_codex":0.000004190313,"about_ca_topic_score_gemma":3.8836853e-7,"teacher_disagreement_score":0.7775445,"about_ca_system_score_codex":0.0000684715,"about_ca_system_score_gemma":0.00008101975,"threshold_uncertainty_score":0.9999586},"labels":[],"label_agreement":null},{"id":"W4254745643","doi":"10.1145/512195.512197","title":"Finding shortest paths in large network systems","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Dijkstra's algorithm; Suurballe's algorithm; Shortest path problem; Computer science; Pathfinding; Yen's algorithm; Floyd–Warshall algorithm; Shortest Path Faster Algorithm; K shortest path routing; Graph; A* search algorithm; Algorithm; Scalability; Average path length; Theoretical computer science","score_opus":0.01381417334087049,"score_gpt":0.21817233968009103,"score_spread":0.20435816633922055,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4254745643","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17299226,0.0027373543,0.4799739,0.000023381665,0.0008957432,0.00055961864,0.0000054510438,0.0036871282,0.33912516],"genre_scores_gemma":[0.9985185,0.00017405402,0.00058331096,0.000022988663,0.00015431625,0.000027760918,0.0000039788843,0.000020899248,0.0004941583],"study_design_codex":"observational","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993982,0.00001053444,0.00015223431,0.00008397146,0.000061071805,0.00029403172],"domain_scores_gemma":[0.9998068,0.000024380635,0.0000070945525,0.00012042952,0.000006259034,0.000035012603],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001859647,0.000085580825,0.00011747977,0.00005723288,0.000021084084,0.00002813212,0.00007690095,0.00007317089,0.00009266758],"category_scores_gemma":[0.000004272762,0.000080903636,0.0000210068,0.0002151094,0.0000031825525,0.00007509631,0.000012402719,0.000103301056,0.000042260515],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008540859,0.00012026524,0.65202266,0.00016254274,0.00006170455,0.00062584353,0.000528414,0.14913167,0.004349867,0.03276767,0.13874874,0.021472113],"study_design_scores_gemma":[0.0005234788,0.00006906429,0.025657162,0.00033954505,0.000011746766,0.0000849874,0.0002590558,0.85585815,0.0010186182,0.00093082467,0.11440305,0.00084434194],"about_ca_topic_score_codex":0.00002508249,"about_ca_topic_score_gemma":0.000054592594,"teacher_disagreement_score":0.8255263,"about_ca_system_score_codex":0.000039688228,"about_ca_system_score_gemma":0.0000027502265,"threshold_uncertainty_score":0.32991546},"labels":[],"label_agreement":null},{"id":"W4255023136","doi":"10.32920/ryerson.14647368","title":"Parallel Implementation of Non-slicing Floorplans with MPI and OpenMP","year":2021,"lang":"en","type":"preprint","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Parallel computing; Computer science; Floorplan; Benchmark (surveying); Multiprocessing; Very-large-scale integration; Slicing; Computation; Computer architecture; Embedded system; Algorithm","score_opus":0.010706930939589066,"score_gpt":0.259707047487965,"score_spread":0.24900011654837595,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4255023136","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4028732,0.00022323221,0.59005404,0.000022477196,0.000061966435,0.0004389082,0.000020171605,0.0002618577,0.0060441964],"genre_scores_gemma":[0.93623596,0.0003815775,0.06312427,0.000018703038,0.000024400568,0.000056440178,0.00008181323,0.000029147785,0.000047704918],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9994,0.000009562243,0.00020342493,0.00017251057,0.000095294025,0.000119169876],"domain_scores_gemma":[0.9996751,0.000012447771,0.000039555096,0.00020301854,0.000036419435,0.000033467888],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000079108795,0.00016009818,0.00025368104,0.00007031418,0.000014713018,0.000047883364,0.000088309636,0.00010687545,0.00012089645],"category_scores_gemma":[8.769269e-7,0.00013999217,0.000028346154,0.00004794261,0.000013264532,0.00006506019,0.00011022229,0.00017305155,7.326673e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001049391,0.0002105228,0.11373119,0.017506234,0.0037813475,0.00029561933,0.029868152,0.12576403,0.3144097,0.0024899088,0.02326562,0.36857274],"study_design_scores_gemma":[0.002340202,0.00043281403,0.072398715,0.002003509,0.0004180039,0.0000860083,0.0098429285,0.07170837,0.8372565,0.0006634175,0.00060706795,0.0022424958],"about_ca_topic_score_codex":0.00068245817,"about_ca_topic_score_gemma":0.00043584267,"teacher_disagreement_score":0.53336275,"about_ca_system_score_codex":0.000021608503,"about_ca_system_score_gemma":0.000029057332,"threshold_uncertainty_score":0.57087153},"labels":[],"label_agreement":null},{"id":"W4255752943","doi":"10.1007/978-1-4419-0739-4_2","title":"Background","year":2010,"lang":"en","type":"book-chapter","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Application-specific integrated circuit; Computer science; Computer architecture; FPGA prototype; Transistor; Electronic engineering; Embedded system; Engineering; Electrical engineering","score_opus":0.018988971257094617,"score_gpt":0.20589156790583954,"score_spread":0.18690259664874492,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4255752943","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0000028675233,0.00023585765,0.015059489,0.000006379887,0.000276857,0.000085883636,0.0000067828364,0.00162004,0.98270583],"genre_scores_gemma":[0.00087773794,0.0002863218,0.006751642,0.000052430743,0.00027677146,0.000005399276,0.000017156179,0.00011042708,0.9916221],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"not_applicable","domain_scores_codex":[0.99959403,5.347705e-7,0.00011653378,0.00010424848,0.000078620986,0.00010603493],"domain_scores_gemma":[0.9996652,0.000011463885,0.000011307512,0.00025258402,0.000015118054,0.00004432984],"candidate_categories":["insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.000030841136,0.00018786202,0.00016014252,0.00006818947,0.000014448041,0.000022878125,0.00011935194,0.00049220916,0.005818995],"category_scores_gemma":[5.293383e-7,0.00017565813,0.000071535265,0.0000048578336,0.000022874621,0.00003302791,0.000016358124,0.0004590641,0.0010676443],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[9.7726e-7,0.0000029038772,5.432126e-7,0.00010831067,0.0000909716,0.0000330341,0.000016628675,0.0000024853985,0.008990994,0.81154686,0.13062856,0.048577733],"study_design_scores_gemma":[0.000022160382,0.000009313686,8.147448e-7,0.000021579754,0.000011188308,0.000007942831,4.2649074e-7,0.000047061858,0.004037754,0.036291108,0.95930207,0.00024861025],"about_ca_topic_score_codex":0.0000016597907,"about_ca_topic_score_gemma":0.000010457145,"teacher_disagreement_score":0.8286735,"about_ca_system_score_codex":0.000019643343,"about_ca_system_score_gemma":0.000005617318,"threshold_uncertainty_score":0.99971014},"labels":[],"label_agreement":null},{"id":"W4255840877","doi":"10.1109/dac.1992.227805","title":"An efficient algorithm for microword length minimization","year":2003,"lang":"en","type":"article","venue":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Minification; Computer science; Graph; Algorithm; Mathematical optimization; Theoretical computer science; Mathematics; Programming language","score_opus":0.03351824797113805,"score_gpt":0.2569164784611113,"score_spread":0.22339823048997326,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4255840877","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009613523,0.00006327283,0.98417944,0.00004018261,0.0003097357,0.0015055704,0.000028204842,0.0026678958,0.001592188],"genre_scores_gemma":[0.6367944,0.000033415727,0.36246774,0.000057343794,0.00008495991,0.00041048077,0.000035039673,0.00007556303,0.000041075185],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99795765,0.00004171027,0.00057606737,0.00052667747,0.00033245762,0.0005654276],"domain_scores_gemma":[0.9987254,0.00012453395,0.00018397401,0.000306975,0.00045952538,0.00019957665],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00066121254,0.0004306533,0.00036343353,0.0003186098,0.00021916885,0.0003612007,0.0005056009,0.00030228822,0.000069973874],"category_scores_gemma":[0.00020266512,0.00046327058,0.00008729693,0.00036441817,0.00006053518,0.0006017502,0.000014886003,0.00020631445,0.000034736648],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005558741,0.00045051478,0.00012331412,0.00075851654,0.0001584311,0.000005065037,0.0039553232,0.017955426,0.5652549,0.031951416,0.022533866,0.3567976],"study_design_scores_gemma":[0.00044655456,0.000186862,0.00005137483,0.00007479499,0.000035482695,0.000015331505,0.00012924864,0.71406454,0.28059053,0.002305068,0.0016384429,0.0004617618],"about_ca_topic_score_codex":0.000004917175,"about_ca_topic_score_gemma":8.808803e-7,"teacher_disagreement_score":0.6961091,"about_ca_system_score_codex":0.0001638667,"about_ca_system_score_gemma":0.00011382409,"threshold_uncertainty_score":0.9997819},"labels":[],"label_agreement":null},{"id":"W4256228596","doi":"10.1109/isocc.2018.8649963","title":"ISOCC 2018 Front Matter","year":2018,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Samsung; University of Tokushima; Polytechnique Montréal","keywords":"Front (military); Computer science; Geology; Oceanography","score_opus":0.007659060495802687,"score_gpt":0.20087769663575777,"score_spread":0.19321863613995507,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4256228596","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007208283,0.000061971456,0.27511066,0.00007663262,0.00025116155,0.00006421679,0.0000016228248,0.0011581623,0.71606725],"genre_scores_gemma":[0.9713379,0.000011089349,0.014073998,0.00062456063,0.00029990764,0.000010446092,0.0000013226442,0.00002517299,0.013615576],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9997179,0.0000028297127,0.00006369359,0.000058599762,0.000040843915,0.0001161378],"domain_scores_gemma":[0.9998209,0.0000041597405,0.0000033159724,0.00013428654,0.000010803062,0.000026548138],"candidate_categories":["insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.000030750405,0.00005789481,0.00005313721,0.000025773545,0.0000168251,0.000013919387,0.00006761664,0.00004167023,0.010187061],"category_scores_gemma":[8.897201e-7,0.000048503225,0.000018689063,0.00002221339,0.000020786221,0.000056387304,0.000010720916,0.000035852714,0.012051505],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[5.4617414e-7,0.0000030356314,0.00051977794,0.000005023096,0.0000066095527,6.6624426e-7,0.000059662067,9.90942e-7,0.008107944,0.000120306875,0.9882003,0.0029751179],"study_design_scores_gemma":[0.00015930943,0.00010080362,0.0054822466,0.000018974019,0.000010133774,0.000010361407,0.000029793942,0.006950846,0.3843222,0.0028073967,0.5996927,0.0004152613],"about_ca_topic_score_codex":0.000012851654,"about_ca_topic_score_gemma":0.000006967193,"teacher_disagreement_score":0.9641296,"about_ca_system_score_codex":0.000014215953,"about_ca_system_score_gemma":0.000001414574,"threshold_uncertainty_score":0.99071777},"labels":[],"label_agreement":null},{"id":"W4256429711","doi":"10.1109/date.2007.364599","title":"A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs","year":2007,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Correctness; Symbolic computation; Symbolic trajectory evaluation; Computer science; Representation (politics); Set (abstract data type); Computation; SIGNAL (programming language); Theoretical computer science; Mixed-signal integrated circuit; Symbolic data analysis; Algebra over a field; Algorithm; Programming language; Mathematics; Integrated circuit; Model checking","score_opus":0.10975798568040666,"score_gpt":0.3126082362462768,"score_spread":0.20285025056587014,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4256429711","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022240046,0.00035043864,0.97616744,0.00002257336,0.000031461812,0.00019307277,0.0000019193558,0.00011893193,0.0008741398],"genre_scores_gemma":[0.90518564,0.000052775176,0.09466208,0.000020540452,0.000023152323,0.000019805337,0.0000015078725,0.000008199834,0.000026273254],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996676,0.000020732507,0.00012304402,0.00005810921,0.000031248528,0.000099270306],"domain_scores_gemma":[0.99920106,0.00065046555,0.000015803864,0.000090166686,0.000024504514,0.000018005943],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0007613419,0.00005063518,0.00009134147,0.00005069673,0.000022770486,0.0000041144417,0.000060133298,0.000055006854,0.00001418063],"category_scores_gemma":[0.000028007846,0.000035232122,0.000024246847,0.00007051139,0.00003206126,0.000023203234,0.000004864949,0.00003595618,5.0539626e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022852098,0.000009199597,0.00028813008,0.000049012106,0.00005257571,3.3351242e-7,0.00029498123,0.00012972894,0.8101977,0.020701762,0.0013236883,0.16693003],"study_design_scores_gemma":[0.0001182917,0.00007502944,0.0061553707,0.000003745421,0.00002786388,0.000004768226,0.00012165517,0.009678791,0.9786556,0.0039908797,0.0010971971,0.00007083398],"about_ca_topic_score_codex":0.000012586828,"about_ca_topic_score_gemma":0.00000975009,"teacher_disagreement_score":0.8829456,"about_ca_system_score_codex":0.000006692531,"about_ca_system_score_gemma":0.0000034396853,"threshold_uncertainty_score":0.14367242},"labels":[],"label_agreement":null},{"id":"W4280548669","doi":"10.1016/j.micpro.2022.104563","title":"Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs","year":2022,"lang":"en","type":"article","venue":"Microprocessors and Microsystems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Computer science; Field-programmable gate array; Block (permutation group theory); Flexibility (engineering); Routing (electronic design automation); Logic block; Metric (unit); Floorplan; Computer hardware; Embedded system; Engineering; Mathematics","score_opus":0.01238930526602027,"score_gpt":0.19411208806279728,"score_spread":0.181722782796777,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4280548669","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.99386287,0.0037104296,0.00096262887,0.000057560403,0.00008303526,0.0010059833,0.00016193817,0.00006472722,0.000090801346],"genre_scores_gemma":[0.999467,0.0000397585,0.000029998657,0.000029091725,0.000023792878,0.00031142076,0.000006523967,0.00003338975,0.00005900315],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99912107,0.00005617369,0.00028688138,0.00017968868,0.00016441151,0.00019179564],"domain_scores_gemma":[0.99937856,0.00023422045,0.000105876294,0.00020882279,0.000045478286,0.000027063774],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0008173164,0.00019140042,0.00031654883,0.000055842953,0.00022635427,0.00003218694,0.00018844963,0.000051919855,0.0000067249325],"category_scores_gemma":[0.000011381757,0.00011328114,0.0000713427,0.00010709954,0.00006093903,0.000022085183,0.00003487826,0.00016119871,1.7211929e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001463526,0.000036791982,0.001181447,0.0020770065,0.000087803965,0.0000013767772,0.0014962852,0.0023366574,0.98776263,0.00002351527,0.0016284438,0.0032217142],"study_design_scores_gemma":[0.0007819239,0.0005560493,0.00006171954,0.00024855346,0.00006342837,0.000020701576,0.00047641853,0.0069908085,0.98601824,0.000011988052,0.004606567,0.00016358985],"about_ca_topic_score_codex":0.000056948862,"about_ca_topic_score_gemma":0.000009936057,"teacher_disagreement_score":0.0056041246,"about_ca_system_score_codex":0.00004337594,"about_ca_system_score_gemma":0.0000164191,"threshold_uncertainty_score":0.46194705},"labels":[],"label_agreement":null},{"id":"W4280560843","doi":"10.23919/date54114.2022.9774530","title":"CR&amp;P: An Efficient Co-operation between Routing and Placement","year":2022,"lang":"en","type":"article","venue":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Routing (electronic design automation); Physical design; Electronic design automation; Placement; Design flow; CONTEST; Network routing; Place and route; Integer programming; Distributed computing; Embedded system; Circuit design; Algorithm","score_opus":0.0573484131648651,"score_gpt":0.2814321515290119,"score_spread":0.2240837383641468,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4280560843","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3298905,0.000092222275,0.6645416,0.00012631611,0.00018982845,0.0011721834,0.0002471959,0.0017466464,0.0019935288],"genre_scores_gemma":[0.97055525,0.00011699425,0.023349589,0.00015603336,0.00013019299,0.00040411772,0.0042383927,0.00012457614,0.0009248402],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9959372,0.00088166294,0.0010548632,0.00077126786,0.0007629264,0.0005920577],"domain_scores_gemma":[0.99824303,0.00036795318,0.0002679785,0.0006899538,0.00021667797,0.0002143831],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0020410267,0.0005139663,0.00047393443,0.0006071466,0.00061383686,0.00043580157,0.0003790775,0.00015699738,0.0024183798],"category_scores_gemma":[0.00032604823,0.00059865654,0.000058488513,0.0007966098,0.000087730754,0.0004917633,0.0001731299,0.00067756686,0.00053512934],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009462949,0.00088984973,0.0076300236,0.00034875842,0.00009417554,0.000021339763,0.011201814,0.35791785,0.57527536,0.0028344314,0.022407891,0.021283895],"study_design_scores_gemma":[0.0053947433,0.0011551534,0.045034956,0.0007596525,0.00029169026,0.00026066857,0.0010029073,0.49102983,0.032811332,0.0013728288,0.41512665,0.005759592],"about_ca_topic_score_codex":0.00006164372,"about_ca_topic_score_gemma":0.00011704692,"teacher_disagreement_score":0.64119196,"about_ca_system_score_codex":0.00030397138,"about_ca_system_score_gemma":0.00013536647,"threshold_uncertainty_score":0.9996465},"labels":[],"label_agreement":null},{"id":"W4280571518","doi":"10.23919/date54114.2022.9774699","title":"Deep Reinforcement Learning for Analog Circuit Structure Synthesis","year":2022,"lang":"en","type":"article","venue":"2022 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Canada Foundation for Innovation","keywords":"Computer science; Reinforcement learning; Construct (python library); Set (abstract data type); Reliability (semiconductor); Circuit extraction; Circuit design; Computer engineering; Artificial intelligence; Equivalent circuit; Engineering; Electrical engineering; Embedded system; Programming language; Voltage","score_opus":0.04201048525884097,"score_gpt":0.2475071451572473,"score_spread":0.20549665989840635,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4280571518","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013385584,0.00013024466,0.979427,0.000098478806,0.00028213818,0.0013708475,0.00009960188,0.0019454155,0.0032607082],"genre_scores_gemma":[0.97547007,0.00018608,0.018566208,0.00016737168,0.000100907375,0.0010960747,0.002252223,0.00015102518,0.002010034],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99659395,0.00052727514,0.0009604511,0.00064484845,0.0006368744,0.0006365891],"domain_scores_gemma":[0.9978743,0.00069286505,0.00031394916,0.0006359187,0.00033602782,0.0001469141],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0010837372,0.00050256576,0.0004972705,0.0007100452,0.0005344978,0.00025237686,0.0005210989,0.00017413887,0.006495759],"category_scores_gemma":[0.001198612,0.000587519,0.00011803188,0.0012224922,0.00006527184,0.00049739255,0.00014194638,0.0007468599,0.0002576052],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000046983714,0.00013165834,0.00054075656,0.0003057933,0.00007184317,0.000011407326,0.0019081277,0.6684227,0.2914398,0.002855493,0.016952025,0.017313411],"study_design_scores_gemma":[0.0016898119,0.0004248298,0.0035605652,0.00041526725,0.00019964084,0.0001565121,0.00032168478,0.55132735,0.024751477,0.0053244038,0.40904865,0.0027798167],"about_ca_topic_score_codex":0.000029783592,"about_ca_topic_score_gemma":0.00009941007,"teacher_disagreement_score":0.9620845,"about_ca_system_score_codex":0.00031538756,"about_ca_system_score_gemma":0.00012841827,"threshold_uncertainty_score":0.99965763},"labels":[],"label_agreement":null},{"id":"W4282036953","doi":"10.1109/fccm53951.2022.9786176","title":"Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm","year":2022,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Block (permutation group theory); Computer science; Tile; Dimension (graph theory); Embedded system; Materials science","score_opus":0.11993569619568333,"score_gpt":0.35602898393206084,"score_spread":0.2360932877363775,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4282036953","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9832428,0.0000382517,0.01515733,0.000036401703,0.000037014343,0.0007100197,0.00006435399,0.00008362756,0.00063017197],"genre_scores_gemma":[0.99807733,9.987948e-7,0.0016978015,0.000031479733,0.0000135682685,0.00012475712,0.0000069279404,0.000026838507,0.000020300242],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999091,0.0000770514,0.0002969075,0.00011144605,0.00022527088,0.00019829828],"domain_scores_gemma":[0.998897,0.0006864037,0.00007762456,0.00028169763,0.000039445553,0.000017791717],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00096813,0.00013590009,0.00020377885,0.00011309345,0.00008341554,0.000008922386,0.00023189618,0.000037957943,0.00022735547],"category_scores_gemma":[0.00013570896,0.000079461955,0.0001806094,0.00023993965,0.00002623058,0.000029864279,0.000038742757,0.00019324048,2.5897867e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000442078,0.00004377827,0.0022147351,0.000018247021,0.000035254507,4.3248806e-7,0.00031726144,0.8681112,0.12731054,0.000041862364,0.00025087883,0.0016116227],"study_design_scores_gemma":[0.00043166365,0.00033815275,0.0006291928,0.00002566701,0.000017846356,0.0000013165564,0.00024909427,0.93399984,0.06407622,0.00013021445,0.00000933613,0.00009144094],"about_ca_topic_score_codex":0.00036903255,"about_ca_topic_score_gemma":0.000022428301,"teacher_disagreement_score":0.06588869,"about_ca_system_score_codex":0.00011913902,"about_ca_system_score_gemma":0.000060170565,"threshold_uncertainty_score":0.32403645},"labels":[],"label_agreement":null},{"id":"W4283687422","doi":"10.1109/isqed54688.2022.9806228","title":"Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network","year":2022,"lang":"en","type":"article","venue":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Routing (electronic design automation); Computer science; Artificial neural network; Estimation; Computer network; Embedded system; Real-time computing; Artificial intelligence; Engineering; Systems engineering","score_opus":0.019961367447600555,"score_gpt":0.27823394752510594,"score_spread":0.25827258007750536,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4283687422","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20059517,0.00021153275,0.79162145,0.00054155005,0.0010723585,0.0014217332,0.00010176619,0.0016194863,0.0028149805],"genre_scores_gemma":[0.9913207,0.000025452639,0.007475168,0.00025595087,0.00025824274,0.00033207898,0.00019387434,0.00006906112,0.0000694351],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9961808,0.0008182995,0.0006963789,0.0005687054,0.0009771165,0.00075875653],"domain_scores_gemma":[0.99885523,0.00028080415,0.00025815846,0.00037638174,0.0001276523,0.00010175342],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0016796205,0.0004033038,0.0004251276,0.0001026251,0.0004205909,0.00014575994,0.0005479829,0.00011000414,0.0003138734],"category_scores_gemma":[0.000063007996,0.0004311472,0.00015221335,0.00055090553,0.000060129056,0.0003568557,0.000119400065,0.00076059473,0.000012643548],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00064405287,0.00011164735,0.00085631985,0.000017912078,0.00019891899,0.000009301595,0.00013349215,0.9753351,0.0061707697,0.012262512,0.0004808983,0.0037790374],"study_design_scores_gemma":[0.0012395888,0.00056029327,0.00040162037,0.00003483555,0.00006968816,0.000087473796,0.000051099418,0.99318963,0.000876832,0.002229768,0.0007331857,0.00052598055],"about_ca_topic_score_codex":0.00015417398,"about_ca_topic_score_gemma":0.000029306388,"teacher_disagreement_score":0.7907256,"about_ca_system_score_codex":0.00364565,"about_ca_system_score_gemma":0.00018101094,"threshold_uncertainty_score":0.99981403},"labels":[],"label_agreement":null},{"id":"W4283701272","doi":"10.1109/isqed54688.2022.9806266","title":"Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits","year":2022,"lang":"en","type":"article","venue":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Canada Foundation for Innovation","keywords":"Process variation; Carbon nanotube field-effect transistor; Computer science; Electronic circuit; Sizing; Robustness (evolution); Electronic engineering; Analogue electronics; Transistor; Process (computing); Field-effect transistor; Engineering; Electrical engineering; Voltage","score_opus":0.030396991637106973,"score_gpt":0.28997532716396696,"score_spread":0.25957833552686,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4283701272","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0037130604,0.00034155976,0.98771715,0.0006489504,0.0013300724,0.0015557157,0.00046364262,0.0011375333,0.0030923404],"genre_scores_gemma":[0.9938607,0.00014062216,0.0016505818,0.0005713375,0.00031244807,0.0019763608,0.0004098596,0.000116387746,0.0009616843],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99681276,0.00041571583,0.0006608068,0.00062483083,0.00077142613,0.00071447453],"domain_scores_gemma":[0.99849766,0.00061687664,0.00019891202,0.0003837969,0.00020415355,0.000098613324],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017464058,0.00037995385,0.00037817954,0.0002988032,0.000420426,0.000106581254,0.00077406503,0.00012595255,0.0005688341],"category_scores_gemma":[0.00011323578,0.00045547858,0.00026836924,0.0004094591,0.0000312026,0.000267059,0.000100905076,0.00070602825,0.000028537983],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005925207,0.0013577022,0.00041805365,0.00018044357,0.0021858967,0.000025774852,0.0035585782,0.23618065,0.6018894,0.113526136,0.0229233,0.017161543],"study_design_scores_gemma":[0.005450164,0.0033542917,0.002818479,0.00008238829,0.00021793286,0.00008854417,0.000740239,0.8024478,0.08503715,0.025727851,0.07102681,0.0030083307],"about_ca_topic_score_codex":0.00007836403,"about_ca_topic_score_gemma":0.00002200819,"teacher_disagreement_score":0.99014765,"about_ca_system_score_codex":0.002257872,"about_ca_system_score_gemma":0.00018852297,"threshold_uncertainty_score":0.9997897},"labels":[],"label_agreement":null},{"id":"W4285346953","doi":"10.1109/rsp53691.2021.9806205","title":"Heterogeneous Logic Implementation for Adders in VTR","year":2021,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Adder; Verilog; Computer science; Field-programmable gate array; Logic block; Routing (electronic design automation); Block (permutation group theory); Computer architecture; Logic synthesis; Scheme (mathematics); Parallel computing; Logic gate; Critical path method; Design flow; Computer hardware; Embedded system; Engineering; Algorithm","score_opus":0.021583703447223393,"score_gpt":0.28815596696771595,"score_spread":0.26657226352049257,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4285346953","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.119211815,0.00055565126,0.8676772,0.00015162776,0.00017933905,0.00051644683,0.000019352316,0.00093983265,0.010748727],"genre_scores_gemma":[0.9859986,0.000041384083,0.013635642,0.00013190655,0.000016619584,0.000066188215,0.000026370846,0.000010254288,0.000073075935],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999726,0.0000045511674,0.00008367048,0.00006143837,0.00002582,0.0000985109],"domain_scores_gemma":[0.9999026,0.000013526546,0.0000038742187,0.0000554521,0.000011569508,0.000012989522],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000032505697,0.000042292373,0.000050567145,0.000028372402,0.000007991615,0.0000104269875,0.00002484306,0.000025754707,0.00027028305],"category_scores_gemma":[0.000002929791,0.000043071494,0.000022938444,0.000053314943,0.000002278458,0.000031668107,0.000004926058,0.000020497499,0.000004716168],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011688082,0.000080753714,0.0034242263,0.00029215866,0.00009961943,0.00011570643,0.0007734012,0.011678537,0.3667718,0.013568614,0.055075925,0.54810756],"study_design_scores_gemma":[0.00039947493,0.00004334751,0.00034357817,0.000006669934,0.000005730761,0.000012310748,0.00035345802,0.012182288,0.97404695,0.0066005653,0.005827178,0.00017846865],"about_ca_topic_score_codex":0.000007723597,"about_ca_topic_score_gemma":0.00017670119,"teacher_disagreement_score":0.8667867,"about_ca_system_score_codex":0.000022239723,"about_ca_system_score_gemma":0.000005346685,"threshold_uncertainty_score":0.29594097},"labels":[],"label_agreement":null},{"id":"W4287236889","doi":"10.48550/arxiv.2104.03546","title":"Graph Partitioning and Sparse Matrix Ordering using Reinforcement\\n Learning and Graph Neural Networks","year":2021,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Computer science; Dense graph; Reinforcement learning; Sparse matrix; Adjacency matrix; Graph; Algorithm; Theoretical computer science; Combinatorics; Artificial intelligence; Mathematics; Line graph; Pathwidth","score_opus":0.04123634730311696,"score_gpt":0.18606070754357898,"score_spread":0.14482436024046202,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4287236889","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.52759695,0.00089135236,0.47057113,0.0000016204382,0.00013323265,0.00012930951,0.0000010052947,0.00040565932,0.0002697628],"genre_scores_gemma":[0.99586236,0.002867996,0.0010478089,0.0000116397605,0.000061650404,0.0000013485347,0.000025630841,0.00005040376,0.00007117901],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988246,0.00006130142,0.00020482799,0.000500591,0.00004998697,0.00035870448],"domain_scores_gemma":[0.9994486,0.000041967123,0.00009439176,0.00023669003,0.000052266834,0.00012607117],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0001407995,0.0003310819,0.00033446267,0.00027466455,0.00022372231,0.00018700548,0.0001345911,0.00028846282,0.000024223264],"category_scores_gemma":[0.00001125258,0.00044144993,0.00010343285,0.00034802494,0.000091289476,0.00027562983,0.00043851626,0.00079738116,4.919988e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000007315199,0.0000042601064,0.010354931,0.00016909809,0.00008932604,0.00016475745,0.000105201114,0.98783785,0.0003101281,0.0006139749,0.000009416632,0.00033372213],"study_design_scores_gemma":[0.00021762952,0.000022525106,0.0002956138,0.00024080435,0.00013530256,0.000021769372,0.00024438236,0.99737823,0.00017952871,0.0007734585,0.000041000374,0.00044974295],"about_ca_topic_score_codex":0.00012328349,"about_ca_topic_score_gemma":0.000026518144,"teacher_disagreement_score":0.4695233,"about_ca_system_score_codex":0.000065244385,"about_ca_system_score_gemma":0.000014093383,"threshold_uncertainty_score":0.9998037},"labels":[],"label_agreement":null},{"id":"W4289827721","doi":"10.1109/ipdpsw55747.2022.00198","title":"EDAML 2022 Invited Speaker 5: Combining Optimization and Machine Learning in Physical Design","year":2022,"lang":"en","type":"article","venue":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Heuristics; Machine learning; Artificial intelligence; Robustness (evolution); Optimization problem; Reinforcement learning; Online machine learning; Mathematical optimization; Active learning (machine learning); Algorithm; Mathematics","score_opus":0.015755746062909682,"score_gpt":0.2355472832429048,"score_spread":0.2197915371799951,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4289827721","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08188277,0.002556639,0.9113867,0.0014881425,0.00050764444,0.00049618364,0.0001824612,0.0008735793,0.00062583934],"genre_scores_gemma":[0.99466395,0.0005030083,0.0032445313,0.00015836915,0.00011052819,0.00021991922,0.0008805767,0.00005764815,0.00016148746],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983349,0.00013294905,0.0003794214,0.00041464192,0.00040708733,0.00033100482],"domain_scores_gemma":[0.99948615,0.00012892169,0.000113445596,0.00011138236,0.00005947587,0.00010063751],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003829682,0.00029585932,0.00029481627,0.00026654731,0.0003461686,0.0002061304,0.00024590557,0.00009171971,0.000080960366],"category_scores_gemma":[0.00003531593,0.00032861356,0.000048759448,0.00053903396,0.00006732968,0.00035942878,0.00015678823,0.0008127549,0.0000013389381],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010406752,0.00011340366,0.0022671495,0.00005139431,0.000046447498,0.000036576323,0.0007768172,0.98568225,0.005589451,0.00007127316,0.0014941251,0.0037670715],"study_design_scores_gemma":[0.00089984224,0.000084813466,0.00035910463,0.00008479288,0.00002389987,0.00006156109,0.00031095863,0.9953961,0.0004233281,0.0005067516,0.0014646619,0.00038423773],"about_ca_topic_score_codex":0.000017819799,"about_ca_topic_score_gemma":0.0000036824872,"teacher_disagreement_score":0.9127812,"about_ca_system_score_codex":0.00018857123,"about_ca_system_score_gemma":0.000026413254,"threshold_uncertainty_score":0.9999166},"labels":[],"label_agreement":null},{"id":"W4292308109","doi":"10.2139/ssrn.4191872","title":"A New Trust-Region-Based Phase Envelope Construction Algorithm","year":2022,"lang":"en","type":"article","venue":"SSRN Electronic Journal","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Envelope (radar); Algorithm; Phase (matter); Computer science; Telecommunications; Physics","score_opus":0.006242635752251582,"score_gpt":0.21559879329997295,"score_spread":0.20935615754772136,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4292308109","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004711779,0.0019223475,0.9913627,0.00019478897,0.00039217144,0.0001312807,0.0000050493713,0.0004394707,0.00084039767],"genre_scores_gemma":[0.9782873,0.0012197389,0.01878414,0.00012182264,0.00056691095,0.00004106028,0.000017633962,0.00008486856,0.00087655155],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.99815947,0.00005502873,0.00023337816,0.00012883944,0.0002392111,0.0011840452],"domain_scores_gemma":[0.9996631,0.000018546318,0.000060047514,0.00013165586,0.000024938023,0.00010172625],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004651291,0.00015667453,0.0001551495,0.00020534244,0.00027666427,0.00003996765,0.00022480618,0.00004936245,0.00028375263],"category_scores_gemma":[0.0000063588554,0.00016745008,0.00010601496,0.00023588251,0.000019268316,0.000118435055,0.000017445745,0.0017973034,0.0000114338845],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023944023,0.000034342556,0.000055736138,0.0000035678802,0.00008351891,0.000023009516,0.000058348178,0.0015975706,0.0007689461,0.006651361,0.0025192504,0.9881804],"study_design_scores_gemma":[0.0130816875,0.0041911565,0.00004171894,0.000046955483,0.00025975765,0.020071868,0.0034976022,0.20296863,0.01733632,0.4687964,0.26763448,0.0020734349],"about_ca_topic_score_codex":0.000023248507,"about_ca_topic_score_gemma":0.00000914904,"teacher_disagreement_score":0.986107,"about_ca_system_score_codex":0.0013046293,"about_ca_system_score_gemma":0.0013807185,"threshold_uncertainty_score":0.7808489},"labels":[],"label_agreement":null},{"id":"W4296700647","doi":"10.18280/isi.270403","title":"Accurate Power Estimation Identity for DSP Blocks Targeted to FPGAs","year":2022,"lang":"en","type":"article","venue":"Ingénierie des systèmes d information","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Digital signal processing; Computer science; Suite; Power (physics); Field-programmable gate array; Block (permutation group theory); Identity (music); Embedded system; Computer engineering; Computer hardware; Mathematics","score_opus":0.011427840728735376,"score_gpt":0.23789237540657285,"score_spread":0.22646453467783748,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4296700647","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07952407,0.00006124762,0.9145107,0.000036801513,0.0005076406,0.0009088243,0.000134718,0.0011012156,0.003214778],"genre_scores_gemma":[0.9860321,0.0000045802703,0.012568741,0.0002151055,0.000027815671,0.0008337024,0.00024927533,0.000023490502,0.000045157314],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99890715,0.000023400535,0.00045908403,0.00009213896,0.00024746518,0.00027075066],"domain_scores_gemma":[0.999472,0.00003641417,0.00009547834,0.0001961039,0.0001274494,0.0000725582],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00043578492,0.0001587068,0.00016359153,0.00031965395,0.00035062016,0.00019478565,0.00022381221,0.00006253919,0.00016369532],"category_scores_gemma":[0.00013623823,0.00018330078,0.00006886116,0.00044921463,0.00001751955,0.003181672,0.00007395274,0.0001282546,0.00004859728],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000094383475,0.000038342925,0.000101755686,0.0005694973,0.00010718567,0.000002672574,0.0126527995,0.83020324,0.006381882,0.009362208,0.04771174,0.09277427],"study_design_scores_gemma":[0.00080874487,0.00053742295,0.0018808686,0.0000904528,0.00004660641,0.00005185787,0.0017271405,0.87788594,0.027795136,0.019537425,0.06869247,0.0009459532],"about_ca_topic_score_codex":0.00001804943,"about_ca_topic_score_gemma":0.0000027962817,"teacher_disagreement_score":0.9065081,"about_ca_system_score_codex":0.0004368651,"about_ca_system_score_gemma":0.000028131359,"threshold_uncertainty_score":0.7474789},"labels":[],"label_agreement":null},{"id":"W4297958057","doi":"","title":"Optimization of meshed electrical networks by increasing algebraic connectivity","year":2017,"lang":"en","type":"article","venue":"HAL (Le Centre pour la Communication Scientifique Directe)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Safran Electronics (Canada)","funders":"","keywords":"Computer science; Algebraic number; Mathematics","score_opus":0.00725811079250767,"score_gpt":0.20355023255956506,"score_spread":0.19629212176705738,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4297958057","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08332105,0.0005336062,0.893267,0.00033826468,0.000049449143,0.00016643995,0.000007771414,0.00036484457,0.021951608],"genre_scores_gemma":[0.9687418,0.00037949072,0.030536886,0.00001347769,0.0000101844125,0.00001569492,0.000053102398,0.000030603027,0.00021877594],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99815786,0.0009989559,0.0002550838,0.00021324163,0.00015707522,0.00021778978],"domain_scores_gemma":[0.9977066,0.0006291809,0.00017611713,0.00097335345,0.00042993517,0.00008483023],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0023067205,0.000144709,0.0002146822,0.000072474046,0.00029893656,0.00016870619,0.00055330584,0.00013863342,0.000048979407],"category_scores_gemma":[0.0010901121,0.00015941646,0.00007096536,0.00015041375,0.00012110495,0.00024666582,0.00011030231,0.0001979842,0.0000024832705],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009808724,0.0014953831,0.038440008,0.00031435405,0.00045550495,0.000011693335,0.0046804845,0.040156413,0.2766742,0.12783714,0.019352723,0.490484],"study_design_scores_gemma":[0.00029950042,5.26605e-7,0.0031214592,0.0001917433,0.000018369183,0.000005452844,0.0000063186026,0.79374945,0.2012711,0.00051747303,0.0006085767,0.00021004048],"about_ca_topic_score_codex":0.00035262367,"about_ca_topic_score_gemma":0.00007910558,"teacher_disagreement_score":0.88542074,"about_ca_system_score_codex":0.0000532485,"about_ca_system_score_gemma":0.00002409028,"threshold_uncertainty_score":0.65008146},"labels":[],"label_agreement":null},{"id":"W4308659767","doi":"10.1109/vlsi-soc54400.2022.9939580","title":"Guiding FPGA Detailed Placement via Reinforcement Learning","year":2022,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Reinforcement learning; Computer science; Field-programmable gate array; Reinforcement; Computer architecture; Embedded system; Artificial intelligence; Engineering; Structural engineering","score_opus":0.017120597731932943,"score_gpt":0.21318589210845248,"score_spread":0.19606529437651954,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4308659767","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010451243,0.0002816919,0.86687666,0.00003713204,0.00025070805,0.00034075562,6.2255225e-7,0.0025849189,0.11917624],"genre_scores_gemma":[0.9953291,0.000028709308,0.0018122304,0.000082902865,0.000032826556,0.00017907166,0.000012938102,0.000030030225,0.002492219],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992096,0.000025592026,0.00020022597,0.0001149587,0.00021660907,0.00023303437],"domain_scores_gemma":[0.99976575,0.000018595474,0.000020402354,0.00013852777,0.0000109418415,0.000045766443],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0002536727,0.00011380869,0.00010700313,0.00009389755,0.00020466941,0.000021403817,0.00013589874,0.00002222348,0.0036952295],"category_scores_gemma":[0.0000052852115,0.000119815886,0.00004608399,0.00012997724,0.0000055887745,0.00006421365,0.00011421542,0.00015355025,0.000043812488],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000073853057,0.000011282613,0.0002413657,0.000018870523,0.000060129085,0.000011266506,0.00032643083,0.93099093,0.040561795,0.0005924119,0.014776216,0.012401902],"study_design_scores_gemma":[0.00042267423,0.00030429836,0.000040584186,0.000009473363,0.000027598911,0.000019669777,0.0005920971,0.6776804,0.15316114,0.00018710455,0.16708201,0.00047299347],"about_ca_topic_score_codex":0.0000088706865,"about_ca_topic_score_gemma":0.0000012111268,"teacher_disagreement_score":0.9848778,"about_ca_system_score_codex":0.00017299826,"about_ca_system_score_gemma":0.0000066726006,"threshold_uncertainty_score":0.9972155},"labels":[],"label_agreement":null},{"id":"W4310251946","doi":"10.1287/ijoc.2022.1248","title":"Cutting Planes from the Branch-and-Bound Tree: Challenges and Opportunities","year":2022,"lang":"en","type":"article","venue":"INFORMS journal on computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"IBM (Canada)","funders":"","keywords":"Integer programming; Branch and bound; Cutting-plane method; Branch and cut; Tree (set theory); Computer science; Simple (philosophy); Operations research; Linear programming; Search tree; Upper and lower bounds; Integer (computer science); Mathematical optimization; Algorithm; Mathematics; Combinatorics; Programming language; Epistemology","score_opus":0.05094025746411535,"score_gpt":0.2295837514378738,"score_spread":0.17864349397375845,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4310251946","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9687133,0.016439984,0.0026766164,0.0009857806,0.00047269274,0.00010864608,0.000010607948,0.0003402503,0.010252137],"genre_scores_gemma":[0.99557734,0.0033504383,0.00029687423,0.00041613288,0.00031543692,0.000002324489,0.0000027473684,0.000018152978,0.000020556938],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99927896,0.00002948876,0.00024629623,0.000071141694,0.00018805117,0.00018605588],"domain_scores_gemma":[0.99944806,0.00031270453,0.000080207385,0.00008364615,0.000014224589,0.00006113313],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00049157115,0.00012518617,0.00014489933,0.0000720345,0.00055867294,0.00015780573,0.00015238517,0.000029717055,0.00001891879],"category_scores_gemma":[0.000015138636,0.000088295346,0.000032016866,0.000029834131,0.000032165757,0.00015682785,0.00010196119,0.00053666835,9.506143e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000006835518,0.0000040049167,0.0002016366,0.000014937825,0.00004471024,0.000032169813,0.004799167,0.0013883761,0.00009248101,0.0011545548,0.00052613346,0.991735],"study_design_scores_gemma":[0.0034402618,0.0017526541,0.049473967,0.0013708487,0.00015916816,0.009086054,0.047645014,0.30471897,0.0026112194,0.04178596,0.535366,0.0025898998],"about_ca_topic_score_codex":0.000007406098,"about_ca_topic_score_gemma":0.0000020776754,"teacher_disagreement_score":0.9891451,"about_ca_system_score_codex":0.00003257363,"about_ca_system_score_gemma":0.000011818775,"threshold_uncertainty_score":0.4296917},"labels":[],"label_agreement":null},{"id":"W4312743307","doi":"10.1177/17483026221130680","title":"Using data-mining techniques to improve combinatorial optimization algorithms","year":2022,"lang":"en","type":"article","venue":"Journal of Algorithms & Computational Technology","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Heuristics; Cluster analysis; Simulated annealing; Algorithm; Granularity; Data mining; Machine learning","score_opus":0.0296336662235397,"score_gpt":0.2934519870529521,"score_spread":0.2638183208294124,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4312743307","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004841563,0.00026133654,0.9918343,0.00036512458,0.0015395292,0.00028629802,0.00008971516,0.00066869974,0.00011346503],"genre_scores_gemma":[0.10622075,0.000021325564,0.8931106,0.00009469534,0.00041389378,0.000025192745,0.00004546963,0.000061343795,0.0000067279166],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9980357,0.000058883925,0.0007698191,0.00026477827,0.00057054876,0.0003002599],"domain_scores_gemma":[0.9988188,0.00009318252,0.00030041666,0.00033233126,0.00036063496,0.00009462026],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007329065,0.00022313675,0.000407868,0.0012735858,0.00023418451,0.00005121852,0.000987331,0.00015862453,0.00005498756],"category_scores_gemma":[0.000081018705,0.00024982376,0.000073779665,0.0010589109,0.000059564736,0.00035993665,0.0005012836,0.0006503434,0.0000015390431],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002079979,0.00009120017,0.00003246965,0.000013574107,0.00011229339,0.000082766404,0.00008941286,0.8751634,0.0029164492,0.0007453432,0.0025776965,0.11815464],"study_design_scores_gemma":[0.0004767654,0.0006765306,0.000008877477,0.000029206338,0.000046011803,0.0008166816,0.00022953875,0.97832316,0.0046345475,0.009047,0.0054099,0.00030175582],"about_ca_topic_score_codex":0.0000044040926,"about_ca_topic_score_gemma":1.3919552e-7,"teacher_disagreement_score":0.11785288,"about_ca_system_score_codex":0.00038558058,"about_ca_system_score_gemma":0.0001530344,"threshold_uncertainty_score":0.9999954},"labels":[],"label_agreement":null},{"id":"W4313854516","doi":"10.1109/icm56065.2022.10005468","title":"An Adaptive Sequential Decision Making Flow for FPGAs using Machine Learning","year":2022,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Application-specific integrated circuit; Computer science; Flow (mathematics); Design flow; Machine learning; Computer architecture; Artificial intelligence; Embedded system; Computer engineering","score_opus":0.03454467919921973,"score_gpt":0.2865079282869275,"score_spread":0.2519632490877078,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4313854516","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03267522,0.00027037147,0.9650612,0.0000026390906,0.00019063536,0.00024354493,0.000020887028,0.0009324219,0.00060309016],"genre_scores_gemma":[0.7036484,0.00000444923,0.2961403,0.000022806991,0.00006516954,0.00003967212,0.000015054219,0.000041642972,0.000022497195],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99926805,0.0000404663,0.00015676608,0.00016788817,0.00015232804,0.00021446985],"domain_scores_gemma":[0.9997278,0.000062007304,0.000022397897,0.00012717245,0.00002335885,0.000037251015],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00026884305,0.00012189953,0.00012799964,0.00012069322,0.0002940656,0.00003893986,0.0001392815,0.00003905995,0.00041907505],"category_scores_gemma":[0.000011623121,0.00012932741,0.000065404376,0.0001253107,0.000007713382,0.00015073988,0.000058243917,0.00021402385,0.0000018142832],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006129681,0.000016885557,0.000080212296,0.000009814869,0.000027351603,0.000009323453,0.00020492855,0.8774368,0.039482765,0.0005232617,0.00021939614,0.081927955],"study_design_scores_gemma":[0.00016241727,0.00019461743,0.000007728615,0.000012627893,0.000018011648,0.000020511368,0.000101604324,0.98857343,0.0076812445,0.0013792003,0.0016742048,0.00017439957],"about_ca_topic_score_codex":0.00002486169,"about_ca_topic_score_gemma":0.000013351332,"teacher_disagreement_score":0.6709732,"about_ca_system_score_codex":0.0001263869,"about_ca_system_score_gemma":0.000011261325,"threshold_uncertainty_score":0.5273819},"labels":[],"label_agreement":null},{"id":"W4316924672","doi":"10.18609/cgti.2022.209","title":"Innovating in iPSC differentiation &amp; engineering","year":2022,"lang":"en","type":"article","venue":"Cell and Gene Therapy Insights","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Chemistry; Cell biology; Engineering; Biology","score_opus":0.011583485698980522,"score_gpt":0.18147300390203616,"score_spread":0.16988951820305564,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4316924672","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9906726,0.0028374516,0.0054523046,0.0000070419173,0.00012299823,0.000107925815,0.0000015927567,0.0002301982,0.0005678731],"genre_scores_gemma":[0.99830586,0.00048800325,0.00096523325,0.00003943524,0.00004117986,0.000054369968,0.000018898008,0.000022461403,0.000064569096],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995488,0.00001643262,0.00013563149,0.000102948805,0.00007526665,0.0001209518],"domain_scores_gemma":[0.9998481,0.000015313295,0.000015218588,0.000094036455,0.000007409559,0.000019915002],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000064044296,0.00009909409,0.00009821755,0.00015352208,0.00006594414,0.000017179815,0.000063565996,0.000029835055,0.000046566733],"category_scores_gemma":[0.0000010089208,0.00009830696,0.000015472478,0.00022276331,0.000004460242,0.000052020026,0.000023092984,0.00015781757,0.0000015857929],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000074414475,0.000033346078,0.00051013107,0.00002613228,0.000010996936,0.000004439097,0.0023899258,0.009543923,0.9594152,0.00017422209,0.00017969198,0.027704556],"study_design_scores_gemma":[0.0016254783,0.00019726792,0.010255663,0.00002396373,0.000006425315,0.000015684742,0.0001002053,0.12224821,0.80477923,0.002240778,0.057632692,0.0008744126],"about_ca_topic_score_codex":0.0000065216514,"about_ca_topic_score_gemma":0.0000028497116,"teacher_disagreement_score":0.15463598,"about_ca_system_score_codex":0.00003223316,"about_ca_system_score_gemma":0.0000034699688,"threshold_uncertainty_score":0.40088418},"labels":[],"label_agreement":null},{"id":"W4318224776","doi":"10.29292/jics.v17i3.648","title":"Towards a Reference Place and Route Flow for Academic Research","year":2022,"lang":"en","type":"article","venue":"Journal of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Conselho Nacional de Desenvolvimento Científico e Tecnológico; Natural Sciences and Engineering Research Council of Canada; Coordenação de Aperfeiçoamento de Pessoal de Nível Superior","keywords":"CONTEST; Computer science; Routing (electronic design automation); Placement; Physical design; Convergence (economics); Flow (mathematics); Work (physics); Closure (psychology); Network routing; Quality (philosophy); Distributed computing; Computer engineering; Computer network; Circuit design; Embedded system; Mathematics; Mechanical engineering; Engineering","score_opus":0.09628015786767685,"score_gpt":0.32215874314364923,"score_spread":0.22587858527597238,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4318224776","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8435158,0.076746635,0.06807026,0.00037192376,0.0019962196,0.0015789026,0.0005051178,0.00031604012,0.006899067],"genre_scores_gemma":[0.9981013,0.0012627346,0.00014799091,0.000012991235,0.0001199943,0.000051307776,0.0000041871435,0.000021443453,0.00027805692],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988248,0.00013952235,0.00040595004,0.000102355305,0.000311963,0.00021540489],"domain_scores_gemma":[0.99934274,0.00012300324,0.00008469444,0.000079954,0.00026594955,0.00010366424],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0021797412,0.00010584634,0.00027441687,0.00027148493,0.0001535294,0.00008054545,0.0001784336,0.00010048417,0.000010799147],"category_scores_gemma":[0.000087441535,0.00008182581,0.000034478548,0.00021269443,0.000028975806,0.00012478106,0.00002555396,0.0010214612,3.578858e-7],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00036286892,0.00012578639,0.002172415,0.0022472856,0.00089796283,0.0003783344,0.011722244,0.014684766,0.29884198,0.02749093,0.2151376,0.42593783],"study_design_scores_gemma":[0.0028606318,0.003749596,0.0008568159,0.001559614,0.00012197538,0.007017695,0.0197956,0.47924387,0.006261699,0.0042698276,0.4733094,0.00095327786],"about_ca_topic_score_codex":0.00004528979,"about_ca_topic_score_gemma":0.0000019271633,"teacher_disagreement_score":0.4645591,"about_ca_system_score_codex":0.00017229587,"about_ca_system_score_gemma":0.00009682628,"threshold_uncertainty_score":0.44377974},"labels":[],"label_agreement":null},{"id":"W4318256895","doi":"10.1145/3557988.3569714","title":"A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA's","year":2022,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Advanced Micro Devices (Canada); University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Process (computing); Upper and lower bounds; Parallel computing; Range (aeronautics); Algorithm; Embedded system; Operating system; Mathematics; Materials science","score_opus":0.029182161719011196,"score_gpt":0.2532017452201226,"score_spread":0.22401958350111142,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4318256895","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010372591,0.00012179492,0.9876473,0.000034180193,0.000061293766,0.0010074901,0.00010052599,0.0011270449,0.008863096],"genre_scores_gemma":[0.79101586,0.0000014663219,0.20610425,0.00015319389,0.000057663787,0.0020859381,0.00025729684,0.000038500162,0.00028581146],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992136,0.00002025372,0.00018274151,0.00017936759,0.0001235486,0.0002805323],"domain_scores_gemma":[0.999735,0.00006583224,0.00002646786,0.000108489454,0.0000216066,0.00004262717],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00030284512,0.00014047575,0.00014966108,0.00004134236,0.00028673344,0.000043351414,0.00014609763,0.000034455476,0.00012434329],"category_scores_gemma":[0.000021834383,0.0001435593,0.000093784176,0.00011743055,0.0000057790994,0.00004493543,0.000041543666,0.00012466889,5.4733977e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000059858914,0.00006256515,0.00026905473,0.000189434,0.00004358528,6.1122455e-7,0.00006204439,0.9656088,0.0025356533,0.002096736,0.0074116467,0.021660026],"study_design_scores_gemma":[0.00069369253,0.000282106,0.000004812436,0.0000021584842,0.000013596794,0.0000022177828,0.00011326207,0.965912,0.0053982534,0.00019308117,0.02719738,0.00018744254],"about_ca_topic_score_codex":0.000013243177,"about_ca_topic_score_gemma":0.0000024252029,"teacher_disagreement_score":0.7899786,"about_ca_system_score_codex":0.00018335783,"about_ca_system_score_gemma":0.000018427418,"threshold_uncertainty_score":0.5854178},"labels":[],"label_agreement":null},{"id":"W4318685218","doi":"10.1145/3566097.3567894","title":"Area-Driven FPGA Logic Synthesis Using Reinforcement Learning","year":2023,"lang":"en","type":"article","venue":"Proceedings of the 28th Asia and South Pacific Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Netlist; Computer science; Reinforcement learning; Electronic circuit; Field-programmable gate array; Artificial intelligence; Algorithm; Computer hardware; Engineering","score_opus":0.04891981962249125,"score_gpt":0.23118123418274789,"score_spread":0.18226141456025663,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4318685218","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3983637,0.000092167946,0.5686346,0.00020169129,0.00030166362,0.0016473526,0.000011047457,0.0046872417,0.026060482],"genre_scores_gemma":[0.9953171,0.000052912554,0.0043529295,0.000006079945,0.000017753451,0.000057733665,0.0000013676396,0.000024433222,0.00016966037],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99897736,0.000018448169,0.00031504114,0.00018969867,0.00024492654,0.00025451355],"domain_scores_gemma":[0.9994775,0.00006508975,0.00016125687,0.00009302498,0.00014776028,0.00005534599],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000406003,0.00019077516,0.00023637593,0.00018823669,0.00017552721,0.00011224359,0.00022022855,0.0001091239,0.00002198163],"category_scores_gemma":[0.00018149122,0.00015178518,0.00005841537,0.00041941242,0.00007615269,0.00021742436,0.000060513394,0.00016444077,0.000011897427],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007219069,0.000042893716,0.011272462,0.0021571275,0.00033545436,0.000005055296,0.032271147,0.15129058,0.74315345,0.020318756,0.0025613483,0.036519527],"study_design_scores_gemma":[0.00009942851,0.00003601376,0.0010688158,0.0002956615,0.00004217247,0.0000069144958,0.0025858192,0.92581344,0.068599276,0.0011833243,0.00005978316,0.00020932565],"about_ca_topic_score_codex":0.0000021009769,"about_ca_topic_score_gemma":4.4261583e-8,"teacher_disagreement_score":0.7745229,"about_ca_system_score_codex":0.000037699887,"about_ca_system_score_gemma":0.000024703697,"threshold_uncertainty_score":0.618962},"labels":[],"label_agreement":null},{"id":"W4320802294","doi":"10.1109/ccdc55256.2022.10033897","title":"Gate-level Circuit Partitioning Algorithm Based on Cut Vertex and Betweenness Centrality","year":2022,"lang":"en","type":"article","venue":"2022 34th Chinese Control and Decision Conference (CCDC)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Betweenness centrality; Algorithm; Computer science; Vertex (graph theory); Logic gate; Centrality; Overhead (engineering); Parallel computing; Mathematics; Theoretical computer science; Combinatorics; Graph","score_opus":0.021940511106329535,"score_gpt":0.2359177682546239,"score_spread":0.21397725714829438,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4320802294","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.31321713,0.0006950132,0.6816272,0.00020278526,0.00064548757,0.00063413393,0.00087871286,0.00058342045,0.0015160865],"genre_scores_gemma":[0.99821067,0.00012435857,0.000937565,0.00035706357,0.00006864173,0.00016182647,0.000059050533,0.0000347476,0.00004606649],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99817973,0.00010944884,0.0003921193,0.00045909185,0.0004762979,0.0003833024],"domain_scores_gemma":[0.99868715,0.0006018476,0.00006470934,0.00034227103,0.00008294337,0.00022109471],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005294405,0.00032517777,0.00047288957,0.00018716053,0.0004357062,0.0001634757,0.00022998203,0.000093097326,0.00063281815],"category_scores_gemma":[0.000120864344,0.00028738903,0.00008559979,0.0002764652,0.00006263195,0.0001751314,0.000093530834,0.00043419603,0.000008876642],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00022818474,0.00017118843,0.0138497595,0.0000737191,0.00009095709,0.0001021468,0.00035415386,0.0065306444,0.0021511328,0.0018084869,0.002806471,0.97183317],"study_design_scores_gemma":[0.002673023,0.00023516176,0.04996495,0.00006059434,0.000038475042,0.000020657058,0.00007225597,0.9164832,0.00012488377,0.028310785,0.0015218813,0.0004941176],"about_ca_topic_score_codex":0.000057372014,"about_ca_topic_score_gemma":0.000024168177,"teacher_disagreement_score":0.97133905,"about_ca_system_score_codex":0.000067165325,"about_ca_system_score_gemma":0.00005124005,"threshold_uncertainty_score":0.9999578},"labels":[],"label_agreement":null},{"id":"W4321021655","doi":"10.1109/tcad.2023.3245979","title":"Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning","year":2023,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":15,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Science Foundation of Zhejiang Province; Natural Sciences and Engineering Research Council of Canada; State Key Laboratory of Millimeter Waves; Canada Foundation for Innovation","keywords":"Computer science; Overhead (engineering); Division (mathematics); Topology (electrical circuits); High-level synthesis; Generalization; Network topology; Operational amplifier; Electronic engineering; Scheme (mathematics); Amplifier; Computer engineering; Engineering; Embedded system; Electrical engineering; Field-programmable gate array; Mathematics; Telecommunications; Arithmetic; Bandwidth (computing)","score_opus":0.02758136896053593,"score_gpt":0.2206906462353084,"score_spread":0.19310927727477248,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4321021655","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.023546869,0.0003041636,0.9727378,0.00001569395,0.00067959895,0.0006398656,0.00016610808,0.0017437882,0.00016613086],"genre_scores_gemma":[0.9987598,0.00051465846,0.00014331975,0.000021756197,0.000046856458,0.00020310257,0.000024229532,0.0001000687,0.00018620785],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9972941,0.0004480199,0.00084950146,0.00052266964,0.0003453391,0.00054033624],"domain_scores_gemma":[0.9982493,0.00097079366,0.000073808376,0.00032510472,0.0001868759,0.00019411778],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006393523,0.0004940813,0.0008466498,0.00075733784,0.00024312732,0.00011799317,0.00030995253,0.00043216112,0.000081497754],"category_scores_gemma":[0.000008963474,0.00045736093,0.0001920695,0.000953923,0.00011496093,0.00019228221,0.0000016558582,0.000633546,0.000039651222],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025053156,0.00012839268,0.000025716823,0.0003989025,0.0005359451,0.00006981436,0.00072349363,0.6114144,0.19825862,0.00015820563,0.0038621733,0.18439928],"study_design_scores_gemma":[0.0005674127,0.00082628103,0.000027952929,0.0007693142,0.00011871748,0.00009006538,0.0005177549,0.8318016,0.16403745,0.00010939046,0.00042679577,0.00070728373],"about_ca_topic_score_codex":0.0001858209,"about_ca_topic_score_gemma":0.0000042765114,"teacher_disagreement_score":0.97521293,"about_ca_system_score_codex":0.000110959765,"about_ca_system_score_gemma":0.000053518652,"threshold_uncertainty_score":0.9997878},"labels":[],"label_agreement":null},{"id":"W4362473375","doi":"10.3390/e25040597","title":"Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm","year":2023,"lang":"en","type":"article","venue":"Entropy","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Central South University; Natural Science Foundation of Hainan Province; National Natural Science Foundation of China","keywords":"Algorithm; Cluster analysis; Computer science; Genetic algorithm; Artificial intelligence; Machine learning","score_opus":0.023088189336178806,"score_gpt":0.23708410285821332,"score_spread":0.2139959135220345,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4362473375","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010046481,0.000065206135,0.98736864,0.000022659913,0.00022898495,0.00020958803,0.000045082772,0.0017065121,0.00030683482],"genre_scores_gemma":[0.8623197,0.00010879317,0.13655628,0.00014400347,0.00041206012,0.00013760579,0.000080517326,0.0001118737,0.00012916587],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99911046,0.000027087373,0.000170624,0.00022761729,0.00012929394,0.00033492013],"domain_scores_gemma":[0.9995884,0.0000349024,0.000020312213,0.0002203915,0.00001846087,0.00011757289],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012042157,0.00016892645,0.00014741048,0.00014566854,0.000093768474,0.00008175222,0.000096143514,0.00008262563,0.000049808317],"category_scores_gemma":[0.000009443822,0.00018076293,0.000035928453,0.00018241824,0.000022815677,0.00009974369,0.000022506021,0.0001409959,0.000048381877],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000058936093,0.000040635277,0.00022491676,0.000084279265,0.000039194943,0.00009044814,0.00033266275,0.02627855,0.052246258,0.00010146009,0.0011480995,0.9194076],"study_design_scores_gemma":[0.00032537628,0.00012620841,0.0027955116,0.00003500739,0.000010195573,0.0000052005603,0.000025907259,0.9848428,0.010666704,0.0004833389,0.00046432993,0.00021944183],"about_ca_topic_score_codex":0.000017107644,"about_ca_topic_score_gemma":0.0000022508914,"teacher_disagreement_score":0.9585642,"about_ca_system_score_codex":0.0000483941,"about_ca_system_score_gemma":0.000009398655,"threshold_uncertainty_score":0.7371298},"labels":[],"label_agreement":null},{"id":"W4362638787","doi":"10.1145/3590962","title":"CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes","year":2023,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Policy-based routing; Static routing; Routing (electronic design automation); Distributed computing; Link-state routing protocol; Placement; Physical design; Multipath routing; Interdependence; Dynamic Source Routing; Computer network; Routing protocol; Embedded system","score_opus":0.018532246439521463,"score_gpt":0.23643783554779124,"score_spread":0.2179055891082698,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4362638787","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.15637594,0.00029650176,0.8417908,0.00006307757,0.000037160313,0.0005598476,0.0000056654744,0.0008332611,0.00003772983],"genre_scores_gemma":[0.99607605,0.00031532935,0.003286493,0.000002233942,0.00000927756,0.00023039793,0.000008429965,0.00002474851,0.000047023277],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990184,0.00006335754,0.00036186664,0.00018287299,0.00011179071,0.000261715],"domain_scores_gemma":[0.99952507,0.00016950919,0.00005353018,0.00018965288,0.00003566412,0.00002656674],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00040549957,0.00014318511,0.00023551831,0.00062002474,0.000074704425,0.000028638044,0.00009175613,0.00014295707,0.000004412888],"category_scores_gemma":[0.00002552936,0.0001538955,0.000016647571,0.0006712985,0.000028507107,0.00017062663,0.0000033843965,0.00017440651,0.0000048568263],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015142893,0.0000207701,0.00037760643,0.00017933457,0.0000664085,0.0000011899549,0.00042768999,0.89220834,0.040784754,0.0007264691,0.00003518819,0.0651571],"study_design_scores_gemma":[0.00078345154,0.00038508844,0.0011438506,0.00031195805,0.00003073937,0.00001500709,0.00055823545,0.9441545,0.051907387,0.00041957406,0.00004036569,0.00024984355],"about_ca_topic_score_codex":0.000011497385,"about_ca_topic_score_gemma":0.000009089279,"teacher_disagreement_score":0.8397001,"about_ca_system_score_codex":0.00014655077,"about_ca_system_score_gemma":0.000026181619,"threshold_uncertainty_score":0.62756765},"labels":[],"label_agreement":null},{"id":"W4364322167","doi":"10.1109/tsusc.2023.3263172","title":"Critical Path Awareness Techniques for Large-Scale Graph Partitioning","year":2023,"lang":"en","type":"article","venue":"IEEE Transactions on Sustainable Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":9,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"National Natural Science Foundation of China","keywords":"Graph partition; Computer science; Critical path method; Longest path problem; Graph; Partition (number theory); Theoretical computer science; Parallel computing; Algorithm; Mathematics; Shortest path problem; Combinatorics; Engineering","score_opus":0.014743603443448921,"score_gpt":0.2775236043878273,"score_spread":0.26278000094437837,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4364322167","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0075407205,0.000039930263,0.98495376,0.00007638805,0.00030634154,0.0004881121,0.000033400112,0.005890393,0.00067096646],"genre_scores_gemma":[0.9864771,0.00003568691,0.012676452,0.00005434328,0.000105754734,0.0002996069,0.000011912063,0.00008061055,0.0002585558],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984104,0.000035962505,0.00029749013,0.0002864863,0.00015907531,0.00081061054],"domain_scores_gemma":[0.99909633,0.00033258327,0.00002151059,0.00023865284,0.0002124785,0.000098465316],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00050645036,0.00021658742,0.00023529446,0.00040881953,0.0007388158,0.00012179968,0.00015758998,0.00015125684,0.000021133364],"category_scores_gemma":[0.000021269152,0.00024635397,0.00015924964,0.0007885989,0.000036699854,0.00024091057,0.0000031785473,0.0002692196,0.000013386527],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014738845,0.0009157066,0.0003129398,0.0076611144,0.00035597055,0.0004304969,0.0069550145,0.68984157,0.01521779,0.02895901,0.031365503,0.21783751],"study_design_scores_gemma":[0.00044919451,0.0002579205,0.000074619915,0.00030670338,0.00006723339,0.000018562161,0.0043782187,0.7729696,0.20263304,0.0105028,0.0075770514,0.0007650512],"about_ca_topic_score_codex":0.00001670253,"about_ca_topic_score_gemma":0.0000042798747,"teacher_disagreement_score":0.9789364,"about_ca_system_score_codex":0.0001236344,"about_ca_system_score_gemma":0.000036658603,"threshold_uncertainty_score":0.99999887},"labels":[],"label_agreement":null},{"id":"W4366724629","doi":"10.1109/mdat.2023.3250618","title":"Interview With Prof. Sung-Mo (Steve) Kang","year":2023,"lang":"en","type":"article","venue":"IEEE Design and Test","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Library science; Management; Supervisor; Engineering; Telecommunications; Art history; Sociology; Art; Computer science","score_opus":0.03209006010813522,"score_gpt":0.22322703486375514,"score_spread":0.19113697475561992,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4366724629","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07362942,0.002879848,0.89762723,0.0007526051,0.00053194346,0.0022929094,0.000032122538,0.013166257,0.0090876585],"genre_scores_gemma":[0.99560684,0.00039804186,0.0027270103,0.00011109806,0.000074877324,0.00010896837,0.000004623334,0.000057231442,0.00091129396],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99940455,0.00002533602,0.00011844823,0.00014607,0.00008522405,0.0002203737],"domain_scores_gemma":[0.99959695,0.00017474324,0.000014057212,0.0001263509,0.00002080385,0.00006709821],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00022264973,0.00014405807,0.00015039636,0.00009544766,0.000042778433,0.00004757328,0.00009320998,0.00006208515,0.000012422379],"category_scores_gemma":[0.00001569972,0.0001150813,0.000021999067,0.00027771064,0.000029943121,0.00009756468,0.000010800996,0.00011088281,0.00009930875],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000030288666,0.00016226203,0.0066450415,0.0018152192,0.0002831007,0.0005486461,0.0019324223,0.0018597054,0.2636311,0.0013477603,0.4371859,0.28455853],"study_design_scores_gemma":[0.0027681221,0.0028953662,0.021481516,0.0025375711,0.00027611761,0.0005271563,0.0003952572,0.23659983,0.595025,0.006160054,0.12785882,0.0034752004],"about_ca_topic_score_codex":0.0000033164708,"about_ca_topic_score_gemma":0.0000021800874,"teacher_disagreement_score":0.92197746,"about_ca_system_score_codex":0.000015110921,"about_ca_system_score_gemma":0.000008647284,"threshold_uncertainty_score":0.4692879},"labels":[],"label_agreement":null},{"id":"W4368232696","doi":"10.1109/tcad.2023.3272582","title":"Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research","year":2023,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":26,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Toronto","funders":"Vector Institute; VMware; National Science Foundation","keywords":"Benchmark (surveying); Field-programmable gate array; Computer science; Computer architecture; Suite; CAD; Computer engineering; Verilog; Electronic design automation; Embedded system; Parallel computing; Engineering","score_opus":0.0593460382996578,"score_gpt":0.2861478695518774,"score_spread":0.2268018312522196,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4368232696","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012555605,0.00042330733,0.9841851,0.00002132946,0.0004026069,0.0015708538,0.000044250646,0.00058181654,0.0002151241],"genre_scores_gemma":[0.9966147,0.0004134853,0.0021281105,0.000010440553,0.00007218358,0.00037506828,0.000020622238,0.00007871916,0.0002866519],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979532,0.00037434715,0.0004992858,0.00042888965,0.00027485803,0.00046946376],"domain_scores_gemma":[0.998238,0.0010216597,0.000067052395,0.0002648535,0.00025024248,0.00015819231],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0014183483,0.00029998436,0.0005199583,0.0007301221,0.00036190837,0.00027824467,0.00033254156,0.00027368174,0.000009642061],"category_scores_gemma":[0.000017676264,0.00026641638,0.000074070864,0.00076976494,0.00012364819,0.00014872056,0.000005732464,0.00074913184,0.000004135977],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000044664637,0.000048214304,0.0000077984405,0.00047015774,0.00018710841,0.000011406152,0.0016605336,0.5659356,0.028188562,0.00013982275,0.0017479035,0.40155825],"study_design_scores_gemma":[0.00076592877,0.0011352836,0.000025279318,0.0006958316,0.000036746736,0.00007976916,0.0009341088,0.96981114,0.02308634,0.00028657043,0.002753352,0.0003896239],"about_ca_topic_score_codex":0.00021643711,"about_ca_topic_score_gemma":0.000014362324,"teacher_disagreement_score":0.9840591,"about_ca_system_score_codex":0.00007213907,"about_ca_system_score_gemma":0.00004323235,"threshold_uncertainty_score":0.9999788},"labels":[],"label_agreement":null},{"id":"W4378800899","doi":"10.1145/3583781.3590312","title":"RL-Ripper:","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta; University of Calgary","funders":"","keywords":"Computer science; Reinforcement learning; Heuristics; Routing (electronic design automation); Heuristic; Distributed computing; Artificial intelligence; Computer network","score_opus":0.00907235228150013,"score_gpt":0.19239736923045025,"score_spread":0.18332501694895012,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4378800899","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.058050442,0.00012616624,0.055256676,0.00016882735,0.00033309785,0.00012859105,0.00000317259,0.024766406,0.8611666],"genre_scores_gemma":[0.99481946,0.00009091574,0.001043745,0.000043132757,0.00003881977,0.00001143406,0.0000028782003,0.000014785094,0.003934805],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9997915,0.0000016122156,0.000040501516,0.000036707253,0.00003526291,0.00009442625],"domain_scores_gemma":[0.99989223,0.000007836037,0.0000011903339,0.000076064694,0.0000035562066,0.000019135787],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.000035960435,0.000035184003,0.000035325113,0.000044508157,0.000010359153,0.000008027237,0.00004505529,0.000025188387,0.00020838079],"category_scores_gemma":[0.000002469866,0.000031066524,0.000015625705,0.00014197097,0.0000037244242,0.000030756502,0.000007843934,0.00003076158,0.0011902172],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[4.36287e-7,0.0000035520993,0.0004836503,0.00002841563,0.000014170558,0.000017068243,0.00011064254,0.0005031064,0.04960324,0.0064955084,0.86698157,0.07575861],"study_design_scores_gemma":[0.00018436776,0.00004628737,0.005468931,0.000020972375,0.000007356739,0.000009472376,0.00010554091,0.12510632,0.34433612,0.008569143,0.51564777,0.00049772375],"about_ca_topic_score_codex":0.0000024054714,"about_ca_topic_score_gemma":0.0000010546656,"teacher_disagreement_score":0.93676907,"about_ca_system_score_codex":0.0000058577125,"about_ca_system_score_gemma":0.0000010908764,"threshold_uncertainty_score":0.9995875},"labels":[],"label_agreement":null},{"id":"W4380610161","doi":"10.12737/2219-0767-2023-16-2-85-93","title":"Routing buses impact analysis on the results on modeling standard digital cell on CMOS 28 nm","year":2023,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Netlist; Routing (electronic design automation); Standard cell; Standard deviation; Set (abstract data type); Computer science; Simulation; CMOS; Real-time computing; Algorithm; Electronic engineering; Embedded system; Statistics; Integrated circuit; Engineering; Mathematics","score_opus":0.033232416721153415,"score_gpt":0.2527429747662627,"score_spread":0.21951055804510927,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4380610161","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8964126,0.00065430143,0.097150214,0.00004189029,0.00007091572,0.00030129662,0.00029269038,0.0007054153,0.0043706526],"genre_scores_gemma":[0.99940914,0.00033086332,0.000034777495,0.000008778537,0.000078387464,0.00002589931,0.000025748217,0.000041208805,0.000045181936],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986498,0.00002064089,0.00044852926,0.00026837178,0.00034555586,0.00026714028],"domain_scores_gemma":[0.99919087,0.00024699184,0.00008133408,0.00027468658,0.00014960686,0.00005652832],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00048651738,0.00023837273,0.00038341622,0.00030755435,0.00014104052,0.00022208782,0.00015733963,0.00009281759,0.0000010470269],"category_scores_gemma":[0.00013825967,0.00015464476,0.000101253296,0.00076063874,0.000013820371,0.00014273504,0.000021508315,0.00017108454,0.000005245739],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007127799,0.000011747524,0.000057170117,0.00037355424,0.000114476985,0.0000023438217,0.000629043,0.9979525,0.00015121151,0.000052244464,0.0001598178,0.00042456793],"study_design_scores_gemma":[0.00014554049,0.00020773991,0.0000026419632,0.000619892,0.000056905905,7.297368e-7,0.0005964933,0.99610925,0.0018577393,0.00020006463,0.000019762218,0.00018322185],"about_ca_topic_score_codex":0.00012102043,"about_ca_topic_score_gemma":0.0000045162287,"teacher_disagreement_score":0.102996536,"about_ca_system_score_codex":0.000041667856,"about_ca_system_score_gemma":0.000032789514,"threshold_uncertainty_score":0.630623},"labels":[],"label_agreement":null},{"id":"W4382403108","doi":"10.3390/designs7040082","title":"Optimal Domain-Partitioning Algorithm for Real-Life Transportation Networks and Finite Element Meshes","year":2023,"lang":"en","type":"article","venue":"Designs","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Polygon mesh; Finite element method; Computer science; Algorithm; Tetrahedron; Heuristic; Volume mesh; Mathematical optimization; Mesh generation; Mathematics; Engineering; Structural engineering; Geometry","score_opus":0.02558619326825956,"score_gpt":0.24935381494174144,"score_spread":0.22376762167348188,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4382403108","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014664317,0.00010735191,0.98363006,0.000029924033,0.00008319592,0.00032801158,0.00004171554,0.00095971266,0.00015571267],"genre_scores_gemma":[0.8296797,0.00094000343,0.16793913,0.0000649585,0.00022845215,0.0005659467,0.00042038763,0.00007294977,0.00008842473],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99934024,0.0000128828415,0.0001877313,0.00013730861,0.00007872262,0.0002431329],"domain_scores_gemma":[0.9996954,0.00010681291,0.00002097295,0.00008312772,0.000022305747,0.00007136163],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00022455028,0.00011491529,0.00012720386,0.00007772507,0.00009257137,0.00003743795,0.000048428497,0.00007225603,0.000015709858],"category_scores_gemma":[0.0000053900203,0.0001235789,0.000041276355,0.00015889187,0.000016518923,0.00009848259,0.0000030415351,0.000062851424,0.000004969353],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000031308482,0.000034172626,0.00068146345,0.00020352083,0.00021517361,0.000041738902,0.0021645008,0.8571442,0.008707588,0.0063027334,0.03210183,0.09237181],"study_design_scores_gemma":[0.00031550782,0.00010199684,0.0017751863,0.000031860967,0.000028617895,8.0646055e-7,0.00015115016,0.9905959,0.0036160147,0.00084230665,0.0023315835,0.00020909656],"about_ca_topic_score_codex":0.00000735404,"about_ca_topic_score_gemma":0.0000064613882,"teacher_disagreement_score":0.81569093,"about_ca_system_score_codex":0.000019301955,"about_ca_system_score_gemma":0.000008080553,"threshold_uncertainty_score":0.5039401},"labels":[],"label_agreement":null},{"id":"W4383749638","doi":"10.1109/fccm57271.2023.00057","title":"Reformulating the FPGA Routability Prediction Problem with Machine Learning","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Field-programmable gate array; Routing (electronic design automation); Computer science; Compiler; Programmable logic array; Embedded system; Field (mathematics); Computer architecture; Gate array; Programmable Array Logic; Logic synthesis; Parallel computing; Computer engineering; Logic gate; Algorithm; Operating system; Mathematics","score_opus":0.010037119380978182,"score_gpt":0.19598174461832527,"score_spread":0.1859446252373471,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4383749638","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.54721105,0.00018020424,0.28712243,0.00043334608,0.00014591207,0.0013467243,0.000015803602,0.029139563,0.13440499],"genre_scores_gemma":[0.9969957,0.000018844654,0.002439309,0.0000091228285,0.000037752157,0.000050036397,0.000015809219,0.000024406307,0.0004090615],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99948245,0.0000205442,0.00012416691,0.000098287535,0.00011165119,0.00016288931],"domain_scores_gemma":[0.99976635,0.000038746537,0.000013870736,0.00014038035,0.000017943725,0.000022684524],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003311722,0.00008553282,0.00007166428,0.000038591617,0.000116596726,0.000028511391,0.00007240948,0.00003974674,0.00003536606],"category_scores_gemma":[0.00000947837,0.00004684479,0.00002099596,0.0002865607,0.0000152023695,0.000112687696,0.000021547647,0.0002118372,0.00002385496],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000040350977,0.00003998429,0.16690445,0.00039024223,0.00023319513,0.000015726573,0.0046042646,0.43182972,0.022318745,0.002651959,0.0032510252,0.36772034],"study_design_scores_gemma":[0.00012862576,0.000104324856,0.008977534,0.00002967215,0.000013840798,0.000009047501,0.00015867487,0.97692543,0.00891564,0.00091770064,0.0036834644,0.00013603603],"about_ca_topic_score_codex":0.0000519927,"about_ca_topic_score_gemma":0.00003319661,"teacher_disagreement_score":0.5450957,"about_ca_system_score_codex":0.000032529017,"about_ca_system_score_gemma":0.00000419819,"threshold_uncertainty_score":0.1910275},"labels":[],"label_agreement":null},{"id":"W4384158358","doi":"10.1109/aiiot58121.2023.10174303","title":"Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Computer science; Computational complexity theory; Path (computing); Computation; Power (physics); Combinational logic; Integer programming; Digital electronics; Integer (computer science); Parallel computing; Logic gate; Algorithm; Electronic circuit; Engineering","score_opus":0.02025489193778845,"score_gpt":0.25567357867198487,"score_spread":0.23541868673419641,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4384158358","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6439488,0.00007930103,0.3505023,0.00001610808,0.00016473621,0.00041393333,0.000019011584,0.002272625,0.0025831566],"genre_scores_gemma":[0.9969007,0.000032489985,0.0026319742,0.00001756613,0.000016808364,0.000090932124,0.000040858296,0.000043630163,0.00022507866],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991729,0.0000056836748,0.00023370395,0.00017400461,0.0000799737,0.00033371005],"domain_scores_gemma":[0.99964595,0.0001439857,0.00001900015,0.0001273266,0.000019301106,0.0000444421],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023791398,0.00013512875,0.0001662552,0.00020893813,0.000040059385,0.00007123829,0.000081070095,0.0000931908,0.00003114533],"category_scores_gemma":[0.000055890356,0.00013954945,0.00004960156,0.00018791233,0.000012631123,0.00023548018,0.00001954816,0.000112154405,0.00003112],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018593657,0.00014154793,0.05353112,0.0012648089,0.00025932826,0.00026341557,0.008891594,0.04196022,0.65328485,0.0048407707,0.025358671,0.21001771],"study_design_scores_gemma":[0.0010497378,0.00024158246,0.0071243015,0.0004744575,0.000014045192,0.000021503429,0.00097122707,0.96997803,0.016044078,0.0027855928,0.0005520068,0.0007434432],"about_ca_topic_score_codex":0.000008400271,"about_ca_topic_score_gemma":0.000008737597,"teacher_disagreement_score":0.9280178,"about_ca_system_score_codex":0.000118552896,"about_ca_system_score_gemma":0.000010600671,"threshold_uncertainty_score":0.5690661},"labels":[],"label_agreement":null},{"id":"W4384833499","doi":"10.1145/3597031.3597054","title":"Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-Clustering","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Computer science; Generality; Design flow; CAD; Limiting; Electronic design automation; Cluster analysis; Block (permutation group theory); Embedded system; Engineering drawing; Engineering; Artificial intelligence","score_opus":0.0328468532435029,"score_gpt":0.2516286160893555,"score_spread":0.2187817628458526,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4384833499","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.027825765,0.00035674617,0.9444542,0.00009286541,0.00016317733,0.0003457025,0.0000065715008,0.009122417,0.01763257],"genre_scores_gemma":[0.9000978,0.00012310068,0.09830385,0.000057827994,0.000051337232,0.000049239774,0.000008680372,0.00008496364,0.0012232065],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99916244,0.0000089106725,0.00016144174,0.00020404797,0.000114503,0.0003486692],"domain_scores_gemma":[0.9996593,0.000036771136,0.000017707242,0.00018892069,0.000021242215,0.00007604826],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001427359,0.00018351151,0.00018640854,0.00016094776,0.00018950205,0.0002699717,0.000097102165,0.000086938424,0.00003872512],"category_scores_gemma":[0.000008634893,0.00015980417,0.000022877119,0.0003100362,0.000073506075,0.00023541378,0.00006528582,0.00014716286,0.000023033106],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020842064,0.0001365566,0.008540835,0.0039092954,0.001336864,0.0008686568,0.035716407,0.26050928,0.26684755,0.0037677062,0.041628957,0.37652948],"study_design_scores_gemma":[0.0010805374,0.00014397723,0.0012799959,0.00040841493,0.00004868046,0.0000950371,0.0014981953,0.8794406,0.10335124,0.0002166037,0.011499971,0.00093673426],"about_ca_topic_score_codex":0.00012384084,"about_ca_topic_score_gemma":0.00012519823,"teacher_disagreement_score":0.872272,"about_ca_system_score_codex":0.000039682734,"about_ca_system_score_gemma":0.000015327489,"threshold_uncertainty_score":0.65166247},"labels":[],"label_agreement":null},{"id":"W4385831788","doi":"10.1109/icet58434.2023.10211575","title":"A Partitioning Algorithm Based-on Vertex-degree of Undirected Graph for VLSI Circuit Simulations","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"National Natural Science Foundation of China","keywords":"Very-large-scale integration; Graph partition; Adjacency list; Partition (number theory); Algorithm; Computer science; Electronic circuit; Vertex (graph theory); Cluster analysis; Breadth-first search; Undirected graph; Graph; Mathematics; Theoretical computer science; Combinatorics","score_opus":0.04946002213238111,"score_gpt":0.2583337447833242,"score_spread":0.20887372265094312,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4385831788","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004126995,0.000015597167,0.9855891,0.00002569491,0.0001205633,0.00031945363,0.00011658074,0.0024592588,0.007226787],"genre_scores_gemma":[0.9895502,0.0000070882256,0.010003914,0.000027928369,0.000024284973,0.0000830876,0.000106963125,0.000032167023,0.00016439016],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99944735,0.000009239504,0.00016537352,0.00010586944,0.00010032172,0.00017187673],"domain_scores_gemma":[0.9995198,0.00021908995,0.00001659417,0.00015662124,0.000051574203,0.00003632069],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008256108,0.00009174524,0.00012274849,0.00024550597,0.00005303631,0.0000132196765,0.0000675328,0.000064145475,0.00008927984],"category_scores_gemma":[0.000035570265,0.000093262344,0.000074096446,0.00049625715,0.000014688512,0.000057163692,0.000005354462,0.000051909163,0.00001610967],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016255317,0.00019751875,0.0013258233,0.00043415301,0.00021471748,0.000010473677,0.00036754366,0.5648267,0.05286866,0.0148755545,0.044773594,0.32008898],"study_design_scores_gemma":[0.000226209,0.00007788566,0.00095631566,0.000042101386,0.000014412987,2.5517676e-7,0.000012327351,0.9617116,0.029563678,0.0065850075,0.00068629597,0.0001239408],"about_ca_topic_score_codex":0.000009579453,"about_ca_topic_score_gemma":0.000010054444,"teacher_disagreement_score":0.9854232,"about_ca_system_score_codex":0.00001628241,"about_ca_system_score_gemma":0.000009914835,"threshold_uncertainty_score":0.3803128},"labels":[],"label_agreement":null},{"id":"W4385834439","doi":"10.1109/tcad.2023.3305579","title":"ILPGRC: ILP-Based Global Routing Optimization With Cell Movements","year":2023,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Conselho Nacional de Desenvolvimento Científico e Tecnológico; Natural Sciences and Engineering Research Council of Canada; Coordenação de Aperfeiçoamento de Pessoal de Nível Superior","keywords":"Routing (electronic design automation); Computer science; Scalability; Integer programming; Speedup; Convergence (economics); Mathematical optimization; Parallel computing; Electronic circuit; Distributed computing; Algorithm; Mathematics; Embedded system; Engineering","score_opus":0.02085004310382225,"score_gpt":0.20937510457765235,"score_spread":0.1885250614738301,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4385834439","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0075586545,0.000060524737,0.98964596,0.0000045510933,0.00051647495,0.00064426695,0.00009121276,0.0011840307,0.00029432325],"genre_scores_gemma":[0.9935609,0.000056019566,0.0061225034,0.000022668608,0.000030431813,0.000082777115,0.000020113286,0.000049371814,0.000055230128],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99851173,0.00011829616,0.00047991896,0.0003021255,0.0002774036,0.00031049925],"domain_scores_gemma":[0.99926233,0.00011594111,0.0000984821,0.00024839616,0.00016849862,0.00010632064],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00028382358,0.00030936688,0.0003826385,0.00028286074,0.00012223274,0.00010908029,0.00016021827,0.00016748362,0.000009283526],"category_scores_gemma":[0.0000014715196,0.00026584746,0.00006479249,0.0008738922,0.000041575244,0.00014272527,8.281798e-7,0.0001919035,0.000008245724],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00001721458,0.000059305657,0.0000215216,0.00014526327,0.000080646045,0.000013133784,0.00008431612,0.9810614,0.006143787,0.000023728058,0.00022898015,0.012120694],"study_design_scores_gemma":[0.00067162194,0.00048410383,0.00001637162,0.00043226202,0.000034370183,0.000012323929,0.00012359582,0.9673061,0.030615794,0.000009756539,0.000021268837,0.00027246878],"about_ca_topic_score_codex":0.00011231748,"about_ca_topic_score_gemma":0.0000029054402,"teacher_disagreement_score":0.9860022,"about_ca_system_score_codex":0.00013717095,"about_ca_system_score_gemma":0.00006146172,"threshold_uncertainty_score":0.9999794},"labels":[],"label_agreement":null},{"id":"W4386159713","doi":"10.1109/iseda59274.2023.10218622","title":"A Multi-Objective Optimization Algorithm Based on Deep Learning for Circuit Partition","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Partition (number theory); Computer science; Algorithm; Partition problem; Graph; Theoretical computer science; Mathematics","score_opus":0.021871157752923785,"score_gpt":0.24099475528251896,"score_spread":0.21912359752959518,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4386159713","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0001118776,0.0000071085356,0.9947055,0.000011923581,0.000074943855,0.00031168584,0.000003952725,0.0027900457,0.0019829639],"genre_scores_gemma":[0.70674187,0.000035871566,0.2916613,0.00008156996,0.00009742926,0.00058357086,0.00023007551,0.0000798412,0.00048846845],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995336,0.000015403975,0.00009622673,0.00012123474,0.00007154131,0.00016202325],"domain_scores_gemma":[0.99976856,0.00007773624,0.00001284689,0.000073214076,0.0000378232,0.000029828248],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012511163,0.00008748248,0.00008055844,0.00014283638,0.000065193686,0.000023998215,0.000038502774,0.000069519716,0.000054020078],"category_scores_gemma":[0.000040776253,0.0000896793,0.000043655138,0.00022346247,0.000006189365,0.00007322998,0.0000039395172,0.000077255245,0.000037989463],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000001992853,0.000010528979,0.000020638714,0.000016597724,0.0000068619647,0.0000010750351,0.00007147073,0.9467878,0.0010674545,0.00004114165,0.0003602023,0.051614262],"study_design_scores_gemma":[0.00027282705,0.000086473294,0.00016741424,0.000015378146,0.0000061670607,2.7671234e-7,0.000047131165,0.9880563,0.010832527,0.0001110746,0.0002879965,0.000116460826],"about_ca_topic_score_codex":0.0000033034755,"about_ca_topic_score_gemma":0.0000017569907,"teacher_disagreement_score":0.70663,"about_ca_system_score_codex":0.000051729003,"about_ca_system_score_gemma":0.000004477499,"threshold_uncertainty_score":0.36570156},"labels":[],"label_agreement":null},{"id":"W4386828169","doi":"10.1007/s11590-023-02058-w","title":"Approximation algorithm for solving the 1-line Steiner tree problem with minimum number of Steiner points","year":2023,"lang":"en","type":"article","venue":"Optimization Letters","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Steiner tree problem; Combinatorics; Mathematics; Line (geometry); Constant (computer programming); Approximation algorithm; Line segment; Discrete mathematics; Euclidean geometry; Point (geometry); Tree (set theory); Computer science; Geometry","score_opus":0.010013078112781465,"score_gpt":0.21826461661679858,"score_spread":0.20825153850401712,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4386828169","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003611537,0.000008017506,0.9938135,0.000976509,0.00005107688,0.0005948229,0.000017257766,0.00049230683,0.00043493923],"genre_scores_gemma":[0.06283027,0.000033441032,0.93534493,0.00040441353,0.00015690847,0.00040985644,0.00028180855,0.00011531166,0.00042305383],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992877,0.00001536145,0.00023049625,0.00013233256,0.00015292042,0.00018117852],"domain_scores_gemma":[0.999583,0.000079257064,0.000067677596,0.00017364325,0.000073263065,0.000023152686],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019094875,0.00013196432,0.0001377095,0.000088857014,0.0000554327,0.00003259591,0.00011089115,0.00005233521,0.00002444819],"category_scores_gemma":[0.000011056373,0.0000943978,0.000042933327,0.00037081738,0.000031961274,0.00018388507,0.000014023877,0.00006356356,0.00000649018],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008950278,0.000013848582,0.000077816505,0.00010439488,0.000055874654,0.0000010354047,0.00038149298,0.9594408,0.007830255,0.000086984786,0.013214764,0.01878378],"study_design_scores_gemma":[0.00040030174,0.000030257284,0.000024240322,0.000047583148,0.000025271343,0.0000031315897,0.000054794175,0.9909074,0.007986117,0.000034760338,0.0003506655,0.00013549799],"about_ca_topic_score_codex":0.0000032881746,"about_ca_topic_score_gemma":0.0000012145283,"teacher_disagreement_score":0.059218735,"about_ca_system_score_codex":0.000025232037,"about_ca_system_score_gemma":0.0000067395986,"threshold_uncertainty_score":0.38494307},"labels":[],"label_agreement":null},{"id":"W4387123818","doi":"10.1109/sbcci60457.2023.10261650","title":"FPGA Placement: Dynamic Decision Making Via Machine Learning","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Netlist; Field-programmable gate array; Computer science; Placement; Set (abstract data type); Design flow; Multi-core processor; Parallel computing; Central processing unit; Embedded system; Computer architecture; Computer engineering; Physical design; Computer hardware; Circuit design","score_opus":0.00851885835249342,"score_gpt":0.24872406537069874,"score_spread":0.24020520701820533,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4387123818","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.02998677,0.00027664672,0.94821566,0.000016292764,0.0001768161,0.00013851243,0.0000022611387,0.006169664,0.015017365],"genre_scores_gemma":[0.9916684,0.00016084498,0.0073647476,0.000023014712,0.000020279156,0.000016330585,0.000017098402,0.000045345016,0.000683938],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993377,0.000011560536,0.00015325268,0.00012827972,0.00013647786,0.00023274058],"domain_scores_gemma":[0.9997316,0.00007945555,0.000012591672,0.0001335043,0.000010359239,0.00003250823],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001794657,0.00011803328,0.00010757879,0.0001876903,0.00006875151,0.000032054606,0.00011143473,0.000063997184,0.0003533443],"category_scores_gemma":[0.000017555614,0.00011021577,0.000040696556,0.00031207537,0.0000070835554,0.000082065155,0.00005070778,0.00017105318,0.0005101715],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015708269,0.000012624768,0.0009086154,0.000063765394,0.000058702488,0.00005797405,0.00026270817,0.09855361,0.04235755,0.00021706594,0.0066133747,0.8508783],"study_design_scores_gemma":[0.00012514545,0.000034187004,0.00053747644,0.00005343078,0.000007622499,0.0000075552775,0.000028203474,0.9862588,0.0065656267,0.0012982116,0.0048949877,0.00018877175],"about_ca_topic_score_codex":0.0000044827316,"about_ca_topic_score_gemma":0.000014339179,"teacher_disagreement_score":0.9616816,"about_ca_system_score_codex":0.00004508334,"about_ca_system_score_gemma":0.0000023950258,"threshold_uncertainty_score":0.6557393},"labels":[],"label_agreement":null},{"id":"W4387164718","doi":"10.1109/tcad.2023.3320984","title":"Statistical Hardware Design With Multimodel Active Learning","year":2023,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University; Polytechnique Montréal","funders":"","keywords":"Computer science; Design space exploration; Field-programmable gate array; Machine learning; Bayesian optimization; Computer engineering; Hardware architecture; Statistical model; Artificial intelligence; Computer hardware; Embedded system; Software","score_opus":0.036241633955858256,"score_gpt":0.23054797562275114,"score_spread":0.1943063416668929,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4387164718","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0033298722,0.00006207989,0.9938102,0.0000045285706,0.00034771618,0.0007754101,0.000104517705,0.0014692218,0.00009644777],"genre_scores_gemma":[0.98772776,0.00014782291,0.011698382,0.000007737554,0.000034279867,0.00016401078,0.000016794253,0.00008310113,0.000120101184],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982064,0.00030347073,0.00045669393,0.00036663626,0.00029383623,0.00037295689],"domain_scores_gemma":[0.9987193,0.0006304283,0.00007808849,0.00022365976,0.00019972364,0.00014881461],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003746488,0.0003626685,0.00053131196,0.00045458856,0.00016494593,0.000101006226,0.0001613771,0.00020002405,0.000014905992],"category_scores_gemma":[0.0000062955364,0.00029840012,0.00005818511,0.000587277,0.00008425474,0.00017673553,0.000001129628,0.000522372,0.000023010776],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000057646223,0.00004652828,0.0000035980581,0.00012764768,0.00020736133,0.00004201152,0.00049076014,0.8985805,0.012233784,0.000082297,0.0005589223,0.08756896],"study_design_scores_gemma":[0.00056270004,0.0009586558,0.000030850017,0.00044438642,0.000055096596,0.000059075195,0.0003383355,0.9670008,0.030097064,0.000042007283,0.000068873596,0.0003421452],"about_ca_topic_score_codex":0.00009357108,"about_ca_topic_score_gemma":0.0000021182148,"teacher_disagreement_score":0.9843979,"about_ca_system_score_codex":0.00009875345,"about_ca_system_score_gemma":0.00006875888,"threshold_uncertainty_score":0.99994683},"labels":[],"label_agreement":null},{"id":"W4388214731","doi":"10.1109/fpl60245.2023.00016","title":"Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; Intel Corporation","keywords":"Stratix; Titan (rocket family); Computer science; Field-programmable gate array; Architecture; Computer architecture; Embedded system; Benchmarking; Parallel computing; Memory footprint; Operating system; Engineering","score_opus":0.024588631513883373,"score_gpt":0.2565920021842202,"score_spread":0.2320033706703368,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4388214731","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.063868634,0.00032010122,0.84371734,0.00024442712,0.000075817836,0.0010319772,0.000008591692,0.004670202,0.086062886],"genre_scores_gemma":[0.99261194,0.000018527136,0.0049093137,0.00008138237,0.00005443165,0.000114454626,0.00003237065,0.000058574467,0.0021189884],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992626,0.00002324746,0.00010144348,0.00016832145,0.00023190647,0.00021250513],"domain_scores_gemma":[0.9996405,0.000025092888,0.000012959298,0.0002244912,0.000045040662,0.000051872776],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00029220074,0.000131322,0.00012038059,0.00012595429,0.000054612985,0.00009496337,0.00021568756,0.00008337902,0.00009935048],"category_scores_gemma":[0.000013691154,0.00009948749,0.000021555445,0.00035619127,0.000011231827,0.000118142954,0.000046515517,0.00017162484,0.000050524934],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000026150652,0.000021023368,0.00027208767,0.00011875768,0.00011897806,0.000027992312,0.0046403413,0.5990671,0.04833473,0.00059120357,0.026499394,0.32028228],"study_design_scores_gemma":[0.00053673104,0.00006937253,0.0002928916,0.00009030369,0.000045580637,0.000027124503,0.00033940826,0.9622995,0.01685661,0.0048167696,0.014185991,0.0004396905],"about_ca_topic_score_codex":0.00007934555,"about_ca_topic_score_gemma":0.00013638703,"teacher_disagreement_score":0.9287433,"about_ca_system_score_codex":0.000049806593,"about_ca_system_score_gemma":0.000022431239,"threshold_uncertainty_score":0.40569824},"labels":[],"label_agreement":null},{"id":"W4388214753","doi":"10.1109/fpl60245.2023.00026","title":"Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Router; Routing (electronic design automation); Static routing; Field-programmable gate array; Distributed computing; Computer network; Embedded system; Parallel computing; Routing protocol","score_opus":0.013278907193128237,"score_gpt":0.2267734085530284,"score_spread":0.21349450135990017,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4388214753","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.61937827,0.00016375638,0.3625895,0.0020611864,0.00022665848,0.0011018453,0.000008784822,0.0026877332,0.011782244],"genre_scores_gemma":[0.99807847,0.00003190319,0.0010276869,0.0001329201,0.00002925111,0.000040444258,0.0000023607424,0.00002092703,0.000636041],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995418,0.000010957412,0.00011539962,0.0001087481,0.000047164915,0.00017592649],"domain_scores_gemma":[0.99969333,0.00014214808,0.0000090444,0.00011024287,0.000013397872,0.00003182195],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003028366,0.00008888242,0.000089511064,0.000050192237,0.000066804634,0.000058616228,0.00007000101,0.00004730915,0.000011608153],"category_scores_gemma":[0.000026278647,0.000057039088,0.000023436527,0.000090490656,0.000026298487,0.000026284364,0.00004956422,0.00007985629,0.000008545141],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010883279,0.00007924588,0.0016056398,0.0012362315,0.00054079934,0.00002313855,0.023466704,0.014107222,0.11489103,0.05456452,0.18960331,0.59977335],"study_design_scores_gemma":[0.00040549398,0.00006723405,0.00077816175,0.000054306223,0.000027180246,0.000011084049,0.00056314096,0.9606718,0.022883728,0.001203718,0.013090212,0.00024393777],"about_ca_topic_score_codex":0.000018308137,"about_ca_topic_score_gemma":0.000010415795,"teacher_disagreement_score":0.94656456,"about_ca_system_score_codex":0.000011939415,"about_ca_system_score_gemma":0.0000023024566,"threshold_uncertainty_score":0.23259865},"labels":[],"label_agreement":null},{"id":"W4389166704","doi":"10.1109/iccad57390.2023.10323720","title":"Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":34,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"University of Toronto","keywords":"Computer science; Reinforcement learning; Network topology; Graph; Dropout (neural networks); Circuit design; Computer engineering; Artificial intelligence; Machine learning; Theoretical computer science; Embedded system","score_opus":0.021850919234680445,"score_gpt":0.24247644395358456,"score_spread":0.22062552471890412,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4389166704","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1254674,0.00008562863,0.8735729,0.000007193177,0.00002040646,0.0003414462,1.9088074e-7,0.00028582985,0.00021903003],"genre_scores_gemma":[0.9700903,0.000079487996,0.02957264,0.000010536736,0.000018334651,0.000016883458,0.0000112409925,0.000028213406,0.00017233843],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993267,0.000027929676,0.00023968809,0.00013701955,0.00010523648,0.000163398],"domain_scores_gemma":[0.99976325,0.000058588354,0.00004527548,0.00006834783,0.000028490376,0.00003603687],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003465151,0.000104785395,0.00014572643,0.00014738264,0.000065527674,0.000042078875,0.00006610595,0.00007029804,0.000018187433],"category_scores_gemma":[0.00001864985,0.000106241474,0.000010921636,0.00043768962,0.0000283271,0.00028305477,0.000059860857,0.000106192594,3.37397e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011582372,0.0000024709473,0.0037942478,0.00006994074,0.00000783667,0.0000014534921,0.00022109885,0.9935003,0.0013304992,0.00019287196,0.000078905985,0.0007887751],"study_design_scores_gemma":[0.00024060954,0.000033941076,0.00077406375,0.000100687445,0.000005947842,0.0000035967628,0.00006768594,0.99697864,0.0013882868,0.00027430936,0.000011697075,0.0001205381],"about_ca_topic_score_codex":0.000014773897,"about_ca_topic_score_gemma":0.000001134202,"teacher_disagreement_score":0.8446229,"about_ca_system_score_codex":0.000019371964,"about_ca_system_score_gemma":0.000011463927,"threshold_uncertainty_score":0.43324018},"labels":[],"label_agreement":null},{"id":"W4390490815","doi":"10.1145/3639055","title":"Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm","year":2024,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Tile; Field-programmable gate array; Computer science; Parallel computing; Computer architecture; Materials science; Embedded system; Composite material","score_opus":0.08032565914206566,"score_gpt":0.33076737371923914,"score_spread":0.25044171457717346,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4390490815","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.92347354,0.0009658765,0.07354131,0.0001822993,0.00018126646,0.000996275,0.00010946987,0.0003196974,0.00023028674],"genre_scores_gemma":[0.99931955,0.00003920117,0.00028900197,0.0000050575695,0.000008773943,0.00026888572,0.000002450578,0.000026587013,0.000040459774],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99905676,0.000054190015,0.0003933872,0.00018545878,0.00009672577,0.00021348422],"domain_scores_gemma":[0.99854165,0.0008858006,0.000061206316,0.0004444066,0.000049311348,0.000017650751],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0006889818,0.00017867901,0.00031056284,0.00053106976,0.00010456306,0.000022540307,0.00024076803,0.00026112038,0.000027024387],"category_scores_gemma":[0.000077976365,0.000109478664,0.00013876133,0.0005178342,0.00010014389,0.00004903173,0.0000017693219,0.00038797583,0.0000010331471],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000803116,0.00007647943,0.00047594652,0.0004057256,0.00032058873,0.0000030400938,0.0003067364,0.7992254,0.16051757,0.00045503327,0.00007890054,0.038054254],"study_design_scores_gemma":[0.0003171213,0.00044404026,0.000047684258,0.00059866474,0.000054450375,0.000021361879,0.00040503877,0.9007335,0.09655027,0.00067500334,0.000030811552,0.00012205248],"about_ca_topic_score_codex":0.00017948194,"about_ca_topic_score_gemma":0.000026290318,"teacher_disagreement_score":0.10150808,"about_ca_system_score_codex":0.00007115125,"about_ca_system_score_gemma":0.000053644846,"threshold_uncertainty_score":0.44644102},"labels":[],"label_agreement":null},{"id":"W4390576950","doi":"10.1137/1.9781611977912.22","title":"Fast Algorithms for Directed Graph Partitioning Using Flows and Reweighted Eigenvalues","year":2024,"lang":"en","type":"book-chapter","venue":"Society for Industrial and Applied Mathematics eBooks","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Semidefinite programming; Eigenvalues and eigenvectors; Multiplicative function; Algorithm; Directed graph; Relaxation (psychology); Mathematics; Vertex (graph theory); Computer science; Linear programming; Combinatorics; Mathematical optimization; Graph; Discrete mathematics","score_opus":0.06993008728173788,"score_gpt":0.24925096009821698,"score_spread":0.1793208728164791,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4390576950","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0033629185,0.0047954046,0.5408971,0.000055694207,0.0019046472,0.01670017,0.0041502877,0.007942234,0.4201916],"genre_scores_gemma":[0.002672291,0.00086099777,0.8937264,0.00008523369,0.004788145,0.0021913762,0.0006669089,0.0012510563,0.09375756],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.99875134,0.0000013828637,0.00046723863,0.0003390368,0.00014455136,0.0002964206],"domain_scores_gemma":[0.9994345,0.00015448614,0.000108119995,0.00016027194,0.000047706213,0.00009493186],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00025089268,0.00045330822,0.0005928828,0.00007347481,0.00023607306,0.0001551665,0.000084378706,0.0008559326,0.000006323767],"category_scores_gemma":[0.0000056537165,0.000427796,0.00036207476,0.000023072122,0.000111289446,0.000026444677,0.000051629966,0.0003982363,9.559548e-7],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000042725285,0.000028901706,1.4888401e-7,0.0060902853,0.002665432,0.0000025588956,0.0045716097,0.000105213476,0.014919475,0.868541,0.018216442,0.0848162],"study_design_scores_gemma":[0.0010405683,0.00009285621,1.7350024e-8,0.0011828223,0.0011733792,0.000012411237,0.0002803773,0.08448032,0.008861408,0.8695408,0.032361716,0.0009733303],"about_ca_topic_score_codex":0.000001271056,"about_ca_topic_score_gemma":0.0000011234417,"teacher_disagreement_score":0.35282937,"about_ca_system_score_codex":0.00005398536,"about_ca_system_score_gemma":0.000028643559,"threshold_uncertainty_score":0.9998174},"labels":[],"label_agreement":null},{"id":"W4390606148","doi":"10.1109/icm60448.2023.10378891","title":"An Adaptive Analytical FPGA Placement flow based on Reinforcement Learning","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Reinforcement learning; Computer science; Placement; Reduction (mathematics); Gate array; State (computer science); Computer engineering; Embedded system; Computer architecture; Parallel computing; Artificial intelligence; Physical design; Algorithm; Circuit design","score_opus":0.022423305879259857,"score_gpt":0.252283605503137,"score_spread":0.22986029962387713,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4390606148","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003488744,0.000005830993,0.89965147,0.00005746142,0.000089214365,0.00026451927,0.0000019432782,0.004438105,0.0920027],"genre_scores_gemma":[0.995941,0.000009030282,0.0029220325,0.00010663527,0.000047855334,0.000043767322,0.000039997776,0.000029742001,0.0008599584],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99919933,0.000022864171,0.00015014216,0.00015177808,0.00021795445,0.00025791785],"domain_scores_gemma":[0.99963677,0.0000486569,0.000009650572,0.00019053489,0.00001843687,0.00009595046],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021301363,0.00013379777,0.000117734875,0.00017693988,0.000053167772,0.00002924481,0.000095042786,0.00006217137,0.00053798],"category_scores_gemma":[0.000011252671,0.00012097916,0.00004513536,0.0002434809,0.000011834597,0.000067627996,0.000012938838,0.00016661767,0.00029959227],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019487945,0.000010976113,0.000029521336,0.0000069045277,0.000018076638,0.000010579867,0.000050803006,0.9842749,0.00046530442,0.0006034496,0.0064559104,0.008054062],"study_design_scores_gemma":[0.00017745902,0.00058618217,0.000094076735,0.00001811599,0.000010052274,2.5119573e-7,0.000107648004,0.9862375,0.010589211,0.0000314564,0.001987316,0.00016071858],"about_ca_topic_score_codex":0.0000059646,"about_ca_topic_score_gemma":0.0000017282628,"teacher_disagreement_score":0.99245226,"about_ca_system_score_codex":0.00007589869,"about_ca_system_score_gemma":0.000010245566,"threshold_uncertainty_score":0.58905035},"labels":[],"label_agreement":null},{"id":"W4391382572","doi":"10.1109/mwscas57524.2023.10405922","title":"Design Space Exploration in the Physical-Design of an AI-Processor at 12 nm Using Relative-Placement Methodology","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"CMC Microsystems","keywords":"Macro; Placement; Computer science; Reduction (mathematics); Electronic design automation; Physical design; Computer Aided Design; Engineering drawing; Computer hardware; Embedded system; Circuit design; Engineering; Operating system; Mathematics; Programming language; Geometry","score_opus":0.2686630754760615,"score_gpt":0.36424553999559367,"score_spread":0.09558246451953217,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4391382572","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.028202817,0.000021331793,0.97027904,0.00011743932,0.000035512425,0.00050406123,0.0000011052236,0.00040314248,0.0004355814],"genre_scores_gemma":[0.7589042,0.000045579713,0.24061316,0.000052755346,0.00004747141,0.0001305501,0.000009180672,0.000039343846,0.00015772872],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987151,0.0005507614,0.0002036229,0.00016413211,0.0001587455,0.00020764011],"domain_scores_gemma":[0.99916196,0.0005295623,0.000042531978,0.00021109814,0.000030344989,0.000024527677],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0013615283,0.00013919071,0.00020825992,0.00015455885,0.00004777576,0.000014278157,0.00015346726,0.000081338156,0.000017923321],"category_scores_gemma":[0.00006001088,0.00010345468,0.000029621127,0.00045402325,0.000030604788,0.00039725972,0.000024601826,0.00013113588,0.000016125003],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000040155956,0.000036415982,0.00001138069,0.00004138209,0.000020048792,0.0000055207793,0.0075111724,0.521343,0.46708757,0.0015134852,0.0008563679,0.0015334971],"study_design_scores_gemma":[0.00014958168,0.00015086634,0.000035555953,0.000016105249,0.0000148499785,0.0000018783526,0.00071331393,0.6524447,0.33699536,0.00932909,0.000035389177,0.00011326804],"about_ca_topic_score_codex":0.000018125638,"about_ca_topic_score_gemma":0.000007530632,"teacher_disagreement_score":0.7307014,"about_ca_system_score_codex":0.00007501132,"about_ca_system_score_gemma":0.000014305062,"threshold_uncertainty_score":0.42187592},"labels":[],"label_agreement":null},{"id":"W4391429101","doi":"10.1109/icfpt59805.2023.00006","title":"A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Computer science; Routing (electronic design automation); Field-programmable gate array; Deep learning; Parallel computing; Artificial intelligence; Computer network; Embedded system","score_opus":0.03938491760042639,"score_gpt":0.26235862266096266,"score_spread":0.22297370506053626,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4391429101","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.002238886,0.0000881547,0.9690752,0.000018812229,0.000080906386,0.00032690167,0.0000065316826,0.0055687767,0.022595806],"genre_scores_gemma":[0.8223539,0.000056580226,0.17563516,0.0000148309755,0.00018944043,0.00009402991,0.00036201955,0.00007867825,0.0012153403],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990738,0.000016223654,0.00019402785,0.000272733,0.00009307049,0.0003501473],"domain_scores_gemma":[0.9994556,0.00009520879,0.000022513519,0.00035720746,0.000021531776,0.000047957183],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00039065187,0.0001379205,0.000171661,0.00012680836,0.00012519294,0.000071591465,0.0003286283,0.00008159251,0.000026212714],"category_scores_gemma":[0.00008666842,0.00013356052,0.000046655776,0.0002950097,0.000012208543,0.0002160174,0.00013451336,0.00016363518,0.00003597283],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008192669,0.00003077889,0.0005093593,0.00048509502,0.00020263717,0.000008705655,0.0017017581,0.68063074,0.019532742,0.0016254829,0.054072827,0.2411917],"study_design_scores_gemma":[0.00010593843,0.000018946183,0.00006653871,0.000020090585,0.000016027412,0.000003210878,0.00036278536,0.9930926,0.0037596575,0.000078697994,0.0022907793,0.00018474636],"about_ca_topic_score_codex":0.000015947815,"about_ca_topic_score_gemma":0.0000011545442,"teacher_disagreement_score":0.82011503,"about_ca_system_score_codex":0.000026430795,"about_ca_system_score_gemma":0.0000070977176,"threshold_uncertainty_score":0.544644},"labels":[],"label_agreement":null},{"id":"W4391455291","doi":"10.1109/icfpt59805.2023.00027","title":"Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer architecture; Computer science; Field-programmable gate array; Design space exploration; Reconfigurable computing; Embedded system; Three-dimensional integrated circuit; Electronic design automation; Chip; Telecommunications","score_opus":0.047513085848725684,"score_gpt":0.26145033658670025,"score_spread":0.21393725073797457,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4391455291","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.033166938,0.00023026395,0.9304153,0.0031550454,0.0004901401,0.0014258828,0.0000057374173,0.004719079,0.026391638],"genre_scores_gemma":[0.9744559,0.00022621042,0.02228691,0.00042039278,0.00027516772,0.0007326147,0.00013679395,0.000045200104,0.0014207893],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995123,0.000015492064,0.00014184181,0.00011042676,0.000081044054,0.00013889579],"domain_scores_gemma":[0.99959373,0.00016831668,0.000016419683,0.00016274439,0.00003800268,0.00002078363],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021741538,0.00009540236,0.000084083505,0.00006167413,0.0001367198,0.00015196651,0.00010054727,0.00006824407,0.000042453594],"category_scores_gemma":[0.000035237255,0.00006279146,0.000036050285,0.00019978953,0.000009010415,0.00044081573,0.000008397891,0.0000815225,0.00006521111],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015873355,0.0000085794145,0.000017326813,0.00013400128,0.000045076915,0.0000013726124,0.004366673,0.028476993,0.11114898,0.003293502,0.108144715,0.7443469],"study_design_scores_gemma":[0.00027098774,0.00014430111,0.00023151512,0.000060472623,0.000026714966,0.000003422402,0.0011282323,0.20378017,0.514943,0.026603961,0.25238413,0.00042305482],"about_ca_topic_score_codex":0.000011692275,"about_ca_topic_score_gemma":0.00009453149,"teacher_disagreement_score":0.941289,"about_ca_system_score_codex":0.00001824013,"about_ca_system_score_gemma":0.000007100245,"threshold_uncertainty_score":0.25605616},"labels":[],"label_agreement":null},{"id":"W4392605854","doi":"10.1007/978-3-031-52113-3_5","title":"Fractional Bamboo Trimming and Distributed Windows Scheduling","year":2024,"lang":"en","type":"book-chapter","venue":"Lecture notes in computer science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia; Simon Fraser University","funders":"","keywords":"Computer science; Trimming; Bamboo; Scheduling (production processes); Parallel computing; Distributed computing; Operating system; Mathematical optimization; Mathematics; Composite material","score_opus":0.011523361404668742,"score_gpt":0.22604654121482046,"score_spread":0.2145231798101517,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4392605854","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00013169684,0.002370167,0.99327695,0.00006806071,0.000818665,0.00016605524,0.000022011962,0.00048583283,0.0026605632],"genre_scores_gemma":[0.81884307,0.00032333843,0.17913574,0.00021988829,0.001085621,0.000015746951,0.00003770394,0.000106476415,0.00023241136],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986586,0.0000037297382,0.00024540385,0.0004998896,0.00030554424,0.0002868439],"domain_scores_gemma":[0.9994287,0.00017316506,0.000033912143,0.00024058844,0.00004402635,0.000079618585],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002432436,0.00030203242,0.00027285624,0.0004184334,0.00008790869,0.00023318792,0.0003044828,0.0002626677,0.000021616112],"category_scores_gemma":[0.000021415774,0.00028844524,0.000056827786,0.0001980196,0.00021099213,0.00018125647,0.0001556586,0.000797935,0.000018481018],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000005840602,0.000009541141,0.00007199898,0.00037641506,0.00005539198,0.00019023968,0.00033366316,0.34414062,0.0033055467,0.009303421,0.00010063008,0.6421067],"study_design_scores_gemma":[0.00009873423,0.00004142116,0.00004247771,0.0007583884,0.000018056424,0.00009112509,2.1127674e-7,0.8756948,0.003480269,0.11466939,0.004589477,0.00051564764],"about_ca_topic_score_codex":0.00000381105,"about_ca_topic_score_gemma":0.0000053131607,"teacher_disagreement_score":0.8187114,"about_ca_system_score_codex":0.00017562685,"about_ca_system_score_gemma":0.000063114014,"threshold_uncertainty_score":0.9999568},"labels":[],"label_agreement":null},{"id":"W4393520386","doi":"10.5281/zenodo.7240327","title":"Koios benchmarks' netlist files (BLIF format)","year":2022,"lang":"en","type":"dataset","venue":"Zenodo (CERN European Organization for Nuclear Research)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Toronto","funders":"National Science Foundation","keywords":"Netlist; Computer science; Programming language; Computer hardware","score_opus":0.01939754294858081,"score_gpt":0.21663053638278154,"score_spread":0.19723299343420073,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4393520386","genre_codex":"dataset","genre_gemma":"dataset","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"dataset","genre_consensus":"dataset","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000016757813,0.0003106187,0.00075908186,0.00004969433,0.00027118498,0.000529188,0.9581783,0.0024749544,0.037410215],"genre_scores_gemma":[0.00034211707,0.0012773267,0.000102789854,0.000093819974,0.00021302982,3.3109143e-7,0.9959349,0.0018207817,0.0002148956],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9979625,0.00020689951,0.00039024302,0.00040370994,0.00051671354,0.00051998533],"domain_scores_gemma":[0.99863356,0.00002780964,0.000102043996,0.0008705192,0.00017579908,0.00019024078],"candidate_categories":["metaepi_narrow","sts","insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.00050225196,0.00033411858,0.0002973352,0.0005062102,0.001687029,0.00085391913,0.001956449,0.00020065297,0.39307854],"category_scores_gemma":[0.00019727732,0.0003847445,0.00010630627,0.000571466,0.00009715702,0.0002765047,0.0015354683,0.0009301916,0.004046075],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010434858,0.00004554036,2.516323e-8,0.00026751743,0.00005568486,0.00003150417,0.000092325274,0.00012407755,0.00012613535,0.000088859066,0.9861973,0.012960622],"study_design_scores_gemma":[0.00017200517,0.00015948352,0.0000043928717,0.00003738637,0.000030262952,0.00011944135,0.00007494201,0.00030823538,0.00008981953,0.00006113719,0.9985357,0.00040720514],"about_ca_topic_score_codex":0.000030945623,"about_ca_topic_score_gemma":7.3738147e-7,"teacher_disagreement_score":0.38903245,"about_ca_system_score_codex":0.00031489797,"about_ca_system_score_gemma":0.0000043539803,"threshold_uncertainty_score":0.99986047},"labels":[],"label_agreement":null},{"id":"W4393578439","doi":"10.1145/3626202.3637572","title":"From Topology to Realization in FPGA/VPR Routing","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"University of Toronto","keywords":"Computer science; Router; Compiler; Equal-cost multi-path routing; Routing (electronic design automation); Parallel computing; Field-programmable gate array; Static routing; Embedded system; Metrics; Application-specific integrated circuit; Routing table; Computer network; Routing protocol; Operating system","score_opus":0.010207253347528216,"score_gpt":0.2500416055364113,"score_spread":0.23983435218888308,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4393578439","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.044556987,0.00023653742,0.9020443,0.00022886755,0.00035446335,0.000114681105,0.0000047039866,0.0020118086,0.050447676],"genre_scores_gemma":[0.9959701,0.000020362959,0.0034694255,0.00008514596,0.00010371158,0.000012473089,0.000009989448,0.000015770236,0.000313052],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996633,0.0000077622035,0.00010176534,0.000094041556,0.0000318369,0.00010132564],"domain_scores_gemma":[0.99986947,0.000027939855,0.0000018452082,0.00007515543,0.0000042325482,0.000021350417],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000059366186,0.000051811134,0.000062675994,0.00009622691,0.000006269815,0.000024941402,0.000046334146,0.000056041757,0.00018387132],"category_scores_gemma":[0.000010402865,0.000049879472,0.000012101412,0.00016905343,0.0000030372319,0.000054370987,0.00001251593,0.000058298847,0.00008184146],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008826811,0.000029732046,0.0029831836,0.00015922946,0.000070474285,0.00019215024,0.010202758,0.014325545,0.18091074,0.15264021,0.15679438,0.48168278],"study_design_scores_gemma":[0.00021135053,0.00009940309,0.003800255,0.00038210448,0.000018895102,0.000010307933,0.0006141004,0.554848,0.30696884,0.05518555,0.07710143,0.0007597332],"about_ca_topic_score_codex":0.0005068877,"about_ca_topic_score_gemma":0.00015727674,"teacher_disagreement_score":0.9514131,"about_ca_system_score_codex":0.00004228998,"about_ca_system_score_gemma":0.0000037645566,"threshold_uncertainty_score":0.20340258},"labels":[],"label_agreement":null},{"id":"W4393971401","doi":"10.1002/9781119763222.ch6","title":"Computation of Fields Via Integration Along Steepest Descent Path","year":2024,"lang":"en","type":"other","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Manitoba","funders":"","keywords":"Computation; Gradient descent; Path (computing); Computer science; Descent (aeronautics); Method of steepest descent; Algorithm; Mathematical optimization; Mathematics; Physics; Artificial intelligence; Meteorology; Computer network","score_opus":0.008845803846726716,"score_gpt":0.22153467550086614,"score_spread":0.2126888716541394,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4393971401","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000009916009,0.0007100845,0.6639473,0.0000045947486,0.00024017814,0.00013253946,0.0000050313156,0.000985098,0.33396527],"genre_scores_gemma":[0.81048167,0.00039771065,0.019445142,0.000031016563,0.00027501123,0.000034389097,0.0001093358,0.0006292794,0.16859648],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995894,0.0000074652594,0.00015517045,0.00009692769,0.00008203452,0.000069044494],"domain_scores_gemma":[0.9998441,0.000005769669,0.000025939027,0.000094192554,0.000012570788,0.000017470495],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000039208368,0.00012811743,0.00015084441,0.0001544902,0.00000298765,0.000013610445,0.000052462536,0.00022124549,0.0002603564],"category_scores_gemma":[0.0000018354996,0.00011061214,0.000045960376,0.000071151444,0.000008468651,0.000018397768,0.000009155193,0.00013009629,0.00007965843],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[7.413901e-7,0.000013024196,0.000008257945,0.0006690874,0.000058267487,0.000005802572,0.00011536762,0.00013432815,0.00080651534,0.0006916836,0.9059677,0.09152919],"study_design_scores_gemma":[0.00074337306,0.00068190735,0.00024661855,0.012278785,0.00053350104,0.000042845626,0.0002947145,0.542374,0.12623267,0.01603388,0.29742238,0.0031153082],"about_ca_topic_score_codex":0.00014531481,"about_ca_topic_score_gemma":0.00014097233,"teacher_disagreement_score":0.8104717,"about_ca_system_score_codex":0.00002476602,"about_ca_system_score_gemma":0.000004872159,"threshold_uncertainty_score":0.45106322},"labels":[],"label_agreement":null},{"id":"W4396958733","doi":"10.1007/s11036-024-02343-7","title":"A Survey on Smart Optimisation Techniques for 6G-oriented Integrated Circuits Design","year":2023,"lang":"en","type":"article","venue":"Mobile Networks and Applications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":12,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Canada Excellence Research Chairs, Government of Canada","keywords":"Computer science; Survey research; Integrated circuit; Computer architecture; Systems engineering; Engineering; Electronic engineering; Business; Operating system","score_opus":0.025280528166018394,"score_gpt":0.25546562729569594,"score_spread":0.23018509912967755,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4396958733","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010690363,0.0001321309,0.99426216,0.000010643734,0.000038158192,0.0020742319,0.000068834146,0.0020277945,0.00031703612],"genre_scores_gemma":[0.9785761,0.00081994943,0.0028538874,0.000055648623,0.00014882833,0.016317632,0.00096404395,0.000066824854,0.00019707142],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993191,0.000030571,0.00018095793,0.00020472333,0.00005910274,0.00020557747],"domain_scores_gemma":[0.99937725,0.0002630293,0.000027321656,0.00020367585,0.00007123942,0.00005750136],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00037245356,0.00013844388,0.00013733258,0.00010741618,0.00013259277,0.000039911607,0.000087051165,0.00012700996,0.000005718241],"category_scores_gemma":[0.0000115830735,0.00013483323,0.00003198569,0.0005638599,0.00002750177,0.000045315504,0.0000120899795,0.00011231944,0.000007765625],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000150831365,0.00007167881,0.0003501289,0.00004389382,0.00004771041,5.780151e-7,0.000050869916,0.33708823,0.0027266738,0.001855066,0.07432971,0.5834204],"study_design_scores_gemma":[0.00019077277,0.00020916942,0.0021956896,0.000051100484,0.000020075991,0.0000011696008,0.00003116148,0.8928288,0.0074547133,0.0007088125,0.09596999,0.0003385268],"about_ca_topic_score_codex":0.000017643562,"about_ca_topic_score_gemma":0.000008171164,"teacher_disagreement_score":0.9914082,"about_ca_system_score_codex":0.000033469987,"about_ca_system_score_gemma":0.0000087277485,"threshold_uncertainty_score":0.54983395},"labels":[],"label_agreement":null},{"id":"W4396976032","doi":"10.1145/3664286","title":"Applying reinforcement learning to learn best net to rip and re-route in global routing","year":2024,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta; University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada; Alberta Machine Intelligence Institute","keywords":"Computer science; Reinforcement learning; Net (polyhedron); Routing (electronic design automation); Artificial intelligence; Machine learning; Computer network","score_opus":0.017003432013078117,"score_gpt":0.25719917338602283,"score_spread":0.24019574137294472,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4396976032","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.009231001,0.0005885605,0.9870925,0.00007484984,0.00016223114,0.0013105433,0.0000036657943,0.000869832,0.0006668253],"genre_scores_gemma":[0.99544644,0.00008282887,0.0034568463,0.000018013365,0.000027841921,0.00066830416,0.0000042968654,0.000033444023,0.00026198343],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99857503,0.0000913881,0.00047180933,0.00025118602,0.00022476436,0.00038582354],"domain_scores_gemma":[0.999485,0.00014112658,0.00003476198,0.00022832419,0.00003080201,0.00007996857],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0006206382,0.00019122112,0.00024339759,0.0003653082,0.00007602261,0.00010901627,0.0001554546,0.00010870803,0.000015668322],"category_scores_gemma":[0.0000337179,0.00020999383,0.00004586176,0.00074277306,0.000008611267,0.00018919588,0.000005117416,0.00027300091,0.00004938491],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000013416485,0.000009937634,0.000016450993,0.00016799322,0.0000479229,0.0000023054383,0.0006708665,0.9292531,0.007090792,0.0006317399,0.00010590601,0.061989583],"study_design_scores_gemma":[0.00020873305,0.0006300387,0.00004850531,0.00085552107,0.000034710567,0.000024820032,0.0005514191,0.9855709,0.008360795,0.00017747963,0.0032423032,0.00029479244],"about_ca_topic_score_codex":0.00015257597,"about_ca_topic_score_gemma":0.000030431358,"teacher_disagreement_score":0.9862154,"about_ca_system_score_codex":0.00068575813,"about_ca_system_score_gemma":0.000055459688,"threshold_uncertainty_score":0.85633},"labels":[],"label_agreement":null},{"id":"W4399487315","doi":"10.1145/3649476.3658793","title":"Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Huawei Technologies (Canada)","funders":"","keywords":"Netlist; Relation (database); Representation (politics); Computer science; Circuit extraction; Computer hardware; Equivalent circuit; Electrical engineering; Engineering; Data mining; Voltage","score_opus":0.04530070946466474,"score_gpt":0.2605373131465432,"score_spread":0.21523660368187847,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4399487315","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014575773,0.00036825467,0.98954934,0.00003082643,0.000092611444,0.00027011786,0.0000050509784,0.0010275256,0.0071987254],"genre_scores_gemma":[0.96075755,0.00014491314,0.037668362,0.000029437582,0.000092316244,0.00005330932,0.00003435173,0.000027454285,0.0011922906],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99964285,0.0000135540095,0.00009185732,0.000121619356,0.00004126797,0.00008884108],"domain_scores_gemma":[0.99980175,0.000085646876,0.0000051186057,0.00006386736,0.000020588872,0.00002301317],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009974399,0.00006446094,0.000064831824,0.000072770876,0.000031085696,0.00007079271,0.00001635905,0.00005401913,0.0000116454],"category_scores_gemma":[0.000010795161,0.000061761726,0.000021358013,0.000107157626,0.000009518714,0.00016854571,0.000003955639,0.00003904816,0.000005570786],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025124,0.0000122199845,0.00029571092,0.00050860096,0.00025202733,0.000055870663,0.0019648036,0.09836363,0.42237583,0.16825601,0.19504064,0.11284951],"study_design_scores_gemma":[0.000063744395,0.00003202193,0.00023137676,0.000017044667,0.000020466254,0.000015645233,0.000024141551,0.92153597,0.064378604,0.011779762,0.001797743,0.00010347793],"about_ca_topic_score_codex":0.000023296345,"about_ca_topic_score_gemma":0.0000024439441,"teacher_disagreement_score":0.9593,"about_ca_system_score_codex":0.000038092527,"about_ca_system_score_gemma":0.000006594588,"threshold_uncertainty_score":0.251857},"labels":[],"label_agreement":null},{"id":"W4399886260","doi":"10.1145/3625223.3649266","title":"The Impact of Heterogeneous Logic on Adders and Multipliers in VTR","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Computer science; Adder; Arithmetic; Logic gate; Logic synthesis; Parallel computing; Programming language; Algorithm; Mathematics; Latency (audio); Telecommunications","score_opus":0.016629321997731757,"score_gpt":0.26445036351862666,"score_spread":0.2478210415208949,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4399886260","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.99354655,0.00012056514,0.0005880251,0.000019848207,0.000025326242,0.00013140553,0.0000030716853,0.0004149575,0.0051502367],"genre_scores_gemma":[0.9995614,0.00026566707,0.00009630036,0.0000069572634,0.000004364731,0.000007995607,8.1088166e-7,0.000008762185,0.00004773544],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99971944,0.0000073764018,0.000073124036,0.000049608483,0.00003602685,0.00011441058],"domain_scores_gemma":[0.9998141,0.00007200589,0.0000057771367,0.00008542106,0.000003614748,0.000019097783],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00007461694,0.000055454595,0.00006265388,0.000060860435,0.00001422366,0.000007357951,0.00004795487,0.00003242942,0.000009554558],"category_scores_gemma":[0.000011067631,0.000032895266,0.000028250157,0.00011029565,0.000020317142,0.000013836091,0.000009671543,0.00004745505,0.000007674168],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000104501196,0.0000766822,0.024533194,0.00012496386,0.000296059,0.00011487421,0.0018823345,0.47272632,0.15240692,0.0019814046,0.05216136,0.29359138],"study_design_scores_gemma":[0.0010366763,0.0008664277,0.080102906,0.0000828557,0.000010173675,0.000018934772,0.0006667638,0.7364699,0.1721985,0.0074651614,0.00044778967,0.00063389476],"about_ca_topic_score_codex":0.000051160703,"about_ca_topic_score_gemma":0.000019244939,"teacher_disagreement_score":0.29295748,"about_ca_system_score_codex":0.00001699048,"about_ca_system_score_gemma":0.0000024815974,"threshold_uncertainty_score":0.134143},"labels":[],"label_agreement":null},{"id":"W4399886299","doi":"10.1145/3625223.3649269","title":"Extending Memory Compatibility with Yosys Front-End in VTR Flow","year":2023,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Compatibility (geochemistry); Computer science; Front and back ends; Operating system; Materials science; Composite material","score_opus":0.014047924878856121,"score_gpt":0.21751232739652712,"score_spread":0.203464402517671,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4399886299","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7821684,0.00017844171,0.120474204,0.00006457134,0.00023101077,0.00052149856,0.000014686378,0.00654538,0.08980183],"genre_scores_gemma":[0.9915159,0.000023294457,0.007949631,0.000018328456,0.000028911201,0.000029835226,0.000011274933,0.000026274527,0.00039657622],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993281,0.00001821281,0.00015205043,0.0001545347,0.00011422878,0.00023291138],"domain_scores_gemma":[0.99967337,0.000044054024,0.000008417424,0.00021860289,0.00001074358,0.000044833127],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00023844965,0.00011396116,0.00016157018,0.00014203235,0.000023423196,0.000019462317,0.000100063524,0.000053337837,0.00031043155],"category_scores_gemma":[0.000008910448,0.00009427639,0.000023752036,0.00024449415,0.000019726684,0.000114766364,0.00002142029,0.00013216659,0.0001291563],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00010193479,0.0002426828,0.11663085,0.0011695803,0.00020810602,0.00065441476,0.0062871003,0.15837237,0.06159784,0.0016912448,0.10371792,0.54932594],"study_design_scores_gemma":[0.00066124584,0.000095872834,0.086586244,0.00013514869,0.00001128223,0.000009900118,0.00055913563,0.85681754,0.051895816,0.0014243805,0.0011908722,0.00061255426],"about_ca_topic_score_codex":0.00011486415,"about_ca_topic_score_gemma":0.0004907659,"teacher_disagreement_score":0.6984452,"about_ca_system_score_codex":0.00006515375,"about_ca_system_score_gemma":0.000008307351,"threshold_uncertainty_score":0.38444793},"labels":[],"label_agreement":null},{"id":"W4400020740","doi":"10.1109/tnsm.2024.3419051","title":"Preemptive Prediction-Based Placement of Time-Critical SFCs With VNF Sharing at the Edge","year":2024,"lang":"en","type":"article","venue":"IEEE Transactions on Network and Service Management","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Queen's University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Enhanced Data Rates for GSM Evolution; Artificial intelligence","score_opus":0.00792640342129182,"score_gpt":0.20299816659373723,"score_spread":0.1950717631724454,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4400020740","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0053276615,0.00041883954,0.98296237,0.0004270552,0.00031661786,0.0005866618,0.000039957642,0.0006184977,0.009302335],"genre_scores_gemma":[0.9972009,0.00037178746,0.0011655149,0.00021773638,0.000069542344,0.00023996618,0.000007692051,0.00004056647,0.0006863177],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992317,0.000018167268,0.00016752347,0.00021295655,0.00017096777,0.00019871829],"domain_scores_gemma":[0.9995926,0.00010602989,0.000009600586,0.00022307993,0.00002249332,0.000046180237],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001485861,0.0001562104,0.00011940447,0.00007318763,0.00014580262,0.000048512447,0.00010561105,0.000046686255,0.00014295327],"category_scores_gemma":[1.417244e-7,0.00011438195,0.000041043037,0.00029498455,0.000038043025,0.000063520245,0.0000039659776,0.00015331805,0.00002149338],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008010465,0.000050712104,0.000014602451,0.0008204807,0.00031868237,0.000011421923,0.00029942248,0.98284763,0.00012960439,0.0002923294,0.002729107,0.012405877],"study_design_scores_gemma":[0.00031112702,0.00025382236,0.00009309768,0.00069962506,0.00035514118,0.0000050569224,0.00012441112,0.98728275,0.0036965518,0.00013212203,0.006832425,0.00021387573],"about_ca_topic_score_codex":0.000009235079,"about_ca_topic_score_gemma":0.000055252476,"teacher_disagreement_score":0.9918732,"about_ca_system_score_codex":0.00006889085,"about_ca_system_score_gemma":0.0000061265764,"threshold_uncertainty_score":0.4664361},"labels":[],"label_agreement":null},{"id":"W4400234134","doi":"10.1109/iscas58744.2024.10558520","title":"Reinforcement-Learning-Based Foggy-Aware Optimal Placement Method for Analog and MixedSignal Circuits","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Newfoundland and Labrador; Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Foundation for Innovation","keywords":"Reinforcement learning; Computer science; Reinforcement; Analogue electronics; Electronic circuit; Artificial intelligence; Electrical engineering; Engineering","score_opus":0.014156752381373951,"score_gpt":0.2669021949000231,"score_spread":0.25274544251864917,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4400234134","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00043729728,0.00047415184,0.9938248,0.000049911803,0.00011424126,0.00040280624,0.000008698016,0.0014960702,0.0031920378],"genre_scores_gemma":[0.94784546,0.000036733392,0.050280165,0.0000993605,0.000090372814,0.00022548893,0.000061574,0.00006131539,0.0012995092],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99915826,0.000020090223,0.00020485824,0.00022083952,0.00012446706,0.0002715061],"domain_scores_gemma":[0.9996055,0.00016367518,0.000012202059,0.00010632293,0.000029274945,0.00008302736],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00032296678,0.00018044122,0.00016800482,0.00016658306,0.00006219303,0.000108463144,0.00007890069,0.00009473638,0.0002542226],"category_scores_gemma":[0.000011781954,0.0001657607,0.000075871234,0.00012709049,0.000014850624,0.00010201124,0.000018013068,0.00015314049,0.000010029475],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000027003305,0.00001999128,0.000057097717,0.0013057989,0.0002919023,0.000027186185,0.00034164905,0.7694115,0.024872078,0.004444988,0.03939341,0.15980738],"study_design_scores_gemma":[0.00025995003,0.00024616078,0.000005944645,0.0000641975,0.000040622235,0.000005562784,0.00005407673,0.93283665,0.045191236,0.00011151608,0.020967398,0.00021666884],"about_ca_topic_score_codex":0.000007878996,"about_ca_topic_score_gemma":0.0000020926284,"teacher_disagreement_score":0.9474082,"about_ca_system_score_codex":0.000058048714,"about_ca_system_score_gemma":0.000024874327,"threshold_uncertainty_score":0.67595255},"labels":[],"label_agreement":null},{"id":"W4400966981","doi":"10.1016/j.compositesa.2024.108379","title":"Data-driven thermal modeling of in-situ Automated Fiber Placement","year":2024,"lang":"en","type":"article","venue":"Composites Part A Applied Science and Manufacturing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"Natural Sciences and Engineering Research Council of Canada; Concordia University","keywords":"Materials science; In situ; Composite material; Thermal; Fiber; Thermodynamics","score_opus":0.025203215375306082,"score_gpt":0.2557525295585128,"score_spread":0.2305493141832067,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4400966981","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9793942,0.00038900206,0.006935326,0.0000124488015,0.000090383386,0.0002415312,0.000010489441,0.0010514762,0.011875148],"genre_scores_gemma":[0.9974564,0.00004015497,0.0024153788,0.000011407277,0.000025525056,0.000017989438,0.000011057354,0.000013851682,0.000008290558],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990428,0.0000042565043,0.00020201811,0.00029108432,0.00021198764,0.00024783562],"domain_scores_gemma":[0.9996261,0.000028580662,0.000012259915,0.0002699828,0.0000102764125,0.000052787185],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00032504444,0.00012440889,0.00014861935,0.00021565665,0.00006475849,0.00010910532,0.00033905284,0.00003675872,0.00001056113],"category_scores_gemma":[0.0000016660454,0.00011134318,0.000012343307,0.00016947511,0.00009281757,0.00029307924,0.00021228376,0.00011810675,0.000010582167],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000046102473,0.000010519778,0.000012736907,0.0001569914,0.00001310432,0.000007042395,0.0003792617,0.2572977,0.73361576,0.00016152403,0.00024754863,0.008093199],"study_design_scores_gemma":[0.00005158202,0.0000068824047,0.00007748401,0.000072521325,0.000006097881,0.0000023842404,0.000022920423,0.66543055,0.33375454,0.000040428426,0.0004392971,0.000095323325],"about_ca_topic_score_codex":0.00000428017,"about_ca_topic_score_gemma":0.0000037268878,"teacher_disagreement_score":0.40813285,"about_ca_system_score_codex":0.000044380115,"about_ca_system_score_gemma":0.000025247738,"threshold_uncertainty_score":0.4540443},"labels":[],"label_agreement":null},{"id":"W4401202373","doi":"10.48550/arxiv.2407.19905","title":"The Bidirected Cut Relaxation for Steiner Tree has Integrality Gap Smaller than 2","year":2024,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Banff International Research Station for Mathematical Innovation and Discovery; Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung","keywords":"Steiner tree problem; Combinatorics; Mathematics; Tree (set theory); Relaxation (psychology); Psychology; Neuroscience","score_opus":0.1119836001463613,"score_gpt":0.1933004115758624,"score_spread":0.08131681142950109,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4401202373","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.40770975,0.0014570659,0.53080064,0.00064387656,0.0036183696,0.0028727427,0.00026190947,0.0075766137,0.04505904],"genre_scores_gemma":[0.9923355,0.00053791585,0.00034342884,0.000013160094,0.00014915169,0.000015756847,0.00007176744,0.00007253894,0.0064607565],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99884003,0.00006824801,0.00021677728,0.0005083758,0.00006266037,0.00030388363],"domain_scores_gemma":[0.9988884,0.00016213374,0.00008335996,0.00066316983,0.00012432675,0.00007866154],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00029237516,0.00033108646,0.0002660061,0.00018220983,0.00016819991,0.00016159199,0.000524268,0.00041173954,0.000019797637],"category_scores_gemma":[0.00004412201,0.00028241286,0.00030032994,0.0002751647,0.00010038875,0.00007774111,0.00031132813,0.0007261435,0.000059287097],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0006958947,0.0002913103,0.002301441,0.003947074,0.0041061905,0.0004060942,0.0027778621,0.20182449,0.005972494,0.47476834,0.24958491,0.053323917],"study_design_scores_gemma":[0.00053861755,0.000109589404,0.0008934097,0.00043281168,0.0005148452,0.000003911376,0.0002346784,0.68943614,0.006741369,0.25381026,0.04614998,0.001134418],"about_ca_topic_score_codex":0.00013520682,"about_ca_topic_score_gemma":0.0006019564,"teacher_disagreement_score":0.5846258,"about_ca_system_score_codex":0.00028041474,"about_ca_system_score_gemma":0.000068276175,"threshold_uncertainty_score":0.9999628},"labels":[],"label_agreement":null},{"id":"W4401863344","doi":"10.1145/3637528.3671895","title":"RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Huawei Technologies (Canada)","funders":"","keywords":"End-to-end principle; Computer science; Placer mining; Graph; Artificial neural network; Parallel computing; Artificial intelligence; Geology; Theoretical computer science","score_opus":0.008779542969212524,"score_gpt":0.22035137153792392,"score_spread":0.2115718285687114,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4401863344","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.30641365,0.0014317078,0.63218904,0.00054649834,0.0012689601,0.0013420815,0.00006988782,0.019601231,0.037136972],"genre_scores_gemma":[0.9935985,0.000017631557,0.005096155,0.00017238718,0.0003037937,0.00008064999,0.000023451981,0.00009186522,0.00061553594],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99877286,0.000034777495,0.00019894389,0.0003569924,0.00019491314,0.00044148503],"domain_scores_gemma":[0.9993023,0.00006674386,0.0000072795897,0.00039941247,0.000025591162,0.0001986551],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020491389,0.00026452675,0.00021469627,0.00012390697,0.00005976747,0.00018969002,0.00018901931,0.00011022386,0.0006963015],"category_scores_gemma":[0.000002923332,0.0002033851,0.00006864271,0.000518069,0.00003212383,0.00036021534,0.000032911103,0.0002837531,0.00006970204],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002662382,0.00016755264,0.0178004,0.0009345184,0.0006458663,0.00052808714,0.0038881032,0.47488934,0.004390176,0.013561184,0.24310434,0.2398242],"study_design_scores_gemma":[0.0006933728,0.0016800072,0.0056179184,0.0004003151,0.00020899212,0.000249074,0.0005404856,0.8782606,0.012158934,0.0044661397,0.093031935,0.002692226],"about_ca_topic_score_codex":0.000076237084,"about_ca_topic_score_gemma":0.00029791464,"teacher_disagreement_score":0.6871849,"about_ca_system_score_codex":0.0000645849,"about_ca_system_score_gemma":0.000018835484,"threshold_uncertainty_score":0.8293804},"labels":[],"label_agreement":null},{"id":"W4402073352","doi":"10.1142/s0217595924500258","title":"Parameterized Approximations for the Minimum Diameter Vertex-Weighted Steiner Tree Problem in Graphs with Parameterized Weights","year":2024,"lang":"en","type":"article","venue":"Asia Pacific Journal of Operational Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Brock University","funders":"National Natural Science Foundation of China; Zhejiang University of Water Resources and Electric Power","keywords":"Parameterized complexity; Steiner tree problem; Vertex (graph theory); Mathematics; Combinatorics; Treewidth; Discrete mathematics; Graph; Computer science; Pathwidth; Line graph","score_opus":0.04196131371238212,"score_gpt":0.31087166920946213,"score_spread":0.26891035549708003,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4402073352","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.31189552,0.008952289,0.6461742,0.009328347,0.0010637381,0.007359756,0.00022014191,0.00045329772,0.014552702],"genre_scores_gemma":[0.9398755,0.00035393142,0.058653764,0.000011189675,0.000091666974,0.00047666917,0.000020130843,0.000052150368,0.00046502418],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997826,0.00020704248,0.000593853,0.00020293682,0.0007728552,0.000397329],"domain_scores_gemma":[0.9974189,0.001772722,0.000040472663,0.00022350019,0.0004439053,0.00010051368],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0019634098,0.00019041613,0.00029761496,0.0007615389,0.00015974224,0.0004473047,0.00033965442,0.000107930406,0.00007409032],"category_scores_gemma":[0.00010970222,0.00010856907,0.00014819372,0.0008808361,0.00015448639,0.00048977905,0.000020608995,0.00068609207,0.000010601008],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0039253337,0.001262707,0.0014664893,0.0019131945,0.0041426914,0.00075536256,0.011136882,0.0047419267,0.44666904,0.20164219,0.10208939,0.2202548],"study_design_scores_gemma":[0.0072020325,0.004337801,0.002580898,0.00219484,0.00022927158,0.0009341044,0.0026674408,0.71035874,0.055602044,0.12663856,0.08586712,0.0013871527],"about_ca_topic_score_codex":0.000004840435,"about_ca_topic_score_gemma":0.000009662715,"teacher_disagreement_score":0.70561683,"about_ca_system_score_codex":0.00012159429,"about_ca_system_score_gemma":0.0002282883,"threshold_uncertainty_score":0.4427318},"labels":[],"label_agreement":null},{"id":"W4402475585","doi":"10.1109/ccece59415.2024.10667338","title":"A Recursive Partitioning Approach to Improving Hypergraph Partitioning","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Hypergraph; Recursive partitioning; Computer science; Parallel computing; Theoretical computer science; Algorithm; Mathematics; Combinatorics; Machine learning","score_opus":0.00886469763933031,"score_gpt":0.20168195109339793,"score_spread":0.1928172534540676,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4402475585","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007879752,0.0007054165,0.84993505,0.00007196543,0.00025933867,0.00022216245,0.0000053148674,0.003964825,0.13695619],"genre_scores_gemma":[0.95350933,0.000025787154,0.045582764,0.00009881877,0.00014929663,0.00020294395,0.000012115654,0.000043963184,0.00037495658],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999242,0.000011437971,0.00016181759,0.00021405434,0.000105060484,0.00026565098],"domain_scores_gemma":[0.99970436,0.000028738423,0.000005606866,0.00014332878,0.000022259592,0.000095681135],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013959498,0.00013060236,0.000109864224,0.000177138,0.00007246621,0.00018655088,0.000086000284,0.00006486439,0.00006520698],"category_scores_gemma":[0.000015614802,0.00012571266,0.00006422538,0.0003962888,0.000013311688,0.0002264274,0.000021007429,0.00015398215,0.00013436782],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012902449,0.000112849906,0.0004525229,0.0014105208,0.0003307567,0.00008700742,0.005736566,0.035556108,0.16571876,0.3777586,0.17674978,0.23607364],"study_design_scores_gemma":[0.00028674662,0.00027407272,0.0004856084,0.0008792269,0.00013562797,0.0001538956,0.0013428226,0.63078547,0.25575683,0.025853861,0.08210137,0.0019444826],"about_ca_topic_score_codex":0.000020558457,"about_ca_topic_score_gemma":0.0000035906407,"teacher_disagreement_score":0.9456296,"about_ca_system_score_codex":0.000054057677,"about_ca_system_score_gemma":0.000010818788,"threshold_uncertainty_score":0.5126413},"labels":[],"label_agreement":null},{"id":"W4402500849","doi":"10.48550/arxiv.2408.08449","title":"Machine Learning for Optimization-Based Separation of Mixed-Integer Rounding Cuts","year":2024,"lang":"en","type":"preprint","venue":"arXiv (Cornell University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; Alliance de recherche numérique du Canada","keywords":"Rounding; Integer (computer science); Separation (statistics); Computer science; Integer programming; Mathematical optimization; Algorithm; Mathematics; Machine learning; Programming language; Operating system","score_opus":0.043855588304896706,"score_gpt":0.19887066843722784,"score_spread":0.15501508013233112,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4402500849","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008858817,0.0002453446,0.9862898,0.000008637732,0.00040746218,0.00038602657,0.000044671462,0.0008690503,0.0028902176],"genre_scores_gemma":[0.99493694,0.00013478429,0.003711355,0.0000049597297,0.000057420744,0.0000051634124,0.0002028044,0.00006238736,0.00088416977],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991799,0.000036935875,0.00020040749,0.00035608,0.000049010425,0.0001776532],"domain_scores_gemma":[0.9994027,0.00010250208,0.00008981629,0.00024955865,0.00010452235,0.00005092264],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00016767107,0.00023788009,0.00027919898,0.0003549963,0.000055717992,0.00004302749,0.00021980084,0.0002741834,0.000035222758],"category_scores_gemma":[0.00002762353,0.00028766925,0.00019977918,0.0002644429,0.000028974118,0.00007812049,0.00011391612,0.0004516499,0.000008297748],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017751192,0.0000133283975,0.00027498076,0.0006077273,0.00008512665,0.0000106283405,0.000045102817,0.99330676,0.00022081811,0.0049725818,0.00032973793,0.00011546885],"study_design_scores_gemma":[0.0001747603,0.00004090677,0.0000048399615,0.00024723634,0.00014306467,5.350834e-7,0.000018283456,0.9910706,0.0032149102,0.0043991655,0.00042054782,0.00026511872],"about_ca_topic_score_codex":0.00003365892,"about_ca_topic_score_gemma":0.000011184134,"teacher_disagreement_score":0.98607814,"about_ca_system_score_codex":0.00019617239,"about_ca_system_score_gemma":0.000057256555,"threshold_uncertainty_score":0.99995756},"labels":[],"label_agreement":null},{"id":"W4402593076","doi":"10.1109/tcad.2024.3462904","title":"Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation","year":2024,"lang":"en","type":"article","venue":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Postdoctoral Science Foundation of Guangxi Province of China; Natural Sciences and Engineering Research Council of Canada; National Natural Science Foundation of China","keywords":"Compensation (psychology); Analogue electronics; Topology (electrical circuits); Computer science; Electronic engineering; Electronic circuit; Electrical engineering; Engineering; Psychology","score_opus":0.02133183242283132,"score_gpt":0.2254494546427416,"score_spread":0.20411762221991028,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4402593076","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021884054,0.0007398084,0.97311795,0.0000115682915,0.0008838249,0.00070424966,0.00018553463,0.0021140256,0.0003589892],"genre_scores_gemma":[0.9973138,0.0002069484,0.002196107,0.000009181437,0.0000342155,0.000121189776,0.000016780847,0.000075600336,0.000026172755],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99777913,0.00030399833,0.0008919769,0.00042611943,0.00027691235,0.00032186587],"domain_scores_gemma":[0.9984895,0.00058782205,0.0001280638,0.00034715654,0.00033285303,0.000114609],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004273622,0.00043793162,0.00081576535,0.00087397755,0.000083779734,0.00010809868,0.00023133201,0.00033393805,0.000032723692],"category_scores_gemma":[0.0000075627618,0.00034738777,0.00011624917,0.0009952537,0.0001728003,0.00022996415,0.000001043554,0.00041895476,0.000007782417],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006117287,0.00034543502,0.00005410906,0.0024129339,0.0021061783,0.0001634852,0.0013231498,0.37114197,0.37166685,0.0032841037,0.0013133131,0.24612729],"study_design_scores_gemma":[0.00028279942,0.00086925505,0.000052896485,0.0021637676,0.00017485389,0.00023114073,0.00020157729,0.8624458,0.13303792,0.000102845726,0.000043525746,0.0003936697],"about_ca_topic_score_codex":0.0004995711,"about_ca_topic_score_gemma":0.000019366964,"teacher_disagreement_score":0.9754298,"about_ca_system_score_codex":0.00016077702,"about_ca_system_score_gemma":0.0001442749,"threshold_uncertainty_score":0.99989784},"labels":[],"label_agreement":null},{"id":"W4402835945","doi":"10.1109/isvlsi61997.2024.00049","title":"Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University; University of British Columbia","funders":"","keywords":"Boosting (machine learning); Field-programmable gate array; Digital signal processing; Computer science; Truncation (statistics); Compensation (psychology); Parallel computing; Computer hardware; Artificial intelligence","score_opus":0.013009273712594421,"score_gpt":0.2162666488218434,"score_spread":0.203257375109249,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4402835945","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07999046,0.00014389429,0.91206443,0.00009248502,0.00016807108,0.00037230697,0.000004778291,0.002507928,0.004655652],"genre_scores_gemma":[0.98401374,0.000008411539,0.015677495,0.000067134846,0.00006212981,0.00004736231,0.000045141518,0.000035030407,0.000043533433],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993373,0.000015572059,0.00018721583,0.00018781902,0.00012426893,0.00014782538],"domain_scores_gemma":[0.999541,0.00025100287,0.000017196004,0.00012143761,0.000025202266,0.000044174027],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017320308,0.00014163845,0.00010428575,0.00017186842,0.00007854938,0.00010901189,0.000046353554,0.00008445924,0.000028441127],"category_scores_gemma":[0.000042332304,0.00013476657,0.000031672163,0.00015058965,0.000018227647,0.0001430433,0.00000729221,0.00013544079,0.000017291008],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000022525375,0.000057376365,0.0022758693,0.0008222625,0.00008370402,0.000010793031,0.0017676484,0.10057829,0.25072998,0.0022925774,0.0022103128,0.63914865],"study_design_scores_gemma":[0.00015355833,0.000025444984,0.00055026077,0.0001111077,0.000009800227,0.0000019338147,0.0000424941,0.9055611,0.09264193,0.0003317114,0.00041572933,0.00015492791],"about_ca_topic_score_codex":0.000021721811,"about_ca_topic_score_gemma":0.00000957799,"teacher_disagreement_score":0.9040233,"about_ca_system_score_codex":0.00008040979,"about_ca_system_score_gemma":0.000009147853,"threshold_uncertainty_score":0.5495621},"labels":[],"label_agreement":null},{"id":"W4403023860","doi":"10.1109/iccims61672.2024.10690349","title":"Optimized FPGA-Based 16-bits Squarers Using LUTs and a Divide-and-Conquer Approach","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Divide and conquer algorithms; Computer science; Field-programmable gate array; Computer architecture; Parallel computing; Computer hardware; Algorithm","score_opus":0.018267259448035502,"score_gpt":0.22798629173866544,"score_spread":0.20971903229062994,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4403023860","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.022800678,0.0023251553,0.95725065,0.00005565993,0.00009221929,0.0002589793,0.0000063776297,0.001908275,0.015301991],"genre_scores_gemma":[0.9179909,0.00006290297,0.08154824,0.000077992656,0.00004407829,0.000028003638,0.0000068900904,0.00004954009,0.00019142423],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99929875,0.000018664721,0.00015280471,0.00022488824,0.000095438445,0.0002094568],"domain_scores_gemma":[0.9997058,0.00006067119,0.000007419384,0.0001292264,0.000012805942,0.000084071035],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001620659,0.00017578238,0.00018759449,0.00014783311,0.000041234525,0.00014757297,0.000055850098,0.00010625685,0.000058772803],"category_scores_gemma":[0.000008422436,0.00015064176,0.00004238893,0.0001414909,0.00004034737,0.00014947103,0.000025621206,0.00014229183,0.0000042462607],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018076198,0.00030192256,0.0011889981,0.01083839,0.0015810651,0.0003605195,0.004706462,0.16750146,0.16790706,0.028148461,0.07324017,0.54404473],"study_design_scores_gemma":[0.00033816905,0.000025757261,0.00002661097,0.00010450056,0.00005145492,0.000026001855,0.000035648824,0.9755749,0.021085791,0.00049390754,0.0019300588,0.0003071773],"about_ca_topic_score_codex":0.000044302134,"about_ca_topic_score_gemma":0.0000011606869,"teacher_disagreement_score":0.89519024,"about_ca_system_score_codex":0.00004766396,"about_ca_system_score_gemma":0.000015225381,"threshold_uncertainty_score":0.61429924},"labels":[],"label_agreement":null},{"id":"W4403165789","doi":"10.61091/jcmcc122-13","title":"Fractional Vertex Cover Reliability of Graphs","year":2024,"lang":"en","type":"article","venue":"Journal of Combinatorial Mathematics and Combinatorial Computing","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":true,"route_about_ca":false,"ca_institutions":"","funders":"","keywords":"Cover (algebra); Reliability (semiconductor); Vertex (graph theory); Combinatorics; Vertex cover; Mathematics; Graph; Physics; Engineering; Quantum mechanics","score_opus":0.008706361647812341,"score_gpt":0.23684661620236158,"score_spread":0.22814025455454923,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4403165789","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.90609,0.0023000562,0.05208375,0.000058344936,0.03491022,0.00029655494,0.000008837663,0.00032279943,0.0039294423],"genre_scores_gemma":[0.9962833,0.0001373869,0.003033074,0.0000041873186,0.00049967074,0.0000011230787,8.337419e-7,0.0000366244,0.000003809081],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9982071,0.000041735417,0.00094024325,0.0001266131,0.0004904542,0.00019383455],"domain_scores_gemma":[0.9984938,0.0007117715,0.00022461204,0.00016300075,0.0002998941,0.00010693175],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010923148,0.00020905292,0.00055494683,0.00022799976,0.00006654949,0.000114820854,0.0002152274,0.00016533704,0.000019959629],"category_scores_gemma":[0.00019508765,0.0001837062,0.00021330934,0.00030497092,0.00007249082,0.00025488698,0.000059416736,0.00049884163,0.0000029557086],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000045343277,0.00029494867,0.00014481107,0.001404494,0.00022747536,0.00003469221,0.0007760256,0.0005421824,0.0047885864,0.98439026,0.0040597175,0.0032914607],"study_design_scores_gemma":[0.0009497472,0.00043455785,0.00008248924,0.0007282052,0.00010651853,0.000100615725,0.00006285685,0.049926393,0.0056955,0.93910193,0.0025684084,0.00024276949],"about_ca_topic_score_codex":0.0000027940812,"about_ca_topic_score_gemma":2.6679778e-8,"teacher_disagreement_score":0.090193294,"about_ca_system_score_codex":0.00007654316,"about_ca_system_score_gemma":0.000076923105,"threshold_uncertainty_score":0.74913216},"labels":[],"label_agreement":null},{"id":"W4403331456","doi":"10.1109/access.2024.3478832","title":"An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning—From Specifications to Layouts","year":2024,"lang":"en","type":"article","venue":"IEEE Access","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Reinforcement learning; Computer science; Open source; Artificial intelligence; Computer architecture; Programming language; Software","score_opus":0.06595372534878907,"score_gpt":0.3090599298475921,"score_spread":0.24310620449880305,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4403331456","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0030763962,0.000036524,0.98582405,0.00011160217,0.00041966437,0.00046269075,0.000008574607,0.0016564878,0.008404026],"genre_scores_gemma":[0.9919669,0.00002675701,0.006809289,0.00034870082,0.0002658425,0.00017336545,0.00009694117,0.00007598064,0.00023619228],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990964,0.000031723728,0.00020623446,0.00029069395,0.00018740408,0.00018754072],"domain_scores_gemma":[0.9992842,0.00009776486,0.000020453925,0.00045252003,0.000031591517,0.00011346997],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013065773,0.00015663118,0.00013143261,0.0001741906,0.000090527465,0.00097082456,0.0007344492,0.00011503179,0.00049120036],"category_scores_gemma":[0.00002495214,0.0001628065,0.000028745482,0.00045122494,0.000010157937,0.0004937403,0.0000347105,0.00027766684,0.00013954644],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050276344,0.000019548019,0.0000665736,0.000019747518,0.000013243851,0.00000414977,0.00027663852,0.98439604,0.0017436417,0.00049198925,0.0034786938,0.009484714],"study_design_scores_gemma":[0.00006529981,0.000105809064,0.00016993536,0.00023677187,0.0000146505945,3.2988387e-7,0.00001874219,0.9656177,0.01966088,0.00041409073,0.01344306,0.00025269281],"about_ca_topic_score_codex":0.00006915175,"about_ca_topic_score_gemma":0.0000037138043,"teacher_disagreement_score":0.9888905,"about_ca_system_score_codex":0.000110413865,"about_ca_system_score_gemma":0.000019576291,"threshold_uncertainty_score":0.9361684},"labels":[],"label_agreement":null},{"id":"W4405709599","doi":"10.23919/emc.2003.10806210","title":"Modeling and Simulation of Electrical Interconnects, Packages and Devices for Highspeed Applications","year":2003,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Computer science; Electronic engineering; Electrical engineering; Engineering","score_opus":0.016080316567936494,"score_gpt":0.2542492122811001,"score_spread":0.2381688957131636,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4405709599","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07054917,0.0005035936,0.9278948,0.0000059339227,0.000003927342,0.00022091561,0.000001428024,0.00012589905,0.00069435284],"genre_scores_gemma":[0.98035103,0.00007094013,0.019504862,0.000009137854,0.000007095265,0.000036864327,0.000001778277,0.000008074372,0.000010231637],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9997574,0.0000045920533,0.00009250618,0.000064197324,0.000021909396,0.000059394722],"domain_scores_gemma":[0.99982566,0.00007903115,0.0000070503283,0.00004540123,0.000023940882,0.00001891983],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005568235,0.000046885172,0.00007235614,0.000043830365,0.000017576278,0.000009793688,0.000017148332,0.000036253423,0.0000024669864],"category_scores_gemma":[0.000014217436,0.000042689237,0.0000099370045,0.000047463964,0.0000065824765,0.000055551383,0.0000028634042,0.000020129004,1.2082104e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002145375,0.000076071155,0.0018533965,0.0008798013,0.00013214709,2.912836e-7,0.00057963486,0.52224445,0.16608997,0.14873743,0.0002839147,0.15910144],"study_design_scores_gemma":[0.00008608998,0.000023902845,0.000025095751,0.000005561103,0.000009192989,6.755677e-7,0.000023120017,0.97370493,0.021611119,0.004074972,0.00037954753,0.000055801884],"about_ca_topic_score_codex":0.0000021725723,"about_ca_topic_score_gemma":0.000004436191,"teacher_disagreement_score":0.90980184,"about_ca_system_score_codex":0.000005282046,"about_ca_system_score_gemma":0.0000019247475,"threshold_uncertainty_score":0.17408165},"labels":[],"label_agreement":null},{"id":"W4405767988","doi":"10.1007/978-3-031-77426-3_10","title":"Enhancing K-Way Circuit Partitioning: A Deep Reinforcement Learning Methodology","year":2024,"lang":"en","type":"book-chapter","venue":"Communications in computer and information science","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Reinforcement learning; Computer science; Artificial intelligence","score_opus":0.07926175215237737,"score_gpt":0.305504035482383,"score_spread":0.22624228333000562,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4405767988","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.000007830429,0.0006789461,0.64519495,0.000040103212,0.00015171882,0.00014795046,8.6147026e-7,0.00027263808,0.35350502],"genre_scores_gemma":[0.7342458,0.023720099,0.2311698,0.0007452456,0.0001921866,0.00025881123,0.00027516932,0.00008420693,0.009308688],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989206,0.000018843259,0.0005518742,0.00013163546,0.00019269579,0.00018434036],"domain_scores_gemma":[0.9989258,0.00017975552,0.00008930437,0.00063348276,0.00011490979,0.000056739445],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010906775,0.00016621468,0.0001979474,0.00078572496,0.00023624208,0.00026720655,0.0006582656,0.00012849667,0.000029539928],"category_scores_gemma":[0.000032064025,0.00017742378,0.000036964673,0.00021553287,0.00032000893,0.0016566907,0.00047217132,0.00059178617,0.000091210786],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[7.330393e-7,0.0000022035329,0.0000062832223,0.00015132061,0.000015385234,6.2644045e-7,0.0043149726,0.027994398,0.00011051043,0.8182899,0.00013010157,0.14898361],"study_design_scores_gemma":[0.0000789452,0.000044803404,0.000030496643,0.0004173633,0.000013402903,0.000024801353,0.000054596316,0.8132258,0.0003382125,0.026889233,0.15857361,0.00030874874],"about_ca_topic_score_codex":0.000004388528,"about_ca_topic_score_gemma":0.000008195116,"teacher_disagreement_score":0.7914006,"about_ca_system_score_codex":0.00016338132,"about_ca_system_score_gemma":0.000045253408,"threshold_uncertainty_score":0.7235132},"labels":[],"label_agreement":null},{"id":"W4406135336","doi":"10.1016/j.aej.2024.12.077","title":"An Auto-Adjusting Hybrid Quantum Genetic Algorithm-Spectre platform for the multi-objective optimization of analog circuit sizing","year":2025,"lang":"en","type":"article","venue":"Alexandria Engineering Journal","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Viet Nam National University Ho Chi Minh City","keywords":"Sizing; Genetic algorithm; Quantum; Optimization algorithm; Computer science; Algorithm; Electronic engineering; Mathematical optimization; Mathematics; Engineering; Machine learning; Physics; Chemistry","score_opus":0.014320476623969727,"score_gpt":0.23326555394190757,"score_spread":0.21894507731793783,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4406135336","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0050401846,0.0025226772,0.9909736,0.00001109727,0.0006856896,0.00032313974,0.000018862896,0.00036367314,0.000061099876],"genre_scores_gemma":[0.7696483,0.00049167324,0.22949558,0.000010908862,0.0002235732,0.00004079649,0.000008185648,0.00006356952,0.000017395676],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988431,0.00001394853,0.00046847784,0.00016661001,0.00014788263,0.00036002338],"domain_scores_gemma":[0.99924046,0.00023396949,0.000094633186,0.00023015407,0.00013452813,0.000066231165],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003494823,0.00023535224,0.00028266484,0.00030637122,0.00018586253,0.0001038485,0.00031627176,0.00009258963,0.000014628331],"category_scores_gemma":[0.00009375938,0.00020474993,0.00013612065,0.00028318522,0.000024815747,0.00025936853,0.000019841484,0.00037521214,4.2114613e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000049563187,0.00001931636,0.00006779457,0.000080349455,0.00015072578,0.0000074518207,0.00018142254,0.954203,0.010464071,0.00023207908,0.0000766803,0.03451215],"study_design_scores_gemma":[0.0005233694,0.00008039781,0.0012283275,0.00018655774,0.000106133426,0.00009832577,0.00010405287,0.98571736,0.011375648,0.00018039637,0.00018933075,0.00021009688],"about_ca_topic_score_codex":0.000008196055,"about_ca_topic_score_gemma":9.604537e-7,"teacher_disagreement_score":0.76460814,"about_ca_system_score_codex":0.00014266031,"about_ca_system_score_gemma":0.00004766162,"threshold_uncertainty_score":0.834946},"labels":[],"label_agreement":null},{"id":"W4406727639","doi":"10.11606/d.45.2024.tde-22012025-113608","title":"On rounding algorithms for the 2-edge-connected spanning subgraph problem","year":2024,"lang":"en","type":"dissertation","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Coordenação de Aperfeiçoamento de Pessoal de Nível Superior; University of Waterloo; Fundação de Amparo à Pesquisa do Estado de São Paulo","keywords":"Rounding; Enhanced Data Rates for GSM Evolution; Computer science; Algorithm; Combinatorics; Mathematics; Artificial intelligence","score_opus":0.01817764118082507,"score_gpt":0.26852990811366434,"score_spread":0.2503522669328393,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4406727639","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017068889,0.0148183,0.64939284,0.00019905141,0.011618154,0.007982422,0.0001301354,0.019022627,0.27976757],"genre_scores_gemma":[0.82820654,0.0015322504,0.043966815,0.00022072827,0.0022520071,0.006733765,0.003756648,0.0015004408,0.1118308],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989511,0.000009157325,0.00027606156,0.00028699363,0.00016727026,0.00030943324],"domain_scores_gemma":[0.99930286,0.00031805382,0.000037762395,0.00024047775,0.00006168253,0.000039161223],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00020725772,0.00034431907,0.00025693973,0.00027729917,0.00012938536,0.00020782188,0.00024517372,0.0003195603,0.0000594168],"category_scores_gemma":[0.00002714333,0.00024105268,0.0002046365,0.00029243183,0.000008919366,0.00006950042,0.000007454408,0.00046109362,0.000040371804],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00013943455,0.00008498204,0.000013719535,0.008052879,0.0023372513,0.000044310174,0.00907782,0.005023966,0.02514724,0.1966612,0.36963034,0.38378686],"study_design_scores_gemma":[0.0010559655,0.0008534709,0.000345759,0.0062813433,0.0015318193,0.00002578085,0.006028114,0.5203182,0.23409502,0.1507506,0.074446425,0.0042674975],"about_ca_topic_score_codex":0.000031096704,"about_ca_topic_score_gemma":0.00006640162,"teacher_disagreement_score":0.8111377,"about_ca_system_score_codex":0.0000791277,"about_ca_system_score_gemma":0.000021720538,"threshold_uncertainty_score":0.9829843},"labels":[],"label_agreement":null},{"id":"W4407362419","doi":"10.1109/rsp64122.2024.10870942","title":"Invited Paper--Circuit Partitioning with Reinforcement Learning and Edge-Based Initialization","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Initialization; Reinforcement learning; Computer science; Enhanced Data Rates for GSM Evolution; Artificial intelligence; Programming language","score_opus":0.011584886393516696,"score_gpt":0.21189103346333862,"score_spread":0.20030614706982192,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4407362419","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0052091503,0.00027861932,0.9773888,0.00010271946,0.0000365087,0.00012788257,4.777871e-7,0.002115102,0.014740742],"genre_scores_gemma":[0.99863106,0.000054040673,0.0008341811,0.00023921495,0.000036125504,0.000038917897,0.00003438089,0.000026167741,0.00010590645],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99959314,0.000010751533,0.000104523184,0.000098812234,0.00008090082,0.00011189397],"domain_scores_gemma":[0.9998646,0.000027853735,0.0000066449984,0.00004920957,0.000016955368,0.000034772365],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000075072945,0.000086736196,0.000065162494,0.00009246015,0.00005010507,0.00011361039,0.000020613392,0.000042161297,0.00013492181],"category_scores_gemma":[0.0000066310135,0.000073876916,0.000011781464,0.00016636701,0.00001663266,0.00017915631,0.0000053789117,0.000099129385,0.0000071985964],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000036336096,0.000036750425,0.007727627,0.0021222804,0.00031753373,0.00017580991,0.0027937144,0.6512517,0.10736867,0.040160563,0.021304367,0.16670468],"study_design_scores_gemma":[0.00026048758,0.00017451744,0.00021978283,0.00054259965,0.000031963064,0.000012228117,0.00007862052,0.8964246,0.055831913,0.0004733231,0.045617606,0.00033236557],"about_ca_topic_score_codex":0.000007942322,"about_ca_topic_score_gemma":0.000004370989,"teacher_disagreement_score":0.9934219,"about_ca_system_score_codex":0.000027755217,"about_ca_system_score_gemma":0.000006355939,"threshold_uncertainty_score":0.30126134},"labels":[],"label_agreement":null},{"id":"W4407560990","doi":"10.3390/technologies13020081","title":"Research on Circuit Partitioning Algorithm Based on Partition Connectivity Clustering and Tabu Search","year":2025,"lang":"en","type":"article","venue":"Technologies","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"Natural Science Foundation of Hainan Province","keywords":"Tabu search; Cluster analysis; Partition (number theory); Benchmark (surveying); Algorithm; Graph partition; Computer science; Vertex (graph theory); Mathematics; Theoretical computer science; Graph; Artificial intelligence","score_opus":0.06252756984955835,"score_gpt":0.3266941586500502,"score_spread":0.2641665888004918,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4407560990","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.16720362,0.00049750827,0.7771469,0.0012459314,0.00018486242,0.00080368837,0.000025358186,0.023896124,0.02899601],"genre_scores_gemma":[0.997707,0.00012763448,0.0018871657,0.000032263433,0.000013133181,0.00018411694,0.00000423583,0.000016434806,0.000028010863],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999029,0.000052661282,0.0001264764,0.00025003203,0.00019881762,0.0003430308],"domain_scores_gemma":[0.99930394,0.00028458287,0.000009506888,0.0003309305,0.00005173976,0.000019323972],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00059697253,0.0001276935,0.00014718538,0.00061665516,0.00020700783,0.00007981954,0.00015757873,0.0002062331,0.000006063347],"category_scores_gemma":[0.00011767391,0.00012770905,0.000024099973,0.0005517673,0.00017192698,0.00008291161,0.00007839657,0.00057567883,0.000015914644],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000023960858,0.00009447521,0.00091739884,0.00026518077,0.00003462416,0.000032229196,0.00008069389,0.012329109,0.014078886,0.023490615,0.006053351,0.9425995],"study_design_scores_gemma":[0.00028382547,0.00031128744,0.0018942219,0.00046389815,0.0000059091153,0.0000020288835,0.0006104735,0.63441104,0.34800184,0.0129475435,0.00084264425,0.00022530695],"about_ca_topic_score_codex":0.000016491838,"about_ca_topic_score_gemma":0.000009079565,"teacher_disagreement_score":0.94237417,"about_ca_system_score_codex":0.00013896721,"about_ca_system_score_gemma":0.000016054415,"threshold_uncertainty_score":0.5207824},"labels":[],"label_agreement":null},{"id":"W4408146705","doi":"10.1109/icmla61862.2024.00012","title":"Leveraging A* Pathfinding for Efficient Deep Reinforcement Learning in Obstacle-Dense Environments","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Thales (Canada)","funders":"","keywords":"Pathfinding; Reinforcement learning; Computer science; Obstacle; Artificial intelligence; Human–computer interaction; Theoretical computer science; Graph; Geography","score_opus":0.01343362425897058,"score_gpt":0.21927688925410566,"score_spread":0.20584326499513508,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4408146705","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.073042825,0.00058593316,0.92165965,0.000015679008,0.00019075137,0.00032324312,3.6526285e-7,0.00086669944,0.0033148513],"genre_scores_gemma":[0.9963871,0.000060338254,0.002429268,0.00002044079,0.0000349248,0.00010072116,0.000007967543,0.000044293498,0.0009149299],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991886,0.000009499695,0.00021415584,0.00017674126,0.00011757387,0.00029343402],"domain_scores_gemma":[0.99978095,0.000072399256,0.000008860526,0.00009530615,0.0000026152522,0.00003985146],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00022952392,0.00013387472,0.000112357826,0.00017999636,0.000043983182,0.000063344276,0.0000711808,0.000057520465,0.0000709376],"category_scores_gemma":[0.0000125237575,0.0001321707,0.000054953285,0.000112036876,0.0000082133,0.000067685345,0.000025794228,0.00016841141,0.000039771177],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000032756116,0.000008320811,0.00016198341,0.00013269622,0.00002091015,0.000024821225,0.0014511468,0.93460554,0.024785819,0.0007305561,0.00020502984,0.037869923],"study_design_scores_gemma":[0.00014566797,0.00003208711,0.0000950169,0.00010236569,0.0000070400524,0.000003869485,0.00018849417,0.9638231,0.028174471,0.00010287104,0.007145578,0.000179482],"about_ca_topic_score_codex":0.000005612058,"about_ca_topic_score_gemma":0.0000011644515,"teacher_disagreement_score":0.9233443,"about_ca_system_score_codex":0.00022299514,"about_ca_system_score_gemma":0.0000053239983,"threshold_uncertainty_score":0.5389765},"labels":[],"label_agreement":null},{"id":"W4408735932","doi":"10.1016/j.eng.2025.03.020","title":"An Exact Algorithm for Placement Optimization in Circuit Design","year":2025,"lang":"en","type":"article","venue":"Engineering","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"HEC Montréal","funders":"Science and Technology Commission of Shanghai Municipality; National Natural Science Foundation of China","keywords":"Computer science; Algorithm; Optimization algorithm; Mathematical optimization; Mathematics","score_opus":0.012105796683843373,"score_gpt":0.22594848984908525,"score_spread":0.21384269316524188,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4408735932","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00030532767,0.00016489133,0.9977877,0.0000033086376,0.00018372422,0.0003867199,0.000003606155,0.00087252504,0.00029221002],"genre_scores_gemma":[0.3885414,0.00005735335,0.6107813,0.0000190758,0.00006814788,0.00038923728,0.000023810278,0.000054333454,0.00006532056],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994737,0.0000069010734,0.00015593549,0.00012023054,0.000048777278,0.00019446426],"domain_scores_gemma":[0.9997662,0.000049149716,0.0000071248605,0.00013379876,0.0000135806795,0.000030199893],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00017773978,0.00011793731,0.000118064534,0.0002347383,0.000016726384,0.000028868997,0.00009929894,0.00007140363,0.000010535199],"category_scores_gemma":[0.000012601032,0.00014114768,0.000023729423,0.00020034007,0.0000026647183,0.00013058266,0.0000058739415,0.00007993055,9.383731e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000010267833,0.000007929525,0.0000072488647,0.00003899848,0.000008958848,0.0000012643451,0.000046703986,0.9697446,0.004154837,0.00016582359,0.00020514622,0.025617436],"study_design_scores_gemma":[0.00021831306,0.000030156574,0.000047800753,0.0000534196,0.0000055071955,5.7699026e-7,0.000011343204,0.97894496,0.020013314,0.000061916624,0.00047577,0.00013694017],"about_ca_topic_score_codex":0.0000023249663,"about_ca_topic_score_gemma":3.217349e-7,"teacher_disagreement_score":0.38823608,"about_ca_system_score_codex":0.00016242506,"about_ca_system_score_gemma":0.000012357015,"threshold_uncertainty_score":0.5755836},"labels":[],"label_agreement":null},{"id":"W4408791630","doi":"10.1109/access.2025.3553743","title":"Generative AI for Analog Integrated Circuit Design: Methodologies and Applications","year":2025,"lang":"en","type":"article","venue":"IEEE Access","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Generative Design; Computer architecture; Generative grammar; Artificial intelligence; Engineering","score_opus":0.12777345340857676,"score_gpt":0.3848454682543568,"score_spread":0.25707201484578,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4408791630","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00040973088,0.0005648383,0.9962533,0.0000635297,0.000097486554,0.00063739525,0.000020003597,0.00063062436,0.0013230907],"genre_scores_gemma":[0.8371588,0.0006467645,0.15693218,0.0008789786,0.0001548748,0.003770513,0.000030458423,0.00004235879,0.00038505235],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9995262,0.000039052673,0.00012954246,0.00014871938,0.000030260664,0.00012624385],"domain_scores_gemma":[0.9994591,0.00029491517,0.000015584495,0.00014446299,0.00006428702,0.000021668859],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018923699,0.000105744446,0.00015227542,0.00012812976,0.000069867914,0.000100198966,0.00020591305,0.000086430446,0.000004848212],"category_scores_gemma":[0.000037308575,0.000095107054,0.000026381462,0.00026489113,0.000036715766,0.00019717544,0.000017061426,0.00009034833,9.594305e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000027592105,0.00002716363,0.0004573194,0.00037187766,0.00035830366,0.0000025518718,0.0002671242,0.016339393,0.2000297,0.031987105,0.09124925,0.6588826],"study_design_scores_gemma":[0.0001969733,0.00003248984,0.00027938618,0.00002913204,0.000054271834,0.0000015412579,0.0000372818,0.024982018,0.8339398,0.12724848,0.012977044,0.00022157373],"about_ca_topic_score_codex":0.000012180487,"about_ca_topic_score_gemma":0.0000068186323,"teacher_disagreement_score":0.83932114,"about_ca_system_score_codex":0.00004057689,"about_ca_system_score_gemma":0.000025757072,"threshold_uncertainty_score":0.3878353},"labels":[],"label_agreement":null},{"id":"W4410295132","doi":"10.1109/edaps64431.2024.10988466","title":"Machine Learning based Netlisting for Hand-drawn Circuit Schematics with Subcircuits for High-Speed Applications","year":2024,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Schematic; Computer science; Computer architecture; Electrical engineering; Engineering","score_opus":0.022249029713486104,"score_gpt":0.2349051326424329,"score_spread":0.2126561029289468,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4410295132","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00045320822,0.00044829954,0.9934797,0.000057738544,0.000048255395,0.001165652,0.000040978317,0.0023492274,0.0019569031],"genre_scores_gemma":[0.92846173,0.0000071768654,0.069235556,0.000036337682,0.00013611905,0.0008537587,0.00016651078,0.00010959548,0.0009932005],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992125,0.000006116057,0.00021402884,0.00021067397,0.000099716985,0.00025694226],"domain_scores_gemma":[0.99934757,0.00033415743,0.000022738215,0.00016404057,0.00007294386,0.000058536472],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019498458,0.00017556519,0.0001885049,0.00011966423,0.00021413912,0.00026795614,0.00011504543,0.00008464641,0.000033369157],"category_scores_gemma":[0.000032089676,0.00015168943,0.00006319175,0.00023226072,0.00003303095,0.000098616765,0.000007221987,0.00014666464,0.0000087073795],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000049576738,0.00015753959,0.00040861606,0.01641775,0.0006659926,0.000013464011,0.0011847115,0.088006064,0.26956424,0.41208142,0.011193494,0.20025714],"study_design_scores_gemma":[0.0003771675,0.00009531618,0.0000059905587,0.00015493842,0.00007573954,0.0000049480927,0.000019151752,0.88806874,0.071222626,0.0038233763,0.035860762,0.00029126485],"about_ca_topic_score_codex":0.000010534996,"about_ca_topic_score_gemma":0.00001051393,"teacher_disagreement_score":0.92800856,"about_ca_system_score_codex":0.000056794066,"about_ca_system_score_gemma":0.000041588315,"threshold_uncertainty_score":0.6185715},"labels":[],"label_agreement":null},{"id":"W4410344137","doi":"10.1145/3734798","title":"VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration","year":2025,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Waterloo; Cerebral Diagnostics (Canada); University of Toronto","funders":"Google","keywords":"Computer science; Field-programmable gate array; CAD; Architecture; Computer architecture; Embedded system; Open source; Computer hardware; Operating system; Engineering drawing; Software","score_opus":0.01694436650770665,"score_gpt":0.24345839648382095,"score_spread":0.2265140299761143,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4410344137","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.006940453,0.0025189542,0.98203,0.0012991478,0.00032354417,0.0011894121,0.000039939725,0.0011400759,0.0045185043],"genre_scores_gemma":[0.9936242,0.0006149078,0.0019189515,0.00007445771,0.0000132884015,0.0010524503,0.000007788572,0.00002840157,0.0026655395],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991755,0.000025372796,0.00025576132,0.00028129813,0.00004339011,0.0002187141],"domain_scores_gemma":[0.9993673,0.00013297393,0.000032940497,0.0003894826,0.00003984799,0.000037429505],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018806678,0.0001866473,0.00029622836,0.000651335,0.00027612655,0.000105510866,0.00028022,0.00038946263,0.00000818761],"category_scores_gemma":[0.000021329139,0.00018091459,0.00003185412,0.0004243588,0.000079019606,0.00017595846,0.000005547595,0.00030954022,0.0000029749249],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005134399,0.000051160157,0.0000473622,0.00054609805,0.0002226744,0.0000025620907,0.00027871208,0.004923646,0.0140740005,0.012538579,0.001839504,0.96542436],"study_design_scores_gemma":[0.004204467,0.0013449208,0.00010219749,0.0012275754,0.00039532885,0.00037268217,0.005995119,0.042792466,0.41186586,0.22011915,0.30973193,0.0018483124],"about_ca_topic_score_codex":0.000028398781,"about_ca_topic_score_gemma":0.000032657856,"teacher_disagreement_score":0.9866838,"about_ca_system_score_codex":0.000032734686,"about_ca_system_score_gemma":0.000016058197,"threshold_uncertainty_score":0.7377483},"labels":[],"label_agreement":null},{"id":"W4411319152","doi":"10.1145/3717823.3718271","title":"Truly Supercritical Trade-Offs for Resolution, Cutting Planes, Monotone Circuits, and Weisfeiler–Leman","year":2025,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Supercritical fluid; Monotone polygon; Computer science; Resolution (logic); Electronic circuit; Mathematics; Artificial intelligence; Geometry; Engineering","score_opus":0.010432146389410344,"score_gpt":0.2331253876517962,"score_spread":0.22269324126238585,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4411319152","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.043956175,0.0023102036,0.9029646,0.0011667702,0.00029699458,0.001008538,0.0000644243,0.002733871,0.045498446],"genre_scores_gemma":[0.9948779,0.00012153997,0.0043441807,0.00016132687,0.000081351965,0.0001120637,0.00002349312,0.0000261128,0.00025207072],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"not_applicable","domain_scores_codex":[0.9991881,0.00001393145,0.00023962019,0.00019679096,0.000068624526,0.00029292481],"domain_scores_gemma":[0.99961084,0.0001493513,0.0000030736367,0.0001526442,0.000017198361,0.000066873086],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00016067509,0.00014785556,0.00019694114,0.00011611154,0.00011554603,0.000047596193,0.00009408134,0.00013997125,0.000022591763],"category_scores_gemma":[0.000040982006,0.00014872685,0.000044551307,0.00011144288,0.000038994174,0.00010631173,0.000017062524,0.0001252334,0.0000025527213],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000040312912,0.00015049597,0.0036892914,0.0021592765,0.0002723622,0.00002884725,0.00090759265,0.00019150556,0.1198272,0.4946104,0.23028873,0.14783397],"study_design_scores_gemma":[0.0034249441,0.00042644722,0.016693905,0.0006942944,0.00029415824,0.00015344899,0.0009267691,0.2524891,0.32007906,0.039195165,0.3635673,0.002055443],"about_ca_topic_score_codex":0.00002075631,"about_ca_topic_score_gemma":0.000015532754,"teacher_disagreement_score":0.9509217,"about_ca_system_score_codex":0.00003773404,"about_ca_system_score_gemma":0.00001158568,"threshold_uncertainty_score":0.60649043},"labels":[],"label_agreement":null},{"id":"W4412695933","doi":"10.1145/3754339","title":"Analog and Mixed-Signal IC Modeling and Optimization: An Artificial Intelligence Perspective","year":2025,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University; Memorial University of Newfoundland","funders":"","keywords":"Computer science; Mixed-signal integrated circuit; Perspective (graphical); Artificial intelligence; Domain (mathematical analysis); Machine learning; Categorization; Analogue electronics; Integrated circuit; Computer engineering; Electronic circuit","score_opus":0.023520556912250166,"score_gpt":0.2606866833356658,"score_spread":0.23716612642341564,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4412695933","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0034877504,0.0012296954,0.99413955,0.00004660296,0.00008640397,0.0004349278,0.0000045529655,0.0004361122,0.00013438649],"genre_scores_gemma":[0.9828131,0.0003393855,0.016698938,0.000006875189,0.00001630901,0.000085514344,0.000003380114,0.000017982722,0.000018522496],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989768,0.0001128307,0.00035778916,0.0002257902,0.00012523019,0.00020152799],"domain_scores_gemma":[0.99943453,0.00012359653,0.000044619635,0.00023290457,0.000121053,0.000043274547],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00033598943,0.00016058492,0.00021544556,0.00038561455,0.0001225644,0.000064332104,0.00012689397,0.00012507758,0.000015326763],"category_scores_gemma":[0.000015761065,0.00017343147,0.000031883683,0.00036338682,0.000041201278,0.0002627363,0.0000023251487,0.00017028421,0.000001195572],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017349561,0.00003028488,6.9126725e-7,0.00005639473,0.00006641387,3.0348008e-7,0.00029748506,0.96598935,0.0027026138,0.011846716,0.0000072467387,0.018985126],"study_design_scores_gemma":[0.0000683995,0.00021430882,0.0000026061987,0.000091383554,0.00004857861,0.000011529607,0.0007914462,0.9654205,0.022056587,0.011155759,0.0000026686964,0.00013623438],"about_ca_topic_score_codex":0.00003943633,"about_ca_topic_score_gemma":0.000009769603,"teacher_disagreement_score":0.97932535,"about_ca_system_score_codex":0.00018157404,"about_ca_system_score_gemma":0.00006317192,"threshold_uncertainty_score":0.707233},"labels":[],"label_agreement":null},{"id":"W4412736065","doi":"10.1016/j.segan.2025.101890","title":"Distributed alternating direction method of multipliers approach for the power distribution network reconfiguration","year":2025,"lang":"en","type":"article","venue":"Sustainable Energy Grids and Networks","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Agence Nationale de la Recherche","keywords":"Control reconfiguration; Power (physics); Distribution (mathematics); Computer science; Distributed computing; Physics; Mathematics; Embedded system; Quantum mechanics","score_opus":0.004207788460870558,"score_gpt":0.2196350846448573,"score_spread":0.21542729618398673,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4412736065","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00028105048,0.0024022385,0.99504733,0.000032890413,0.00023777228,0.00028270527,0.000014497162,0.00017861664,0.0015229171],"genre_scores_gemma":[0.9919091,0.0007431213,0.006013593,0.000024538916,0.0001931943,0.0002683857,0.0003397991,0.000018882298,0.0004894042],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9991696,0.000041895713,0.00024406968,0.00016665415,0.00005855138,0.00031925182],"domain_scores_gemma":[0.99938375,0.00024766946,0.00006129952,0.00015123557,0.00012724387,0.000028828932],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00053176173,0.00014046274,0.00018281935,0.00003783061,0.0002615033,0.000050826653,0.00009244386,0.00014120614,0.0000019317554],"category_scores_gemma":[0.000041145948,0.00011240715,0.00006551315,0.0003573437,0.000034790424,0.00009967835,0.000028448807,0.00011946984,9.81262e-9],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000037940248,0.000011727144,0.00009109113,0.00008394575,0.00009615959,4.4147453e-7,0.000025375562,0.8721832,0.00010216021,0.051724333,0.009398256,0.06624538],"study_design_scores_gemma":[0.00022411867,0.00003771198,0.00028853014,0.000028566883,0.00004768866,0.0000014997169,0.00036698862,0.9704165,0.0018157039,0.002564219,0.024084765,0.00012371557],"about_ca_topic_score_codex":0.00010882494,"about_ca_topic_score_gemma":0.0000044360427,"teacher_disagreement_score":0.99162805,"about_ca_system_score_codex":0.000092625996,"about_ca_system_score_gemma":0.000014319842,"threshold_uncertainty_score":0.45838305},"labels":[],"label_agreement":null},{"id":"W4413321036","doi":"10.23919/ispsd62843.2025.11118084","title":"A Dynamic Gate Driver with Auto-Patterning to Reduce Ringing and Switching Loss","year":2025,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Ringing; Computer science; Logic gate; Electronic engineering; Engineering; Telecommunications; Algorithm","score_opus":0.0032057607731032917,"score_gpt":0.21676096696364358,"score_spread":0.2135552061905403,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4413321036","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.48723426,0.000049537768,0.50656426,0.00008192263,0.000034538924,0.0000954703,4.0050787e-7,0.0007199933,0.0052196193],"genre_scores_gemma":[0.97995365,0.00001572726,0.019159433,0.00013888103,0.000008177929,0.000018998167,6.886603e-7,0.000023165043,0.00068130036],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99944496,0.0000066867606,0.00010832691,0.0001697153,0.00006225069,0.0002080389],"domain_scores_gemma":[0.999766,0.000021733807,0.000008910525,0.00013857847,0.000013387962,0.000051377767],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00008115134,0.00012929748,0.00012900219,0.00016767033,0.00006092932,0.000065834945,0.00008462827,0.000039128885,0.000013979114],"category_scores_gemma":[0.0000049735204,0.00011318727,0.000015095335,0.00017283588,0.00000893625,0.00010894037,0.000046987872,0.0001342586,0.0000070684437],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000039866805,0.000030537485,0.033391614,0.00068504014,0.00028855714,0.00017291421,0.0038390334,0.034506556,0.6959007,0.003164581,0.0014654231,0.22651517],"study_design_scores_gemma":[0.00076550577,0.00011941643,0.041913662,0.0016656012,0.000073744704,0.00007687877,0.0003643709,0.83867323,0.1112378,0.0010728682,0.002964065,0.0010728237],"about_ca_topic_score_codex":0.00002618945,"about_ca_topic_score_gemma":0.000020345158,"teacher_disagreement_score":0.80416673,"about_ca_system_score_codex":0.00005290703,"about_ca_system_score_gemma":0.0000076273313,"threshold_uncertainty_score":0.4615643},"labels":[],"label_agreement":null},{"id":"W4414603913","doi":"10.1109/tcomm.2025.3615774","title":"Full-Diversity Construction-D Lattices: Design and Decoding Perspective on Block-Fading Channels","year":2025,"lang":"en","type":"article","venue":"IEEE Transactions on Communications","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Okanagan University College; University of British Columbia, Okanagan Campus","funders":"","keywords":"Decoding methods; Lattice (music); Algebraic number; Additive white Gaussian noise; Error detection and correction; Coding (social sciences); Generator matrix; List decoding; Concatenated error correction code","score_opus":0.037425545459896375,"score_gpt":0.2737209845405429,"score_spread":0.2362954390806465,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4414603913","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00384614,0.00026923948,0.98425156,0.00061747147,0.0002981579,0.00036934335,0.000019680972,0.0007614888,0.009566902],"genre_scores_gemma":[0.96889156,0.0014224619,0.029368393,0.000078572884,0.000010286265,0.00008041735,0.0000012614134,0.000016203034,0.00013084995],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99931324,0.00009445901,0.00016658801,0.00017762171,0.00008601206,0.00016209538],"domain_scores_gemma":[0.9986565,0.0005141113,0.000026903692,0.0006608541,0.00008563152,0.00005600296],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015714888,0.00015892247,0.00015392415,0.00035188903,0.0010530768,0.00005890394,0.0003657365,0.00010786397,0.000019515599],"category_scores_gemma":[0.000008143487,0.0001829468,0.000062534185,0.00037341862,0.0001561546,0.000157804,0.000010139521,0.0004107648,0.000014396226],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00029548822,0.0010437842,0.00011180816,0.00023462756,0.0018538882,0.00000868565,0.017442638,0.75322086,0.023505889,0.09626381,0.003673216,0.10234529],"study_design_scores_gemma":[0.0019908529,0.0005845747,0.00013697549,0.0009898911,0.00066453655,0.00007479229,0.008248843,0.82206863,0.13758698,0.022927724,0.0033030005,0.0014232111],"about_ca_topic_score_codex":0.0000428657,"about_ca_topic_score_gemma":0.000031561558,"teacher_disagreement_score":0.9650454,"about_ca_system_score_codex":0.00023833306,"about_ca_system_score_gemma":0.00002279197,"threshold_uncertainty_score":0.80995214},"labels":[],"label_agreement":null},{"id":"W4414769834","doi":"10.4230/lipics.esa.2025.29","title":"The Tape Reconfiguration Problem and Its Consequences for Dominating Set Reconfiguration","year":2025,"lang":"en","type":"preprint","venue":"ArXiv.org","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Montréal","funders":"Agence Nationale de la Recherche","keywords":"Dominating set; Security token; Parameterized complexity; Control reconfiguration; Vertex (graph theory); Bounded function; Maximal independent set; Independent set; Pathwidth","score_opus":0.04951096408318916,"score_gpt":0.28166396013357514,"score_spread":0.23215299605038597,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4414769834","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.85413563,0.010109864,0.07049671,0.004275051,0.003166343,0.009334355,0.00055772107,0.0031000192,0.044824287],"genre_scores_gemma":[0.9937738,0.0017744856,0.0019750851,0.000057505003,0.00017028417,0.0011095116,0.00013771633,0.00002916388,0.00097245915],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9988619,0.00006108577,0.00044050135,0.000321579,0.00008632801,0.0002286065],"domain_scores_gemma":[0.9990425,0.00036875028,0.00015101484,0.00023881029,0.0001610912,0.000037796282],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00055487227,0.00025283583,0.00025226665,0.00008376824,0.0002505018,0.00016282036,0.00021127556,0.0003111227,0.000011794639],"category_scores_gemma":[0.00017749998,0.00021186734,0.0000707495,0.00007763191,0.000051206713,0.00014363865,0.000052686846,0.00036722966,0.00000557929],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020009693,0.00006811268,0.008601012,0.011278038,0.0012738771,0.000017646204,0.010203972,0.006275745,0.3965192,0.028420735,0.040155806,0.49698573],"study_design_scores_gemma":[0.0009525669,0.0002620859,0.0030732949,0.0026841972,0.00029974384,0.000029315932,0.0009850209,0.13016866,0.7726774,0.057655517,0.029373862,0.0018383013],"about_ca_topic_score_codex":0.000015293392,"about_ca_topic_score_gemma":0.000049660208,"teacher_disagreement_score":0.49514744,"about_ca_system_score_codex":0.00007337425,"about_ca_system_score_gemma":0.000078617035,"threshold_uncertainty_score":0.8639699},"labels":[],"label_agreement":null},{"id":"W4415947855","doi":"10.48550/arxiv.2510.15930","title":"Implémentation Efficiente de Fonctions de Convolution sur FPGA à l'Aide de Blocs Paramétrables et d'Approximations Polynomiales","year":2025,"lang":"","type":"preprint","venue":"ArXiv.org","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"L'Alliance Boviteq","funders":"","keywords":"Field-programmable gate array; Convolution (computer science); Convolutional neural network; Routing (electronic design automation); Resource (disambiguation); Artificial neural network; Selection (genetic algorithm)","score_opus":0.047186191283737064,"score_gpt":0.2901680122472983,"score_spread":0.24298182096356125,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4415947855","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.48216859,0.00099844,0.5117971,0.00042230877,0.0006691011,0.0010148773,0.00023348576,0.00096356915,0.0017325779],"genre_scores_gemma":[0.96847737,0.0031261286,0.024974132,0.00035184514,0.00034732113,0.0009946225,0.00048072918,0.00011554048,0.0011323108],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9957592,0.0005283334,0.0012128826,0.0009011937,0.00031466823,0.0012837256],"domain_scores_gemma":[0.9975259,0.00054906285,0.00037753856,0.00094929605,0.00026975592,0.00032847156],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001481195,0.00084240997,0.00074002147,0.0007017407,0.0006139992,0.0002708063,0.00063924777,0.0010383575,0.00009953763],"category_scores_gemma":[0.00041392044,0.0010752745,0.00050347304,0.00066837127,0.0002019156,0.0004138039,0.00029834398,0.0015278624,0.00006715907],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001662939,0.0013119456,0.32806462,0.003113211,0.0015883537,0.000044071425,0.008434598,0.4492221,0.17691307,0.008504845,0.009755234,0.01288168],"study_design_scores_gemma":[0.0023364036,0.00027110457,0.29704133,0.0029611967,0.001838349,0.00015992267,0.0018755283,0.33152694,0.34701586,0.0056551313,0.006591002,0.0027272354],"about_ca_topic_score_codex":0.0022231757,"about_ca_topic_score_gemma":0.00044571777,"teacher_disagreement_score":0.48682293,"about_ca_system_score_codex":0.002439676,"about_ca_system_score_gemma":0.001559728,"threshold_uncertainty_score":0.99916977},"labels":[],"label_agreement":null},{"id":"W4416576669","doi":"10.3390/microelectronics1020006","title":"Scaling the Area of Synthesizable FPGA Tiles Across Semiconductor Process Nodes","year":2025,"lang":"en","type":"article","venue":"Microelectronics","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Field-programmable gate array; Scaling; Process (computing); Routing (electronic design automation); Benchmarking; Place and route","score_opus":0.006798110372653086,"score_gpt":0.24594536348598567,"score_spread":0.23914725311333257,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4416576669","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.96043354,0.009785825,0.025733843,0.00008128421,0.000107026666,0.00028270716,0.000028705217,0.0005562671,0.002990819],"genre_scores_gemma":[0.99884015,0.0004190004,0.00033852144,0.000055127584,0.000021768226,0.00003669786,0.0000048112593,0.000028848457,0.00025505066],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99909806,0.000017319131,0.00023109556,0.00015331329,0.00008386248,0.0004163671],"domain_scores_gemma":[0.9994805,0.00010846093,0.00003492329,0.00029172053,0.00006467717,0.000019755544],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00021024683,0.00016075472,0.00021161819,0.000049793456,0.00010352577,0.000043204273,0.0003620745,0.00010585956,0.000017355598],"category_scores_gemma":[0.00003988021,0.00012499497,0.00007016163,0.0002956311,0.00006889771,0.00007883165,0.000033544642,0.0002457258,0.0000038327894],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010227065,0.000032261883,0.00025690763,0.00034857896,0.00010930573,0.0000010824457,0.00078798307,0.0026819012,0.9735349,0.00061481487,0.0028759434,0.01874611],"study_design_scores_gemma":[0.00008232635,0.000014150181,0.00002964338,0.00011470571,0.000022991831,0.000004621369,0.00022127648,0.0068121534,0.98574454,0.0014071637,0.0054176855,0.00012873326],"about_ca_topic_score_codex":0.000011328621,"about_ca_topic_score_gemma":0.000014396962,"teacher_disagreement_score":0.03840665,"about_ca_system_score_codex":0.00008695138,"about_ca_system_score_gemma":0.00006881776,"threshold_uncertainty_score":0.5097147},"labels":[],"label_agreement":null},{"id":"W4416676700","doi":"10.1109/tcpmt.2025.3614737","title":"Corrections to “Stable HIPPO-Based Circuit Macro-Modeling”","year":2025,"lang":"","type":"article","venue":"IEEE Transactions on Components Packaging and Manufacturing Technology","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Equivalent circuit; Integrated circuit; Network analysis; Electronic circuit; Circuit design; Transient analysis; Control theory (sociology)","score_opus":0.017829663256093684,"score_gpt":0.23713007161565666,"score_spread":0.219300408359563,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4416676700","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18535905,0.00028360405,0.805108,0.0015991887,0.0026127691,0.0007965323,0.000075173084,0.0032772052,0.00088844955],"genre_scores_gemma":[0.9935169,0.00027080972,0.0043614795,0.00042102902,0.000038093942,0.00030613822,0.0000070388137,0.00011986013,0.00095864886],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99666137,0.000074537355,0.0007657748,0.0010864878,0.00026866008,0.001143168],"domain_scores_gemma":[0.99831617,0.0001535468,0.000080712016,0.0010932619,0.000086258646,0.00027004743],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00027295685,0.0008090359,0.0007913082,0.003632731,0.0010673293,0.00020901306,0.0005832541,0.00077780435,0.00008829492],"category_scores_gemma":[0.000010285561,0.0009820206,0.00021920502,0.0009355646,0.00018929163,0.00016907703,0.000017614528,0.0016525644,0.00009134215],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001597394,0.00073369255,0.000103555096,0.00073322456,0.0006621111,0.00005445068,0.00030915128,0.6345924,0.05528736,0.0005807604,0.0008382026,0.30594534],"study_design_scores_gemma":[0.0011655526,0.0002576092,0.00006412855,0.0013076458,0.00030025575,0.00003010034,0.00018606562,0.2649079,0.7204607,0.0039253132,0.006375612,0.0010191221],"about_ca_topic_score_codex":0.00026735934,"about_ca_topic_score_gemma":0.0000570391,"teacher_disagreement_score":0.80815786,"about_ca_system_score_codex":0.0005034392,"about_ca_system_score_gemma":0.000088766225,"threshold_uncertainty_score":0.99926305},"labels":[],"label_agreement":null},{"id":"W4417065140","doi":"10.1145/3779435","title":"Multi-Agent Reinforcement Learning in Designing the Low-Dropout Regulator Circuits","year":2025,"lang":"en","type":"article","venue":"ACM Transactions on Design Automation of Electronic Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Memorial University of Newfoundland; Canada Excellence Research Chairs, Government of Canada","keywords":"Sizing; Reinforcement learning; Automation; Particle swarm optimization; Electronic design automation; Process (computing); Rendering (computer graphics); Engineering design process","score_opus":0.015634768870744924,"score_gpt":0.2408618695294796,"score_spread":0.2252271006587347,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4417065140","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003804396,0.0007388007,0.99308366,0.000051908715,0.00021432072,0.0011040401,7.93712e-7,0.0007178689,0.00028418924],"genre_scores_gemma":[0.9965909,0.00016157384,0.001963337,0.000018030649,0.000012321022,0.00043108684,0.000003446061,0.000031396496,0.0007879207],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982507,0.00025644802,0.0006413084,0.00020871544,0.00024663194,0.00039618788],"domain_scores_gemma":[0.99899405,0.0003205433,0.00010796668,0.00047915755,0.000066323206,0.000031948402],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00090066536,0.00021806477,0.00028249077,0.00046764145,0.00015115216,0.000048778576,0.00035262707,0.00014951866,0.000023788598],"category_scores_gemma":[0.000051136947,0.00019447689,0.000091796785,0.0006596824,0.000032291147,0.00015561866,0.0000036604881,0.00040939343,0.000017821378],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000008675461,0.00003830833,0.000017809127,0.00015247051,0.000095263706,7.8155307e-7,0.00035679073,0.93001586,0.056191143,0.00041198634,0.00013306514,0.0125778355],"study_design_scores_gemma":[0.00053804193,0.00013932645,0.00015708656,0.00048550015,0.00003681548,0.000005490093,0.00022776847,0.86431366,0.13348016,0.0001377352,0.0002946309,0.00018380333],"about_ca_topic_score_codex":0.000035994977,"about_ca_topic_score_gemma":0.000007639937,"teacher_disagreement_score":0.99278647,"about_ca_system_score_codex":0.00061865617,"about_ca_system_score_gemma":0.00012576356,"threshold_uncertainty_score":0.79305375},"labels":[],"label_agreement":null},{"id":"W4417169614","doi":"10.1109/icecs66544.2025.11270804","title":"Leveraging Convolutional Autoencoders for Post-Layout Performance Estimation of Analog ICs","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"Natural Sciences and Engineering Research Council of Canada; Canada Foundation for Innovation","keywords":"Convolutional neural network; Inference; Pattern recognition (psychology); Floorplan; Analogue electronics; Feature (linguistics); Feature extraction; Convolution (computer science)","score_opus":0.012530137359657382,"score_gpt":0.24611794592229708,"score_spread":0.2335878085626397,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4417169614","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.029760713,0.0005032003,0.95770836,0.00021454875,0.00042363504,0.00055333605,0.000045741534,0.0003030475,0.010487411],"genre_scores_gemma":[0.89891064,0.000111296526,0.099708036,0.00012627017,0.000029741812,0.000051099883,0.00005750155,0.000020968071,0.0009844421],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99861723,0.00002003414,0.00060242653,0.0002461545,0.0001753033,0.0003388439],"domain_scores_gemma":[0.99918437,0.00017408094,0.00009234536,0.00020730543,0.00029347002,0.000048429785],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00037055902,0.0002432137,0.00033026046,0.00036005565,0.00014314134,0.00003625454,0.00018724299,0.00019792012,0.00009370195],"category_scores_gemma":[0.00007665407,0.000269812,0.00015032433,0.00033518413,0.000086907516,0.0003099242,0.00004172512,0.00017264234,0.0000064953906],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000095227675,0.00011502649,0.0023495117,0.003333018,0.00036229967,7.893185e-7,0.0007408774,0.8129891,0.007967235,0.039491855,0.0036039047,0.12895115],"study_design_scores_gemma":[0.00047044654,0.00010779423,0.0053434754,0.00033660347,0.00009355577,0.0000020864127,0.0001240226,0.9680897,0.023187572,0.0017754862,0.00022935911,0.00023992412],"about_ca_topic_score_codex":0.000042857882,"about_ca_topic_score_gemma":0.0000016417931,"teacher_disagreement_score":0.8691499,"about_ca_system_score_codex":0.00019185575,"about_ca_system_score_gemma":0.00021327197,"threshold_uncertainty_score":0.9999754},"labels":[],"label_agreement":null},{"id":"W4417327756","doi":"10.1145/3778036","title":"Corrigendum: VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration","year":2025,"lang":"en","type":"article","venue":"ACM Transactions on Reconfigurable Technology and Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick; University of Waterloo; Cerebral Diagnostics (Canada); University of Toronto","funders":"","keywords":"CAD; Field-programmable gate array; Architecture; Reconfigurable computing; FPGA prototype","score_opus":0.02288544452266987,"score_gpt":0.2453232970090476,"score_spread":0.2224378524863777,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4417327756","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005012038,0.0025811514,0.98364466,0.0011440134,0.00062604895,0.0012941039,0.000052554216,0.0011737096,0.004471698],"genre_scores_gemma":[0.9905435,0.00063774205,0.0017386676,0.00008096292,0.000015544098,0.0011272561,0.000010900118,0.000033190645,0.005812256],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9991025,0.00002768176,0.00027785444,0.00030424984,0.000048076687,0.00023964983],"domain_scores_gemma":[0.99937475,0.000084863845,0.00003860797,0.00041401378,0.00004495168,0.000042801512],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00019026212,0.00020412685,0.00031936634,0.0006704743,0.00030787598,0.000109024535,0.00030312553,0.0004182085,0.000010822016],"category_scores_gemma":[0.000020414898,0.00019849834,0.000034765526,0.00044927103,0.000085095475,0.00017892422,0.000006009931,0.00033560372,0.0000036434712],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006375822,0.00006284648,0.000062485444,0.00058372295,0.00026146192,0.0000036956574,0.0003462792,0.0036853317,0.014647915,0.013277263,0.0047609033,0.96224433],"study_design_scores_gemma":[0.0039808224,0.0013820726,0.00010740745,0.001138038,0.0004148114,0.00042128577,0.0064736605,0.045582794,0.35499713,0.1723255,0.41127235,0.0019041302],"about_ca_topic_score_codex":0.000036805992,"about_ca_topic_score_gemma":0.00004286818,"teacher_disagreement_score":0.98553145,"about_ca_system_score_codex":0.000037962214,"about_ca_system_score_gemma":0.000019636467,"threshold_uncertainty_score":0.8094527},"labels":[],"label_agreement":null},{"id":"W4417337665","doi":"10.1109/iceccme64568.2025.11277649","title":"A Dataset for Selecting a Faster to Route Solution During the Early Stages of FPGA Placement","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Simulated annealing; Routing (electronic design automation); Benchmark (surveying); Suite; Field-programmable gate array; Selection (genetic algorithm)","score_opus":0.014968031127931955,"score_gpt":0.263506198496317,"score_spread":0.24853816736838505,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4417337665","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09977977,0.00023529606,0.8942871,0.00040216098,0.00022780414,0.0021167758,0.0019857257,0.00015745276,0.0008079001],"genre_scores_gemma":[0.9855202,0.00003519234,0.011208032,0.00012571248,0.000069078604,0.0002880222,0.000106929096,0.000030773732,0.0026160544],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99844694,0.000043156397,0.0005462839,0.00031151768,0.00016987088,0.00048220233],"domain_scores_gemma":[0.99916416,0.00016027024,0.00007466124,0.00046002213,0.00008470096,0.000056196008],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00051783817,0.00025455156,0.0002871412,0.00021817775,0.0002201051,0.00011495031,0.00031615768,0.000109796994,0.00006366236],"category_scores_gemma":[0.00006562422,0.00020923099,0.000095710566,0.00040267617,0.000022907947,0.00018971025,0.00020578605,0.0001799686,0.000006629666],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00067423424,0.00025971857,0.005393432,0.004871673,0.0014095556,0.0000036389051,0.0064273058,0.015372785,0.8450602,0.002176167,0.08091392,0.037437335],"study_design_scores_gemma":[0.001191675,0.0005359603,0.0038671403,0.00078478,0.00022881161,0.000002365783,0.00079387473,0.019393126,0.95209545,0.00018979797,0.020361107,0.000555923],"about_ca_topic_score_codex":0.00023597582,"about_ca_topic_score_gemma":0.00010567196,"teacher_disagreement_score":0.88574046,"about_ca_system_score_codex":0.00019171872,"about_ca_system_score_gemma":0.000044288867,"threshold_uncertainty_score":0.8532192},"labels":[],"label_agreement":null},{"id":"W612637280","doi":"","title":"An Efficient Shortest Distance Decomposition Algorithm for Large-Scale Transportation Network Problems","year":2014,"lang":"en","type":"article","venue":"Transportation Research Board 93rd Annual MeetingTransportation Research Board","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Algorithm; Partition (number theory); Computer science; Flow network; Heuristic; Domain (mathematical analysis); Boundary (topology); Scale (ratio); Graph; Mathematical optimization; Mathematics; Theoretical computer science; Combinatorics","score_opus":0.024391584481572644,"score_gpt":0.33933463750880954,"score_spread":0.3149430530272369,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W612637280","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.27131066,0.0002547303,0.7209317,0.00021133042,0.0002943337,0.0034501085,0.0017099258,0.0014317422,0.0004054564],"genre_scores_gemma":[0.93287736,0.0003113092,0.058347568,0.000053713393,0.00065947475,0.0026726415,0.004666189,0.00028151704,0.00013025211],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99038607,0.0008136438,0.0016382227,0.0013935051,0.0031186936,0.0026498735],"domain_scores_gemma":[0.99399644,0.0009918683,0.00017098592,0.00083500496,0.003137297,0.0008684015],"candidate_categories":["metaepi_narrow","sts"],"consensus_categories":[],"category_scores_codex":[0.008082079,0.0006654471,0.0007677808,0.0009696173,0.0013899795,0.00031358338,0.0008816588,0.00056940713,0.00011412762],"category_scores_gemma":[0.000063717984,0.00072815694,0.00034662816,0.0022415346,0.0004032733,0.0009354549,0.0000045720903,0.0015888521,0.000045006524],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0010738668,0.0020399587,0.024579637,0.0026442471,0.00034374578,0.00008110454,0.02920656,0.79244953,0.022787146,0.023750745,0.016661968,0.08438147],"study_design_scores_gemma":[0.00400039,0.002859032,0.16013163,0.0009861126,0.00015271256,0.0000010372706,0.0054574762,0.740102,0.01174468,0.0072700647,0.065285794,0.0020090863],"about_ca_topic_score_codex":0.0006908254,"about_ca_topic_score_gemma":0.012080184,"teacher_disagreement_score":0.6625841,"about_ca_system_score_codex":0.00029420684,"about_ca_system_score_gemma":0.00017394623,"threshold_uncertainty_score":0.99991006},"labels":[],"label_agreement":null},{"id":"W6902968859","doi":"10.1016/j.tre.2025.104317","title":"Expansion of bi-modal express transit networks − a hybrid optimization approach","year":2025,"lang":"en","type":"article","venue":"Transportation Research Part E Logistics and Transportation Review","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada; Alberta Innovates; University of Calgary","keywords":"Rail transit; Hybrid system; Transit (satellite); Genetic algorithm; Optimization problem; Public transport","score_opus":0.05079707550349272,"score_gpt":0.32071672181634187,"score_spread":0.26991964631284915,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6902968859","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015085136,0.025378961,0.9705746,0.00008048917,0.000077858684,0.0011215901,0.00022449132,0.00020966677,0.0008237968],"genre_scores_gemma":[0.7940309,0.18799382,0.015608315,0.00008428847,0.000026357699,0.0003368065,0.0018284817,0.00003693524,0.0000541145],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979603,0.00010210358,0.00086049637,0.00033349352,0.00041921673,0.00032436664],"domain_scores_gemma":[0.999033,0.0001300408,0.00007786882,0.00026589548,0.00038541117,0.00010782613],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0007348091,0.00023132727,0.0004914774,0.00025868538,0.00011840061,0.00002619585,0.00016773396,0.00012936165,0.00006560482],"category_scores_gemma":[0.00001865001,0.00022643126,0.00011211847,0.00073490053,0.00018682881,0.00016170177,0.0000013186443,0.00034472792,6.770223e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007353754,0.00017465398,0.0010311576,0.019444069,0.0001522725,0.000024279301,0.00032509284,0.93162745,0.00057642226,0.020885209,0.0046420987,0.021043776],"study_design_scores_gemma":[0.0024178033,0.0003904317,0.01341945,0.012428847,0.0009670137,0.0000031948803,0.0003071826,0.9378278,0.0054630735,0.0022795952,0.023168314,0.0013272578],"about_ca_topic_score_codex":0.000051647166,"about_ca_topic_score_gemma":0.000031976204,"teacher_disagreement_score":0.9549663,"about_ca_system_score_codex":0.000020999467,"about_ca_system_score_gemma":0.000055299945,"threshold_uncertainty_score":0.92335993},"labels":[],"label_agreement":null},{"id":"W6910346424","doi":"10.48336/zmmm-4z03","title":"Automated topology synthesis for analog integrated circuits","year":2023,"lang":"en","type":"article","venue":"Memorial University Research Repository (Memorial University)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Memorial University of Newfoundland","funders":"","keywords":"Integrated circuit; Electronic design automation; Process (computing); Circuit design; Automation; Computation; Sizing; Circuit extraction; Integrated circuit design","score_opus":0.035886324772656,"score_gpt":0.2637229486468699,"score_spread":0.2278366238742139,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6910346424","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.71071815,0.00008101259,0.01774263,0.00042996835,0.025231784,0.0044377684,0.00069145556,0.031684395,0.20898286],"genre_scores_gemma":[0.9798316,0.00020554176,0.00048313945,0.0000050325657,0.0023996285,0.0000050547615,0.00010974583,0.000088734494,0.01687155],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.99700063,0.00061172096,0.00023963717,0.0006143254,0.00052265957,0.0010110294],"domain_scores_gemma":[0.9974423,0.001018214,0.000060173614,0.0005425541,0.000590076,0.00034670517],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0009201273,0.00031261437,0.0004912377,0.0022534863,0.0010423075,0.00010424696,0.0011652991,0.0005362456,0.000051897197],"category_scores_gemma":[0.0003444961,0.0003879161,0.00026120056,0.0035285756,0.0004083386,0.0005077963,0.0002690676,0.0006127325,0.00011202308],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0027624322,0.00032072654,0.00066257257,0.00063316425,0.0014144139,0.008866565,0.0014119957,0.0038263889,0.38062602,0.027837519,0.5587881,0.0128501225],"study_design_scores_gemma":[0.0044539673,0.00093225174,0.00058440655,0.00018849489,0.00033013854,0.00005968739,0.005601461,0.0577898,0.17255816,0.000759556,0.7552163,0.001525792],"about_ca_topic_score_codex":0.0005257227,"about_ca_topic_score_gemma":0.000090878886,"teacher_disagreement_score":0.26911345,"about_ca_system_score_codex":0.0011303569,"about_ca_system_score_gemma":0.00037512864,"threshold_uncertainty_score":0.99985725},"labels":[],"label_agreement":null},{"id":"W6927484181","doi":"10.34726/hss.2013.23219","title":"A new partition-based heuristic for the Steiner tree problem in large graphs","year":2013,"lang":"de","type":"article","venue":"reposiTUm (TU Wien)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph; Graph theory","score_opus":0.00869429609720999,"score_gpt":0.21276276119930596,"score_spread":0.20406846510209598,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6927484181","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.007542969,0.01205514,0.96772313,0.0020609181,0.0010053986,0.0055050068,0.0000763818,0.0009390786,0.0030919549],"genre_scores_gemma":[0.9853825,0.0001531507,0.01082189,0.00023211664,0.0003119732,0.0013046522,0.00004463055,0.00010452351,0.0016445413],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997844,0.00007175467,0.0006617066,0.0004173947,0.00025660315,0.0007485517],"domain_scores_gemma":[0.9985672,0.00036116628,0.00012994061,0.00065824063,0.000105785024,0.00017762663],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003700084,0.00037516232,0.00038720842,0.00019516372,0.00017750636,0.00022349785,0.00033534912,0.00023362438,0.00016373987],"category_scores_gemma":[0.00007376623,0.0002935873,0.00025145806,0.00046587986,0.00004085594,0.0004184109,0.000038660986,0.00034494535,0.0002017391],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00048187358,0.0029982445,0.032604627,0.006715079,0.002187994,0.00050199986,0.0073959846,0.029695714,0.100059725,0.11536956,0.5455585,0.15643066],"study_design_scores_gemma":[0.0074891513,0.0016250345,0.023097496,0.0025003066,0.0011526897,0.00004683049,0.00024382291,0.72444403,0.03768625,0.072716,0.12607583,0.0029225582],"about_ca_topic_score_codex":0.0005800571,"about_ca_topic_score_gemma":0.00034575694,"teacher_disagreement_score":0.9778395,"about_ca_system_score_codex":0.00012207699,"about_ca_system_score_gemma":0.000117177195,"threshold_uncertainty_score":0.9999516},"labels":[],"label_agreement":null},{"id":"W6930504932","doi":"10.5281/zenodo.12827109","title":"Fig. 4 in The Arthropod Associates of 155 North American Cynipid Oak Galls","year":2022,"lang":"en","type":"other","venue":"Zenodo (CERN European Organization for Nuclear Research)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Gall; Nearctic ecozone; Fagaceae; Taxonomy (biology); Floristics; Arthropod","score_opus":0.01697878330350285,"score_gpt":0.21865409585265166,"score_spread":0.2016753125491488,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6930504932","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014567509,0.0008438466,0.00045425887,0.00019713398,0.00011424494,0.00081667246,0.0011361549,0.0027667454,0.9922142],"genre_scores_gemma":[0.73149693,0.026704837,0.0028314725,0.0014342105,0.0019234582,0.0000034788402,0.027031044,0.075114585,0.13345999],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9985257,0.0003412304,0.00024749056,0.0002349749,0.00036888363,0.00028172872],"domain_scores_gemma":[0.9992397,0.00002997799,0.00013882932,0.0004649872,0.00007887909,0.000047654077],"candidate_categories":["insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.00045348992,0.00018412407,0.00027745793,0.00039137277,0.00025484746,0.00011923285,0.001077305,0.000059944574,0.021887396],"category_scores_gemma":[0.00019330668,0.00016992318,0.000063017666,0.0008607519,0.00016154347,0.000049968025,0.000363294,0.00046183047,0.00091890583],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000040240125,0.00004788863,0.000016426007,0.00010459232,0.000069304944,0.0000144819105,0.00073728454,0.00006387151,0.00015829768,0.00020648229,0.9689062,0.029671129],"study_design_scores_gemma":[0.000119339675,0.00013432151,0.0003177332,0.000038015896,0.000012693187,0.000016032403,0.00037076973,0.000079152924,0.000067251545,0.000026974543,0.9986411,0.00017664311],"about_ca_topic_score_codex":0.000044886525,"about_ca_topic_score_gemma":0.000010590418,"teacher_disagreement_score":0.8587542,"about_ca_system_score_codex":0.00016682711,"about_ca_system_score_gemma":0.0000025568988,"threshold_uncertainty_score":0.999859},"labels":[],"label_agreement":null},{"id":"W6957570961","doi":"10.60692/fayrj-ped32","title":"Optimal control results for impulsive fractional delay integrodifferential equations of order 1 < r < 2 via sectorial operator","year":2023,"lang":"en","type":"article","venue":"Greater South Information System","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Manitoba","funders":"","keywords":"Optimal control; Operator (biology); Nonlinear system; Order (exchange); Point (geometry); Fractional calculus","score_opus":0.019982515213713085,"score_gpt":0.21917353186744531,"score_spread":0.19919101665373223,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6957570961","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06972657,9.205469e-7,0.9260644,0.000010903808,0.0011367764,0.0006281853,0.0013547827,0.000735515,0.00034198572],"genre_scores_gemma":[0.9977403,1.1284405e-7,0.0012911895,0.000011034116,0.00033426034,0.00029466097,0.0002833762,0.000016666983,0.000028369766],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988225,0.000025253416,0.0006603788,0.00009143162,0.00020646174,0.00019393479],"domain_scores_gemma":[0.9992119,0.000045465287,0.0001389936,0.00017026612,0.00038133556,0.000052049563],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00026178503,0.00015098046,0.00022699019,0.0002994818,0.00008136363,0.00006634416,0.000111134344,0.00014499397,0.0000141543205],"category_scores_gemma":[0.000062151295,0.00013233823,0.000086509164,0.00026798283,0.00001488511,0.00045618357,0.000014809362,0.000089744164,0.00014259096],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.003156673,0.000023678838,0.0034996967,0.003303109,0.0017576943,0.00000854404,0.16867673,0.7785963,0.0034615938,0.0040360703,0.029356143,0.0041237855],"study_design_scores_gemma":[0.003463298,0.00012475863,0.0010236591,0.000084363164,0.000054180746,0.000009103197,0.0017967965,0.98468304,0.0079246415,0.0000049692553,0.0005641827,0.0002670085],"about_ca_topic_score_codex":0.0000053078297,"about_ca_topic_score_gemma":2.1380173e-7,"teacher_disagreement_score":0.92801374,"about_ca_system_score_codex":0.00008691917,"about_ca_system_score_gemma":0.000030255014,"threshold_uncertainty_score":0.5396597},"labels":[],"label_agreement":null},{"id":"W6977586799","doi":"10.6084/m9.figshare.26640943","title":"Additional file 3 of Long-term humoral and cellular immunity after primary SARS-CoV-2 infection: a 20-month longitudinal study","year":2024,"lang":"en","type":"article","venue":"Figshare","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto; University Health Network; Toronto General Hospital","funders":"","keywords":"Cellular immunity; Immune system; Statistical analysis; Humoral immunity; Longitudinal study; Wilcoxon signed-rank test; Interleukin 4; Interleukin 2; Longitudinal data","score_opus":0.03162485995955267,"score_gpt":0.25186699428024006,"score_spread":0.2202421343206874,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6977586799","genre_codex":"dataset","genre_gemma":"dataset","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"dataset","genre_consensus":"dataset","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011117914,0.00065312587,0.000017330296,0.0000012923618,0.00003305852,0.00026049896,0.98439634,0.00047154268,0.0030489194],"genre_scores_gemma":[0.4837381,0.000002302519,0.00011805883,0.000009265023,0.0001162238,0.0011032517,0.51476455,0.00003195295,0.00011626813],"study_design_codex":"not_applicable","study_design_gemma":"observational","domain_scores_codex":[0.9993828,0.000021833654,0.00016189489,0.00016108213,0.00013276789,0.00013964344],"domain_scores_gemma":[0.9995782,0.00015952853,0.000019560068,0.00017176944,0.00004278323,0.000028168217],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00002276579,0.00015353393,0.00016057245,0.00010641364,0.000037221344,0.00006539513,0.000075598575,0.00007603675,0.86429024],"category_scores_gemma":[0.000049248454,0.00015457039,0.00006703334,0.0001562822,0.000010246351,0.00020678247,0.000079087746,0.0002184746,0.00033108948],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050013823,0.000053296,0.00024296515,0.00057653163,0.000053516484,0.00018258076,0.00007058942,0.0000016542037,0.00037321856,2.745565e-7,0.99604875,0.0023916187],"study_design_scores_gemma":[0.00033637392,0.00059814187,0.79122204,0.008608227,0.000073275754,0.00012709796,0.000015304502,0.0010525733,0.017169833,0.00006732091,0.17986922,0.0008605732],"about_ca_topic_score_codex":0.0000050707413,"about_ca_topic_score_gemma":0.000028332403,"teacher_disagreement_score":0.86395913,"about_ca_system_score_codex":0.000046033445,"about_ca_system_score_gemma":0.000027583137,"threshold_uncertainty_score":0.6303197},"labels":[],"label_agreement":null},{"id":"W6987253941","doi":"","title":"Software for mesh partitioning","year":2010,"lang":"en","type":"dissertation","venue":"RECERCAT (Consorci de Serveis Universitaris de Catalunya)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph partition; Computation; Software; Graph; Finite element method; Mesh generation; Range (aeronautics)","score_opus":0.009461660098427136,"score_gpt":0.2225803870111723,"score_spread":0.21311872691274517,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6987253941","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.77013284,0.0065691383,0.13350068,0.0003455223,0.004744604,0.004737076,0.0027946082,0.011543498,0.06563205],"genre_scores_gemma":[0.8132655,0.0045227413,0.10531703,0.0003120728,0.0012204082,0.00061509944,0.0330104,0.0011628483,0.04057391],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9982328,0.00004197096,0.0003357399,0.00047007436,0.0001943904,0.0007250677],"domain_scores_gemma":[0.9985798,0.00017861272,0.00012853454,0.0005412278,0.00030065363,0.00027119435],"candidate_categories":["metaepi_narrow","research_integrity"],"consensus_categories":[],"category_scores_codex":[0.0003014871,0.00051262375,0.00051463436,0.0005397081,0.0002931507,0.00011322132,0.00058960944,0.0013291404,0.00031841034],"category_scores_gemma":[0.00013572011,0.00066688546,0.0003166706,0.000443846,0.00004680628,0.00035353343,0.000032336688,0.0010003962,0.00005636876],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0010961512,0.00050808507,0.009768891,0.01451597,0.003977773,0.0005338289,0.020862892,0.005291833,0.120034635,0.016074756,0.5963132,0.211022],"study_design_scores_gemma":[0.003242799,0.00054280827,0.007685122,0.0021007252,0.0027027961,0.00019677744,0.007733763,0.013296192,0.4407063,0.011947494,0.503499,0.00634626],"about_ca_topic_score_codex":0.00021427727,"about_ca_topic_score_gemma":0.0010819337,"teacher_disagreement_score":0.32067168,"about_ca_system_score_codex":0.00073598186,"about_ca_system_score_gemma":0.0003200291,"threshold_uncertainty_score":0.99996734},"labels":[],"label_agreement":null},{"id":"W6991706004","doi":"","title":"Improving FPGA Placement with Dynamically Adaptive Stochastic Tunneling","year":2010,"lang":"en","type":"article","venue":"Journal of International Crisis and Risk Communication Research","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Benchmark (surveying); Field-programmable gate array; Simulated annealing; Suite; Reduction (mathematics); Schedule; Routing (electronic design automation); Software","score_opus":0.021739657055164497,"score_gpt":0.31508524605154886,"score_spread":0.29334558899638435,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6991706004","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.67006016,0.00093830883,0.32681054,0.0005730747,0.00015696885,0.00018282497,0.000012823046,0.000051387255,0.0012138868],"genre_scores_gemma":[0.9716205,0.0022580263,0.02598577,0.000009468355,0.000077416145,0.000010053604,0.0000027033773,0.000015878062,0.000020172127],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99886334,0.00010046298,0.00031409995,0.0000759993,0.00051092554,0.00013519886],"domain_scores_gemma":[0.99833554,0.00031926495,0.00013236099,0.0002206495,0.00090666785,0.000085487096],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0017236742,0.0000816163,0.00012120782,0.00032491665,0.00015076641,0.000115891686,0.000483985,0.00006221476,0.000043530083],"category_scores_gemma":[0.00015607126,0.000060443854,0.000036712165,0.00011335607,0.00008485384,0.00022038363,0.00010217302,0.0012735423,0.0000023362468],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.003293462,0.0015713207,0.0252451,0.00025655862,0.0040146993,0.00010061276,0.012274459,0.15910368,0.20203668,0.031782642,0.028437462,0.53188336],"study_design_scores_gemma":[0.0022160597,0.0012985871,0.012082387,0.00044116215,0.00010143577,0.00035691808,0.00808233,0.95573527,0.009302134,0.0068347314,0.0030054282,0.00054356194],"about_ca_topic_score_codex":0.00009715943,"about_ca_topic_score_gemma":0.00009640997,"teacher_disagreement_score":0.7966316,"about_ca_system_score_codex":0.00007313235,"about_ca_system_score_gemma":0.00004043736,"threshold_uncertainty_score":0.5532978},"labels":[],"label_agreement":null},{"id":"W6991933582","doi":"","title":"International Conference on Parallel Processing workshops proceedings ; 18 - 21 August 2002, Vancouver, B.C., Canada","year":2002,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Parallel processing; Data processing","score_opus":0.027596932442190462,"score_gpt":0.2207115529013121,"score_spread":0.19311462045912164,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6991933582","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014113302,0.00013776228,0.01625314,0.0001843113,0.0006482014,0.00017204061,0.0000057598277,0.0009391502,0.98024833],"genre_scores_gemma":[0.9694748,0.0001869844,0.00516307,0.00024806673,0.0001467625,0.00004339323,0.0000028390145,0.000034687346,0.024699435],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99912286,0.0000023026194,0.00018280672,0.0001806975,0.00026159268,0.00024974308],"domain_scores_gemma":[0.99970335,0.00001019804,0.000029208972,0.00007927899,0.00009266508,0.000085284344],"candidate_categories":["insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00004150462,0.0001718711,0.00012908167,0.00006692824,0.00005225609,0.00008766907,0.00024158262,0.00007839629,0.0052075367],"category_scores_gemma":[0.000012470662,0.00016093324,0.000023829907,0.00012817355,0.00001870781,0.00023351212,0.000020012065,0.00020232271,0.000023457638],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":true,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000032782432,0.000020325344,0.000093337505,0.00002937367,0.000014070019,0.000007979627,0.00006019759,0.00035168722,0.00039837585,0.000723006,0.9732277,0.025070691],"study_design_scores_gemma":[0.00054772844,0.00006169024,0.00022606195,0.00031021642,0.000015661199,0.000016646145,0.0005186633,0.64457005,0.004523371,0.00047705363,0.3478709,0.0008619344],"about_ca_topic_score_codex":0.0052433223,"about_ca_topic_score_gemma":0.029280968,"teacher_disagreement_score":0.9680634,"about_ca_system_score_codex":0.00017872217,"about_ca_system_score_gemma":0.000030308162,"threshold_uncertainty_score":0.99570185},"labels":[],"label_agreement":null},{"id":"W6992979114","doi":"","title":"MultiQueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism","year":2024,"lang":"en","type":"article","venue":"Infoscience (Ecole Polytechnique Fédérale de Lausanne)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; VMware; Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung; National Science Foundation","keywords":"Field-programmable gate array; Scheduling (production processes); Routing (electronic design automation); Equal-cost multi-path routing; Benchmark (surveying); Critical path method; Queue; Place and route","score_opus":0.012794439328311834,"score_gpt":0.25725385868080847,"score_spread":0.24445941935249663,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W6992979114","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.013931724,0.0006801834,0.9713888,0.00052516564,0.00065990415,0.0019104317,0.0000861778,0.008700693,0.002116883],"genre_scores_gemma":[0.85249525,0.00015375807,0.14471205,0.00042369985,0.00021920046,0.0013718916,0.000022608752,0.00012728799,0.0004742704],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9973771,0.000047295653,0.0006138914,0.00063304265,0.0002369908,0.0010916522],"domain_scores_gemma":[0.99865127,0.0002836291,0.00007405501,0.0006202614,0.000108195454,0.00026259644],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0011421228,0.0004591856,0.0004063413,0.0004196835,0.00024575955,0.0003861106,0.00075814285,0.00045891962,0.00003739537],"category_scores_gemma":[0.00024096647,0.00048577433,0.0002522186,0.0008342811,0.00017800428,0.0006428103,0.00009296194,0.00062473834,0.000019659523],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006368118,0.00014913426,0.00041344896,0.0010512384,0.00006471543,0.00007012119,0.00088165316,0.006991201,0.83853304,0.009469548,0.013724188,0.12858802],"study_design_scores_gemma":[0.00025935267,0.0001816671,0.00017293244,0.0003266775,0.000021969141,0.00001896991,0.00002410978,0.5785473,0.38665715,0.0021162112,0.031060295,0.0006133869],"about_ca_topic_score_codex":0.00012383856,"about_ca_topic_score_gemma":0.00006558161,"teacher_disagreement_score":0.8385635,"about_ca_system_score_codex":0.00038363293,"about_ca_system_score_gemma":0.0002876761,"threshold_uncertainty_score":0.9997594},"labels":[],"label_agreement":null},{"id":"W7011726493","doi":"","title":"Mixing buffers and pass transistors in FPGA routing architecture","year":2001,"lang":"en","type":"other","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Mixing (physics); Field-programmable gate array; Routing (electronic design automation); Transistor; Architecture","score_opus":0.008383809605480734,"score_gpt":0.2354768337465003,"score_spread":0.22709302414101956,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7011726493","genre_codex":"other","genre_gemma":"other","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"other","genre_consensus":"other","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014083864,0.006281146,0.08682749,0.000112956215,0.00022850196,0.00042363437,0.000007754808,0.0024824096,0.9022277],"genre_scores_gemma":[0.3036764,0.0046497383,0.02713531,0.00019247865,0.0011719842,0.0001291408,0.000047082685,0.0032551626,0.6597427],"study_design_codex":"not_applicable","study_design_gemma":"not_applicable","domain_scores_codex":[0.9993268,0.00002098636,0.00011212512,0.00019317324,0.000086156455,0.0002607178],"domain_scores_gemma":[0.9997325,0.00002263114,0.000025587155,0.0001635422,0.0000027030455,0.000053041436],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00007196138,0.00025023537,0.0002805517,0.00027696844,0.0000142833505,0.000018875131,0.00009415547,0.00030418465,0.00025119892],"category_scores_gemma":[0.0000065436443,0.00025720065,0.00004071276,0.00013807233,0.000025188474,0.000013234919,0.0000104125575,0.00037234876,0.000005822811],"study_design_candidate":"not_applicable","study_design_consensus":"not_applicable","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000017816315,0.000056718065,0.0020511101,0.002295134,0.00032221337,0.00050126173,0.021188045,0.002480919,0.012892363,0.00025394163,0.60729694,0.35064355],"study_design_scores_gemma":[0.0005613543,0.000047072474,0.00028225276,0.0016468905,0.000055521625,0.000048248236,0.0007070117,0.0012512376,0.002235843,0.00017356899,0.9917382,0.001252787],"about_ca_topic_score_codex":0.0007125201,"about_ca_topic_score_gemma":0.0006506354,"teacher_disagreement_score":0.38444126,"about_ca_system_score_codex":0.00005651308,"about_ca_system_score_gemma":0.0000062802515,"threshold_uncertainty_score":0.999988},"labels":[],"label_agreement":null},{"id":"W7014269565","doi":"","title":"Parallel FPGA Routing with On-the-Fly Net Decomposition","year":2024,"lang":"en","type":"article","venue":"Infoscience (Ecole Polytechnique Fédérale de Lausanne)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; VMware; Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung; National Science Foundation","keywords":"Router; Scalability; Speedup; Field-programmable gate array; Routing (electronic design automation); Scheduling (production processes); Baseline (sea); Path (computing)","score_opus":0.01075766068769782,"score_gpt":0.24081768669773082,"score_spread":0.230060026010033,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7014269565","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.05967431,0.00047530726,0.889424,0.0014024773,0.00036601984,0.0012357561,0.000039293445,0.00766078,0.03972205],"genre_scores_gemma":[0.9770307,0.00011459121,0.020999338,0.00079288223,0.0001480717,0.00046835144,0.000008016734,0.00006932061,0.000368751],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99816823,0.000054667635,0.00033017987,0.00039147312,0.0003470611,0.0007083749],"domain_scores_gemma":[0.9990537,0.00021389693,0.000044586366,0.0004926572,0.00004229679,0.00015287302],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006851584,0.0003254396,0.00021894336,0.00027369807,0.00025084277,0.0004024307,0.0006190576,0.0001877002,0.00008960025],"category_scores_gemma":[0.00003381609,0.00024986235,0.00009479859,0.00087211997,0.00019681115,0.0005012992,0.00006139001,0.00058079854,0.000104553576],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001655879,0.00032222536,0.0024931685,0.0007161701,0.00023715047,0.001014561,0.003853721,0.06605697,0.33435842,0.26526263,0.17069146,0.15482795],"study_design_scores_gemma":[0.00026644592,0.00092601695,0.0012695843,0.0018138268,0.00005170284,0.0004033435,0.00016416576,0.34039208,0.6121039,0.009029716,0.032135233,0.0014440026],"about_ca_topic_score_codex":0.00005589954,"about_ca_topic_score_gemma":0.00003168767,"teacher_disagreement_score":0.9173564,"about_ca_system_score_codex":0.00021997833,"about_ca_system_score_gemma":0.00009918219,"threshold_uncertainty_score":0.99999535},"labels":[],"label_agreement":null},{"id":"W7014364441","doi":"","title":"Partial parallelization of graph partitioning algorithm METIS","year":2004,"lang":"en","type":"dissertation","venue":"DSpace@MIT (Massachusetts Institute of Technology)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Metis; Graph; Graph partition; Computation; Graph theory; Algorithm design","score_opus":0.008157820742773008,"score_gpt":0.23130457616716815,"score_spread":0.22314675542439513,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7014364441","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.20013595,0.0224073,0.72552484,0.0007642475,0.008773237,0.004477225,0.0013385636,0.012924934,0.023653723],"genre_scores_gemma":[0.8833683,0.0033868663,0.10998081,0.000014657775,0.00015376564,0.00043087496,0.0019441503,0.00022349234,0.0004970853],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99763733,0.000019544994,0.00095766137,0.00046997398,0.0004404754,0.00047503572],"domain_scores_gemma":[0.9984241,0.000014412074,0.0004960234,0.0007128718,0.00027471042,0.00007789631],"candidate_categories":["metaepi_narrow","research_integrity"],"consensus_categories":[],"category_scores_codex":[0.0001601094,0.00057482364,0.00095649855,0.0015939062,0.000107246095,0.000024679099,0.00059242686,0.00159563,0.000054239412],"category_scores_gemma":[0.00009806328,0.000646369,0.0002900466,0.0012840002,0.0002865772,0.0003364118,0.00004273449,0.00070243893,0.0000128535985],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017662671,0.001061235,0.0026290629,0.007579883,0.0045870882,0.00030365633,0.0027176682,0.03989487,0.15413897,0.081555635,0.015653778,0.68970156],"study_design_scores_gemma":[0.0012932396,0.000384726,0.0005647154,0.0023747224,0.0006380012,0.000025905394,0.00032993476,0.0026052915,0.9257307,0.018085318,0.04646005,0.0015073713],"about_ca_topic_score_codex":0.00006702984,"about_ca_topic_score_gemma":0.00017359442,"teacher_disagreement_score":0.7715918,"about_ca_system_score_codex":0.00015764625,"about_ca_system_score_gemma":0.00014997729,"threshold_uncertainty_score":0.9997005},"labels":[],"label_agreement":null},{"id":"W7017163985","doi":"","title":"Approches primales et duales pour l'énumération des chambres d'un arrangement d'hyperplans réel - Le rapport complet","year":2025,"lang":"en","type":"report","venue":"HAL (Le Centre pour la Communication Scientifique Directe)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Sherbrooke","funders":"","keywords":"Hyperplane; Matroid; Completeness (order theory); Cardinality (data modeling); Affine transformation; Linear programming; Set (abstract data type); Algebraic number; Semiring","score_opus":0.03203503542487369,"score_gpt":0.2434137369661433,"score_spread":0.21137870154126961,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7017163985","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008403586,0.006077859,0.61147326,0.002206719,0.00030325234,0.00098063,0.0002992049,0.0019661833,0.36828932],"genre_scores_gemma":[0.70857495,0.026264524,0.1883703,0.00020318002,0.00019728398,0.00089509547,0.007899828,0.00035233103,0.06724251],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9958918,0.0015526935,0.0007826419,0.0006484846,0.0006593947,0.00046498148],"domain_scores_gemma":[0.9958245,0.0006655647,0.00032896333,0.0013529663,0.001679923,0.00014803707],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.005123063,0.00056098006,0.0006466561,0.00039868188,0.00038992305,0.00033607773,0.00083858904,0.00040958257,0.000090456415],"category_scores_gemma":[0.0006052135,0.0006087123,0.00026716513,0.00040331506,0.00025015554,0.00025530125,0.00028309552,0.0005767036,0.000022759903],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004473484,0.0030695812,0.0046840818,0.0066455426,0.0019159204,0.00007842859,0.028659254,0.0005181957,0.072775096,0.07959708,0.36223215,0.43977994],"study_design_scores_gemma":[0.0013335485,0.0000042002134,0.009139009,0.00782382,0.00033953026,0.000144495,0.0012395689,0.012403573,0.35415417,0.0073378365,0.6035237,0.002556538],"about_ca_topic_score_codex":0.0007724498,"about_ca_topic_score_gemma":0.00094627764,"teacher_disagreement_score":0.70017135,"about_ca_system_score_codex":0.00023959945,"about_ca_system_score_gemma":0.00084413437,"threshold_uncertainty_score":0.9996364},"labels":[],"label_agreement":null},{"id":"W7020619181","doi":"","title":"Low-power multi-threshold CMOS circuits optimization and CAD tool design","year":2004,"lang":"en","type":"dissertation","venue":"The Atrium (University of Guelph)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"CMOS; Application-specific integrated circuit; Leakage (economics); Subthreshold conduction; Microelectronics; Transistor; Sizing; Circuit design; Reduction (mathematics); Integrated circuit design","score_opus":0.014768785461832573,"score_gpt":0.20298810209498927,"score_spread":0.1882193166331567,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7020619181","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13188578,0.0018840358,0.8598098,0.000049761784,0.00044662404,0.0012887872,0.000052771764,0.00081046374,0.003771945],"genre_scores_gemma":[0.9906439,0.00094287004,0.0068644336,0.000009277784,0.000025299229,0.0000012294273,0.00013802454,0.00004908104,0.0013258725],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9992478,0.00003080231,0.00014238335,0.0002074317,0.00017832874,0.00019326062],"domain_scores_gemma":[0.9994119,0.000038495466,0.00010948112,0.000288585,0.00010199627,0.00004953998],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00016839358,0.0002348785,0.00028388624,0.00017509506,0.00015424045,0.000022880244,0.00034266536,0.00034621183,0.00009289279],"category_scores_gemma":[0.000011407019,0.00025443654,0.00010009714,0.00020376749,0.000059022277,0.00020256737,0.000027972714,0.00028111314,0.000012787245],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00022986843,0.00022450731,0.000092784256,0.0019788544,0.0007273869,0.00013554539,0.024044108,0.5710288,0.37928185,0.0009343337,0.0067238617,0.014598098],"study_design_scores_gemma":[0.013196932,0.0016817745,0.08742426,0.0044794786,0.0041337395,0.00014498926,0.034320183,0.6745437,0.16499233,0.0035249065,0.0027826473,0.00877509],"about_ca_topic_score_codex":0.00008202813,"about_ca_topic_score_gemma":0.00004276782,"teacher_disagreement_score":0.85875815,"about_ca_system_score_codex":0.00009647869,"about_ca_system_score_gemma":0.000056414363,"threshold_uncertainty_score":0.99999076},"labels":[],"label_agreement":null},{"id":"W7028217537","doi":"","title":"Efficient Octree-based 3 Dimensional Pathfinding","year":2024,"lang":"en","type":"dissertation","venue":"eScholarship@McGill (McGill)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Pathfinding; Octree; Representation (politics); Path (computing); Grid; Graph; Flexibility (engineering); Computation; Computer graphics","score_opus":0.010648101797531194,"score_gpt":0.21891750234597118,"score_spread":0.20826940054843998,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7028217537","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9007192,0.0018335913,0.0000065458703,0.000005676646,0.0039013568,0.00082556193,0.0012027913,0.0044291303,0.087076105],"genre_scores_gemma":[0.9937279,0.00007609523,0.001390296,0.00009563811,0.00009513904,0.00027542948,0.0013679923,0.0005309104,0.0024405795],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9962321,0.00011152057,0.0008589176,0.000994661,0.000934931,0.00086787774],"domain_scores_gemma":[0.99841744,0.00020873618,0.0001549824,0.00070962484,0.0001820908,0.0003271539],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0006263369,0.0010241121,0.00075245986,0.0008790744,0.0005219607,0.00014013113,0.00055971066,0.0010914329,0.00031440152],"category_scores_gemma":[0.0001407941,0.0010815578,0.0005398688,0.0007352249,0.00003791566,0.0001417412,0.00006898399,0.0021075448,0.0010335383],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00021416141,0.00050111883,0.000011663985,0.004160844,0.0008991428,0.0011938472,0.00003324229,0.044334162,0.6038982,0.056861192,0.00043824685,0.28745413],"study_design_scores_gemma":[0.001135251,0.0002970582,0.0002587038,0.004729442,0.0006207894,0.00006604811,0.0001411872,0.048483133,0.85333335,0.01620745,0.07039095,0.004336666],"about_ca_topic_score_codex":0.00004024296,"about_ca_topic_score_gemma":0.00009739134,"teacher_disagreement_score":0.28311747,"about_ca_system_score_codex":0.00095431664,"about_ca_system_score_gemma":0.000053986827,"threshold_uncertainty_score":0.9997443},"labels":[],"label_agreement":null},{"id":"W7065631118","doi":"","title":"Fast Heuristic Techniques for FPGA Placement based on Multilevel Clustering","year":2003,"lang":"en","type":"article","venue":"The Atrium (University of Guelph)","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Field-programmable gate array; Heuristic; Cluster analysis; Sign (mathematics); Gate array; Digital electronics; Programmable logic device; Logic gate","score_opus":0.017847502034413182,"score_gpt":0.21095302089118967,"score_spread":0.1931055188567765,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7065631118","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005598691,0.000038531885,0.98720086,0.00008944852,0.00008948329,0.00051902875,0.000037201968,0.0004697969,0.0059569683],"genre_scores_gemma":[0.9749046,0.000019453244,0.024645777,0.000033282064,0.000019617168,0.000002775024,0.0000063572493,0.000021809043,0.00034631984],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99943554,0.000033043358,0.00009399875,0.0001285194,0.000119086944,0.00018980782],"domain_scores_gemma":[0.99948025,0.00010967932,0.000042626492,0.00028094611,0.00004523461,0.00004127609],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002481296,0.00012962929,0.00015900806,0.000110842295,0.00013216134,0.000008690825,0.00025438936,0.000073282434,0.00005360062],"category_scores_gemma":[0.000021976015,0.00012893604,0.00010040179,0.00009824709,0.000052831118,0.00005958386,0.000026070842,0.000105223415,0.000008027698],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000858399,0.00047180566,0.00030320085,0.0016875996,0.00035978478,0.000052171043,0.003683701,0.10771376,0.7139584,0.0046328697,0.061399635,0.104878694],"study_design_scores_gemma":[0.0025307331,0.001029962,0.0037045775,0.00032162742,0.00024003978,0.000010856498,0.0019758798,0.767778,0.16255684,0.0011038595,0.057724327,0.0010233024],"about_ca_topic_score_codex":0.000023804105,"about_ca_topic_score_gemma":0.000012735201,"teacher_disagreement_score":0.96930593,"about_ca_system_score_codex":0.00007744434,"about_ca_system_score_gemma":0.000015283982,"threshold_uncertainty_score":0.5257859},"labels":[],"label_agreement":null},{"id":"W7095561659","doi":"","title":"Toronto, ON","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Complex programmable logic device; Simulated annealing; Programmable logic device; Logic synthesis; Programmable logic array; Programmable logic controller","score_opus":0.01298394285280654,"score_gpt":0.18857107877298823,"score_spread":0.1755871359201817,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7095561659","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01873102,0.00013102798,0.020065721,0.000007000847,0.00005951845,0.00003188361,3.3832265e-7,0.0013955538,0.9595779],"genre_scores_gemma":[0.99553823,0.00013827784,0.001913758,0.00007375615,0.000034057255,0.0000043774044,4.17224e-7,0.000007768966,0.002289365],"study_design_codex":"not_applicable","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.999849,0.0000012655775,0.000031299114,0.000029683099,0.00003231564,0.00005642216],"domain_scores_gemma":[0.99990624,0.0000047019594,0.0000011581648,0.00006819824,0.0000028295026,0.000016884218],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000009747553,0.000033065015,0.000030807958,0.0000060659527,0.000012432297,0.0000016674646,0.000030348725,0.000020353706,0.0005058491],"category_scores_gemma":[9.935605e-7,0.000027820985,0.000012316009,0.00001142263,0.000004096896,0.00003599044,0.0000019907754,0.000020597176,0.000113195456],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004207533,0.00004373204,0.00050991366,0.000016658778,0.000025415457,0.00005116655,0.00040919453,0.00042415273,0.02276279,0.02689699,0.8731256,0.075730145],"study_design_scores_gemma":[0.00030508047,0.00025801547,0.006785556,0.000018087592,0.0000042888123,0.00006584121,0.00004161445,0.011814136,0.62926215,0.0010186423,0.34985766,0.0005689671],"about_ca_topic_score_codex":0.000021808548,"about_ca_topic_score_gemma":0.00000722083,"teacher_disagreement_score":0.9768072,"about_ca_system_score_codex":0.00002186348,"about_ca_system_score_gemma":0.0000010130435,"threshold_uncertainty_score":0.55386925},"labels":[],"label_agreement":null},{"id":"W7095777721","doi":"","title":"A dynamic diffusion optimization method for irregular finite element graph partitioning,” The","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Computation; Finite element method; Graph; Heuristics; Graph partition; Load balancing (electrical power); Graph theory","score_opus":0.006998421151511156,"score_gpt":0.23073787363724996,"score_spread":0.2237394524857388,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7095777721","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00047759293,0.00006939249,0.9968024,0.00023833624,0.00006184914,0.0006632188,0.0000035016242,0.0005174608,0.001166258],"genre_scores_gemma":[0.21153538,0.00012779313,0.7863433,0.00020308257,0.000025744177,0.0011170022,0.00005462617,0.00003552087,0.00055758725],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9995175,0.000020646705,0.00014410848,0.00009401917,0.00007225828,0.0001514506],"domain_scores_gemma":[0.9996726,0.00008045581,0.000018697601,0.00016012334,0.0000409513,0.00002716232],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015382584,0.000091071815,0.0000769792,0.00004939374,0.000088327186,0.000053631058,0.00008812163,0.000046871533,0.00037552803],"category_scores_gemma":[0.000012897536,0.000061590275,0.0000543465,0.000097872005,0.0000101582045,0.000101707825,0.000013749494,0.000046827547,0.000012400364],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000028968807,0.00003322474,0.000049533133,0.000055265748,0.000048883754,2.3662467e-7,0.00021523991,0.92282,0.0129092,0.004526129,0.018050876,0.041288566],"study_design_scores_gemma":[0.00011405546,0.00003101138,0.000106366526,0.000009636376,0.000012458329,7.068602e-7,0.000037990576,0.98780286,0.0043885023,0.0055277725,0.0018744795,0.00009418464],"about_ca_topic_score_codex":0.000021133854,"about_ca_topic_score_gemma":0.0000075375483,"teacher_disagreement_score":0.21105778,"about_ca_system_score_codex":0.000022585251,"about_ca_system_score_gemma":0.0000026202981,"threshold_uncertainty_score":0.41117686},"labels":[],"label_agreement":null},{"id":"W7095863864","doi":"","title":"Stochastic Spatial Routing for Reconfigurable","year":2013,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Routing (electronic design automation); Obstacle; Scheme (mathematics); Field-programmable gate array; Sketch; Implementation; Reconfigurable computing; Path (computing)","score_opus":0.011476829836949675,"score_gpt":0.20136184425361559,"score_spread":0.18988501441666591,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7095863864","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0036525521,0.000021702992,0.9579118,0.000030409876,0.00011336019,0.00034322884,0.000001623204,0.00087325834,0.037052058],"genre_scores_gemma":[0.99098295,0.0000014371261,0.0077758487,0.00003534421,0.00008366818,0.00017060434,0.0000031665998,0.000020332423,0.0009266681],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99964285,0.0000022675003,0.00009733312,0.00006565159,0.000031161795,0.00016072884],"domain_scores_gemma":[0.99982435,0.000030118515,0.0000072794005,0.00008165709,0.000024053248,0.000032547217],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000046801317,0.00006523115,0.00007425225,0.000026739268,0.000026824073,0.000031958432,0.00005580868,0.000042104923,0.0006066007],"category_scores_gemma":[0.000016607255,0.00005881844,0.000027789312,0.000026532916,0.0000049011483,0.000087942775,0.0000028336704,0.000040975887,0.00012649856],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000004901742,0.000026946926,0.0000749084,0.00013484567,0.00005010093,7.4653525e-7,0.00029600816,0.0090288585,0.19181196,0.0074289246,0.1476199,0.6435219],"study_design_scores_gemma":[0.0002443194,0.00007284348,0.0001910292,0.000025808406,0.000009236989,0.0000036937122,0.000054601194,0.8987185,0.09106057,0.0072813085,0.0020438028,0.0002943044],"about_ca_topic_score_codex":0.00012505027,"about_ca_topic_score_gemma":0.000007926094,"teacher_disagreement_score":0.9873304,"about_ca_system_score_codex":0.00001580269,"about_ca_system_score_gemma":0.0000031960278,"threshold_uncertainty_score":0.6641853},"labels":[],"label_agreement":null},{"id":"W7096408914","doi":"","title":"The effect of logic block granularity on deep-submicron FPGA performance and density,” M.A.Sc thesis","year":2001,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Block (permutation group theory); Granularity; Reproduction; Field-programmable gate array; Object (grammar); Government (linguistics)","score_opus":0.005706866964370105,"score_gpt":0.19146061390884453,"score_spread":0.1857537469444744,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7096408914","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.98753124,0.0003036438,0.0021905599,0.000027844018,0.00003898276,0.00019900968,4.7411447e-7,0.0002734607,0.009434773],"genre_scores_gemma":[0.9986151,0.0009622843,0.00023831431,0.000025268193,0.000019851464,0.000012297616,5.470295e-7,0.000013488414,0.00011284365],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99946934,0.00003627787,0.00012395848,0.0001006988,0.00009437108,0.00017534626],"domain_scores_gemma":[0.99954695,0.00017424006,0.00001769505,0.0002144065,0.000014727395,0.000032007214],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002897917,0.00013020425,0.0001571502,0.000037797407,0.00008927119,0.00002099513,0.000116202194,0.00007752861,0.000010138391],"category_scores_gemma":[0.000017818296,0.00007722317,0.000042184853,0.000086426815,0.000050219416,0.00004478459,0.000024241464,0.00012378294,0.000009552372],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003256997,0.00007483534,0.24028008,0.0005665757,0.00018309262,0.00003129656,0.00027506312,0.0009730608,0.096497774,0.0011028678,0.0041223466,0.6555673],"study_design_scores_gemma":[0.00031985942,0.0007362975,0.070255086,0.00004580158,0.000039684142,0.000047199643,0.000009011438,0.014956315,0.91183627,0.0004460751,0.0010708628,0.00023752521],"about_ca_topic_score_codex":0.000014901148,"about_ca_topic_score_gemma":0.00001971341,"teacher_disagreement_score":0.8153385,"about_ca_system_score_codex":0.000017902496,"about_ca_system_score_gemma":0.000001518185,"threshold_uncertainty_score":0.31490695},"labels":[],"label_agreement":null},{"id":"W7097389683","doi":"","title":"Parallel Synthesis of Large Combinational Circuits for FPGAs","year":2008,"lang":"en","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Combinational logic; Partition (number theory); Logic synthesis; Digital electronics; Computation; Register-transfer level; Sequential logic; Interconnection; Field-programmable gate array","score_opus":0.02109942822801255,"score_gpt":0.2293240281689985,"score_spread":0.20822459994098594,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7097389683","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.024727793,0.00009469641,0.92789775,0.00004071306,0.00006480996,0.0002889191,0.000048677113,0.0006250785,0.046211567],"genre_scores_gemma":[0.9936752,0.00004249732,0.005824647,0.000022087197,0.000015108677,0.00008004108,0.0000056922486,0.0000136291865,0.00032113167],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9996476,0.0000043273662,0.00011479639,0.000054714223,0.00007116555,0.00010740849],"domain_scores_gemma":[0.9997493,0.000100192556,0.000011409627,0.000078212404,0.000039456874,0.00002141507],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000068934176,0.0000564877,0.000102337595,0.00004734167,0.000027767403,0.0000019776128,0.00006808314,0.000045069188,0.00012241055],"category_scores_gemma":[0.000028620663,0.000054531894,0.000048707912,0.00004638505,0.000012649339,0.000047529527,0.0000051921784,0.000025079165,0.000010035725],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000011225925,0.0009321258,0.0065283594,0.0011123843,0.00046862612,0.00002042693,0.0010044009,0.0039583086,0.07639636,0.42007577,0.4017369,0.087755114],"study_design_scores_gemma":[0.0014239022,0.00015121917,0.019542616,0.00008338944,0.00004503296,0.000044328484,0.00005666654,0.08965623,0.84357196,0.0122905895,0.032419093,0.0007149603],"about_ca_topic_score_codex":0.0000017427066,"about_ca_topic_score_gemma":9.7239e-7,"teacher_disagreement_score":0.96894735,"about_ca_system_score_codex":0.000011386028,"about_ca_system_score_gemma":0.0000068184368,"threshold_uncertainty_score":0.22237462},"labels":[],"label_agreement":null},{"id":"W7105641753","doi":"10.1109/ijcnn64981.2025.11229099","title":"Dual Graph Neural Networks for Optimizing Circuit Partitioning: A Synergistic Approach","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Graph partition; Partition (number theory); Graph; Node (physics); Artificial neural network; Key (lock)","score_opus":0.024849877211822333,"score_gpt":0.23739953759720275,"score_spread":0.21254966038538042,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7105641753","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0003383643,0.0024181583,0.9437974,0.00008234821,0.0009799176,0.0011869584,0.000016637146,0.0012833239,0.0498969],"genre_scores_gemma":[0.96151304,0.00019966054,0.035090614,0.0002292556,0.0003939476,0.0007365657,0.00007133323,0.000088112705,0.0016774837],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997364,0.00006429938,0.0007721578,0.0006402625,0.0001721871,0.0009871201],"domain_scores_gemma":[0.9987903,0.00031157004,0.00008427062,0.00051680155,0.00012592397,0.00017112229],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00042938924,0.0005314898,0.00059853104,0.0003805521,0.00040400436,0.00036368528,0.00031164614,0.00045139197,0.00009874687],"category_scores_gemma":[0.00008204777,0.0005837018,0.0004045264,0.0008292621,0.00011869536,0.00025685385,0.00009072929,0.00051151164,0.000003149888],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000033740424,0.00014944428,0.00008084449,0.0007256894,0.00037721172,0.000010560797,0.0001577269,0.80332315,0.00082830753,0.16207923,0.015421568,0.016812544],"study_design_scores_gemma":[0.00060588977,0.000118888915,0.00003855642,0.00017753075,0.00029843484,0.000009584906,0.00016162511,0.98930895,0.0014645746,0.0065057436,0.00071636325,0.00059384515],"about_ca_topic_score_codex":0.000028995619,"about_ca_topic_score_gemma":0.0000032547985,"teacher_disagreement_score":0.96117467,"about_ca_system_score_codex":0.00012494,"about_ca_system_score_gemma":0.000047018617,"threshold_uncertainty_score":0.99966145},"labels":[],"label_agreement":null},{"id":"W7117052908","doi":"10.1109/icsj66986.2025.11302602","title":"Digital-Twin-Driven Machine Learning for Thermal Optimization of Flip-Chip Packages","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Ottawa","funders":"","keywords":"Bayesian optimization; Bayesian probability; Thermal; Thermal resistance; Ball grid array; Work (physics)","score_opus":0.00906152705938497,"score_gpt":0.22573185896286893,"score_spread":0.21667033190348395,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7117052908","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0024648784,0.00094403327,0.92896044,0.00013361729,0.00019064835,0.0006912844,0.00004752474,0.0005573553,0.0660102],"genre_scores_gemma":[0.9514053,0.00034620264,0.039073676,0.000035093733,0.0000696819,0.00005255031,0.00009653538,0.00006793041,0.008853042],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99863166,0.000034631157,0.0005578594,0.00028604097,0.00014040626,0.00034942958],"domain_scores_gemma":[0.99918026,0.00024242436,0.000104840656,0.00027598007,0.00013697361,0.00005951524],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00017628001,0.00031611708,0.00043132808,0.00027718506,0.00011095628,0.0001348068,0.00024633037,0.00024059905,0.00032287787],"category_scores_gemma":[0.00016227784,0.0003122404,0.00022212537,0.00034105298,0.000057051722,0.00036151288,0.00008670424,0.00024969463,0.0000055418573],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000046428773,0.0000769879,0.0019211868,0.0005082311,0.0002385841,0.0000011726457,0.0002366979,0.85854346,0.016442323,0.0027604536,0.000596861,0.11862764],"study_design_scores_gemma":[0.0005717577,0.00021207145,0.00022315269,0.00023635001,0.00008947656,8.129968e-7,0.00007866154,0.9273511,0.06825992,0.0002095488,0.0024645515,0.00030259383],"about_ca_topic_score_codex":0.000011497976,"about_ca_topic_score_gemma":0.0000017521048,"teacher_disagreement_score":0.9489404,"about_ca_system_score_codex":0.000054736764,"about_ca_system_score_gemma":0.000040528703,"threshold_uncertainty_score":0.99993294},"labels":[],"label_agreement":null},{"id":"W7123334896","doi":"10.1109/icm66518.2025.11322520","title":"Effective Partitioning Approaches for High Performance FPGA Routing","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Scalability; Field-programmable gate array; Routing (electronic design automation); Workload; Multi-core processor; Parallelism (grammar); Scheduling (production processes); Thread (computing)","score_opus":0.018021350018006945,"score_gpt":0.22250295654695637,"score_spread":0.20448160652894942,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7123334896","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.053148467,0.0005996912,0.89451057,0.000126097,0.00056083413,0.0018367624,0.0000112989965,0.0009394657,0.04826679],"genre_scores_gemma":[0.97868526,0.00011064331,0.017716212,0.000076125594,0.00020893321,0.0011437323,0.000017551754,0.000049014525,0.0019925009],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983695,0.000044480854,0.00045656672,0.0004216586,0.00011335066,0.00059443526],"domain_scores_gemma":[0.9991387,0.00035359093,0.000062848696,0.00030859013,0.00007615178,0.000060110324],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005625764,0.0003552745,0.0004056591,0.00019779392,0.0003924346,0.00015679355,0.0002080368,0.00026455274,0.000064292006],"category_scores_gemma":[0.00008707546,0.0003701132,0.00013533133,0.00040528024,0.000058924776,0.00034203162,0.00007648317,0.00030183213,0.000020869344],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000072019,0.00010963837,0.0024325252,0.0024409562,0.00045631418,0.000001378242,0.0006710323,0.021038594,0.002321325,0.15709765,0.0026347237,0.81072384],"study_design_scores_gemma":[0.00067335804,0.00023956684,0.0049101566,0.0007525875,0.00015516255,0.0000017484488,0.00020582217,0.5693787,0.417487,0.0047806134,0.0009141635,0.00050117983],"about_ca_topic_score_codex":0.00003045703,"about_ca_topic_score_gemma":0.000003752305,"teacher_disagreement_score":0.9255368,"about_ca_system_score_codex":0.00021473471,"about_ca_system_score_gemma":0.000040979387,"threshold_uncertainty_score":0.99987507},"labels":[],"label_agreement":null},{"id":"W7127350437","doi":"10.1109/icfpt67023.2025.00043","title":"Congestion-Aware CAD Optimizations for Routing-Constrained FPGAs","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Routing (electronic design automation); Multipath routing; Equal-cost multi-path routing; Benchmark (surveying); Static routing; Field-programmable gate array; Critical path method; Path (computing); Minification","score_opus":0.01207941861877767,"score_gpt":0.25890302294324324,"score_spread":0.24682360432446557,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7127350437","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00013645508,0.00040489147,0.9339804,0.0012697824,0.00068931957,0.0013330029,0.00016799409,0.0014122948,0.060605884],"genre_scores_gemma":[0.91322553,0.0002480414,0.07327304,0.0003014931,0.00013281182,0.00032756708,0.0000891016,0.00006095344,0.012341477],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99829376,0.00003253188,0.0006272567,0.00040435954,0.00011074889,0.000531375],"domain_scores_gemma":[0.9987665,0.0003529339,0.000062332176,0.00040969206,0.0002898556,0.0001187109],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00025754166,0.00037323087,0.0004019017,0.0003034774,0.00032223537,0.00017822701,0.0002768266,0.00039264312,0.0005802345],"category_scores_gemma":[0.00022266903,0.0004156381,0.00020464492,0.0005479577,0.000105132574,0.00019673296,0.00005433423,0.00024498196,0.000022536582],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000045444198,0.00022856692,0.0007168442,0.00093955494,0.00076841144,0.000008694232,0.0005486322,0.20962629,0.002866678,0.6235642,0.083049044,0.07763769],"study_design_scores_gemma":[0.0011308095,0.000120742916,0.00016320353,0.00045318707,0.00028447874,0.0000063253447,0.0003571448,0.9655531,0.016347546,0.0046140435,0.010320234,0.0006491683],"about_ca_topic_score_codex":0.000048111153,"about_ca_topic_score_gemma":0.000026340716,"teacher_disagreement_score":0.91308904,"about_ca_system_score_codex":0.00015751286,"about_ca_system_score_gemma":0.00021323356,"threshold_uncertainty_score":0.99982953},"labels":[],"label_agreement":null},{"id":"W7127395105","doi":"10.1109/icfpt67023.2025.00042","title":"Efficient FPGA Resource Graph Learning with Graph Neural Networks for Router Runtime Prediction","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Router; Field-programmable gate array; Convolutional neural network; Artificial neural network; Routing (electronic design automation); Graph; Key (lock); Resource (disambiguation)","score_opus":0.005103181421566539,"score_gpt":0.19567787911054296,"score_spread":0.19057469768897642,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7127395105","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.01247805,0.0013298579,0.97179043,0.00015824835,0.00053081027,0.0015386203,0.000012235523,0.0019718108,0.010189943],"genre_scores_gemma":[0.99060506,0.000087115426,0.0048561413,0.00019337492,0.00026489704,0.00028538183,0.00004730718,0.00010980179,0.0035509288],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9974102,0.00010061899,0.0006451907,0.00068404427,0.0002719727,0.0008880114],"domain_scores_gemma":[0.9989261,0.00020994667,0.00010793867,0.0004700139,0.0001388899,0.00014708789],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005207372,0.0005685484,0.000507221,0.0006107178,0.00049148133,0.00024640159,0.00030180035,0.00042633375,0.000071283815],"category_scores_gemma":[0.000025804815,0.0005092802,0.0003213744,0.0011838423,0.000115822506,0.00011515169,0.0000894022,0.0008256426,0.000003411926],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00021081475,0.00007882254,0.0012859675,0.00019508328,0.00027262868,0.0000050087647,0.00022400785,0.9619474,0.0002652607,0.00082247145,0.0068252496,0.027867312],"study_design_scores_gemma":[0.00106796,0.00070143427,0.0010781621,0.0003741221,0.00029758198,0.000009577551,0.00018868168,0.9864658,0.0020299766,0.00015766169,0.007133831,0.0004952],"about_ca_topic_score_codex":0.000032663087,"about_ca_topic_score_gemma":0.0000075053654,"teacher_disagreement_score":0.978127,"about_ca_system_score_codex":0.000105965206,"about_ca_system_score_gemma":0.000024425157,"threshold_uncertainty_score":0.9997359},"labels":[],"label_agreement":null},{"id":"W7132875402","doi":"","title":"Machine Learning for Cutting Planes in Mixed Integer Linear Programming","year":2024,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Integer programming; Linear programming; Cutting-plane method; Artificial neural network; Feature selection; Graph; Constraint (computer-aided design); Constraint programming; Column generation","score_opus":0.01808971292237653,"score_gpt":0.31969596156181596,"score_spread":0.3016062486394394,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132875402","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.2974062,0.12155362,0.50603527,0.0013556198,0.013341179,0.017930802,0.00011269875,0.0125969695,0.029667605],"genre_scores_gemma":[0.93349427,0.0012382925,0.032144852,0.000014263798,0.00087407004,0.0011558912,0.0024801968,0.00066528935,0.027932873],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9973033,0.000079174475,0.00078967784,0.0007280956,0.00026024124,0.00083952106],"domain_scores_gemma":[0.9989026,0.00042401758,0.00019227316,0.00026212528,0.000100397985,0.000118583775],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006975069,0.000782472,0.00081167644,0.00075194053,0.0001545335,0.0002285041,0.00030430095,0.0008008698,0.00008541175],"category_scores_gemma":[0.00039379246,0.0008513337,0.00029796784,0.00059651805,0.000026485764,0.0001398556,0.00005236658,0.0019839664,0.00009266708],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00079989014,0.00038424705,0.0037564458,0.052263625,0.0012388908,0.00043956,0.18384989,0.049815968,0.065547094,0.0061576082,0.0011512169,0.6345956],"study_design_scores_gemma":[0.00065675273,0.00043928222,0.00007625651,0.0065178745,0.0002949743,0.000024147734,0.010900288,0.8944086,0.024739461,0.0005520843,0.059821203,0.0015690877],"about_ca_topic_score_codex":0.0006286845,"about_ca_topic_score_gemma":0.00040435887,"teacher_disagreement_score":0.84459263,"about_ca_system_score_codex":0.0002145984,"about_ca_system_score_gemma":0.00007390584,"threshold_uncertainty_score":0.99939376},"labels":[],"label_agreement":null},{"id":"W7132923394","doi":"","title":"Synthesizeable Heterogeneous FPGA Fabrics","year":2019,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Stratix; Suite; Process (computing); FPGA prototype; Carry (investment); Reconfigurable computing","score_opus":0.016154035128383423,"score_gpt":0.28176001858931826,"score_spread":0.26560598346093484,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132923394","genre_codex":"other","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.24941736,0.04456287,0.11764626,0.00042633156,0.011850613,0.006898936,0.00013511372,0.005830382,0.5632321],"genre_scores_gemma":[0.8816976,0.0033221615,0.0023760404,0.000055047563,0.00030992887,0.00014213104,0.00026306818,0.000459696,0.11137431],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9970344,0.000084674735,0.0006373765,0.00078478025,0.0005089124,0.0009499128],"domain_scores_gemma":[0.9979471,0.0002764746,0.0002601235,0.0011289432,0.00015916157,0.00022822445],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":["insufficient_payload"],"category_scores_codex":[0.00023857635,0.0009914231,0.0010372491,0.00036515988,0.00015955076,0.0002201024,0.0006739203,0.0012753257,0.0025830057],"category_scores_gemma":[0.00010192658,0.001150981,0.00043520765,0.00039945383,0.000035322526,0.00016122498,0.000056222587,0.00089214585,0.003182459],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0006163961,0.00087005895,0.0005274113,0.023112787,0.0034356704,0.00069654896,0.051549703,0.079370975,0.5502114,0.003466567,0.04653042,0.23961204],"study_design_scores_gemma":[0.00061693223,0.0005179928,0.00011697623,0.0020688965,0.00067054114,0.00010394008,0.0023290496,0.051689923,0.8994847,0.00076492416,0.038020533,0.0036156035],"about_ca_topic_score_codex":0.00027731198,"about_ca_topic_score_gemma":0.000024703319,"teacher_disagreement_score":0.63228023,"about_ca_system_score_codex":0.00030918643,"about_ca_system_score_gemma":0.00013324822,"threshold_uncertainty_score":0.999094},"labels":[],"label_agreement":null},{"id":"W7132936008","doi":"","title":"Design Mapping And Optimization For Field Programmable Gate Arrays With Embedded Networks On Chip","year":2023,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Netlist; Field-programmable gate array; Gate array; Design flow; Place and route; Latency (audio); Bandwidth (computing); System on a chip; Electronic design automation; Network on a chip","score_opus":0.028531560003283215,"score_gpt":0.2834819846349308,"score_spread":0.2549504246316476,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132936008","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0014124218,0.00044467914,0.99219,0.00010242032,0.00035912922,0.0034728895,0.0000025606112,0.0009917415,0.0010241716],"genre_scores_gemma":[0.13933773,0.0044395737,0.8298344,0.00015692414,0.0009031593,0.0048226244,0.0015642338,0.001077676,0.017863648],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979667,0.00006561837,0.000399205,0.00064418657,0.00022026878,0.00070398994],"domain_scores_gemma":[0.9985867,0.00052285835,0.00023424737,0.0003654062,0.00014244675,0.00014831977],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00039841095,0.0006589142,0.00059059606,0.00031433447,0.00029876456,0.0002804812,0.00018488942,0.00069367734,0.000053213764],"category_scores_gemma":[0.000084735315,0.0006605079,0.00009621205,0.0005416861,0.000024193865,0.00013739473,0.000016221558,0.0005360602,0.0000068312984],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00047271652,0.000030077505,0.000006914436,0.0009883211,0.00018952443,0.000008255748,0.0054029454,0.9746801,0.00059084105,0.00014014491,0.0009825795,0.01650755],"study_design_scores_gemma":[0.00070378697,0.0013040175,0.000014057764,0.0019008322,0.00016377564,0.0000043304753,0.0020020162,0.9834674,0.009299117,0.00022927357,0.00011000293,0.0008014165],"about_ca_topic_score_codex":0.00004729639,"about_ca_topic_score_gemma":0.000027734146,"teacher_disagreement_score":0.16235556,"about_ca_system_score_codex":0.0000740034,"about_ca_system_score_gemma":0.000055667777,"threshold_uncertainty_score":0.9995846},"labels":[],"label_agreement":null},{"id":"W7132936157","doi":"","title":"Automated FPGA design, verification and layout","year":2004,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Field-programmable gate array; Process (computing); Integrated circuit layout; IC layout editor; Page layout; FPGA prototype; Design layout record; Electronic design automation","score_opus":0.02126753463756011,"score_gpt":0.3060845718431392,"score_spread":0.2848170372055791,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132936157","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.18229155,0.027245,0.7194423,0.0008422578,0.0028924833,0.0070049455,0.00005427339,0.020881856,0.03934531],"genre_scores_gemma":[0.97216386,0.002379165,0.019472487,0.000024795007,0.00014221753,0.0001984455,0.00047090548,0.0002283193,0.004919819],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9980547,0.000092426555,0.0004935556,0.000591798,0.00028246045,0.00048506854],"domain_scores_gemma":[0.99886966,0.000097767814,0.00020767526,0.0005011741,0.00013779078,0.00018593445],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00028244793,0.00065693125,0.00055201986,0.00032348145,0.00019191328,0.00018767765,0.00024623345,0.0009171277,0.00023947036],"category_scores_gemma":[0.00007953098,0.00076933537,0.00009868377,0.00038523143,0.00005612079,0.0002033628,0.00002017199,0.0005237602,0.00020492313],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00044423112,0.0003860797,0.00012712406,0.006715912,0.0009123738,0.000117751115,0.087017566,0.035660222,0.79312515,0.004640546,0.013809585,0.05704348],"study_design_scores_gemma":[0.0019836172,0.00076001236,0.007980233,0.0031192855,0.0007956262,0.00007432382,0.004383748,0.2839262,0.6869362,0.0034655377,0.0029301937,0.0036450261],"about_ca_topic_score_codex":0.00029107157,"about_ca_topic_score_gemma":0.000019602889,"teacher_disagreement_score":0.7898723,"about_ca_system_score_codex":0.00028889385,"about_ca_system_score_gemma":0.0001624278,"threshold_uncertainty_score":0.9994758},"labels":[],"label_agreement":null},{"id":"W7132988041","doi":"","title":"Increasing FPGA CAD Adaptability using Reinforcement Learning and Smart Perturbations","year":2024,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"University of Toronto; VMware","keywords":"Adaptability; Field-programmable gate array; Exploit; CAD; Critical path method; Block (permutation group theory); Reinforcement learning; Path (computing)","score_opus":0.023747556715854986,"score_gpt":0.3119064644131156,"score_spread":0.2881589076972606,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132988041","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.90240616,0.014810739,0.04678894,0.00013278918,0.0011214002,0.0013070921,0.0000072231323,0.0011964489,0.032229226],"genre_scores_gemma":[0.9835111,0.0012765493,0.0055412557,0.000012804126,0.00023124678,0.00006690892,0.00020543164,0.000197941,0.008956791],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9973236,0.00018891765,0.0007261231,0.0007434497,0.0004078505,0.0006100982],"domain_scores_gemma":[0.99872905,0.00033321773,0.0001904192,0.00036850115,0.00016827586,0.00021055367],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007727511,0.00074784394,0.0006592717,0.00044146756,0.00052797876,0.00039987295,0.00016258728,0.0006632605,0.00043190844],"category_scores_gemma":[0.0003990596,0.0008572907,0.00020416304,0.00048250754,0.00008072588,0.00027589186,0.00010273402,0.0014871312,0.00004476699],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00049557345,0.00018434208,0.007241286,0.020623215,0.001961151,0.0001344075,0.20188783,0.11126339,0.5886902,0.0053814407,0.0007540219,0.061383124],"study_design_scores_gemma":[0.0003735576,0.0002617557,0.0014697852,0.0037977695,0.001076226,0.00010829283,0.015562333,0.9486106,0.015687902,0.0007511213,0.01039631,0.0019043678],"about_ca_topic_score_codex":0.0036424696,"about_ca_topic_score_gemma":0.00016624258,"teacher_disagreement_score":0.8373472,"about_ca_system_score_codex":0.00059250096,"about_ca_system_score_gemma":0.00018699406,"threshold_uncertainty_score":0.9993878},"labels":[],"label_agreement":null},{"id":"W7132988363","doi":"","title":"Architecture and CAD Techniques for Efficient FPGA Implementation of Machine Learning and Other Applications","year":2022,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Flexibility (engineering); Convolutional neural network; Convolution (computer science); Software; Architecture; Reconfigurable computing; Kernel (algebra); Artificial neural network","score_opus":0.0090377371999655,"score_gpt":0.33652820650948356,"score_spread":0.3274904693095181,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7132988363","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.081126004,0.01969239,0.88224655,0.00031477868,0.00014038688,0.010745927,0.000804515,0.0009515676,0.003977868],"genre_scores_gemma":[0.9618919,0.0016542214,0.028512329,0.000031906628,0.0001177801,0.004714104,0.001009402,0.00025173105,0.0018166408],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99865687,0.000061767685,0.00041624287,0.000411947,0.00018852467,0.0002646721],"domain_scores_gemma":[0.99919647,0.00017952427,0.00030237436,0.00018365693,0.00006706365,0.00007089865],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00031447472,0.00036517583,0.00041409195,0.00035273947,0.00028337835,0.000041449293,0.000119647135,0.00020457798,0.00031720795],"category_scores_gemma":[0.00001857138,0.00040720843,0.00008765329,0.0002254058,0.000049730777,0.000024979832,0.000051891595,0.00046326546,3.6326895e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014378277,0.00010199073,0.0011355878,0.0052164784,0.0002787168,9.0226416e-7,0.036082845,0.0016622512,0.18610771,0.003012196,0.0001594521,0.7660981],"study_design_scores_gemma":[0.0012959967,0.0013892278,0.00083907275,0.00038770237,0.0007107904,0.00003251301,0.023491042,0.0121763665,0.7521902,0.0019787077,0.2039152,0.0015932324],"about_ca_topic_score_codex":0.00064248435,"about_ca_topic_score_gemma":0.00017395389,"teacher_disagreement_score":0.88076586,"about_ca_system_score_codex":0.00006948215,"about_ca_system_score_gemma":0.000036038084,"threshold_uncertainty_score":0.999838},"labels":[],"label_agreement":null},{"id":"W7133014279","doi":"","title":"Fast CAD for FPGAs","year":2014,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; CAD; Routing (electronic design automation); Process (computing); FPGA prototype; Reconfigurable computing; Reduction (mathematics)","score_opus":0.015239062565291285,"score_gpt":0.31255763309588996,"score_spread":0.2973185705305987,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7133014279","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016386095,0.0031980695,0.82247233,0.00037671116,0.003086176,0.0029953714,0.00006955269,0.0014889091,0.14992675],"genre_scores_gemma":[0.8003416,0.0009974119,0.023435509,0.00010286695,0.0018300194,0.0011942156,0.0014618894,0.000638259,0.16999824],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99814826,0.000036039415,0.00044622816,0.00050928764,0.00022949598,0.0006307131],"domain_scores_gemma":[0.9987123,0.00020616362,0.00017906255,0.00054580526,0.00018466113,0.00017198279],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00026501872,0.00064247585,0.00068151136,0.00023684729,0.00016298098,0.00011040452,0.00038000912,0.0008696429,0.00044395402],"category_scores_gemma":[0.00011702955,0.0007371825,0.0003404931,0.0001785502,0.000026651023,0.00008615908,0.000018038509,0.00047039703,0.00026029922],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00051554875,0.0002904515,0.00013232077,0.022271967,0.001278399,0.000022558575,0.051608514,0.0065314863,0.27808854,0.041050408,0.219055,0.3791548],"study_design_scores_gemma":[0.0022636724,0.0011387232,0.0005750406,0.003270094,0.0010808854,0.000019072879,0.0044474937,0.09814499,0.5643671,0.0075235157,0.31228918,0.0048802164],"about_ca_topic_score_codex":0.00016839827,"about_ca_topic_score_gemma":0.00011799459,"teacher_disagreement_score":0.79903686,"about_ca_system_score_codex":0.0001249746,"about_ca_system_score_gemma":0.000058848054,"threshold_uncertainty_score":0.9995079},"labels":[],"label_agreement":null},{"id":"W7133044443","doi":"","title":"Technology migration for hard Ips","year":2003,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Bibliographical Society of Canada; University of Toronto","funders":"","keywords":"Constraint (computer-aided design); Process (computing); TRACE (psycholinguistics); Design technology; Port (circuit theory); Key (lock); Architecture; Power (physics)","score_opus":0.018033390110788236,"score_gpt":0.3027783493887197,"score_spread":0.2847449592779315,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7133044443","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14992632,0.020198151,0.7612252,0.0032357024,0.005444369,0.007945926,0.00009632456,0.004331966,0.047596034],"genre_scores_gemma":[0.43598875,0.0062093907,0.17960483,0.0001679555,0.00082657224,0.0050446913,0.0028602951,0.0010349388,0.3682626],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99818885,0.000029601846,0.00048777706,0.0005434514,0.00017924015,0.0005710706],"domain_scores_gemma":[0.9988375,0.00008563206,0.00020285149,0.00054122973,0.00024492445,0.000087901906],"candidate_categories":["metaepi_narrow","research_integrity"],"consensus_categories":[],"category_scores_codex":[0.00020156197,0.00059070473,0.0005934142,0.0006749161,0.00018227623,0.00008172035,0.00029923467,0.0015945502,0.0003099449],"category_scores_gemma":[0.00018604861,0.0007054965,0.00023829221,0.0005581338,0.000039778493,0.000118708114,0.000010367322,0.00054412923,0.00013283214],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015236062,0.00022437425,0.00043333153,0.004222815,0.0006219487,0.000014248565,0.010104939,0.00052010966,0.74641365,0.044275954,0.10348865,0.08952763],"study_design_scores_gemma":[0.0007310565,0.0005633497,0.00010604195,0.00062763516,0.00037992644,0.000018155226,0.004141094,0.006558037,0.79752076,0.010976794,0.17680064,0.0015764992],"about_ca_topic_score_codex":0.000033780307,"about_ca_topic_score_gemma":0.00011004737,"teacher_disagreement_score":0.5816204,"about_ca_system_score_codex":0.00018138425,"about_ca_system_score_gemma":0.000088926754,"threshold_uncertainty_score":0.9997016},"labels":[],"label_agreement":null},{"id":"W7133087281","doi":"","title":"Device Placement Optimization with Deep Reinforcement Learning","year":2023,"lang":"","type":"dissertation","venue":"TSpace","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Pipeline (software); Reinforcement learning; Deep learning; Artificial neural network; Deep neural networks; Generalizability theory; Scheduling (production processes); Granularity","score_opus":0.01492511900388855,"score_gpt":0.2835500901668331,"score_spread":0.26862497116294454,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7133087281","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.003664847,0.00070631405,0.9528095,0.000088184956,0.0005577618,0.0016244068,7.6103913e-7,0.0019190047,0.0386292],"genre_scores_gemma":[0.7285752,0.006567709,0.032120626,0.00007213746,0.00051561644,0.0012817167,0.0046538776,0.0010882943,0.22512479],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99733883,0.00007601902,0.00061007164,0.00059540186,0.00067067664,0.0007090194],"domain_scores_gemma":[0.99866647,0.00013114497,0.00035222253,0.00042516427,0.00024060543,0.00018442245],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0003146211,0.00077379844,0.0005743165,0.00045235959,0.000336605,0.00019750973,0.00029042145,0.0005127742,0.0014228992],"category_scores_gemma":[0.00007014226,0.00081219437,0.000120551544,0.0008119208,0.000026731654,0.00019704145,0.000048198097,0.00087658054,0.00047215124],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014170485,0.000019781472,0.000046367928,0.00095318566,0.00026630383,0.000021340009,0.011379073,0.9841798,0.0008613002,0.00011785233,0.00044776726,0.0015655333],"study_design_scores_gemma":[0.0007198339,0.000591292,0.00005597642,0.001404111,0.00033306194,0.000005601256,0.013214373,0.97235847,0.008973489,0.000008743607,0.0012151606,0.0011198712],"about_ca_topic_score_codex":0.00025080435,"about_ca_topic_score_gemma":0.00014182697,"teacher_disagreement_score":0.92068887,"about_ca_system_score_codex":0.00044874486,"about_ca_system_score_gemma":0.000107202206,"threshold_uncertainty_score":0.99948996},"labels":[],"label_agreement":null},{"id":"W7133197846","doi":"10.5753/eradse.2025.16932","title":"Modelo de refinamento em paralelo para malhas de elementos finitos","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Work (physics); GLUE; Finite element method; 3d model","score_opus":0.019163837631545822,"score_gpt":0.2778028173552908,"score_spread":0.25863897972374494,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7133197846","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0434133,0.0020957764,0.869179,0.00066434033,0.00022298304,0.0007576632,0.000025131418,0.001317105,0.08232471],"genre_scores_gemma":[0.91831505,0.0018860765,0.056497205,0.0010984391,0.00013459347,0.0003770311,0.000014781023,0.00008452516,0.021592306],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9968058,0.00012568137,0.0008343719,0.0005652982,0.00027512544,0.0013937624],"domain_scores_gemma":[0.99863404,0.000116023635,0.00007786849,0.0008247377,0.00007383347,0.00027346934],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0006710585,0.00059463416,0.00054744596,0.00037141953,0.00019894497,0.00029748926,0.00062390807,0.0005057277,0.0013287027],"category_scores_gemma":[0.000053470707,0.00066404155,0.00025702495,0.0005694393,0.000050724226,0.00026583066,0.00018421176,0.0005882033,0.00016121364],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000356043,0.0012944397,0.016144998,0.0031803434,0.0021330891,0.0003867486,0.0064820102,0.053870946,0.12031954,0.15446949,0.33511838,0.30624396],"study_design_scores_gemma":[0.0015088663,0.00033319765,0.0019755242,0.00075861043,0.00038083273,0.000024650306,0.0009421082,0.6835792,0.21878399,0.033229593,0.05697228,0.0015111611],"about_ca_topic_score_codex":0.00027687792,"about_ca_topic_score_gemma":0.000090951144,"teacher_disagreement_score":0.8749018,"about_ca_system_score_codex":0.0008142563,"about_ca_system_score_gemma":0.00028977438,"threshold_uncertainty_score":0.9995842},"labels":[],"label_agreement":null},{"id":"W7140458299","doi":"10.1109/fpl68686.2025.00056","title":"Using Data to Reduce Uncertainty in FPGA Routing","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Routing (electronic design automation); Field-programmable gate array; Ideal (ethics); Closure (psychology); Network routing; Retard","score_opus":0.10326613648350451,"score_gpt":0.34837182880878964,"score_spread":0.24510569232528512,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7140458299","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.052873854,0.0010884843,0.8635565,0.00077446015,0.0011226645,0.0011882867,0.000060185546,0.00088757,0.07844796],"genre_scores_gemma":[0.9531463,0.000085475236,0.045245472,0.00033536373,0.00011256808,0.000010750172,0.000017734761,0.000039234885,0.0010071308],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99770814,0.00007414405,0.00069639063,0.0006909946,0.00016566724,0.00066465384],"domain_scores_gemma":[0.9981754,0.00012173725,0.00003704857,0.0015021149,0.000048678376,0.00011502893],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00091983983,0.0003287976,0.00042072826,0.0005038068,0.0000970338,0.00015939173,0.0010643235,0.0002364126,0.00018055043],"category_scores_gemma":[0.00028497566,0.0003704294,0.00004848662,0.0014863297,0.000027011003,0.00036150354,0.0009241927,0.00043707248,0.000029261697],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007516177,0.00020201084,0.0018011462,0.0006524459,0.00021343237,0.0000894549,0.0014630941,0.2974802,0.25140142,0.013174318,0.026437046,0.4070103],"study_design_scores_gemma":[0.00031641682,0.000025873152,0.00043669718,0.0012240936,0.00004728535,0.000004129751,0.0004886752,0.95173633,0.038186476,0.0007073129,0.0063020806,0.00052464893],"about_ca_topic_score_codex":0.002231382,"about_ca_topic_score_gemma":0.00029942667,"teacher_disagreement_score":0.9002724,"about_ca_system_score_codex":0.00047209143,"about_ca_system_score_gemma":0.00017476935,"threshold_uncertainty_score":0.9998748},"labels":[],"label_agreement":null},{"id":"W7140692658","doi":"10.1109/fpl68686.2025.00068","title":"Compile in Seconds and Run on an FPGA with DynaRapid","year":2025,"lang":"","type":"article","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Advanced Micro Devices (Canada)","funders":"","keywords":"Field-programmable gate array; Compile time; Compiler; Key (lock)","score_opus":0.006051528091407388,"score_gpt":0.22169109976548404,"score_spread":0.21563957167407666,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7140692658","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.5956502,0.0012198384,0.044652473,0.00025020997,0.00019028013,0.0007596828,0.000020156132,0.00078986376,0.3564673],"genre_scores_gemma":[0.9949492,0.00023714398,0.002849494,0.00035266756,0.000023178836,0.000030770356,0.0000068683603,0.000029426383,0.0015212276],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989177,0.00004318764,0.00027638522,0.0003465159,0.000095802396,0.00032043346],"domain_scores_gemma":[0.9994582,0.00006159134,0.0000204873,0.00034482768,0.00002246819,0.00009241041],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00018439243,0.00027601182,0.00032832538,0.00037026394,0.00005579757,0.000090560236,0.00014370227,0.00018347614,0.00046965902],"category_scores_gemma":[0.0000042399147,0.000247122,0.000025432457,0.00037659632,0.00006355914,0.00020234838,0.00003622268,0.00035621552,0.000010669756],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00089438504,0.0017925291,0.06370249,0.002503573,0.0005725595,0.0003572885,0.0037690615,0.009167871,0.026720598,0.18992078,0.01057017,0.69002867],"study_design_scores_gemma":[0.008225295,0.008456209,0.14923982,0.0035479995,0.00018318105,0.000059399703,0.0025279555,0.5430931,0.24654682,0.015074949,0.01950864,0.0035366614],"about_ca_topic_score_codex":0.000100935315,"about_ca_topic_score_gemma":0.00041031686,"teacher_disagreement_score":0.686492,"about_ca_system_score_codex":0.00007625746,"about_ca_system_score_gemma":0.00003293054,"threshold_uncertainty_score":0.9999981},"labels":[],"label_agreement":null},{"id":"W7148362437","doi":"10.70675/5559690az1cf0z4119z83c3zc03ef82e2977","title":"Load Balancing of Multi-physics Simulation by Multi-criteria Graph Partitioning","year":2017,"lang":"","type":"dissertation","venue":"","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Graph; Partition (number theory); Processor scheduling","score_opus":0.028830410806294945,"score_gpt":0.3173507336935314,"score_spread":0.28852032288723645,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W7148362437","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016025094,0.0014798754,0.9760941,0.0000062306203,0.0010819978,0.0009775006,0.00018507287,0.0005258508,0.0036242588],"genre_scores_gemma":[0.970915,0.0005039476,0.023501838,0.00001059099,0.00016827637,0.00009225352,0.001463074,0.00017690154,0.0031681252],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9969121,0.00008033792,0.0012183479,0.0006502617,0.0004896929,0.00064923905],"domain_scores_gemma":[0.99742275,0.0001701057,0.00079734746,0.0008425204,0.0005951628,0.0001720998],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004161769,0.0008000541,0.0009792617,0.00018500973,0.00042712776,0.0002532901,0.00047052526,0.00085019955,0.0004460481],"category_scores_gemma":[0.00023758893,0.0009315388,0.00041090132,0.00019983618,0.000083460436,0.0008110265,0.000033089163,0.00055437797,0.000042445376],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009541506,0.00066232565,0.0027349691,0.0038697182,0.0005832556,0.000008827343,0.0047513,0.103289045,0.82015294,0.00034361903,0.0013394174,0.06216919],"study_design_scores_gemma":[0.0009569736,0.00008159676,0.001306662,0.0013243125,0.00018928254,7.021264e-7,0.00020932894,0.7474177,0.247106,0.00033711828,0.00017797633,0.000892389],"about_ca_topic_score_codex":0.00067269604,"about_ca_topic_score_gemma":0.00017564755,"teacher_disagreement_score":0.9548899,"about_ca_system_score_codex":0.00021367765,"about_ca_system_score_gemma":0.00011092419,"threshold_uncertainty_score":0.99931353},"labels":[],"label_agreement":null}]}