{"meta":{"query_hash":"4d0a679da2cb","filters":{"venue":"27th ACM/IEEE Design Automation Conference"},"cohort_total":3,"direct_labels_cover":0,"predictions_cover":3,"exported":3,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/4d0a679da2cb","api":"https://metacan.xera.ac/api/v1/cohort?venue=27th+ACM%2FIEEE+Design+Automation+Conference"},"results":[{"id":"W3150866691","doi":"10.1109/dac.1990.114841","title":"Timing analysis in precharge/unate networks","year":2002,"lang":"en","type":"article","venue":"27th ACM/IEEE Design Automation Conference","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Computer science; Path (computing); Computer network","score_opus":0.06115887695551186,"score_gpt":0.23859867988254765,"score_spread":0.1774398029270358,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3150866691","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07032813,0.00025961446,0.92493373,0.00007175157,0.0005330262,0.00049106614,0.0000056111007,0.0012343845,0.0021427087],"genre_scores_gemma":[0.98596203,0.00025691546,0.013231554,0.000065644,0.000077521574,0.00012281549,0.00001991575,0.000050056362,0.0002135213],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99786395,0.00014904732,0.00063038425,0.0004006593,0.00035086425,0.00060509006],"domain_scores_gemma":[0.9986874,0.00023242625,0.00012024628,0.0007092756,0.000112711496,0.00013793315],"candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.00054977357,0.00035392,0.00045689172,0.0008145131,0.000094396695,0.00017967129,0.0005981902,0.00023314483,0.0011359219],"category_scores_gemma":[0.00010124878,0.0003780379,0.000103876235,0.0020650679,0.000041391275,0.0007518817,0.000034616492,0.00035660423,0.0004753378],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000070550127,0.000038437065,0.001656195,0.00004483605,0.00016960764,0.000014720091,0.0009963698,0.9747434,0.0029442632,0.00018775612,0.002554431,0.016642908],"study_design_scores_gemma":[0.0003886935,0.000029615305,0.006212602,0.0000613817,0.00010329093,0.0000036266779,0.000019634519,0.9875299,0.004902545,0.00016009042,0.00016238172,0.00042624687],"about_ca_topic_score_codex":0.000016399872,"about_ca_topic_score_gemma":0.000022284226,"teacher_disagreement_score":0.9156339,"about_ca_system_score_codex":0.0002035462,"about_ca_system_score_gemma":0.000027037018,"threshold_uncertainty_score":0.99986714},"labels":[],"label_agreement":null},{"id":"W4246796329","doi":"10.1109/dac.1990.114892","title":"System simulation of printed circuit boards including packages and connectors","year":2002,"lang":"en","type":"article","venue":"27th ACM/IEEE Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Quantic EMC (Canada)","funders":"","keywords":"Printed circuit board; Computer science; Integrated circuit packaging; Circuit extraction; Electronic packaging; Engineering drawing; Electrical engineering; Electronic engineering; Engineering; Integrated circuit; Equivalent circuit; Operating system; Voltage","score_opus":0.10636625896206409,"score_gpt":0.2685288992032618,"score_spread":0.1621626402411977,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4246796329","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11878449,0.00012873921,0.87730736,0.000013632219,0.00014558596,0.00044435315,0.000009921812,0.0015826197,0.0015832888],"genre_scores_gemma":[0.99547285,0.000050420367,0.0043328954,0.000009373499,0.000032517193,0.00004182791,0.0000051610064,0.000030725845,0.000024228188],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.998809,0.00010691299,0.00043480413,0.00021081923,0.00022970092,0.00020879936],"domain_scores_gemma":[0.9989433,0.00034118778,0.00013562826,0.00033124522,0.0001714537,0.000077153156],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000319545,0.0002064692,0.0002954629,0.00021987892,0.00007544811,0.00008348056,0.00020494129,0.00015229234,0.00008623313],"category_scores_gemma":[0.00019289131,0.00021412029,0.000038377322,0.00023513955,0.000050333456,0.00030812953,0.000027204076,0.00012256906,0.000020467061],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000024750778,0.000101525526,0.0021936763,0.002698319,0.00025425415,0.00002270596,0.007217248,0.18299724,0.6469566,0.017915932,0.0018633838,0.13775437],"study_design_scores_gemma":[0.00022197614,0.000055400695,0.0010555292,0.00023621935,0.000022268612,0.000006958368,0.000097862205,0.9047612,0.09280235,0.0004709575,0.000054224547,0.00021507856],"about_ca_topic_score_codex":0.0000072543594,"about_ca_topic_score_gemma":7.906504e-7,"teacher_disagreement_score":0.87668836,"about_ca_system_score_codex":0.00009820629,"about_ca_system_score_gemma":0.0000151749455,"threshold_uncertainty_score":0.8731572},"labels":[],"label_agreement":null},{"id":"W4251954744","doi":"10.1109/dac.1990.114927","title":"Chortle: a technology mapping program for lookup table-based field programmable gate arrays","year":2002,"lang":"en","type":"article","venue":"27th ACM/IEEE Design Automation Conference","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":88,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Lookup table; Computer science; Combinational logic; Table (database); Boolean function; Function (biology); Truth table; Logic synthesis; Algorithm; Logic gate; Theoretical computer science; Parallel computing; Data mining; Programming language","score_opus":0.09718467946465961,"score_gpt":0.2815929967923899,"score_spread":0.1844083173277303,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4251954744","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0015233274,0.00008664652,0.9905543,0.0022308994,0.00027766786,0.0017422218,0.0000033608587,0.0027787932,0.0008028183],"genre_scores_gemma":[0.6666368,0.000005752621,0.33164304,0.00037158345,0.000062769264,0.0010691254,0.000007762156,0.000019195466,0.00018393896],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976013,0.00008956806,0.0005059741,0.00070993573,0.00032410314,0.00076913147],"domain_scores_gemma":[0.9977024,0.00044270238,0.00032325793,0.000935884,0.0004527467,0.00014299677],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005416717,0.00030073835,0.00032752356,0.00039526672,0.0003829751,0.00070706796,0.0015171429,0.00022857035,0.00006854248],"category_scores_gemma":[0.0008270323,0.00030325967,0.000085885076,0.0013727709,0.000074754884,0.00061771576,0.00008424849,0.00025284637,0.00009062012],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000013846469,0.000195621,0.00031161308,0.00012363524,0.000023899544,0.000013776795,0.00027073736,0.0012579327,0.0059078294,0.0065236688,0.0020215583,0.98334837],"study_design_scores_gemma":[0.0006597471,0.00043376128,0.000050898845,0.0001849715,0.000013248446,0.000020513162,0.000028796248,0.97196,0.015856331,0.006738733,0.0036703455,0.00038262925],"about_ca_topic_score_codex":0.000011984446,"about_ca_topic_score_gemma":0.0000039297483,"teacher_disagreement_score":0.9829657,"about_ca_system_score_codex":0.00006599935,"about_ca_system_score_gemma":0.00021856726,"threshold_uncertainty_score":0.99994195},"labels":[],"label_agreement":null}]}