{"meta":{"query_hash":"8bd72d0a35d3","filters":{"venue":"Circuits and Systems"},"cohort_total":3,"direct_labels_cover":0,"predictions_cover":3,"exported":3,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/8bd72d0a35d3","api":"https://metacan.xera.ac/api/v1/cohort?venue=Circuits+and+Systems"},"results":[{"id":"W2028312043","doi":"10.4236/cs.2015.61002","title":"A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop","year":2015,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Jitter; Control theory (sociology); Offset (computer science); Phase-locked loop; Charge pump; Loop gain; Delay-locked loop; Phase frequency detector; Detector; Voltage; Electronic engineering; Materials science; Engineering; Electrical engineering; Computer science; Capacitor","score_opus":0.06926467194022638,"score_gpt":0.30327115762297496,"score_spread":0.23400648568274857,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2028312043","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.19072562,0.0017719698,0.80351615,0.000023548899,0.0011705803,0.0014336028,0.00006476843,0.0007838482,0.0005098885],"genre_scores_gemma":[0.9982746,0.00004454477,0.0008570145,0.0000038792596,0.0000745192,0.0005293658,0.00002201848,0.000022152832,0.0001718783],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993889,0.000009641119,0.00020631785,0.00014011753,0.00007964886,0.00017540068],"domain_scores_gemma":[0.99968046,0.000022053076,0.000038598224,0.00014838403,0.000055473516,0.000055056986],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018913216,0.00011047294,0.00016651207,0.0000780485,0.00005824739,0.000034273668,0.00006799434,0.0000813597,6.5588966e-7],"category_scores_gemma":[0.00005169501,0.00009919798,0.000018023982,0.00008539792,0.000031313255,0.0001239381,0.000012982693,0.00007090669,0.0000024829271],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00006413096,0.00028770146,0.00044627205,0.0033410196,0.00036568052,0.000035296016,0.0039255847,0.032350317,0.3628165,0.009649223,0.035493508,0.55122477],"study_design_scores_gemma":[0.009339878,0.0011072721,0.000019562225,0.0009132707,0.00013402058,0.0006211692,0.01840951,0.7486262,0.06257571,0.0070421863,0.14963678,0.0015744893],"about_ca_topic_score_codex":0.000007189467,"about_ca_topic_score_gemma":5.17089e-7,"teacher_disagreement_score":0.807549,"about_ca_system_score_codex":0.00005891167,"about_ca_system_score_gemma":0.00000951371,"threshold_uncertainty_score":0.40451762},"labels":[],"label_agreement":null},{"id":"W2044990188","doi":"10.4236/cs.2011.24050","title":"Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution","year":2011,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Simon Fraser University","funders":"","keywords":"Vernier scale; Time-to-digital converter; CMOS; Electronic engineering; Detector; Dynamic range; Resolution (logic); Phase detector; Dead time; Delay calculation; Computer science; Electrical engineering; Engineering; Physics; Propagation delay; Voltage; Optics; Telecommunications; Jitter","score_opus":0.022931542241212258,"score_gpt":0.1817303548176828,"score_spread":0.15879881257647055,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2044990188","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.86706334,0.0010051337,0.038532887,0.000010530048,0.00039882254,0.0009004633,0.00011630406,0.0014470931,0.09052545],"genre_scores_gemma":[0.9952707,0.000007420891,0.000036151323,0.000009780644,0.000034513458,0.00003219442,0.000009417944,0.00002967635,0.004570131],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9993131,0.000006573692,0.00016028718,0.00017803165,0.00010584427,0.00023615568],"domain_scores_gemma":[0.9996678,0.000011966585,0.000029447123,0.00019744101,0.000030068488,0.00006328256],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005455322,0.00014576108,0.0001738411,0.000065753135,0.00004940409,0.00006340398,0.000099036195,0.000079045916,0.000051453066],"category_scores_gemma":[0.0000075388025,0.00011653764,0.000015860005,0.00008691265,0.000051864183,0.00022389131,0.000027847353,0.00007432017,0.0005525604],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003108563,0.00071032194,0.017025085,0.0026594354,0.0020199332,0.0008989825,0.012091997,0.023665452,0.28085494,0.006154159,0.04502812,0.6085807],"study_design_scores_gemma":[0.0041482113,0.0026929001,0.003777533,0.0018798175,0.00016632614,0.0005331226,0.001847643,0.36388093,0.02631718,0.00036919955,0.5904013,0.0039858636],"about_ca_topic_score_codex":0.0000041659173,"about_ca_topic_score_gemma":6.466626e-7,"teacher_disagreement_score":0.6045948,"about_ca_system_score_codex":0.000042765558,"about_ca_system_score_gemma":0.0000044185795,"threshold_uncertainty_score":0.710223},"labels":[],"label_agreement":null},{"id":"W2147083707","doi":"10.4236/cs.2014.512030","title":"CFOA Based Low Pass and High Pass Ladder Filter—A New Configuration","year":2014,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Campbell Scientific (Canada)","funders":"","keywords":"High-pass filter; Low-pass filter; Filter (signal processing); Current-feedback operational amplifier; Active filter; Capacitor-input filter; Signal-flow graph; Voltage-controlled filter; Filter design; Engineering; Electronic engineering; Control theory (sociology); Computer science; Operational amplifier; Amplifier; Electrical engineering; Voltage; Artificial intelligence; CMOS","score_opus":0.012622525942023462,"score_gpt":0.18020831637224757,"score_spread":0.16758579043022412,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2147083707","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04378401,0.0018676958,0.9444647,0.000028792987,0.00086404925,0.0003410531,0.000020313812,0.00026451857,0.008364883],"genre_scores_gemma":[0.99868405,0.000024161553,0.0000030347192,0.000098748016,0.00040328028,0.000017652186,0.000027126476,0.000031071693,0.00071084744],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99908185,0.000070059934,0.00024422092,0.00022336919,0.00014206542,0.00023843996],"domain_scores_gemma":[0.99944556,0.00010522229,0.00004160613,0.00017780028,0.000040062856,0.00018972982],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00022786712,0.00018197058,0.00028138235,0.00006804714,0.000086614615,0.00016150108,0.00006784966,0.00013143245,0.000035223595],"category_scores_gemma":[0.000021715992,0.00016581852,0.00003058806,0.00007290181,0.000028910239,0.00011409327,0.000004764371,0.000113549584,0.000031666],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019587127,0.000093081595,0.0068743513,0.0039177905,0.0004948495,0.000074579824,0.0022245252,0.02974662,0.15358455,0.44373187,0.11215362,0.24708457],"study_design_scores_gemma":[0.009876567,0.00086983177,0.06865193,0.0019788418,0.00045364388,0.00026795478,0.0010247858,0.70056397,0.010018052,0.009707695,0.19245565,0.004131099],"about_ca_topic_score_codex":0.00015670634,"about_ca_topic_score_gemma":0.000014546349,"teacher_disagreement_score":0.9549001,"about_ca_system_score_codex":0.000020554271,"about_ca_system_score_gemma":0.000022730414,"threshold_uncertainty_score":0.67618835},"labels":[],"label_agreement":null}]}