{"meta":{"query_hash":"015f665a58ab","filters":{"venue":"IET Computers & Digital Techniques"},"cohort_total":36,"direct_labels_cover":0,"predictions_cover":36,"exported":36,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/015f665a58ab","api":"https://metacan.xera.ac/api/v1/cohort?venue=IET+Computers+%26+Digital+Techniques"},"results":[{"id":"W1041293701","doi":"10.1049/iet-cdt.2014.0188","title":"Accuracy‐aware processor customisation for fixed‐point arithmetic","year":2015,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Fonds Québécois de la Recherche sur la Nature et les Technologies","keywords":"Computer science; Latency (audio); Benchmark (surveying); Word (group theory); FLOPS; Microarchitecture; Fixed-point arithmetic; Fixed point; Parallel computing; Computer hardware; Floating point; Computer engineering; Arithmetic; Algorithm; Mathematics","score_opus":0.039268405653066156,"score_gpt":0.3119840696708274,"score_spread":0.27271566401776126,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1041293701","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00026475312,0.00006523377,0.99426746,0.0017665991,0.00040607303,0.00079561846,0.00001809591,0.001457773,0.0009584003],"genre_scores_gemma":[0.08291347,0.0000060908524,0.9158237,0.0006492037,0.0002365208,0.0002246117,0.000016964052,0.000026596555,0.00010281496],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9982666,0.000045118373,0.00037367037,0.00057088054,0.00034795984,0.0003957674],"domain_scores_gemma":[0.99831635,0.00036745184,0.00019511688,0.00051227317,0.00035607157,0.00025273976],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004214755,0.00026011802,0.00031209397,0.00014208056,0.00008818424,0.0008948247,0.0010555517,0.0000994845,8.365109e-7],"category_scores_gemma":[0.0002921074,0.00022537854,0.00014412079,0.0004312175,0.00007225659,0.00182854,0.0003898803,0.0001413359,0.000015162996],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000012017341,0.000110986664,0.000029129995,0.00003286549,0.000013012736,0.0000070159595,0.00022257303,0.000012095269,0.00007578283,0.004608532,0.011801296,0.98307467],"study_design_scores_gemma":[0.0011951199,0.0022425868,0.00010189792,0.00028690603,0.00002260926,0.00016922146,0.000116545256,0.33330092,0.053804938,0.35718295,0.25005674,0.0015195907],"about_ca_topic_score_codex":0.000008441904,"about_ca_topic_score_gemma":2.397927e-7,"teacher_disagreement_score":0.9815551,"about_ca_system_score_codex":0.000103861064,"about_ca_system_score_gemma":0.00012058678,"threshold_uncertainty_score":0.91906697},"labels":[],"label_agreement":null},{"id":"W1511491629","doi":"10.1049/iet-cdt.2010.0021","title":"Bit-serial and digit-serial GF(2 <sup> <i>m</i> </sup> ) Montgomery multipliers using linear feedback shift registers","year":2011,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Cryptography and Residue Arithmetic","field":"Computer Science","cited_by":37,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Trinomial; GF(2); Arithmetic; Shift register; Multiplication (music); Computer science; Finite field; Parallel computing; Binary number; Numerical digit; Block (permutation group theory); Mathematics; Discrete mathematics; Chip; Combinatorics","score_opus":0.02419302560343754,"score_gpt":0.22997076009410644,"score_spread":0.2057777344906689,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1511491629","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.42410868,0.00019166953,0.5682952,0.00025486934,0.00090941385,0.00090317754,0.000051847226,0.00224214,0.0030430488],"genre_scores_gemma":[0.725804,0.000054686076,0.27324253,0.00040999148,0.00037004615,0.00002400186,0.000014940603,0.000056481607,0.000023340486],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9970067,0.00007494197,0.0006416775,0.0010614767,0.00044159807,0.0007735918],"domain_scores_gemma":[0.9981539,0.00013816537,0.00025080933,0.0009852224,0.00010154676,0.0003703559],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00022390002,0.00057070324,0.00055635336,0.00045677973,0.00028824518,0.0011010374,0.0013879137,0.0002789278,0.000003648205],"category_scores_gemma":[0.00003296052,0.00054134143,0.0003104537,0.00071992143,0.0005756825,0.0026074192,0.0010877226,0.00033708688,0.000010977197],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0016698869,0.0027689703,0.020586932,0.0006126011,0.0012011752,0.0014471846,0.03155824,0.0011624362,0.005422465,0.030278224,0.017323466,0.8859684],"study_design_scores_gemma":[0.018321047,0.01132731,0.018536242,0.0045065773,0.00063851406,0.0038457273,0.0019933688,0.43993834,0.2234354,0.15092702,0.106508106,0.020022335],"about_ca_topic_score_codex":0.00017237259,"about_ca_topic_score_gemma":0.0000051195548,"teacher_disagreement_score":0.86594605,"about_ca_system_score_codex":0.000058841684,"about_ca_system_score_gemma":0.000084513704,"threshold_uncertainty_score":0.9999359},"labels":[],"label_agreement":null},{"id":"W1551456964","doi":"10.1049/iet-cdt.2011.0089","title":"Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture","year":2012,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Rounding; Decimal; CORDIC; Computer science; Critical path method; Parallel computing; Algorithm; Floating point; Double-precision floating-point format; Standard cell; Field-programmable gate array; Latency (audio); Architecture; Arithmetic; Computer hardware; Mathematics; Integrated circuit; Engineering","score_opus":0.008669592829528056,"score_gpt":0.25062490886247935,"score_spread":0.24195531603295128,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1551456964","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0008944098,0.000055211785,0.9962223,0.0006158672,0.0003621312,0.0002952989,0.00001592055,0.00094516587,0.0005936685],"genre_scores_gemma":[0.14103556,0.0000044363173,0.857444,0.0012162453,0.00021016136,0.00001758074,0.000010286266,0.00002481748,0.000036938476],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99819005,0.00010123834,0.00028352978,0.00053248,0.00033606554,0.00055662554],"domain_scores_gemma":[0.9989685,0.00028048267,0.00012149629,0.0003169222,0.000059464248,0.00025312713],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00033711718,0.00032529782,0.0003098042,0.00018834138,0.00015438447,0.0006934577,0.00047349193,0.00012321779,0.000003352826],"category_scores_gemma":[0.000035125304,0.00027962794,0.00010325765,0.00037886036,0.00010627568,0.0010745915,0.00024329568,0.0003291176,0.0000070803653],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000067322926,0.00015907577,0.00040318514,0.000009347913,0.000012178457,0.000004227707,0.000080344704,0.0000037220138,0.00076303445,0.0007735061,0.0025025706,0.99528205],"study_design_scores_gemma":[0.0006803789,0.0020276678,0.00087193726,0.00021103928,0.000016249745,0.00030365033,0.000015535386,0.8758321,0.05573714,0.008352994,0.05468885,0.0012625054],"about_ca_topic_score_codex":0.000015283904,"about_ca_topic_score_gemma":7.8216e-8,"teacher_disagreement_score":0.99401957,"about_ca_system_score_codex":0.000077418896,"about_ca_system_score_gemma":0.000023920322,"threshold_uncertainty_score":0.9999656},"labels":[],"label_agreement":null},{"id":"W1970019860","doi":"10.1049/iet-cdt.2010.0024","title":"Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus","year":2011,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Heuristics; Operand; Computer science; Parallel computing; Integer (computer science); Power (physics); Reduction (mathematics); Computation; Integer programming; Embedded system; Code (set theory); Dissipation; Computer hardware; Programming language; Algorithm; Operating system; Mathematics","score_opus":0.02590197359389883,"score_gpt":0.2451128317876077,"score_spread":0.21921085819370886,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1970019860","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21197161,0.00001194148,0.7729541,0.0014263389,0.00041590715,0.00052401284,0.0000017882902,0.0017855196,0.010908765],"genre_scores_gemma":[0.8700283,0.0000141519,0.12903467,0.0006743234,0.00008601393,0.00009563253,0.0000011797796,0.00002077139,0.00004494981],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9983022,0.00010541594,0.00038774236,0.0005246782,0.0003050059,0.00037495545],"domain_scores_gemma":[0.9986039,0.00021787573,0.0001646984,0.0008654635,0.00007487891,0.00007320465],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00042427945,0.00028073118,0.00021473327,0.00037836272,0.00038610172,0.00071191334,0.0015911064,0.000094409785,0.0000018916796],"category_scores_gemma":[0.00007071158,0.00019751507,0.000099770215,0.001056175,0.00008006135,0.00102795,0.0006037247,0.00044590156,0.000005472293],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000046284105,0.00021478925,0.00047006155,0.00001286003,0.00004262591,0.000019152092,0.0063712243,0.0014418137,0.0009758962,0.078606114,0.005687684,0.9061115],"study_design_scores_gemma":[0.0012747259,0.0030055167,0.012100202,0.0025540113,0.00003584742,0.0011985042,0.0019702727,0.22071707,0.56594336,0.15045667,0.03655733,0.004186468],"about_ca_topic_score_codex":0.000092417264,"about_ca_topic_score_gemma":0.000010361918,"teacher_disagreement_score":0.901925,"about_ca_system_score_codex":0.000121822384,"about_ca_system_score_gemma":0.000055968987,"threshold_uncertainty_score":0.8054431},"labels":[],"label_agreement":null},{"id":"W1991225420","doi":"10.1049/iet-cdt.2011.0173","title":"Contention‐aware selection strategy for application‐specific network‐on‐chip","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Computer science; Selection (genetic algorithm); Routing (electronic design automation); Network on a chip; Static routing; Network packet; Selection algorithm; Adaptive routing; Routing protocol; Computer network","score_opus":0.02258229929357752,"score_gpt":0.2455796995939078,"score_spread":0.22299740030033027,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1991225420","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0007464906,0.000041332132,0.9902489,0.00046518916,0.00062983675,0.0014572458,0.000006910427,0.001550233,0.0048538293],"genre_scores_gemma":[0.97499263,0.0000087840945,0.022229677,0.0004921894,0.0008285946,0.0008262922,0.00003619372,0.000027669917,0.0005579683],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9982785,0.00004138566,0.0004500785,0.00059072924,0.00021555233,0.00042374112],"domain_scores_gemma":[0.99870265,0.00015462813,0.00019637049,0.00046663915,0.00037016318,0.00010953471],"candidate_categories":["scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.0001887666,0.00025452801,0.00026269586,0.00012594507,0.00023945369,0.0014371057,0.0007151865,0.0001356934,0.000007769072],"category_scores_gemma":[0.000005539724,0.0002364805,0.00019224362,0.0003763232,0.000041956802,0.0012469857,0.00010871744,0.00015811274,0.000111678266],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000015519947,0.00012082837,0.00018521745,0.000021663367,0.000045914163,0.0000010449056,0.000052550906,0.0021779505,0.00018353999,0.19623706,0.39075065,0.41020805],"study_design_scores_gemma":[0.00046375178,0.0013544491,0.0006267666,0.00019414653,0.000005643713,0.00009765767,0.000033299548,0.6875526,0.0021394454,0.0728164,0.23389843,0.000817424],"about_ca_topic_score_codex":0.000019340294,"about_ca_topic_score_gemma":0.0000030982403,"teacher_disagreement_score":0.97424614,"about_ca_system_score_codex":0.00010704574,"about_ca_system_score_gemma":0.000024119188,"threshold_uncertainty_score":0.9995995},"labels":[],"label_agreement":null},{"id":"W1995613452","doi":"10.1049/iet-cdt:20070120","title":"SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays","year":2008,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Design space exploration; Computer science; Gate array; Field-programmable gate array; Field (mathematics); Genetic algorithm; Computer Aided Design; Design tool; Computer architecture; Space exploration; Core (optical fiber); Space (punctuation); Embedded system; Multi-core processor; Computer engineering; Computer hardware; Parallel computing; Engineering; Aerospace engineering; Operating system","score_opus":0.04922049004676316,"score_gpt":0.25872247149558575,"score_spread":0.2095019814488226,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1995613452","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0027828615,0.000110768764,0.99044126,0.000047926664,0.0001367867,0.0031497772,0.00003601332,0.0032059439,0.00008868132],"genre_scores_gemma":[0.34811464,0.000053368065,0.65095204,0.000045200173,0.00013882916,0.0005462658,0.000052183153,0.00007607584,0.000021364787],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9981446,0.00003786865,0.0005869342,0.0003938044,0.00022005664,0.0006167313],"domain_scores_gemma":[0.9987247,0.00038556845,0.00017742196,0.00032812275,0.00027514677,0.00010906991],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00024748393,0.00041941038,0.00053054746,0.00024300959,0.00016077436,0.00025620498,0.00039833225,0.00022028219,0.0000013597939],"category_scores_gemma":[0.000045529025,0.00043465305,0.0002102217,0.00030845747,0.00009545463,0.0014762208,0.000053183223,0.00014858128,8.455383e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000851699,0.00053850806,0.00018281926,0.0015500104,0.00029776894,0.000042769392,0.0030345672,0.052442417,0.04070648,0.0016239075,0.09550616,0.8032229],"study_design_scores_gemma":[0.0005548648,0.0017973972,0.000012559375,0.00041394506,0.000031596555,0.00003839859,0.00002989013,0.38031948,0.6047333,0.008725984,0.0027168526,0.00062572764],"about_ca_topic_score_codex":0.000004508902,"about_ca_topic_score_gemma":4.4958367e-7,"teacher_disagreement_score":0.80259717,"about_ca_system_score_codex":0.000072600735,"about_ca_system_score_gemma":0.00008094771,"threshold_uncertainty_score":0.9998105},"labels":[],"label_agreement":null},{"id":"W2007102977","doi":"10.1049/iet-cdt.2013.0016","title":"Temperature control in three‐network on chips using task migration","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Scalability; Overhead (engineering); Network on a chip; Multiprocessing; Computer science; Chip; Interconnection; Reliability (semiconductor); Dissipation; Three-dimensional integrated circuit; System on a chip; Thermal management of electronic devices and systems; Integrated circuit; Embedded system; Power (physics); Parallel computing; Engineering; Computer network; Telecommunications","score_opus":0.00968258682185651,"score_gpt":0.21422684694753008,"score_spread":0.20454426012567356,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2007102977","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13330865,0.00007149108,0.8608753,0.00090573047,0.0009548264,0.0009367156,0.00000387227,0.00084033055,0.0021030596],"genre_scores_gemma":[0.9846832,0.0000034812956,0.013431872,0.0012620757,0.00049166905,0.00006722518,0.000006660505,0.000018287836,0.000035490324],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983956,0.00007275593,0.00042017855,0.00046748476,0.00024573665,0.00039820682],"domain_scores_gemma":[0.9990851,0.00011471187,0.0001389165,0.00046346264,0.00011445546,0.00008330002],"candidate_categories":["scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00021813199,0.00025478497,0.00030212486,0.0001718752,0.00011122262,0.0012985449,0.0006012197,0.00016873375,0.0000029799583],"category_scores_gemma":[0.000010351638,0.00021976662,0.00011686883,0.00044261245,0.000035429504,0.0013781809,0.00011390197,0.0002860921,0.00003052803],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014190639,0.0011043379,0.030545983,0.00013104586,0.000292152,0.0002209592,0.002257991,0.04582201,0.014649663,0.14210382,0.3469634,0.41576672],"study_design_scores_gemma":[0.00064231234,0.000740941,0.0035053047,0.0009145593,0.000005188032,0.00014589477,0.000025448833,0.95157987,0.0014457139,0.032364942,0.007714585,0.0009152569],"about_ca_topic_score_codex":0.00012587305,"about_ca_topic_score_gemma":0.00004423813,"teacher_disagreement_score":0.90575784,"about_ca_system_score_codex":0.00011080159,"about_ca_system_score_gemma":0.000027564787,"threshold_uncertainty_score":0.9997382},"labels":[],"label_agreement":null},{"id":"W2011813090","doi":"10.1049/iet-cdt:20060199","title":"Bridging fault diagnostic tool based on Δ <i>I</i> <sub>DDQ</sub> probabilistic signatures, circuit layout parasitics and logic errors","year":2007,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"École de Technologie Supérieure","funders":"CMC Microsystems","keywords":"Bridging (networking); Iddq testing; Parasitic extraction; Probabilistic logic; Fault coverage; Fault (geology); Computer science; Algorithm; Logic gate; Stuck-at fault; Fault detection and isolation; Engineering; Electronic engineering; Computer engineering; Reliability engineering; Electronic circuit; Electrical engineering; Artificial intelligence; CMOS","score_opus":0.013708788878061725,"score_gpt":0.23266124691496257,"score_spread":0.21895245803690083,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2011813090","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08400845,0.000103909915,0.9106061,0.00028573556,0.00021661421,0.0005982126,0.00002075305,0.0020115636,0.0021486762],"genre_scores_gemma":[0.9890416,0.000007967287,0.0074957428,0.0031733767,0.00017989195,0.000026812915,0.000027777478,0.000040747174,0.000006043844],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9970162,0.000059040765,0.000566986,0.00095089414,0.0005733378,0.0008335276],"domain_scores_gemma":[0.99678355,0.0018914578,0.00021997624,0.000693334,0.00015954563,0.00025214275],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00059878686,0.00048954034,0.00042024386,0.00032435943,0.0002558532,0.0009802508,0.000948134,0.00020560843,5.3204093e-7],"category_scores_gemma":[0.0007108848,0.00047889492,0.00015016683,0.0005883117,0.00020621713,0.0008238835,0.00028153256,0.00049261487,0.000011220188],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000365645,0.00035572096,0.0036127658,0.00013855929,0.000027713282,0.0008882431,0.00023529412,0.001911692,0.0026461564,0.016721569,0.0017365816,0.97172207],"study_design_scores_gemma":[0.0020547996,0.00386118,0.021864373,0.004374616,0.00013388338,0.0010347299,0.00006770661,0.75580263,0.10306638,0.09908395,0.0026380497,0.0060177],"about_ca_topic_score_codex":0.000008297833,"about_ca_topic_score_gemma":0.0000036242502,"teacher_disagreement_score":0.9657043,"about_ca_system_score_codex":0.00014113994,"about_ca_system_score_gemma":0.000093350245,"threshold_uncertainty_score":0.9997663},"labels":[],"label_agreement":null},{"id":"W2021731414","doi":"10.1049/iet-cdt.2013.0109","title":"Column selection solutions for <i>L</i> 1 data caches implemented using eight‐transistor cells","year":2014,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Cache; Computer science; Overhead (engineering); Transistor; Static random-access memory; Dissipation; Scaling; Selection (genetic algorithm); CPU cache; Column (typography); Voltage; Computer hardware; Embedded system; Parallel computing; Electrical engineering; Computer network; Engineering; Artificial intelligence; Mathematics; Operating system; Physics","score_opus":0.03887342976144327,"score_gpt":0.2441999563159854,"score_spread":0.20532652655454214,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2021731414","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.008640458,0.00004340798,0.9869434,0.000047899346,0.00048943143,0.0007049215,0.0003686773,0.0021444766,0.00061731716],"genre_scores_gemma":[0.8613576,0.000020948944,0.1376665,0.00008503837,0.00028137033,0.00006449191,0.00041126544,0.000089663015,0.00002309604],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985261,0.000017446855,0.00036109777,0.00037411426,0.00017386112,0.00054741016],"domain_scores_gemma":[0.99914944,0.000093510265,0.000059745802,0.0005215001,0.00008325409,0.00009253915],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002544877,0.00027062406,0.00026582053,0.00017055098,0.00020304268,0.00027527483,0.0005297955,0.00010901861,0.0000038205817],"category_scores_gemma":[0.000009363917,0.00030220835,0.000083514264,0.00026954565,0.000058792888,0.0012236135,0.00013621719,0.0001371602,0.00000768186],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000060504,0.0002835351,0.00043168708,0.00059153954,0.00041976082,0.0000039232054,0.00038280681,0.009438452,0.21898437,0.0008683674,0.55998206,0.20855297],"study_design_scores_gemma":[0.00027803486,0.00017902942,0.00002618468,0.00007740808,0.0000456123,0.000017396904,0.000007224886,0.7015846,0.100321814,0.00024029426,0.19675997,0.0004624284],"about_ca_topic_score_codex":0.000030751486,"about_ca_topic_score_gemma":0.000019950085,"teacher_disagreement_score":0.85271716,"about_ca_system_score_codex":0.00019562796,"about_ca_system_score_gemma":0.00003441996,"threshold_uncertainty_score":0.999943},"labels":[],"label_agreement":null},{"id":"W2031883009","doi":"10.1049/iet-cdt.2013.0055","title":"Challenges and advances in Toffoli network optimisation","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Quantum Computing Algorithms and Architecture","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of New Brunswick","funders":"","keywords":"Template; Toffoli gate; Computer science; Heuristics; Matching (statistics); Combinatory logic; Computer engineering; Theoretical computer science; Algorithm; Quantum gate; Programming language; Mathematics; Quantum computer; Quantum","score_opus":0.009906054993092708,"score_gpt":0.2286296666313555,"score_spread":0.2187236116382628,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2031883009","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03640666,0.013347097,0.92944694,0.0045390152,0.00048899377,0.0008171826,0.0000018385314,0.002167404,0.012784848],"genre_scores_gemma":[0.6821725,0.001528283,0.3157524,0.0002872985,0.00019016747,0.000037727514,0.000002635688,0.000014222618,0.000014763883],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9987409,0.00003511609,0.00023872122,0.00046864222,0.00016633874,0.00035024417],"domain_scores_gemma":[0.9992937,0.00016800374,0.000081698156,0.00032580184,0.00004393036,0.00008686813],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00013937672,0.00019997924,0.0002141319,0.000121609635,0.00006286578,0.00047533508,0.0005231158,0.00007097922,8.57625e-7],"category_scores_gemma":[0.000014067085,0.00017777724,0.000043877153,0.00020274158,0.00006386432,0.0016667036,0.00043045662,0.0001622461,0.000006791176],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[9.944445e-7,0.0000262089,0.000094375144,0.000013401266,0.0000032097007,0.0000064485685,0.00030341218,0.0006961225,0.000008827246,0.009280731,0.00041946064,0.9891468],"study_design_scores_gemma":[0.00035617588,0.0006152256,0.011075226,0.000554343,0.0000027988665,0.0001895262,0.000045567802,0.6607994,0.00061916775,0.28169206,0.04309858,0.0009519379],"about_ca_topic_score_codex":0.000009111312,"about_ca_topic_score_gemma":0.00000311034,"teacher_disagreement_score":0.9881949,"about_ca_system_score_codex":0.000021126083,"about_ca_system_score_gemma":0.0000137233965,"threshold_uncertainty_score":0.72495455},"labels":[],"label_agreement":null},{"id":"W2068411283","doi":"10.1049/iet-cdt.2013.0053","title":"Sample preparation with multiple dilutions on digital microfluidic biochips","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Electrowetting and Microfluidic Technologies","field":"Engineering","cited_by":24,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Indian Statistical Institute; Innovation, Science and Economic Development Canada","keywords":"Biochip; Microfluidics; Digital microfluidics; Serial dilution; Sample (material); Dilution; Sample preparation; Computer science; Computer hardware; Lab-on-a-chip; Nanotechnology; Electrowetting; Process engineering; Embedded system; Electrode; Materials science; Chromatography; Chemistry; Engineering","score_opus":0.005253316474402197,"score_gpt":0.18986712384177673,"score_spread":0.18461380736737454,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2068411283","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.60028374,0.00062226097,0.3839211,0.00025274724,0.00010590326,0.00075840566,0.00013138184,0.011226853,0.0026975886],"genre_scores_gemma":[0.9913754,0.000109399465,0.008026552,0.00006113426,0.000052570867,0.00013600456,0.00013411648,0.00005406529,0.000050790288],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99893653,0.0000062727004,0.00023335809,0.00029999032,0.00013930343,0.0003845478],"domain_scores_gemma":[0.99931276,0.00014322693,0.00004037207,0.00037864616,0.000059360347,0.000065634325],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00003120425,0.00028515034,0.00019714994,0.00019239214,0.000096462674,0.0005412363,0.0002823297,0.00012993126,0.0000037437328],"category_scores_gemma":[0.000044887383,0.00024756233,0.00007198085,0.0002502417,0.000119093886,0.00076971785,0.00006886318,0.00021594824,0.000073654526],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000039582694,0.00025748461,0.0027995287,0.00007238331,0.00016910626,0.000010394941,0.00024619134,0.00007310011,0.17825897,0.0012448779,0.33394393,0.48288444],"study_design_scores_gemma":[0.00024850684,0.0008927021,0.0004288833,0.00019395663,0.000009507953,0.00006104563,0.000055460856,0.00086582935,0.93881744,0.0025054542,0.055296972,0.00062426215],"about_ca_topic_score_codex":0.00002772047,"about_ca_topic_score_gemma":9.2941565e-7,"teacher_disagreement_score":0.7605584,"about_ca_system_score_codex":0.00010087317,"about_ca_system_score_gemma":0.000015680062,"threshold_uncertainty_score":0.9999977},"labels":[],"label_agreement":null},{"id":"W2077045439","doi":"10.1049/iet-cdt.2012.0038","title":"High-performance low-power sensing scheme for nanoscale SRAMs","year":2012,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Advancements in Semiconductor Devices and Circuit Design","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Static random-access memory; CMOS; Dissipation; Process variation; Overhead (engineering); Computer science; Electronic engineering; Leakage (economics); Integrated circuit; Power (physics); Reduction (mathematics); Amplifier; Electronic circuit; Leakage power; Electrical engineering; Engineering; Transistor; Voltage; Physics","score_opus":0.0106758076462873,"score_gpt":0.21924112964637413,"score_spread":0.20856532200008682,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2077045439","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4888633,0.00028367632,0.5050974,0.000011027847,0.0011846545,0.00046093366,0.00004617262,0.001842181,0.0022106671],"genre_scores_gemma":[0.9301074,0.000026814232,0.0692657,0.00013344339,0.00028008583,0.000023790315,0.000038718117,0.000065979846,0.00005804554],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99891967,0.000004333407,0.0002578523,0.0001870371,0.00014115334,0.00048996834],"domain_scores_gemma":[0.9994936,0.000047437814,0.000046758858,0.00026574277,0.000046524823,0.00009992902],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000082802166,0.0002425002,0.0002224043,0.00006325793,0.00006442405,0.00012438017,0.00019318279,0.000098671,0.0000071836525],"category_scores_gemma":[0.0000051951456,0.0002450861,0.000071632305,0.000115366835,0.000046621873,0.0011408513,0.000045581244,0.000118626944,0.000022539638],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003155687,0.00022089065,0.0017994172,0.0005717959,0.00022575994,0.0000063474527,0.00056079053,0.0006721163,0.11325143,0.0021156284,0.043216567,0.8373277],"study_design_scores_gemma":[0.0004296008,0.00024036402,0.00016407126,0.00045811603,0.000019898403,0.000051331575,0.00005803799,0.014337765,0.76873684,0.0010584821,0.21326943,0.0011760934],"about_ca_topic_score_codex":7.1201947e-7,"about_ca_topic_score_gemma":5.675432e-8,"teacher_disagreement_score":0.8361516,"about_ca_system_score_codex":0.00008785946,"about_ca_system_score_gemma":0.000005710322,"threshold_uncertainty_score":0.9994321},"labels":[],"label_agreement":null},{"id":"W2091507826","doi":"10.1049/iet-cdt:20060209","title":"Debug enhancements in assertion-checker generation","year":2007,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Radiation Effects in Electronics","field":"Engineering","cited_by":30,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Assertion; Debugging; Computer science; Background debug mode interface; Set (abstract data type); Overhead (engineering); Programming language; Algorithmic program debugging; Embedded system; Computer architecture","score_opus":0.006455475369999442,"score_gpt":0.23035297385902168,"score_spread":0.22389749848902224,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2091507826","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.37422782,0.00009589523,0.6192323,0.0000170896,0.0002684526,0.00024072714,0.0000020231353,0.0009964602,0.004919236],"genre_scores_gemma":[0.9849826,0.000018429488,0.014639362,0.00008955033,0.00014301107,0.00002341011,0.00004285522,0.000030313342,0.000030475145],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9991364,0.000008151369,0.00026029276,0.00015891733,0.00015033725,0.00028591155],"domain_scores_gemma":[0.9997048,0.00003476406,0.000028940362,0.00016101668,0.00002697332,0.000043521464],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00018899966,0.0001414411,0.00011641332,0.0001786325,0.000022184158,0.00010720463,0.00013259039,0.00008934384,0.0000036817223],"category_scores_gemma":[0.000012744945,0.00016122914,0.000036574005,0.00023233108,0.000015419668,0.0005278126,0.000020220366,0.00013911884,0.000016060678],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016835715,0.00018695739,0.0025148375,0.000060216244,0.00007203216,0.000035342495,0.00035537177,0.037277643,0.05526133,0.0024681806,0.02081364,0.88093764],"study_design_scores_gemma":[0.00026186218,0.00016019699,0.0033002954,0.00006753519,0.0000046508535,0.000014198453,0.0000068197114,0.4219237,0.55474454,0.0010048439,0.018009102,0.0005022432],"about_ca_topic_score_codex":0.000004122324,"about_ca_topic_score_gemma":0.000019732359,"teacher_disagreement_score":0.88043535,"about_ca_system_score_codex":0.0002934615,"about_ca_system_score_gemma":0.000011339551,"threshold_uncertainty_score":0.6574733},"labels":[],"label_agreement":null},{"id":"W2093498840","doi":"10.1049/iet-cdt.2012.0088","title":"Customised soft processor design: a compromise between architecture description languages and parameterisable processors","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Fonds Québécois de la Recherche sur la Nature et les Technologies","keywords":"Datapath; Computer science; Computer architecture; Flexibility (engineering); Microarchitecture; Instruction set; Processor design; Process (computing); Set (abstract data type); Architecture; Design space exploration; Embedded system; Parallel computing; Operating system; Programming language","score_opus":0.017170812662659483,"score_gpt":0.2531135861739861,"score_spread":0.23594277351132661,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2093498840","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018372381,0.00014569885,0.97415787,0.0006376623,0.00003660198,0.0014010489,0.000006464233,0.004353942,0.0008883588],"genre_scores_gemma":[0.51003736,0.0000127780295,0.48932567,0.00023962292,0.000050802155,0.00018331267,0.000014694124,0.000026677819,0.00010904346],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997773,0.000100136676,0.0004722006,0.00078944647,0.00033962267,0.0005256144],"domain_scores_gemma":[0.99852866,0.00022895705,0.00025498902,0.00054660847,0.00021240077,0.00022837879],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00025816637,0.00043161842,0.00046113672,0.00030751943,0.0002262078,0.00211781,0.0011134862,0.00019193592,0.0000035374478],"category_scores_gemma":[0.00007521323,0.0003874471,0.00009216317,0.0005058385,0.00016920872,0.0020140451,0.0005070138,0.00029878554,0.000019283947],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000371917,0.0002711788,0.0022402513,0.00029603165,0.0001049038,0.000024567651,0.0017336273,0.0015436341,0.0015711826,0.00076314365,0.020878516,0.97053576],"study_design_scores_gemma":[0.00246485,0.0033751808,0.005330129,0.0017396215,0.0000925268,0.00054516474,0.00019637105,0.69907016,0.13443974,0.13189135,0.015677253,0.005177661],"about_ca_topic_score_codex":0.000032555687,"about_ca_topic_score_gemma":3.350995e-7,"teacher_disagreement_score":0.96535814,"about_ca_system_score_codex":0.0000570684,"about_ca_system_score_gemma":0.000060898143,"threshold_uncertainty_score":0.9998577},"labels":[],"label_agreement":null},{"id":"W2103884101","doi":"10.1049/iet-cdt.2010.0005","title":"Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks","year":2010,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":18,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Flip-flop; Signal edge; Electronic engineering; Clock rate; Clock signal; Reduction (mathematics); Power (physics); Amplifier; Sense amplifier; Enhanced Data Rates for GSM Evolution; Clock network; Computer science; Electrical engineering; Engineering; Synchronous circuit; Voltage; Electronic circuit; CMOS; Physics; Telecommunications; Digital signal processing","score_opus":0.005852492083715271,"score_gpt":0.20439028531057887,"score_spread":0.1985377932268636,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2103884101","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.11647852,0.00012395665,0.87529534,0.00007932035,0.0017540603,0.0010835478,0.000315142,0.003922033,0.0009480759],"genre_scores_gemma":[0.9799355,0.000055398403,0.01825118,0.00007109477,0.00074291544,0.00017691504,0.0005542609,0.00010842304,0.00010429401],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9982585,0.000013270331,0.00047054555,0.00040048893,0.0002170276,0.00064018945],"domain_scores_gemma":[0.99889964,0.00016667433,0.000076376135,0.0005518553,0.00013118281,0.00017424687],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00023019988,0.00040165905,0.00037355212,0.00012181645,0.00012275865,0.0003987467,0.00026701053,0.00032576645,0.0000053722283],"category_scores_gemma":[0.000033692522,0.0003883222,0.00018822224,0.0003120952,0.00010381839,0.00071452593,0.000102178834,0.0004514599,0.00002218624],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00016949668,0.00019986085,0.00026830367,0.00016311544,0.00016989195,0.00007744745,0.00019648955,0.0017179034,0.01213975,0.005340676,0.3995297,0.58002734],"study_design_scores_gemma":[0.0008311762,0.00039316536,0.00069463445,0.00018033148,0.000038249378,0.00017267311,0.000011135924,0.2803814,0.06756665,0.0014504597,0.64700913,0.0012709814],"about_ca_topic_score_codex":0.0000038359694,"about_ca_topic_score_gemma":0.000002730722,"teacher_disagreement_score":0.863457,"about_ca_system_score_codex":0.00011730437,"about_ca_system_score_gemma":0.000027390995,"threshold_uncertainty_score":0.9998569},"labels":[],"label_agreement":null},{"id":"W2108211345","doi":"10.1049/iet-cdt.2008.0155","title":"Skew compensation in energy recovery clock distribution networks","year":2009,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Clock skew; Digital clock manager; FLOPS; Clock domain crossing; Timing failure; Synchronous circuit; Clock signal; Skew; Clock network; Electronic engineering; Clock gating; Computer science; CPU multiplier; Jitter; Engineering; Parallel computing; Telecommunications","score_opus":0.003651611229473612,"score_gpt":0.17792410096381917,"score_spread":0.17427248973434556,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2108211345","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.03535298,0.00025069402,0.95837,0.00007999699,0.0003732186,0.00021008727,0.000021113534,0.0021888101,0.003153149],"genre_scores_gemma":[0.99530756,0.00024322038,0.003737479,0.00015048374,0.00016620987,0.000017443588,0.000333203,0.000027302298,0.000017121725],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9989042,0.00001612957,0.0003463895,0.00022939328,0.00015819365,0.0003456955],"domain_scores_gemma":[0.99955696,0.000043982738,0.000046883903,0.00025180305,0.0000352217,0.00006513416],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000092098395,0.00023777976,0.00023663673,0.00014264123,0.000035109344,0.00021198155,0.00022705675,0.00015683463,0.000002560736],"category_scores_gemma":[0.000005547528,0.00025910873,0.00007311135,0.0003779249,0.00002734999,0.0009506165,0.00003384012,0.00018282792,0.000008025274],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003692099,0.000118380325,0.00054280635,0.000023252434,0.000025991261,0.000036428464,0.000059445727,0.07187899,0.0005241822,0.0050225095,0.051372614,0.87035847],"study_design_scores_gemma":[0.00065269764,0.00086564815,0.012413043,0.0005867908,0.000015300557,0.00007431813,0.000009046239,0.8576489,0.026792744,0.012302995,0.08716325,0.0014752831],"about_ca_topic_score_codex":0.000008656013,"about_ca_topic_score_gemma":0.0000029415532,"teacher_disagreement_score":0.95995456,"about_ca_system_score_codex":0.0002691739,"about_ca_system_score_gemma":0.000011369772,"threshold_uncertainty_score":0.9999861},"labels":[],"label_agreement":null},{"id":"W2124879637","doi":"10.1049/iet-cdt:20060074","title":"Optimised realisations of large integer multipliers and squarers using embedded blocks","year":2007,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":22,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal; Royal Military College of Canada","funders":"","keywords":"Multiplier (economics); Field-programmable gate array; Arithmetic; Integer (computer science); Multiplication (music); Computer science; Mathematics; Adder; Parallel computing; Computer hardware; Combinatorics","score_opus":0.009338906035856749,"score_gpt":0.24396789190980128,"score_spread":0.23462898587394454,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2124879637","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.35009837,0.0000608863,0.6452391,0.000010733933,0.0001639262,0.00032493458,0.00003893473,0.0010847604,0.002978349],"genre_scores_gemma":[0.9096219,0.000017600907,0.09019194,0.000035557772,0.000047365666,0.0000066763237,0.000022062137,0.00004561127,0.000011320651],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988501,0.000007718858,0.0003896085,0.00021194028,0.00017929834,0.00036134946],"domain_scores_gemma":[0.9993803,0.00009353564,0.000068510046,0.00027394318,0.00007283802,0.00011087728],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000224557,0.0002320307,0.0002601451,0.00031084134,0.000055932545,0.000093070405,0.00019057922,0.0001303705,0.0000048029497],"category_scores_gemma":[0.000015668073,0.00024123224,0.00007308412,0.0002827739,0.00010884731,0.0005704383,0.0000764597,0.0001644974,0.0000014327185],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00056879426,0.0014623464,0.021404933,0.001957255,0.0017980625,0.00036699668,0.033492696,0.10043491,0.30660474,0.0054744445,0.07394762,0.4524872],"study_design_scores_gemma":[0.0013637599,0.00035964727,0.00096740614,0.00064247934,0.00006618305,0.00009884951,0.00081398163,0.52361673,0.46409774,0.00061472866,0.006000378,0.0013581357],"about_ca_topic_score_codex":0.000008885674,"about_ca_topic_score_gemma":0.0000019870267,"teacher_disagreement_score":0.55952346,"about_ca_system_score_codex":0.00010245864,"about_ca_system_score_gemma":0.000016466922,"threshold_uncertainty_score":0.9837165},"labels":[],"label_agreement":null},{"id":"W2130393477","doi":"10.1049/iet-cdt.2010.0167","title":"Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays","year":2012,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Computer science; Field-programmable gate array; Algorithm; Encoder; Scalability; Motion estimation; Block (permutation group theory); Encoding (memory); Virtex; Parallel computing; Data compression; Video quality; Computer hardware; Artificial intelligence; Mathematics","score_opus":0.015100661303857111,"score_gpt":0.2567706746588784,"score_spread":0.24167001335502125,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2130393477","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4092075,0.000024961046,0.58949935,0.0004023382,0.00012353937,0.00025645952,0.0000021050603,0.0002733166,0.00021045012],"genre_scores_gemma":[0.97963977,0.000015617832,0.020205803,0.00006034617,0.000026216077,0.000035557958,0.0000015064942,0.0000062699028,0.000008891877],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99894035,0.000077539735,0.00020803115,0.00020031363,0.00036636402,0.00020742649],"domain_scores_gemma":[0.99868804,0.0005920227,0.00015104479,0.00047530673,0.00006239464,0.000031172294],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005169148,0.00014630574,0.00016385272,0.00010739075,0.00016145248,0.0001390215,0.0006283536,0.000080929065,9.322347e-7],"category_scores_gemma":[0.00007806478,0.00008318341,0.00007745923,0.00026397282,0.00010980546,0.00054224307,0.00033347885,0.00024253651,0.0000017698977],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002781781,0.00006121637,0.0008017462,0.00003370726,0.000010455862,2.0542355e-7,0.00008921025,0.0005162499,0.0003833776,0.0018446482,0.0002871808,0.9959442],"study_design_scores_gemma":[0.00009756992,0.0014555537,0.0010387832,0.00043899956,0.000004696235,0.000016137088,0.000010960347,0.45264125,0.54284173,0.0012140751,0.0001241063,0.00011613817],"about_ca_topic_score_codex":0.0000048812335,"about_ca_topic_score_gemma":4.199158e-8,"teacher_disagreement_score":0.99582803,"about_ca_system_score_codex":0.000024867282,"about_ca_system_score_gemma":0.000010707776,"threshold_uncertainty_score":0.3392121},"labels":[],"label_agreement":null},{"id":"W2169353951","doi":"10.1049/iet-cdt.2013.0017","title":"Unified multi‐objective mapping and architecture customisation of networks‐on‐chip","year":2013,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":25,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria; Thompson Rivers University","funders":"","keywords":"Benchmark (surveying); Network on a chip; Reliability (semiconductor); Computer science; Network topology; Routing (electronic design automation); Network architecture; Computer architecture; Chip; Embedded system; Power (physics); Reliability engineering; Topology (electrical circuits); Engineering; Computer network","score_opus":0.013069255694701205,"score_gpt":0.21691017945727575,"score_spread":0.20384092376257454,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2169353951","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019952634,0.00003616524,0.9757542,0.00023705576,0.00030072566,0.0005873004,0.0000022179288,0.00050542725,0.0026242526],"genre_scores_gemma":[0.9478672,0.0000066725165,0.051583614,0.00026597246,0.00012962858,0.00004921086,0.000004300458,0.000013570054,0.000079786536],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99879074,0.00006633901,0.00034178933,0.00039039718,0.00016914161,0.00024159114],"domain_scores_gemma":[0.9990399,0.0001831193,0.00018630197,0.00036291892,0.00014665768,0.000081104336],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015622648,0.00020569768,0.0002621957,0.00021110839,0.00008163045,0.0004406389,0.00042277566,0.00011199726,0.0000018094729],"category_scores_gemma":[0.000017434253,0.0001769763,0.000087743596,0.00028762204,0.00007824661,0.00066250114,0.00021343361,0.00019524009,0.0000053828644],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002200387,0.00016615594,0.0009842733,0.000061728795,0.00009914576,0.000008855522,0.0025099674,0.0036344172,0.0007983313,0.03193384,0.008064941,0.95171636],"study_design_scores_gemma":[0.0007445259,0.0010240173,0.0065319613,0.0009006414,0.0000075506687,0.00017299468,0.00022870043,0.9596372,0.006153593,0.016112426,0.0075222985,0.00096408476],"about_ca_topic_score_codex":0.00005318378,"about_ca_topic_score_gemma":0.000002313153,"teacher_disagreement_score":0.9560028,"about_ca_system_score_codex":0.0000406384,"about_ca_system_score_gemma":0.000014996257,"threshold_uncertainty_score":0.72168845},"labels":[],"label_agreement":null},{"id":"W2255454767","doi":"10.1049/iet-cdt.2015.0056","title":"Evaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics","year":2015,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Seventh Framework Programme; European Commission; Queen's University; Ministerio de Economía y Competitividad; Federación Española de Enfermedades Raras; Engineering and Physical Sciences Research Council; Universidad Complutense de Madrid","keywords":"Emulation; Computer science; Multi-core processor; Embedded system; Fault tolerance; Frequency scaling; Implementation; Reliability (semiconductor); Energy consumption; Supercomputer; Reliability engineering; Power (physics); Distributed computing; Engineering; Parallel computing; Electrical engineering","score_opus":0.10094770743611232,"score_gpt":0.34727397872046256,"score_spread":0.24632627128435025,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2255454767","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019262023,0.00022049977,0.96785074,0.00013516232,0.00086324324,0.00074838387,0.000012682207,0.0043061413,0.0066011185],"genre_scores_gemma":[0.5994316,0.000009792885,0.39968434,0.00053372735,0.0001869139,0.000028954488,0.000010300126,0.000039894705,0.00007452228],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99616575,0.00020474657,0.0007477137,0.001018354,0.0012183246,0.00064510206],"domain_scores_gemma":[0.99688584,0.00053328264,0.00045493318,0.0011705535,0.0006247167,0.0003307052],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.0009918021,0.0005284268,0.0005582647,0.0012670178,0.00023377329,0.0016912491,0.0018552396,0.00022358456,3.8563408e-7],"category_scores_gemma":[0.00056452997,0.00050438003,0.00018053087,0.0025896963,0.00008321897,0.001096359,0.0006089335,0.00043818395,0.000037035414],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000084509506,0.0008317388,0.00088989077,0.000098206154,0.000079445264,0.00011864164,0.00070747465,0.4115128,0.00014386814,0.022661809,0.025043111,0.5378285],"study_design_scores_gemma":[0.00039073417,0.0012187634,0.000046822115,0.0004040375,0.000007402197,0.000072175004,0.000014757428,0.98973876,0.0037106408,0.0013524011,0.0024127564,0.0006307345],"about_ca_topic_score_codex":0.000033234966,"about_ca_topic_score_gemma":1.3353115e-7,"teacher_disagreement_score":0.58016956,"about_ca_system_score_codex":0.00040155993,"about_ca_system_score_gemma":0.00016270998,"threshold_uncertainty_score":0.9997408},"labels":[],"label_agreement":null},{"id":"W2273070579","doi":"10.1049/iet-cdt.2015.0066","title":"Design of a novel energy efficient topology for maximum magnitude generator","year":2016,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"","keywords":"Multiplexer; Computer science; Least significant bit; 4-bit; Comparator; Algorithm; Parallel computing; Verilog; Generator (circuit theory); Mathematics; Topology (electrical circuits); Computer hardware; Electronic engineering; CMOS; Multiplexing; Field-programmable gate array; Power (physics); Engineering; Electrical engineering; Voltage","score_opus":0.028594193466471494,"score_gpt":0.277706297829231,"score_spread":0.24911210436275952,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2273070579","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00023084831,0.000049729602,0.9977535,0.0007350978,0.00033735522,0.00028418028,0.000029286255,0.0004381215,0.00014189939],"genre_scores_gemma":[0.046085157,0.000009987052,0.953262,0.00036957036,0.0001090957,0.00008644955,0.0000013905873,0.000018357357,0.000058011035],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9985395,0.00005662788,0.0003565928,0.0004823401,0.00019268975,0.00037225863],"domain_scores_gemma":[0.9984761,0.00059712847,0.0001554775,0.0004883859,0.00016988326,0.00011303897],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00028139024,0.00021097109,0.00032903586,0.0001373369,0.000051014937,0.0001289832,0.0009782013,0.000090717076,0.0000017116912],"category_scores_gemma":[0.00006437603,0.00014447633,0.00013648812,0.00023609232,0.00014711403,0.000274598,0.00038209735,0.00004235185,0.0000014929992],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000016475853,0.00025004277,0.000005029629,0.0000090701,0.000021156804,0.000004646534,0.0000262374,0.00005044706,0.032930937,0.040738717,0.0012477086,0.92469954],"study_design_scores_gemma":[0.0011944921,0.0024376072,0.000024529883,0.00017253846,0.000013517007,0.000096237265,0.0000050356844,0.21714446,0.6607939,0.08152859,0.035737067,0.00085201394],"about_ca_topic_score_codex":0.0000065365803,"about_ca_topic_score_gemma":8.3207766e-8,"teacher_disagreement_score":0.9238475,"about_ca_system_score_codex":0.000042329288,"about_ca_system_score_gemma":0.000053526113,"threshold_uncertainty_score":0.5891574},"labels":[],"label_agreement":null},{"id":"W2341796638","doi":"10.1049/iet-cdt.2015.0058","title":"Decimal floating‐point fused multiply‐add with redundant internal encodings","year":2015,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada; University of Saskatchewan","keywords":"Rounding; Adder; Arithmetic; Decimal; Critical path method; Computer science; Floating point; Square root; Binary number; Division (mathematics); Parallel computing; Multiplier (economics); Multiplication algorithm; Algorithm; Mathematics; Engineering; Latency (audio)","score_opus":0.022599201386390284,"score_gpt":0.2639737822558015,"score_spread":0.2413745808694112,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2341796638","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0063712155,0.000034120083,0.9859297,0.0006167005,0.00039019092,0.00029729563,0.0000072948606,0.0016300665,0.0047234055],"genre_scores_gemma":[0.25100988,0.0000026700052,0.7482535,0.00043841673,0.00017076165,0.000017338933,0.0000032860032,0.000025659396,0.00007848829],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99766654,0.00007269305,0.00043844077,0.0007137902,0.0005809025,0.0005276072],"domain_scores_gemma":[0.9983111,0.00019882232,0.0002114458,0.00062438473,0.00024438853,0.00040986054],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00043681473,0.00035888574,0.00040399822,0.0001713892,0.00009136964,0.0012102402,0.0014862696,0.000085967564,0.000002581682],"category_scores_gemma":[0.000111497284,0.0002764312,0.00013444874,0.0004780442,0.00018164913,0.0016874995,0.00084672094,0.00030782074,0.000022408949],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005922443,0.0002277381,0.00057995087,0.000012729962,0.000045068606,0.00021412542,0.0008800466,0.00001618186,0.0008998612,0.004696062,0.0076172138,0.9847518],"study_design_scores_gemma":[0.0049908166,0.013138137,0.0012801915,0.001965858,0.000053007832,0.0030793431,0.0005273924,0.36339644,0.27224308,0.12371275,0.21033943,0.0052735466],"about_ca_topic_score_codex":0.000055054486,"about_ca_topic_score_gemma":0.0000012202532,"teacher_disagreement_score":0.97947824,"about_ca_system_score_codex":0.00012923391,"about_ca_system_score_gemma":0.00009978561,"threshold_uncertainty_score":0.99996877},"labels":[],"label_agreement":null},{"id":"W2590023945","doi":"10.1049/iet-cdt.2016.0100","title":"Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA","year":2017,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":18,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada; University of Saskatchewan","keywords":"Multiplier (economics); Field-programmable gate array; Digital signal processing; Computer science; Virtex; Application-specific integrated circuit; Clock rate; Computer hardware; Floating point; Double-precision floating-point format; Embedded system; Parallel computing; Algorithm; Chip; Telecommunications","score_opus":0.030274449641461147,"score_gpt":0.2961824391776271,"score_spread":0.26590798953616596,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2590023945","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.023862392,0.00003730002,0.9649009,0.00090385723,0.00057667156,0.0004495313,0.000012275807,0.00070395553,0.0085531045],"genre_scores_gemma":[0.5663103,0.0000042344295,0.43329826,0.00023567876,0.000061474944,0.000013842263,0.000002168302,0.000017171029,0.00005685346],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99782974,0.000058288224,0.00039236218,0.00085938664,0.00043721258,0.00042302074],"domain_scores_gemma":[0.9979159,0.00026328836,0.0003070424,0.0011435787,0.00014587195,0.00022430124],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00036074678,0.00036891445,0.00040036096,0.00015555632,0.0005140544,0.002621131,0.0012834915,0.00011053958,0.0000032527842],"category_scores_gemma":[0.00014879195,0.00029838958,0.00014151649,0.00014844141,0.00021255217,0.0010785356,0.0012193988,0.00026231984,0.00001223172],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004493219,0.00032378605,0.00007002358,0.000009338892,0.000020105219,0.00004995954,0.00073137955,0.00003061329,0.0020323521,0.004142246,0.0009618742,0.9915834],"study_design_scores_gemma":[0.0036183153,0.007920267,0.005480664,0.0022245788,0.000028693612,0.00023058149,0.00015070089,0.35295397,0.5209234,0.06613302,0.036492404,0.0038434237],"about_ca_topic_score_codex":0.000011599123,"about_ca_topic_score_gemma":3.049509e-7,"teacher_disagreement_score":0.98774,"about_ca_system_score_codex":0.00007282733,"about_ca_system_score_gemma":0.000019334588,"threshold_uncertainty_score":0.99994683},"labels":[],"label_agreement":null},{"id":"W2752065998","doi":"10.1049/iet-cdt.2016.0200","title":"High performance and energy efficient single‐precision and double‐precision merged floating‐point adder on FPGA","year":2017,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada; University of Saskatchewan","keywords":"Adder; Field-programmable gate array; Double-precision floating-point format; Computer science; Single-precision floating-point format; Stratix; Computer hardware; Carry-save adder; Throughput; Efficient energy use; Parallel computing; Floating point; Embedded system; Algorithm; Engineering; Latency (audio); Electrical engineering","score_opus":0.01911748253702997,"score_gpt":0.26412505777196205,"score_spread":0.24500757523493208,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2752065998","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1469363,0.00007099205,0.84904003,0.0005824798,0.00058269466,0.0001707146,0.00000572067,0.0004979545,0.0021131032],"genre_scores_gemma":[0.65442467,0.000050965144,0.34514713,0.00018000204,0.00010073343,0.000010384345,0.0000020870468,0.000016987937,0.00006701385],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99793386,0.000049414914,0.0003744699,0.0008116589,0.00044802533,0.00038258504],"domain_scores_gemma":[0.99821955,0.00023427719,0.00026258035,0.0009713036,0.000103900085,0.00020840477],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00038260894,0.00033530215,0.0003817149,0.00015780012,0.00052321353,0.001882938,0.0009895677,0.000117040974,0.0000018423605],"category_scores_gemma":[0.000068904235,0.00026925988,0.0000741751,0.0001405677,0.0001977817,0.0010749352,0.0013966722,0.00019171878,0.0000036936913],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000040098887,0.00011552321,0.00004023297,0.000010043495,0.0000086028485,0.000012261878,0.00009033153,0.000043355307,0.00090091,0.0027634606,0.00054344774,0.9954317],"study_design_scores_gemma":[0.002752475,0.006553309,0.009919095,0.0016571111,0.000029241586,0.0002519612,0.00003297168,0.48095986,0.42309245,0.033713747,0.038450558,0.002587205],"about_ca_topic_score_codex":0.00004051102,"about_ca_topic_score_gemma":4.611081e-7,"teacher_disagreement_score":0.9928445,"about_ca_system_score_codex":0.00004570019,"about_ca_system_score_gemma":0.000015145678,"threshold_uncertainty_score":0.999976},"labels":[],"label_agreement":null},{"id":"W2910067318","doi":"10.1049/iet-cdt.2018.5043","title":"Probabilistic timing analysis of time‐randomised caches with fault detection mechanisms","year":2019,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Real-Time Systems Scheduling","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Computer science; Probabilistic logic; Cache; Probabilistic analysis of algorithms; Static timing analysis; Fault detection and isolation; Real-time computing; Reliability engineering; Algorithm; Parallel computing; Embedded system; Artificial intelligence; Engineering","score_opus":0.007505424122112765,"score_gpt":0.21055296918920588,"score_spread":0.2030475450670931,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2910067318","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.115549326,0.000010870313,0.8802955,0.000030297713,0.00008082316,0.00088700757,0.0000053923645,0.00085707806,0.0022836616],"genre_scores_gemma":[0.8621945,9.451169e-7,0.13760203,0.000024481364,0.000018032506,0.000045046585,0.000011424209,0.000021612492,0.00008194213],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99791235,0.00007623988,0.00053997687,0.00065115566,0.00049824844,0.0003220479],"domain_scores_gemma":[0.9981559,0.0002714525,0.00039622845,0.0008555219,0.00022428292,0.000096631906],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00041441756,0.0002914153,0.00069119106,0.00059437606,0.00005782635,0.00049726403,0.00085497607,0.00011378655,0.0000055113064],"category_scores_gemma":[0.000034386885,0.0002427548,0.0002622321,0.0014341676,0.00005928109,0.0013314115,0.00024576404,0.0001352537,0.000027771623],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0012262637,0.0011390531,0.0020081657,0.0009915248,0.0074830083,0.00013580322,0.0049083363,0.07158728,0.3290772,0.02139164,0.0003755225,0.5596762],"study_design_scores_gemma":[0.001219626,0.000827854,0.00027555032,0.00028143526,0.00023533269,0.000059418664,0.000033385448,0.8312417,0.16244166,0.0026784136,0.0000824528,0.00062314386],"about_ca_topic_score_codex":0.000050475974,"about_ca_topic_score_gemma":0.000005086886,"teacher_disagreement_score":0.75965446,"about_ca_system_score_codex":0.000104335086,"about_ca_system_score_gemma":0.00005564108,"threshold_uncertainty_score":0.9899254},"labels":[],"label_agreement":null},{"id":"W2912351760","doi":"10.1049/iet-cdt.2018.5055","title":"KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC","year":2019,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":17,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Department of Science and Technology, Ministry of Science and Technology, India","keywords":"Computer science; Particle swarm optimization; Network on a chip; Network topology; Computer architecture; Distributed computing; Computer engineering; Embedded system; Machine learning; Computer network","score_opus":0.019259411816609416,"score_gpt":0.2558613399660693,"score_spread":0.23660192814945988,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2912351760","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00047886028,0.000051834475,0.9845026,0.00006954271,0.0004719855,0.0018694514,0.00001080955,0.0013393223,0.011205587],"genre_scores_gemma":[0.5729601,7.748363e-7,0.42603263,0.0001699893,0.00016074193,0.00040481234,0.0000294608,0.000020989659,0.0002205256],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9983003,0.000044550798,0.00038502883,0.00073905423,0.00017082329,0.00036021724],"domain_scores_gemma":[0.99861425,0.00017851246,0.00019218911,0.00065139437,0.0002817111,0.0000819168],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00030944642,0.00026509646,0.0003316863,0.00023273301,0.00011637579,0.00058209547,0.00084945647,0.00014822313,7.155174e-7],"category_scores_gemma":[0.000011908504,0.0002519923,0.00020695709,0.00043259992,0.000038967522,0.00085448753,0.00022551007,0.00015148282,0.00003498443],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000067297486,0.0012430815,0.0012854586,0.0005041619,0.00017456533,0.0000036754682,0.0024961336,0.0018609097,0.0021330665,0.050317764,0.01949611,0.9204178],"study_design_scores_gemma":[0.0003847005,0.0002250906,0.00007247584,0.00009907991,0.0000029466978,0.000018313152,0.00004251816,0.96215576,0.0018651583,0.0006962308,0.034081895,0.0003558164],"about_ca_topic_score_codex":0.000011823448,"about_ca_topic_score_gemma":0.0000012779461,"teacher_disagreement_score":0.96029484,"about_ca_system_score_codex":0.00014773331,"about_ca_system_score_gemma":0.000058129866,"threshold_uncertainty_score":0.9999932},"labels":[],"label_agreement":null},{"id":"W2953295373","doi":"10.1049/iet-cdt.2019.0115","title":"Efficient spiking neural network training and inference with reduced precision memory and computing","year":2019,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Advanced Memory and Neural Computing","field":"Engineering","cited_by":11,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"","keywords":"Floating point; Computer science; Computer hardware; MNIST database; Fixed-point arithmetic; Spiking neural network; Integer (computer science); Memory footprint; Algorithm; Artificial neural network; Parallel computing; Artificial intelligence","score_opus":0.012287004193813508,"score_gpt":0.23135087901512577,"score_spread":0.21906387482131226,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2953295373","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.90937585,0.00019173852,0.08772051,0.0000145842705,0.00018835663,0.00033023453,0.00000144822,0.0011272917,0.0010499911],"genre_scores_gemma":[0.97674096,0.000008577709,0.023011668,0.000058066424,0.00012812154,0.0000029977682,0.0000037171728,0.000038756163,0.000007149277],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9988505,0.000017266524,0.0002454271,0.00036350483,0.00014711119,0.00037617795],"domain_scores_gemma":[0.9993407,0.0002885607,0.00006579016,0.00017674107,0.000029306055,0.00009887619],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00012886491,0.00026594923,0.00030066344,0.000077042845,0.00010876083,0.00022345077,0.00013334533,0.000063413936,7.9846296e-7],"category_scores_gemma":[0.000012473699,0.00023914131,0.000031861044,0.00018109426,0.00006692207,0.00026447664,0.00019453133,0.00027304998,0.0000010315681],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000024659634,0.000009919303,0.0007381309,0.00008697851,0.000017480248,0.000021587672,0.0007408326,0.38909966,0.004540899,0.000095887845,0.00003616051,0.6045878],"study_design_scores_gemma":[0.00037061938,0.0004442211,0.0017871716,0.0011796545,0.000010645238,0.00026607528,0.0001421427,0.98375,0.0107635865,0.00039266993,0.00025080878,0.0006424334],"about_ca_topic_score_codex":7.268136e-7,"about_ca_topic_score_gemma":2.3893236e-7,"teacher_disagreement_score":0.6039454,"about_ca_system_score_codex":0.000026221373,"about_ca_system_score_gemma":0.000007700571,"threshold_uncertainty_score":0.9751899},"labels":[],"label_agreement":null},{"id":"W3084828086","doi":"10.1049/iet-cdt.2019.0179","title":"High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications","year":2020,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Cryptographic Implementations and Security","field":"Computer Science","cited_by":44,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Field-programmable gate array; Computer science; Advanced Encryption Standard; Loop unrolling; Throughput; Byte; AES implementations; Encryption; Parallel computing; Embedded system; Computer hardware; Computer network; Operating system","score_opus":0.01814031823590541,"score_gpt":0.28334244665298514,"score_spread":0.26520212841707974,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3084828086","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07164299,0.000037611695,0.9242778,0.0022888514,0.000044965273,0.0010587244,0.00018685107,0.0004260997,0.000036122558],"genre_scores_gemma":[0.82301533,0.000017753173,0.17627612,0.000350139,0.00003926237,0.00019745485,0.00009381927,0.000009465901,6.36845e-7],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9987602,0.000014175631,0.0003951562,0.0004214758,0.00019621554,0.00021277502],"domain_scores_gemma":[0.9992194,0.00010887561,0.00017625808,0.00027087878,0.00013375371,0.00009082784],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009588083,0.00016532083,0.00021789779,0.00011426058,0.0001260382,0.00029109413,0.00042914433,0.00004120755,0.0000034358636],"category_scores_gemma":[0.0000050396807,0.00016439178,0.00008444729,0.0004342699,0.000089299836,0.00043492927,0.00024833082,0.00005863024,7.626468e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000010482307,0.00015257242,0.0001579902,0.00008938184,0.000050952767,0.0000012234166,0.0014736806,0.00012577674,0.00041232767,0.20387676,0.005003572,0.78864527],"study_design_scores_gemma":[0.008300502,0.009886449,0.013834728,0.0003313143,0.00027713785,0.00011628315,0.0047418824,0.11101785,0.43767306,0.22153817,0.18755683,0.0047257678],"about_ca_topic_score_codex":0.000031279294,"about_ca_topic_score_gemma":0.000005770397,"teacher_disagreement_score":0.7839195,"about_ca_system_score_codex":0.000020343618,"about_ca_system_score_gemma":0.000037678044,"threshold_uncertainty_score":0.6703702},"labels":[],"label_agreement":null},{"id":"W3091655542","doi":"10.1049/iet-cdt.2019.0082","title":"Power efficient error correction coding for on‐chip interconnection links","year":2020,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"","keywords":"Interconnection; Chip; Computer science; Coding (social sciences); Power (physics); Electronic engineering; Embedded system; Engineering; Telecommunications; Mathematics; Physics","score_opus":0.01470135790045721,"score_gpt":0.22456365496956227,"score_spread":0.20986229706910506,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3091655542","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10585058,0.000021205627,0.8815286,0.00029637862,0.002388264,0.00073956547,0.000024372657,0.0045916736,0.004559329],"genre_scores_gemma":[0.9938423,0.0000052543023,0.005223726,0.00045551473,0.0002654128,0.00008130939,0.000027188602,0.00007359061,0.000025719699],"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99890924,0.000009803592,0.00029542117,0.00031980555,0.00016482992,0.0003009151],"domain_scores_gemma":[0.9994729,0.000114469105,0.00005133902,0.00018692062,0.00006082346,0.00011352876],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00008652026,0.00026716423,0.00023563,0.00016014278,0.000074842115,0.0002303952,0.00022127297,0.00018163776,0.000007365714],"category_scores_gemma":[0.00003844124,0.0002721001,0.00013552514,0.0002460742,0.000033436267,0.0003587235,0.000051696104,0.0003442458,0.000046912846],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00059745205,0.0004142298,0.0003756328,0.000570884,0.00033879976,0.000038106555,0.0055838516,0.111680955,0.029642092,0.0020302648,0.46722078,0.38150695],"study_design_scores_gemma":[0.00041982604,0.0014691468,0.00010583728,0.00032261497,0.000014082543,0.000024498611,0.000089035304,0.75200075,0.2060761,0.00012074586,0.038715012,0.00064233656],"about_ca_topic_score_codex":9.778958e-7,"about_ca_topic_score_gemma":2.4133365e-7,"teacher_disagreement_score":0.8879917,"about_ca_system_score_codex":0.00016114031,"about_ca_system_score_gemma":0.000010993443,"threshold_uncertainty_score":0.9999731},"labels":[],"label_agreement":null},{"id":"W3134549106","doi":"10.1049/cdt2.12012","title":"Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Quantum-Dot Cellular Automata","field":"Computer Science","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Saskatchewan","funders":"","keywords":"NAND gate; CMOS; Inverter; Logic gate; Electronic engineering; Computer science; Gate equivalent; Quantum dot cellular automaton; NAND logic; Electronic circuit; AND-OR-Invert; AND gate; Adder; Logic synthesis; Electrical engineering; Engineering; Logic family; Gate oxide; Transistor","score_opus":0.011531768087022514,"score_gpt":0.24311944106203645,"score_spread":0.23158767297501393,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3134549106","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13999243,0.0006590071,0.8476125,0.0018401777,0.0006898869,0.0005469295,0.000014099564,0.004449445,0.00419553],"genre_scores_gemma":[0.68803674,0.00003241207,0.31110612,0.0005140863,0.000059465718,0.000033005126,0.00001944648,0.00004948557,0.00014926659],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9970534,0.000055704197,0.0006358991,0.0010494497,0.00042162428,0.00078396226],"domain_scores_gemma":[0.99786556,0.00009329411,0.00019143868,0.0015127565,0.00020284853,0.00013413012],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002698925,0.00039964425,0.00052579807,0.00063298666,0.00012581662,0.0009232561,0.0018545439,0.00029045498,0.0000060256843],"category_scores_gemma":[0.000068476664,0.00043456804,0.00015586107,0.002156246,0.00017915938,0.0017848792,0.0019657828,0.00044664647,0.00004461065],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005133439,0.0023181846,0.011523138,0.00042256076,0.00025526312,0.012026175,0.0013536353,0.0017014772,0.06373607,0.24316008,0.024945287,0.63850677],"study_design_scores_gemma":[0.00081846287,0.00041955942,0.0003190577,0.000842791,0.000016957167,0.0021530127,0.00006951969,0.36260056,0.4300674,0.13991979,0.06103254,0.0017403597],"about_ca_topic_score_codex":0.000033680943,"about_ca_topic_score_gemma":0.000006627649,"teacher_disagreement_score":0.63676643,"about_ca_system_score_codex":0.0002155087,"about_ca_system_score_gemma":0.0002562142,"threshold_uncertainty_score":0.99981064},"labels":[],"label_agreement":null},{"id":"W3135842381","doi":"10.1049/cdt2.12026","title":"Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 <sup> <i>m</i> </sup> )","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Coding theory and cryptography","field":"Computer Science","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Multiplier (economics); Very-large-scale integration; Arithmetic; Application-specific integrated circuit; Systolic array; Computer science; Multiplication (music); GF(2); Binary number; Cryptography; Finite field; Computer hardware; Parallel computing; Mathematics; Algorithm; Embedded system; Discrete mathematics; Combinatorics","score_opus":0.007820306266085804,"score_gpt":0.230148635912285,"score_spread":0.2223283296461992,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3135842381","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.025475873,0.00006831498,0.96944004,0.0011542378,0.00034502405,0.0006463396,0.000053209347,0.0018064108,0.0010105264],"genre_scores_gemma":[0.7919886,0.000011090822,0.20626554,0.00093887374,0.00040159107,0.00018513032,0.000075910364,0.00004365991,0.00008960005],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99784315,0.00009020586,0.00040306777,0.0008861112,0.0002840741,0.00049342203],"domain_scores_gemma":[0.998036,0.00034177737,0.00016962177,0.0010809279,0.00020634366,0.00016529633],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00022071466,0.00038145494,0.00038672326,0.00024469607,0.00018293287,0.0011112553,0.0012550197,0.00017345254,0.000003999387],"category_scores_gemma":[0.00006863709,0.00037891368,0.00041385661,0.00069485034,0.00012607526,0.00089219864,0.00045012642,0.00024776495,0.000010072419],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003025624,0.00095080386,0.0002564772,0.0003660653,0.00027406332,0.00006772959,0.004016689,0.0004783607,0.0607854,0.17600238,0.029220108,0.72727937],"study_design_scores_gemma":[0.001621993,0.0010721441,0.00013590304,0.00093225256,0.00004475519,0.00036984307,0.00011265544,0.022414017,0.57322985,0.15366566,0.24457723,0.0018237127],"about_ca_topic_score_codex":0.000003701693,"about_ca_topic_score_gemma":0.000002698954,"teacher_disagreement_score":0.76651275,"about_ca_system_score_codex":0.00006549856,"about_ca_system_score_gemma":0.00007846986,"threshold_uncertainty_score":0.9999257},"labels":[],"label_agreement":null},{"id":"W3137786380","doi":"10.1049/cdt2.12019","title":"Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Alberta","funders":"","keywords":"Logarithm; Multiplexer; Computation; Multiplier (economics); Binary number; Detector; Algorithm; Multiplication (music); Computer science; Scaling; Arithmetic; Mathematics; Parallel computing; Multiplexing; Combinatorics; Mathematical analysis","score_opus":0.012124931183356386,"score_gpt":0.25848350127571584,"score_spread":0.24635857009235945,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3137786380","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0057047787,0.00017671916,0.9914827,0.0003962214,0.00042438332,0.00021161578,0.000014692508,0.0008717596,0.0007171448],"genre_scores_gemma":[0.33090517,0.000008740915,0.66838676,0.00048304562,0.00010541005,0.000017290642,0.000006097147,0.000023965522,0.00006352541],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9979681,0.000058447335,0.00038014396,0.00080415147,0.00027476385,0.00051440817],"domain_scores_gemma":[0.9985899,0.00040918734,0.0001355699,0.00046900165,0.00019971807,0.00019667034],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002285974,0.0002950298,0.00042374464,0.00013843537,0.00018520793,0.0009807812,0.0006140355,0.0001074094,0.0000016609491],"category_scores_gemma":[0.00006914593,0.00029117952,0.00016885548,0.00047628462,0.00013226166,0.00040358852,0.00084507366,0.0001603178,0.0000027872622],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000050833,0.0001718258,0.00003094306,0.000029967861,0.000031176067,0.000037105554,0.00013637434,0.00007548567,0.002310186,0.013238449,0.0005023694,0.98343104],"study_design_scores_gemma":[0.0007898489,0.0011103404,0.0003633781,0.00057537435,0.000021619922,0.00037050858,0.000065342174,0.69950044,0.23948169,0.030092156,0.026031727,0.0015975756],"about_ca_topic_score_codex":0.0000058084374,"about_ca_topic_score_gemma":4.3229397e-7,"teacher_disagreement_score":0.98183346,"about_ca_system_score_codex":0.00006195539,"about_ca_system_score_gemma":0.00005546239,"threshold_uncertainty_score":0.99995404},"labels":[],"label_agreement":null},{"id":"W3138924352","doi":"10.1049/cdt2.12021","title":"Static power model for CMOS and FPGA circuits","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Toronto Metropolitan University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Spice; Computer science; Electronic engineering; Field-programmable gate array; CMOS; Transistor; Power (physics); Dynamic demand; Static timing analysis; Power consumption; Power analysis; Process (computing); Voltage; Embedded system; Engineering; Electrical engineering; Algorithm","score_opus":0.010933282171275475,"score_gpt":0.21186501680104272,"score_spread":0.20093173462976724,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3138924352","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.040124845,0.00019445085,0.9541255,0.00010085266,0.00019963445,0.00040854287,0.00008532695,0.001740018,0.0030208016],"genre_scores_gemma":[0.95250064,0.000052525673,0.046838723,0.00023574772,0.000041031566,0.00007706633,0.000036352023,0.00006957555,0.00014836424],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9990107,0.000005623699,0.00024216843,0.0002709455,0.00014545467,0.0003251511],"domain_scores_gemma":[0.9994425,0.00007574115,0.00002711342,0.00027362423,0.00008396612,0.00009703719],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000064611355,0.00022913545,0.00024266995,0.00009438501,0.00004570491,0.000292039,0.00016525928,0.00009049825,0.0000034667835],"category_scores_gemma":[0.000013543378,0.00024339637,0.00006947472,0.00014694233,0.000045129902,0.0007103517,0.00007487602,0.00011423492,0.0000066434777],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00002925555,0.00030373572,0.0004104488,0.0012113906,0.00043160058,0.00017567186,0.0036321296,0.023816142,0.019904098,0.004928895,0.25789008,0.6872666],"study_design_scores_gemma":[0.00044892172,0.00019900737,0.00009590535,0.00022161363,0.000022933498,0.00009278834,0.000037362886,0.8810127,0.09272269,0.0082740635,0.016092734,0.0007793024],"about_ca_topic_score_codex":4.6335325e-7,"about_ca_topic_score_gemma":4.619898e-7,"teacher_disagreement_score":0.91237575,"about_ca_system_score_codex":0.00006248299,"about_ca_system_score_gemma":0.000034012246,"threshold_uncertainty_score":0.99254155},"labels":[],"label_agreement":null},{"id":"W3163808675","doi":"10.1049/cdt2.12031","title":"Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Cryptographic Implementations and Security","field":"Computer Science","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"South Health Campus","funders":"","keywords":"Computer science; Advanced Encryption Standard; Byte; Pipeline (software); Reliability (semiconductor); Fault tolerance; Resilience (materials science); Encryption; Error detection and correction; Embedded system; Computer engineering; Distributed computing; Computer network; Computer hardware; Algorithm; Operating system","score_opus":0.01565170674294585,"score_gpt":0.28350205492381436,"score_spread":0.2678503481808685,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3163808675","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10607149,0.000029091936,0.89043504,0.001249844,0.00025713397,0.00033460825,0.000014050111,0.0008528769,0.00075587124],"genre_scores_gemma":[0.8308999,0.0000035919682,0.16841556,0.00029593913,0.000100201345,0.00003038298,0.0001878637,0.000014211815,0.00005237389],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99836516,0.0000428556,0.000390359,0.0005165242,0.00035577355,0.00032935306],"domain_scores_gemma":[0.9990156,0.000098260425,0.00018867361,0.00035816693,0.0002155568,0.00012373256],"candidate_categories":["scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.00010372685,0.00024111458,0.0002065624,0.00018594408,0.00023082382,0.0012206378,0.00036599592,0.000050366034,0.000032984084],"category_scores_gemma":[0.000014035649,0.00022695323,0.00010648001,0.0007198781,0.00005483062,0.0013385345,0.00018785532,0.00016450936,0.000004253861],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025957315,0.0001291605,0.003792676,0.000021928867,0.00010051656,0.00005714029,0.0021176485,0.000038156675,0.0022517743,0.036113907,0.0072150403,0.9481361],"study_design_scores_gemma":[0.0071886126,0.005074011,0.0410713,0.0010411047,0.00014648054,0.0040564626,0.0063484726,0.12559399,0.6718397,0.03257246,0.099719316,0.005348069],"about_ca_topic_score_codex":0.00011835842,"about_ca_topic_score_gemma":0.0002775716,"teacher_disagreement_score":0.942788,"about_ca_system_score_codex":0.00006282271,"about_ca_system_score_gemma":0.00020146869,"threshold_uncertainty_score":0.9998162},"labels":[],"label_agreement":null},{"id":"W3168383044","doi":"10.1049/cdt2.12032","title":"Introducing <i>KeyRing</i> self‐timed microarchitecture and timing‐driven design flow","year":2021,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"École de Technologie Supérieure; Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; Canadian Network for Research and Innovation in Machining Technology, Natural Sciences and Engineering Research Council of Canada","keywords":"Microarchitecture; Static timing analysis; Computer science; Design flow; Clock gating; Electronic design automation; Computer architecture; Standard cell; Circuit design; Processor design; Physical design; Embedded system; Integrated circuit design; Electronic circuit; Parallel computing; Integrated circuit; Clock skew; Clock signal; Engineering; Jitter","score_opus":0.0061295776355333705,"score_gpt":0.1850439377866857,"score_spread":0.17891436015115234,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3168383044","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.041123666,0.0006862252,0.94986707,0.0002331687,0.0004196209,0.00047985534,0.000023557255,0.0052924575,0.001874382],"genre_scores_gemma":[0.48509762,0.00012615281,0.514049,0.0001973339,0.0002905115,0.000036564732,0.000034177403,0.00010840952,0.000060240644],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9984491,0.000035105462,0.00032122736,0.000497648,0.00021248165,0.00048444368],"domain_scores_gemma":[0.99913466,0.0001277619,0.000043078468,0.00046829574,0.00008062416,0.00014555882],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00012645489,0.00039013257,0.00036869402,0.0001845289,0.000093098206,0.00048035092,0.00029979178,0.00015847365,0.0000081099215],"category_scores_gemma":[0.00002070022,0.00040595888,0.00008982191,0.00034526293,0.00007537609,0.00058670325,0.00021460536,0.0003584669,0.000021744292],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00005617233,0.0002496433,0.00070634414,0.0007802124,0.00060345844,0.00065940985,0.0052007255,0.11154131,0.12462311,0.00010788539,0.18046519,0.57500654],"study_design_scores_gemma":[0.0004841201,0.00023001824,0.00014157838,0.0004360618,0.00004897359,0.0006422098,0.00003138311,0.3306027,0.6264269,0.00050562347,0.0393029,0.0011475737],"about_ca_topic_score_codex":0.0000015876882,"about_ca_topic_score_gemma":5.104751e-7,"teacher_disagreement_score":0.573859,"about_ca_system_score_codex":0.00011115296,"about_ca_system_score_gemma":0.000043586755,"threshold_uncertainty_score":0.99983925},"labels":[],"label_agreement":null},{"id":"W4416306598","doi":"10.1049/cdt2/5384331","title":"A Systematic Literature Review on the Applications, Models, Limitations, and Future Directions of Generative Adversarial Networks","year":2025,"lang":"en","type":"article","venue":"IET Computers & Digital Techniques","topic":"Adversarial Robustness in Machine Learning","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Moncton","funders":"","keywords":"Adversarial system; Key (lock); Domain (mathematical analysis); Systematic review; Similarity (geometry); Generative grammar; Taxonomy (biology); Architecture","score_opus":0.01106865353179942,"score_gpt":0.2506989948505807,"score_spread":0.2396303413187813,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4416306598","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.00000478718,0.041161448,0.9491391,0.0051164525,0.00023781558,0.0015135753,0.000007907072,0.00039113133,0.002427792],"genre_scores_gemma":[0.11892105,0.20595154,0.6563828,0.012666888,0.0016182872,0.0036972591,0.00016021084,0.000092315335,0.0005096391],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985839,0.00020993406,0.00044278114,0.00038945716,0.00021378852,0.00016014597],"domain_scores_gemma":[0.9980871,0.0007432573,0.000256631,0.0006721639,0.00020070687,0.000040111954],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003522744,0.00022543223,0.00038025383,0.00017235223,0.00024504506,0.00039045987,0.00076412957,0.00010302791,3.3903055e-7],"category_scores_gemma":[0.00008740672,0.00015885998,0.00011967579,0.00099147,0.00008733918,0.0007152668,0.00033552098,0.00034599588,6.8906064e-7],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00000955835,0.00009161679,0.0000059156055,0.005196001,0.00014913744,0.000003213819,0.0004991272,0.002572061,0.0000047513504,0.8521579,0.009136678,0.13017404],"study_design_scores_gemma":[0.0003883024,0.00030120168,0.000041655843,0.09602891,0.00020298798,0.00007651778,0.0001712533,0.7730823,0.00015994874,0.06536436,0.06333899,0.0008435502],"about_ca_topic_score_codex":0.0000016927208,"about_ca_topic_score_gemma":5.943445e-7,"teacher_disagreement_score":0.78679353,"about_ca_system_score_codex":0.000050303224,"about_ca_system_score_gemma":0.00004643149,"threshold_uncertainty_score":0.6478122},"labels":[],"label_agreement":null}]}