{"meta":{"query_hash":"0a973c333757","filters":{"venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)"},"cohort_total":6,"direct_labels_cover":0,"predictions_cover":6,"exported":6,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/0a973c333757","api":"https://metacan.xera.ac/api/v1/cohort?venue=Proceedings+2003.+Design+Automation+Conference+%28IEEE+Cat.+No.03CH37451%29"},"results":[{"id":"W3145549985","doi":"10.1109/dac.2003.1218834","title":"A static pattern-independent technique for power grid voltage integrity verification","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":18,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Power grid; Grid; Voltage; Power (physics); Electrical engineering; Engineering; Mathematics","score_opus":0.027139963955979497,"score_gpt":0.24214913160905038,"score_spread":0.21500916765307088,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3145549985","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0018986923,0.000046800655,0.9947437,0.000093970215,0.000025063611,0.00006961251,0.000038361894,0.0010557459,0.0020280606],"genre_scores_gemma":[0.21816906,0.00035180966,0.77492386,0.00037599925,0.000089566085,0.00048572567,0.00037306448,0.0007053753,0.004525624],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9967623,0.0005607351,0.00024950836,0.00040921138,0.0017823669,0.00023583898],"domain_scores_gemma":[0.9961371,0.0011317681,0.00031653544,0.0016973753,0.0006614678,0.000055696415],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.001699016,0.00097283727,0.0007020694,0.0014001795,0.0010099607,0.0015876037,0.0019122581,0.00083606126,0.0048918105],"category_scores_gemma":[0.006507435,0.00089402724,0.0017889232,0.001424732,0.002045717,0.003901088,0.001966227,0.0022698,0.0012940951],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00024917076,0.00019884825,0.0017589607,0.000523565,0.0001377429,0.0006398667,0.00039879774,0.084019706,0.075069346,0.35794237,0.008058968,0.47100258],"study_design_scores_gemma":[0.00012859015,0.0003877776,0.00072111393,0.00018819114,0.00019732864,0.0011183369,0.00012322447,0.4887319,0.15069616,0.3076756,0.04991871,0.00011300921],"about_ca_topic_score_codex":0.0012061927,"about_ca_topic_score_gemma":0.0016507305,"teacher_disagreement_score":0.0048918105,"about_ca_system_score_codex":0.0010699354,"about_ca_system_score_gemma":0.0021976973,"threshold_uncertainty_score":0.016364753},"labels":[],"label_agreement":null},{"id":"W4229722470","doi":"10.1109/dac.2003.1219088","title":"Synthesizing optimal filters for crosstalk-cancellation for high-speed buses","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Crosstalk; Computer science; Electronic engineering; Performance metric; Speedup; Bandwidth (computing); Computer engineering; Algorithm; Telecommunications; Parallel computing; Engineering","score_opus":0.031132588258845115,"score_gpt":0.23741667127861002,"score_spread":0.20628408301976492,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4229722470","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.010447626,0.00007219212,0.9874423,0.000037633123,0.000013909258,0.000020661622,0.000020909241,0.00032910562,0.001615664],"genre_scores_gemma":[0.22135063,0.00013974024,0.7761128,0.00007568741,0.000034809418,0.00009808766,0.00008409757,0.00010693993,0.0019972732],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99958223,0.00009148245,0.00002593365,0.000066771056,0.0001727052,0.000060913375],"domain_scores_gemma":[0.9994468,0.0002584739,0.00009989091,0.00005198216,0.00012607012,0.000016852864],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00053393934,0.0009800354,0.00040849886,0.00050646137,0.00035408055,0.0007963011,0.00053278916,0.0008161472,0.0027406733],"category_scores_gemma":[0.0017592433,0.00036833217,0.00044671423,0.00043040855,0.0004263379,0.00068966177,0.000305037,0.00055959704,0.00090633344],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00023620276,0.0001610131,0.0007828954,0.0003298067,0.000089364745,0.00013930643,0.00023536976,0.41930464,0.20601915,0.045926735,0.0028505572,0.32392493],"study_design_scores_gemma":[0.00006623827,0.00024227751,0.00021220112,0.000023801496,0.000034678,0.000112940055,0.000048181784,0.8834985,0.09627992,0.013542886,0.005914359,0.000024016419],"about_ca_topic_score_codex":0.0010865803,"about_ca_topic_score_gemma":0.0027196347,"teacher_disagreement_score":0.0027406733,"about_ca_system_score_codex":0.0007790011,"about_ca_system_score_gemma":0.00085043395,"threshold_uncertainty_score":0.009168506},"labels":[],"label_agreement":null},{"id":"W4234208104","doi":"10.1109/dac.2003.1219120","title":"A retargetable microarchitecture simulator","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Microarchitecture; Computer science; Computer architecture; Microprocessor; Instruction set; Embedded system; Branch predictor; Computer architecture simulator; Parallel computing","score_opus":0.02517826436919297,"score_gpt":0.24624760849092725,"score_spread":0.2210693441217343,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4234208104","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.12711985,0.00029436313,0.8322159,0.0002654315,0.00018226648,0.00033082662,0.0023965186,0.02029848,0.016896272],"genre_scores_gemma":[0.44351432,0.00049319473,0.5333041,0.00017455257,0.000044509863,0.00067906315,0.0043708594,0.0012669823,0.016152471],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99982244,0.00002634893,0.000012368966,0.000021012207,0.000097334465,0.000020400914],"domain_scores_gemma":[0.9995919,0.00014479262,0.00003911058,0.00010393068,0.000093773,0.00002657449],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003062863,0.00040461143,0.00030793383,0.00032827366,0.0001790237,0.00032927573,0.0011032947,0.0005749996,0.0035557281],"category_scores_gemma":[0.0010074505,0.00036121692,0.00045330886,0.00028151314,0.00022615927,0.00049366005,0.00046071873,0.0008517124,0.0007444953],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011572395,0.000087090506,0.0014613485,0.00013081542,0.000057976948,0.00020812779,0.00012287003,0.8762872,0.050124872,0.023083292,0.006426302,0.0418944],"study_design_scores_gemma":[0.000033759057,0.00005147455,0.00023622335,0.000003932356,0.000013053077,0.000040983356,0.0000041639214,0.9784388,0.008596759,0.0021384684,0.010433737,0.000008527417],"about_ca_topic_score_codex":0.0018924564,"about_ca_topic_score_gemma":0.0023816116,"teacher_disagreement_score":0.0035557281,"about_ca_system_score_codex":0.0002797748,"about_ca_system_score_gemma":0.00088560744,"threshold_uncertainty_score":0.011895061},"labels":[],"label_agreement":null},{"id":"W4242199054","doi":"10.1109/dac.2003.1219139","title":"Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Die (integrated circuit); Power grid; Voltage; Voltage drop; Leakage (economics); Grid; Leakage power; Computer science; Environmental science; Electrical engineering; Electronic engineering; Power (physics); Engineering; Mechanical engineering; Transistor; Mathematics; Physics","score_opus":0.04336309476274766,"score_gpt":0.2768579591042649,"score_spread":0.23349486434151726,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4242199054","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.27908415,0.00012154633,0.7188141,0.000057149697,0.0000108818795,0.00003324312,0.000227784,0.0010143134,0.0006368922],"genre_scores_gemma":[0.9616405,0.000094761395,0.037462823,0.000020152307,0.000023024802,0.00003120941,0.00046167232,0.000061599465,0.00020433939],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9993492,0.00015117864,0.000042472653,0.000097042,0.00031743984,0.000042532032],"domain_scores_gemma":[0.99319094,0.0044650575,0.000839511,0.0007294309,0.0006745213,0.00010046481],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00079244806,0.00037508176,0.00042892725,0.0008520713,0.0001257396,0.0003985372,0.0005072835,0.00033988795,0.00029438123],"category_scores_gemma":[0.010764705,0.00026264318,0.00025187194,0.00083541067,0.00028689238,0.00073658815,0.00042718512,0.00042648727,0.0001566044],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003322656,0.000090461086,0.041180007,0.000107370295,0.00011800466,0.00041333618,0.000100401325,0.7882366,0.052752886,0.0047727004,0.0005412608,0.11135458],"study_design_scores_gemma":[0.0000036237855,0.00005167966,0.0058928295,0.0000028321938,0.000008684798,0.00011334173,0.000007577934,0.98211735,0.010508561,0.0011772937,0.00010838365,0.000007855891],"about_ca_topic_score_codex":0.0007177349,"about_ca_topic_score_gemma":0.0011029468,"teacher_disagreement_score":0.0008520713,"about_ca_system_score_codex":0.00030820462,"about_ca_system_score_gemma":0.00035944558,"threshold_uncertainty_score":0.004190922},"labels":[],"label_agreement":null},{"id":"W4244938795","doi":"10.1109/dac.2003.1219137","title":"Design of a 17-million gate network processor using a design factory","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":false,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":true,"ca_institutions":"","funders":"","keywords":"Factory (object-oriented programming); Computer science; Network processor; Computer network; Programming language","score_opus":0.08659970242603296,"score_gpt":0.2826864506209027,"score_spread":0.19608674819486974,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4244938795","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.17968446,0.0003522096,0.78766876,0.00043372664,0.00010243736,0.00039974722,0.00021916667,0.0030009018,0.02813857],"genre_scores_gemma":[0.54765534,0.0002099349,0.4357421,0.00020705935,0.000021664719,0.0003630551,0.00032314265,0.00016031801,0.0153173385],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.999821,0.000034318073,0.00000998433,0.000034286866,0.00006379087,0.000036644735],"domain_scores_gemma":[0.99988365,0.000028450431,0.000014656582,0.00001808366,0.000040803607,0.0000143837115],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00036806188,0.0002974728,0.0002122734,0.00018956642,0.00029088627,0.00072724913,0.0004944526,0.00036047128,0.0034579604],"category_scores_gemma":[0.00037449237,0.00023118287,0.00034799345,0.00017602835,0.00018582612,0.0003611169,0.00022048081,0.0003194069,0.0009827956],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0008153056,0.0004233898,0.0066350745,0.0003946115,0.00025055587,0.001207161,0.0006819263,0.24418853,0.24570689,0.06672531,0.0158899,0.41708133],"study_design_scores_gemma":[0.00065186084,0.002505828,0.004635976,0.0000914444,0.00020399658,0.0012905109,0.00017677444,0.66192013,0.17122997,0.0156114055,0.14159098,0.00009113099],"about_ca_topic_score_codex":0.0013556385,"about_ca_topic_score_gemma":0.0013863827,"teacher_disagreement_score":0.0034579604,"about_ca_system_score_codex":0.00055716746,"about_ca_system_score_gemma":0.001321206,"threshold_uncertainty_score":0.011568069},"labels":[],"label_agreement":null},{"id":"W4252940155","doi":"10.1109/dac.2003.1219000","title":"Model order reduction of nonuniform transmission lines using integrated congruence transform","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Model Reduction and Neural Networks","field":"Physics and Astronomy","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Orthonormal basis; Basis function; Algorithm; Computer science; Congruence (geometry); Model order reduction; Orthogonal basis; Basis (linear algebra); Mathematics; Orthonormality; Topology (electrical circuits); Mathematical optimization; Projection (relational algebra); Mathematical analysis","score_opus":0.05159047128044988,"score_gpt":0.2770223753109597,"score_spread":0.2254319040305098,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4252940155","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005258632,0.000016026233,0.9935654,0.000021493173,0.000008223676,0.000013196379,0.000013426415,0.000095467345,0.0010082251],"genre_scores_gemma":[0.34139237,0.00016040418,0.653652,0.0000548154,0.00003549454,0.00012732497,0.00020099517,0.00024342471,0.004133158],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996716,0.000076120865,0.000016507865,0.000059719183,0.00014737724,0.000028586515],"domain_scores_gemma":[0.99977356,0.00008355251,0.000032370437,0.000047465797,0.000050090766,0.00001290336],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004934528,0.00061376253,0.0006572238,0.0003601352,0.00036231382,0.00059966784,0.00072150055,0.00035162558,0.0027289793],"category_scores_gemma":[0.0013291035,0.00024357934,0.00072377623,0.0003967389,0.00054827094,0.0010001303,0.0009831927,0.0008987298,0.00059860316],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011691417,0.00006999417,0.00073229015,0.000096590564,0.000035150628,0.00022767737,0.00020330978,0.5568838,0.029754225,0.20170167,0.0017413143,0.20843711],"study_design_scores_gemma":[0.000010870146,0.000031341642,0.000057839334,0.0000030849335,0.0000048380684,0.00003247542,0.000013388435,0.97412574,0.0033389614,0.020843318,0.0015328574,0.000005294751],"about_ca_topic_score_codex":0.0016846474,"about_ca_topic_score_gemma":0.0018864747,"teacher_disagreement_score":0.0027289793,"about_ca_system_score_codex":0.0004676547,"about_ca_system_score_gemma":0.00077216694,"threshold_uncertainty_score":0.009129286},"labels":[],"label_agreement":null}]}