{"meta":{"query_hash":"34e9ba243374","filters":{"venue":"Proceedings EURO-DAC '92: European Design Automation Conference"},"cohort_total":2,"direct_labels_cover":0,"predictions_cover":2,"exported":2,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/34e9ba243374","api":"https://metacan.xera.ac/api/v1/cohort?venue=Proceedings+EURO-DAC+%2792%3A+European+Design+Automation+Conference"},"results":[{"id":"W4229764280","doi":"10.1109/eurdac.1992.246233","title":"Efficient constrained encoding for VLSI sequential logic synthesis","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Encoding (memory); Heuristic; Computer science; Asynchronous communication; Sequential logic; Variety (cybernetics); Algorithm; State (computer science); Theoretical computer science; Parallel computing; Arithmetic; Logic gate; Artificial intelligence; Mathematics","score_opus":0.05243470574356956,"score_gpt":0.24200893338452087,"score_spread":0.1895742276409513,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4229764280","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011416179,0.00007436498,0.87875605,0.000060833365,0.00027038032,0.0012087879,0.000020794423,0.0035448913,0.104647726],"genre_scores_gemma":[0.9393107,0.000042094103,0.059999764,0.00008691075,0.00009962438,0.00017309698,0.0000071683676,0.00013170645,0.00014890594],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976103,0.00015198007,0.00069057214,0.0005716435,0.00034554765,0.0006299796],"domain_scores_gemma":[0.9986477,0.00028818168,0.00021936167,0.00020380325,0.00044890287,0.00019206291],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0016130845,0.00048301963,0.00039771863,0.0003200073,0.00026119783,0.00041860272,0.00044480275,0.0001206232,0.00019049496],"category_scores_gemma":[0.0011313765,0.000499812,0.00014163768,0.0003899197,0.00012340004,0.00024625813,0.000041370142,0.00025268923,0.0001577399],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000036576625,0.00011056546,0.000081387654,0.0005913998,0.000104956795,0.00002564911,0.00125629,0.005774688,0.88442534,0.084822364,0.006158582,0.016612213],"study_design_scores_gemma":[0.0007462182,0.00022733335,0.00019370789,0.00038396148,0.00013380719,0.00011300699,0.00025439134,0.51364875,0.47691008,0.0023272408,0.003911695,0.0011498167],"about_ca_topic_score_codex":6.731334e-7,"about_ca_topic_score_gemma":7.8627565e-8,"teacher_disagreement_score":0.92789453,"about_ca_system_score_codex":0.00012339394,"about_ca_system_score_gemma":0.00007377194,"threshold_uncertainty_score":0.99974537},"labels":[],"label_agreement":null},{"id":"W4251343752","doi":"10.1109/eurdac.1992.246230","title":"Routing algorithms for multi-chip modules","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Static routing; Routing (electronic design automation); Link-state routing protocol; Equal-cost multi-path routing; Policy-based routing; Placement; Multipath routing; Dynamic Source Routing; Destination-Sequenced Distance Vector routing; Algorithm; Channel (broadcasting); Distributed computing; Computer network; Physical design; Routing protocol; Embedded system; Circuit design","score_opus":0.09028723337086844,"score_gpt":0.26703503960550923,"score_spread":0.1767478062346408,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4251343752","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004865196,0.00011657502,0.96695733,0.000029567324,0.00022669029,0.0010562787,0.000013648281,0.004125399,0.022609318],"genre_scores_gemma":[0.6970292,0.00006620241,0.30213398,0.0000681003,0.00009829121,0.000099299374,0.000011084635,0.00015274754,0.00034111852],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9977682,0.00010916606,0.0006575508,0.000558199,0.00029278058,0.00061408663],"domain_scores_gemma":[0.9988188,0.00011488458,0.00020547744,0.00021381781,0.00046526603,0.00018176815],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0013830992,0.00047593506,0.0003530021,0.00025194188,0.00025510223,0.00044292372,0.00045510713,0.000112161615,0.000048692014],"category_scores_gemma":[0.0006581701,0.00050351786,0.00011537898,0.00035029426,0.00006469727,0.0006432746,0.00004424214,0.00029335855,0.00015153381],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000054195392,0.00033683635,0.001086227,0.0013370252,0.0002506475,0.00003624826,0.0062260036,0.002768036,0.6313299,0.08424545,0.026333986,0.24599546],"study_design_scores_gemma":[0.00081853283,0.00015366993,0.0012446663,0.00021186241,0.000047058147,0.000039909028,0.00016588293,0.857233,0.13344747,0.001254344,0.004583997,0.0007996366],"about_ca_topic_score_codex":0.0000013204613,"about_ca_topic_score_gemma":1.7167099e-7,"teacher_disagreement_score":0.85446495,"about_ca_system_score_codex":0.00008525833,"about_ca_system_score_gemma":0.000037529004,"threshold_uncertainty_score":0.9997417},"labels":[],"label_agreement":null}]}