{"meta":{"query_hash":"ea9efcbaf870","filters":{"venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005."},"cohort_total":8,"direct_labels_cover":0,"predictions_cover":8,"exported":8,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/ea9efcbaf870","api":"https://metacan.xera.ac/api/v1/cohort?venue=Proceedings+of+the+ASP-DAC+2005.+Asia+and+South+Pacific+Design+Automation+Conference%2C+2005."},"results":[{"id":"W4230771668","doi":"10.1109/aspdac.2005.1466516","title":"BDD-based two variable sharing extraction","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Formal Methods in Verification","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Binary decision diagram; Computer science; Variable (mathematics); Theoretical computer science; Algorithm; Binary number; Product (mathematics); Exploit; Mathematics; Arithmetic","score_opus":0.03509736295451807,"score_gpt":0.27371557636361077,"score_spread":0.2386182134090927,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4230771668","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0071913227,0.00010008897,0.9888764,0.000043857686,0.000025307805,0.00009988539,0.00016023239,0.0016218828,0.0018809541],"genre_scores_gemma":[0.1479761,0.00016764383,0.8470536,0.000060131446,0.0000148861345,0.0001828479,0.0008783925,0.00031649615,0.0033499184],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99853575,0.0001920895,0.00013842156,0.000278266,0.0007043531,0.00015110703],"domain_scores_gemma":[0.99862206,0.0005235519,0.00010263761,0.00038305228,0.00033850086,0.000030230936],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00095794135,0.0009882881,0.000929605,0.0016069004,0.00070073747,0.0011275327,0.0009937055,0.0005494941,0.0049358467],"category_scores_gemma":[0.0032381741,0.00063957745,0.0014866812,0.0013606178,0.00079831143,0.002085473,0.0018127295,0.00091411266,0.0012553995],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00032092762,0.00013109794,0.0017000264,0.00055253867,0.00011807184,0.00026030786,0.00024026983,0.14267485,0.03660455,0.075069025,0.00461867,0.73770964],"study_design_scores_gemma":[0.00010709216,0.00013030089,0.0005766854,0.0000691253,0.00013747365,0.00030065933,0.0000809837,0.759787,0.107877485,0.099681444,0.03118951,0.00006218836],"about_ca_topic_score_codex":0.0020972406,"about_ca_topic_score_gemma":0.0025753886,"teacher_disagreement_score":0.0049358467,"about_ca_system_score_codex":0.00087101996,"about_ca_system_score_gemma":0.0016723769,"threshold_uncertainty_score":0.016512096},"labels":[],"label_agreement":null},{"id":"W4231097844","doi":"10.1109/aspdac.2005.1466550","title":"Register-transfer level functional scan for hierarchical designs","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Register-transfer level; Scan chain; Design for testing; Computer science; Abstraction; Testability; Transfer (computing); Shift register; High-level synthesis; Register (sociolinguistics); Logic synthesis; Parallel computing; Computer architecture; Logic gate; Embedded system; Reliability engineering; Algorithm; Integrated circuit; Engineering; Field-programmable gate array","score_opus":0.08925124745465288,"score_gpt":0.24746071642811046,"score_spread":0.15820946897345758,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4231097844","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.043737713,0.0004341179,0.9430285,0.00011805675,0.000024375378,0.000082659724,0.00011405552,0.0015584852,0.010902097],"genre_scores_gemma":[0.6110209,0.0003421933,0.3839407,0.00016389515,0.000031797987,0.00012246391,0.00027402354,0.00016698637,0.0039369795],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99964416,0.00009260205,0.00002140909,0.00004565657,0.00015096577,0.000045087054],"domain_scores_gemma":[0.9990546,0.0004152588,0.00009823918,0.0003007825,0.00011008438,0.000021071693],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004780131,0.00034488656,0.00019111525,0.00035602855,0.0002394815,0.0004490814,0.0004738593,0.00030726346,0.0053722598],"category_scores_gemma":[0.0015507813,0.0001645569,0.00035583664,0.00038148568,0.0005373975,0.0007361433,0.0004751916,0.0005619563,0.0007390984],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00035557593,0.00006986857,0.002429997,0.000656976,0.000051147752,0.00054302113,0.00038137686,0.21488449,0.1479048,0.25221634,0.0034850645,0.3770213],"study_design_scores_gemma":[0.00008452589,0.00091846235,0.0014642664,0.00012974655,0.000075001146,0.00067514036,0.00010654142,0.7278408,0.09728756,0.1286843,0.042680804,0.000052882842],"about_ca_topic_score_codex":0.0008278645,"about_ca_topic_score_gemma":0.0023441436,"teacher_disagreement_score":0.0053722598,"about_ca_system_score_codex":0.00048266887,"about_ca_system_score_gemma":0.00052038435,"threshold_uncertainty_score":0.017971992},"labels":[],"label_agreement":null},{"id":"W4234808533","doi":"10.1109/aspdac.2005.1466422","title":"A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Photonic and Optical Devices","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Retiming; Transmitter; CMOS; Backplane; Current-mode logic; Electronic engineering; Finite impulse response; Emphasis (telecommunications); Electrical engineering; Computer science; Engineering; Channel (broadcasting)","score_opus":0.012031669298268247,"score_gpt":0.20710529379797868,"score_spread":0.19507362449971044,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4234808533","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.87309194,0.00075505953,0.11185845,0.00045477608,0.00013541577,0.00013956557,0.0002807815,0.0026744076,0.01060967],"genre_scores_gemma":[0.89033866,0.00028729218,0.099461295,0.00010716093,0.000026972659,0.00004537527,0.00012578172,0.00003590739,0.009571603],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9998847,0.000013226542,0.0000055758915,0.00002345401,0.00004130121,0.00003169798],"domain_scores_gemma":[0.9998945,0.000023707571,0.00002294081,0.000009915923,0.00003257625,0.000016424323],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00015664966,0.00022740125,0.0001876723,0.00013780172,0.00023035884,0.0002552224,0.00034476674,0.0003005533,0.0022891392],"category_scores_gemma":[0.0002221705,0.00014711663,0.00014372932,0.00013576563,0.00012311897,0.000311984,0.00013801239,0.00029522635,0.000680083],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000266709,0.0000732766,0.0015869378,0.00012624938,0.000019144953,0.00041316004,0.0001724981,0.003935868,0.9601022,0.00245707,0.0010218876,0.029825024],"study_design_scores_gemma":[0.00018198676,0.0021526099,0.0046729264,0.00004707235,0.00010052794,0.0017406244,0.00009013278,0.053522006,0.9106142,0.00069626,0.026133494,0.0000482654],"about_ca_topic_score_codex":0.0012640589,"about_ca_topic_score_gemma":0.0018814246,"teacher_disagreement_score":0.0022891392,"about_ca_system_score_codex":0.00044933215,"about_ca_system_score_gemma":0.00054134947,"threshold_uncertainty_score":0.007657945},"labels":[],"label_agreement":null},{"id":"W4243129105","doi":"10.1109/aspdac.2005.1466217","title":"Scalable interprocedural register allocation for high level synthesis","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Register allocation; Speedup; Scalability; Parallel computing; Relation (database); Branch predictor; Theoretical computer science; Programming language; Compiler","score_opus":0.03924881455436664,"score_gpt":0.24645044981976824,"score_spread":0.20720163526540158,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4243129105","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.016251042,0.00046975564,0.9748531,0.000097940036,0.00002975147,0.0000613444,0.00006041552,0.0056574144,0.0025191696],"genre_scores_gemma":[0.22473335,0.00032599625,0.7720241,0.00008149409,0.000037157668,0.00015047735,0.00022816751,0.0005525294,0.0018667122],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99934727,0.00019274329,0.00003397566,0.00009354483,0.00024239627,0.00008999842],"domain_scores_gemma":[0.9991881,0.00037716367,0.00006111374,0.00025659593,0.00008917933,0.00002773856],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00063104404,0.00087268103,0.000587637,0.00095384836,0.00044229286,0.00077258126,0.0010112807,0.00045480145,0.004697177],"category_scores_gemma":[0.0014199702,0.00046668836,0.0006420736,0.00092044304,0.0005363837,0.0011419246,0.00076726347,0.0012459477,0.0009961544],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003032068,0.00012655099,0.0006997035,0.0003115579,0.0000640457,0.0001216247,0.00012853283,0.28528622,0.10279341,0.026345583,0.0055214907,0.5782981],"study_design_scores_gemma":[0.00005945202,0.000121525605,0.00030526717,0.000022418615,0.000031419375,0.000059651815,0.000023005041,0.93335944,0.04269074,0.017338516,0.0059684087,0.000020152764],"about_ca_topic_score_codex":0.0023869355,"about_ca_topic_score_gemma":0.004522896,"teacher_disagreement_score":0.004697177,"about_ca_system_score_codex":0.0010117216,"about_ca_system_score_gemma":0.0015923398,"threshold_uncertainty_score":0.015713632},"labels":[],"label_agreement":null},{"id":"W4247631688","doi":"10.1109/aspdac.2005.1466116","title":"Leakage power: trends, analysis and avoidance","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Leakage (economics); Subthreshold conduction; Leakage power; Electronic engineering; Transistor; Electrical engineering; Scaling; Computer science; Circuit design; Voltage; Engineering; Mathematics","score_opus":0.009213849121891968,"score_gpt":0.19374001573804053,"score_spread":0.18452616661614857,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4247631688","genre_codex":"review","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005173655,0.9372146,0.023125395,0.0032216103,0.0010118441,0.000044551,0.00042588913,0.0004829395,0.02929942],"genre_scores_gemma":[0.046245925,0.90961736,0.016206164,0.001734485,0.0023679219,0.000089140616,0.00084827904,0.00019286554,0.022697922],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9994373,0.00005745878,0.00003294983,0.000107987646,0.00032178216,0.000042413372],"domain_scores_gemma":[0.99943453,0.00018381551,0.00006820706,0.00003588926,0.00025579613,0.000021821128],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005855916,0.0008839496,0.0006934052,0.002106088,0.00031684866,0.0025745595,0.0010853983,0.0012446311,0.0037395093],"category_scores_gemma":[0.0014136294,0.0005573544,0.0005161783,0.0037157286,0.0005499788,0.004154105,0.00063387403,0.0017895688,0.0029438382],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000083034254,0.00008411244,0.0019283751,0.0051913965,0.00007095236,0.00021392027,0.00025427778,0.009071509,0.0066649662,0.064223975,0.063695095,0.8485184],"study_design_scores_gemma":[0.000009404837,0.00028074055,0.003718967,0.0025950186,0.0000711441,0.0016646112,0.00025351119,0.012608545,0.0060935654,0.03848289,0.934145,0.0000766448],"about_ca_topic_score_codex":0.0011030918,"about_ca_topic_score_gemma":0.0010131742,"teacher_disagreement_score":0.0037395093,"about_ca_system_score_codex":0.0009514499,"about_ca_system_score_gemma":0.0008111352,"threshold_uncertainty_score":0.012509882},"labels":[],"label_agreement":null},{"id":"W4250137794","doi":"10.1109/aspdac.2005.1466487","title":"Crossbar based design schemes for switch boxes and programmable interconnection networks","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Wilfrid Laurier University","funders":"","keywords":"Crossbar switch; Interconnection; Computer science; Routing (electronic design automation); Crossover switch; Field-programmable gate array; Topology (electrical circuits); Network on a chip; Network topology; Parallel computing; Embedded system; Computer architecture; Computer network; Engineering; Electrical engineering; Telecommunications","score_opus":0.025511391140629478,"score_gpt":0.23102644318365506,"score_spread":0.2055150520430256,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4250137794","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.014793085,0.0027978716,0.96161497,0.00024673628,0.0003803746,0.000118035314,0.00009824118,0.00072536187,0.019225292],"genre_scores_gemma":[0.29827863,0.003302445,0.6776101,0.0005712762,0.00022215728,0.00045837075,0.00022610318,0.00020540314,0.019125514],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996512,0.0000994962,0.000031308944,0.00007699286,0.000108830805,0.000032158576],"domain_scores_gemma":[0.9997296,0.000067291636,0.000051888033,0.00006476083,0.00007453344,0.000012017954],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00044244574,0.00073029246,0.00022243525,0.00052182877,0.00030810945,0.0008995082,0.00089229504,0.0006766507,0.0045232926],"category_scores_gemma":[0.0007442914,0.00029220516,0.0003643182,0.000668421,0.0005753584,0.0010268776,0.0005174461,0.000857033,0.00091043464],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00011857295,0.000047719983,0.00024678657,0.0006401575,0.00005344359,0.00020177767,0.00020304167,0.042701617,0.07464257,0.70971286,0.0047197817,0.1667117],"study_design_scores_gemma":[0.00017049511,0.0006622136,0.0006185099,0.00030900893,0.00014084807,0.0018172358,0.00013186895,0.23330748,0.118170455,0.24456747,0.40001836,0.000086162356],"about_ca_topic_score_codex":0.00020073143,"about_ca_topic_score_gemma":0.0003954649,"teacher_disagreement_score":0.0045232926,"about_ca_system_score_codex":0.00062098785,"about_ca_system_score_gemma":0.00032829493,"threshold_uncertainty_score":0.01513195},"labels":[],"label_agreement":null},{"id":"W4255096096","doi":"10.1109/aspdac.2005.1466524","title":"XTW: a parallel and distributed logic simulator","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Rollback; Computer science; Queue; Scheduling (production processes); Parallel computing; Schedule; Logic simulation; Distributed computing; Discrete event simulation; Logic gate; Real-time computing; Simulation; Computer network; Algorithm; Operating system; Engineering; Database transaction","score_opus":0.02255839538384482,"score_gpt":0.23686956836543874,"score_spread":0.2143111729815939,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4255096096","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04815875,0.00022708006,0.91036576,0.00032569573,0.00014322948,0.00034865743,0.001969166,0.025691876,0.012769827],"genre_scores_gemma":[0.5045209,0.0004998621,0.47351208,0.0003961742,0.00005694274,0.0009843154,0.0038099247,0.0020178687,0.014201857],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9996792,0.000082670194,0.000023280601,0.000042641863,0.000140542,0.000031707816],"domain_scores_gemma":[0.9994567,0.00023495306,0.000048161884,0.00013179358,0.00008993578,0.000038510512],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005374277,0.00050544547,0.00038399894,0.00039204292,0.00024497116,0.0007379108,0.002162536,0.0005204761,0.008162523],"category_scores_gemma":[0.0014960984,0.0005112216,0.000497699,0.00044230258,0.00040401577,0.0013477703,0.00081821845,0.0010135358,0.0010532461],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00039731563,0.0001321827,0.0019167168,0.0002893677,0.00010042341,0.00018861957,0.00009951959,0.86827546,0.021102348,0.032721885,0.012142117,0.06263407],"study_design_scores_gemma":[0.000058281057,0.000056942434,0.00009288042,0.0000045589863,0.000012565193,0.00003944223,0.0000059865743,0.98236024,0.0055718403,0.0043441937,0.0074436907,0.000009425337],"about_ca_topic_score_codex":0.0022992373,"about_ca_topic_score_gemma":0.0027815201,"teacher_disagreement_score":0.008162523,"about_ca_system_score_codex":0.0005294025,"about_ca_system_score_gemma":0.0013013615,"threshold_uncertainty_score":0.027306378},"labels":[],"label_agreement":null},{"id":"W4256280318","doi":"10.1109/aspdac.2005.1466203","title":"Integration of supercubing and learning in a SAT solver","year":2005,"lang":"en","type":"article","venue":"Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.","topic":"Formal Methods in Verification","field":"Computer Science","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of British Columbia","funders":"","keywords":"Exploit; Solver; Pruning; Computer science; Boolean satisfiability problem; Enhanced Data Rates for GSM Evolution; Point (geometry); Theoretical computer science; Artificial intelligence; Mathematics; Programming language","score_opus":0.03063839314547008,"score_gpt":0.24974613998915138,"score_spread":0.21910774684368128,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4256280318","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"metacan-v3-hybrid-931329e0061c","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.058138162,0.0003233918,0.9317817,0.0005409568,0.000044738415,0.00022777643,0.00009322632,0.0017701603,0.007079979],"genre_scores_gemma":[0.36749235,0.00021467138,0.62791187,0.00034113927,0.00004089287,0.00024213268,0.00034206023,0.00025937957,0.0031554936],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99614304,0.0016169079,0.00020135347,0.00059267716,0.0011597583,0.00028630602],"domain_scores_gemma":[0.99084353,0.005640102,0.0004775997,0.0017249652,0.0011022607,0.00021158138],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0029601,0.00093548384,0.0013605639,0.0011413879,0.0007882065,0.0015761639,0.0027325763,0.0014531652,0.0035218133],"category_scores_gemma":[0.013453605,0.0006637356,0.000736136,0.0014782689,0.0014789052,0.0028338982,0.0030392811,0.002631639,0.0009914968],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00043072356,0.00055831997,0.005715359,0.00032180766,0.000109748595,0.0003912585,0.0003776714,0.27490354,0.01029374,0.082976244,0.004252265,0.61966944],"study_design_scores_gemma":[0.000033509594,0.00015955295,0.00039910286,0.000030671694,0.000031620944,0.000170081,0.000064284286,0.9225723,0.013341869,0.058837987,0.0043397737,0.00001928229],"about_ca_topic_score_codex":0.0018969128,"about_ca_topic_score_gemma":0.004055464,"teacher_disagreement_score":0.0035218133,"about_ca_system_score_codex":0.000987999,"about_ca_system_score_gemma":0.0016739873,"threshold_uncertainty_score":0.015654683},"labels":[],"label_agreement":null}]}