{"meta":{"query_hash":"85c6ca2a43f1","filters":{"venue":"SYNCHROINFO JOURNAL"},"cohort_total":3,"direct_labels_cover":0,"predictions_cover":3,"exported":3,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/85c6ca2a43f1","api":"https://metacan.xera.ac/api/v1/cohort?venue=SYNCHROINFO+JOURNAL"},"results":[{"id":"W3206782637","doi":"10.36724/2664-066x-2021-7-3-31-35","title":"A 19 MW, 12.5 B, 2.1 MS/S SINGLE-BIT DS ADC IN 0.18 MM DIGITAL CMOS PROCESS","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Oversampling; CMOS; Delta-sigma modulation; Computer science; Bandwidth (computing); Electronic engineering; Effective number of bits; Switched capacitor; Electrical engineering; Low-power electronics; Dissipation; Dynamic range; Voltage; Power (physics); Capacitor; Engineering; Physics; Telecommunications; Power consumption","score_opus":0.018059502541116046,"score_gpt":0.2218679147422079,"score_spread":0.20380841220109186,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3206782637","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.46618685,0.009235521,0.22085443,0.00013454599,0.001905999,0.00043385933,0.00007161789,0.00065325043,0.30052394],"genre_scores_gemma":[0.9981368,0.00010688362,0.00007406644,0.00010962803,0.00061762996,0.0000073297,0.000015983536,0.0000627239,0.0008689158],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9981221,0.00004134331,0.00056868803,0.00023347003,0.0004183595,0.00061604095],"domain_scores_gemma":[0.9991466,0.0000818169,0.00008848162,0.00021332204,0.00013160017,0.00033819137],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00025957698,0.00028772597,0.0003676242,0.00021885775,0.00012166732,0.00040901106,0.00026842603,0.00015512883,0.0007838322],"category_scores_gemma":[0.00017363172,0.00029017802,0.0001754403,0.00042913033,0.000054062253,0.0005741013,0.000028780718,0.0007488237,0.00018779204],"study_design_candidate":"not_applicable","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00033975035,0.0018640943,0.06203214,0.0030448036,0.0020699073,0.039162274,0.018725183,0.20676036,0.110036366,0.006926203,0.14198634,0.40705258],"study_design_scores_gemma":[0.035303365,0.0036321902,0.026283445,0.0103071155,0.0011042916,0.1337572,0.026009832,0.08043642,0.1418415,0.16847995,0.35663506,0.016209615],"about_ca_topic_score_codex":0.0000052056644,"about_ca_topic_score_gemma":0.000022557526,"teacher_disagreement_score":0.53195,"about_ca_system_score_codex":0.0002899081,"about_ca_system_score_gemma":0.0002981097,"threshold_uncertainty_score":0.99995506},"labels":[],"label_agreement":null},{"id":"W3207568191","doi":"10.36724/2664-066x-2021-7-3-27-30","title":"TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Electronic engineering; Mixed-signal integrated circuit; Computer science; Electronics; Automatic test equipment; Integrated circuit; Engineering; Electrical engineering","score_opus":0.015981842894420048,"score_gpt":0.229053941566265,"score_spread":0.21307209867184496,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W3207568191","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.1556931,0.001358835,0.756351,0.0031788088,0.0024560993,0.00017422119,0.000020007981,0.0007670697,0.08000089],"genre_scores_gemma":[0.99156743,0.000023554028,0.004687273,0.0007055109,0.0006321097,0.0000015724074,0.000005212433,0.000019951103,0.0023573658],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9981798,0.000058504887,0.00044162112,0.00032277068,0.00046998126,0.00052734243],"domain_scores_gemma":[0.99841666,0.0003476675,0.00021012232,0.00037907565,0.0003182632,0.00032818448],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00039519253,0.0001983723,0.0002550787,0.000117665586,0.0003905479,0.0008085012,0.00084505026,0.00006821925,0.00042084118],"category_scores_gemma":[0.0004870979,0.00018431747,0.0002068169,0.0004718692,0.00008230588,0.00076030515,0.00022466667,0.0004992315,0.00061517773],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000015688415,0.000376069,0.013572819,0.000057324087,0.00019196303,0.010391323,0.0019092766,0.00058884174,0.072765745,0.0035184463,0.054677125,0.8419495],"study_design_scores_gemma":[0.0077323588,0.0017980367,0.028873045,0.0031054893,0.00021295635,0.18738884,0.0025941483,0.6106495,0.05987072,0.036229365,0.05669646,0.004849066],"about_ca_topic_score_codex":0.000002180737,"about_ca_topic_score_gemma":0.000002884275,"teacher_disagreement_score":0.83710045,"about_ca_system_score_codex":0.00010422666,"about_ca_system_score_gemma":0.00050869625,"threshold_uncertainty_score":0.79070705},"labels":[],"label_agreement":null},{"id":"W4317415683","doi":"10.36724/2664-066x-2021-7-4-7-11","title":"A 36 MW, 13 B, 2.1 MS/S MULTI-BIT DS ADC IN 0.18 M DIGITAL CMOS PROCESS USING AN EFFICIENT TOP-DOWN DESIGN METHODOLOGY","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"CMC Microsystems","keywords":"CMOS; Block (permutation group theory); Capacitor; Dynamic range; Switched capacitor; Electronic engineering; Nyquist–Shannon sampling theorem; Computer science; 12-bit; Decimation; Integrated circuit design; Nyquist rate; Electrical engineering; Engineering; Telecommunications; Mathematics; Sampling (signal processing); Bandwidth (computing); Voltage","score_opus":0.1007972913452806,"score_gpt":0.31510812647035596,"score_spread":0.21431083512507537,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W4317415683","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21226366,0.0011223154,0.7845176,0.0000044800195,0.00042113615,0.00017199095,0.000012147787,0.000108113796,0.0013785765],"genre_scores_gemma":[0.98828137,0.00005161874,0.011100331,0.000058508835,0.00033768776,0.000008376101,0.000009814567,0.00007749496,0.000074771044],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9973816,0.0003681016,0.0007242091,0.00035938402,0.00037685828,0.00078983203],"domain_scores_gemma":[0.99872583,0.00026494195,0.00013595,0.00028205803,0.00022559855,0.00036563404],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0011847852,0.00036683743,0.0005517432,0.00033845514,0.00020423088,0.00031249705,0.000336359,0.00023301048,0.00042451604],"category_scores_gemma":[0.0002991183,0.00036357954,0.00017461175,0.0005931258,0.00008204863,0.00043480753,0.00003165476,0.00085130107,0.00009549598],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00004866419,0.00018890727,0.0008417704,0.000101805024,0.00011789985,0.0014605604,0.0023652927,0.96830475,0.0184758,0.00014967122,0.00017655017,0.0077683204],"study_design_scores_gemma":[0.003745653,0.0003873528,0.001585917,0.00054173666,0.00016825394,0.011949076,0.004507234,0.94355,0.028353896,0.0030683994,0.00067761075,0.0014648712],"about_ca_topic_score_codex":0.0000206007,"about_ca_topic_score_gemma":0.000027911625,"teacher_disagreement_score":0.7760177,"about_ca_system_score_codex":0.00031086302,"about_ca_system_score_gemma":0.0005101963,"threshold_uncertainty_score":0.9998816},"labels":[],"label_agreement":null}]}