{"meta":{"query_hash":"856371b91185","filters":{"venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004."},"cohort_total":39,"direct_labels_cover":0,"predictions_cover":39,"exported":39,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/856371b91185","api":"https://metacan.xera.ac/api/v1/cohort?venue=The+2nd+Annual+IEEE+Northeast+Workshop+on+Circuits+and+Systems%2C+2004.+NEWCAS+2004."},"results":[{"id":"W1520420928","doi":"10.1109/newcas.2004.1359030","title":"A technology portable analytical model for DSM CMOS inverter short-circuit power estimation","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"CMOS; Spice; Inverter; Electronic engineering; MOSFET; Computer science; Dimension (graph theory); Semiconductor device modeling; Software portability; Power (physics); Electrical engineering; Engineering; Transistor; Mathematics; Voltage; Physics","score_opus":0.03284775881531621,"score_gpt":0.25254403906227696,"score_spread":0.21969628024696075,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1520420928","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4858617,0.004347225,0.49672133,0.0008773927,0.0024474878,0.003643804,0.00044421898,0.0014938773,0.0041629802],"genre_scores_gemma":[0.9971241,0.00006635633,0.000106499385,0.00021066952,0.00031721423,0.00029112305,0.000038001486,0.00016873275,0.0016773113],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9965251,0.0000474009,0.00097310386,0.00071188295,0.0005826802,0.0011598283],"domain_scores_gemma":[0.9982556,0.00012804805,0.0001307645,0.0009097417,0.00025362062,0.00032218924],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00067007006,0.000704194,0.00082985783,0.0004915678,0.0004422236,0.0002324762,0.0005337733,0.0005677567,0.000022538272],"category_scores_gemma":[0.00004907663,0.0005483025,0.00017243208,0.00082006596,0.00024031922,0.0005664984,0.000033358636,0.0006593408,0.0001181411],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003555619,0.00013302361,0.0002857245,0.00017548977,0.00019547292,0.000027931252,0.0013820285,0.9762327,0.00024170583,0.0046727583,0.006067192,0.010550417],"study_design_scores_gemma":[0.0015143737,0.00021746593,0.00014604347,0.00056492124,0.00016137597,0.00026659112,0.0010816957,0.99118704,0.00016725693,0.0013536558,0.0023919195,0.0009476459],"about_ca_topic_score_codex":0.000044112436,"about_ca_topic_score_gemma":0.00006564984,"teacher_disagreement_score":0.5112624,"about_ca_system_score_codex":0.0002972475,"about_ca_system_score_gemma":0.00016606683,"threshold_uncertainty_score":0.99969685},"labels":[],"label_agreement":null},{"id":"W1652701076","doi":"10.1109/newcas.2004.1359112","title":"Low-overhead asynchronous RISC microprocessor - a design experiment","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Microprocessor; Asynchronous communication; Computer science; Reduced instruction set computing; Embedded system; Overhead (engineering); Asynchronous system; Computer architecture; Instruction set; Computer hardware; Operating system; Synchronous circuit; Computer network; Telecommunications","score_opus":0.022866402537980834,"score_gpt":0.2366097314948731,"score_spread":0.21374332895689227,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1652701076","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.8253606,0.042159453,0.1141332,0.0004959817,0.0064178547,0.0043889354,0.0003185241,0.001757274,0.004968154],"genre_scores_gemma":[0.9964836,0.00048493446,0.000100269965,0.00020630602,0.0011168456,0.00025691188,0.00001654963,0.00022510263,0.0011094329],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9957996,0.00018143939,0.0010156491,0.000821161,0.0008200027,0.0013621468],"domain_scores_gemma":[0.99792284,0.00020360254,0.00021222874,0.0010044499,0.00019025925,0.00046664596],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00082338747,0.00095400854,0.00090391934,0.00028264232,0.00061210484,0.00039937653,0.0007003304,0.00039438237,0.00007592104],"category_scores_gemma":[0.000026047073,0.00071753317,0.00017182744,0.0006664207,0.000251333,0.0005392273,0.000044571425,0.0007473977,0.00075260527],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0001385618,0.0004583154,0.00010588396,0.00048887223,0.0003738666,0.00018878993,0.008563768,0.9542553,0.005680367,0.00030073416,0.015374614,0.014070938],"study_design_scores_gemma":[0.079610646,0.012238422,0.007185107,0.0409221,0.003019445,0.013564,0.11127621,0.20983377,0.2711518,0.002527657,0.20855841,0.04011241],"about_ca_topic_score_codex":0.00020763207,"about_ca_topic_score_gemma":0.00005560262,"teacher_disagreement_score":0.74442154,"about_ca_system_score_codex":0.00055265176,"about_ca_system_score_gemma":0.00021515852,"threshold_uncertainty_score":0.9995276},"labels":[],"label_agreement":null},{"id":"W1656104036","doi":"10.1109/newcas.2004.1359047","title":"An efficient, low-complexity, normalized LMS algorithm for echo cancellation","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advanced Adaptive Filtering Techniques","field":"Engineering","cited_by":20,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Echo (communications protocol); Algorithm; Computer science; Teleconference; Adaptive filter; Least mean squares filter; Filter (signal processing); Telecommunications","score_opus":0.03689725271583761,"score_gpt":0.2827494242252918,"score_spread":0.2458521715094542,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1656104036","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.14383918,0.001965124,0.84616214,0.00010074188,0.0017754281,0.0024349068,0.0009940374,0.0014530343,0.0012754397],"genre_scores_gemma":[0.9963122,0.00008563658,0.001816095,0.0000819561,0.0009781175,0.0002195099,0.00008293054,0.00015551886,0.00026805676],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9974128,0.000093680654,0.0006662418,0.0005911735,0.00042621943,0.0008098601],"domain_scores_gemma":[0.99851745,0.00013651424,0.0001791342,0.0007047915,0.0001838079,0.00027828422],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004630087,0.000579203,0.000598378,0.0001911446,0.0004797555,0.00019359212,0.00044431153,0.00023710953,0.000011729898],"category_scores_gemma":[0.000017936645,0.00047237013,0.00012842828,0.00036367602,0.00019788259,0.00030018954,0.000027801509,0.00040130236,0.00001984692],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000038996888,0.00012670559,0.000026359241,0.00016016261,0.000058462003,0.0000142254285,0.001271568,0.95345587,0.0018199821,0.0011213699,0.00040295476,0.041503374],"study_design_scores_gemma":[0.008245749,0.0011977385,0.0012736715,0.003492715,0.00023755801,0.00049900345,0.0053445343,0.94871724,0.008643145,0.003652519,0.014576137,0.0041199657],"about_ca_topic_score_codex":0.0002589176,"about_ca_topic_score_gemma":0.00014564826,"teacher_disagreement_score":0.852473,"about_ca_system_score_codex":0.00026300832,"about_ca_system_score_gemma":0.000059221224,"threshold_uncertainty_score":0.9997728},"labels":[],"label_agreement":null},{"id":"W1671315370","doi":"10.1109/newcas.2004.1359095","title":"High voltage charge pump using standard CMOS technology","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Innovative Energy Harvesting Technologies","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal; Dalsa Corporation","funders":"","keywords":"Charge pump; CMOS; Voltage; Electrical engineering; Materials science; Charge (physics); Electronic circuit; Optoelectronics; High voltage; Engineering; Physics; Capacitor","score_opus":0.02787324244440681,"score_gpt":0.24800722302892755,"score_spread":0.22013398058452074,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1671315370","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9660194,0.0036994063,0.022261752,0.0006363486,0.0024972025,0.000856092,0.0003602906,0.0025375565,0.0011319709],"genre_scores_gemma":[0.9980503,0.00011562499,0.00014250638,0.000099987636,0.0006107044,0.00007481189,0.000016452728,0.00016649075,0.00072312565],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99672586,0.000073169176,0.0008504043,0.0006669159,0.00056274654,0.0011209238],"domain_scores_gemma":[0.99817365,0.00012680402,0.00023893488,0.0009870575,0.00032612527,0.0001474043],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00068594754,0.0007362217,0.00084766594,0.00060447096,0.00061167363,0.00021365116,0.0007158006,0.0006016868,0.000024151579],"category_scores_gemma":[0.00014047117,0.00057103066,0.00009899266,0.0015921885,0.00049945794,0.00033032687,0.00009214176,0.0010751688,0.000082860424],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007565818,0.00018318657,0.0011216347,0.00038228402,0.00053057197,0.00036720687,0.0015070776,0.8735798,0.009380264,0.07464388,0.0034290536,0.03479937],"study_design_scores_gemma":[0.05089211,0.006810336,0.007760247,0.039408587,0.0022300347,0.014510031,0.10609361,0.09981246,0.1840472,0.066536866,0.38615403,0.035744492],"about_ca_topic_score_codex":0.00027725092,"about_ca_topic_score_gemma":0.00007987454,"teacher_disagreement_score":0.77376735,"about_ca_system_score_codex":0.00044407378,"about_ca_system_score_gemma":0.000116295625,"threshold_uncertainty_score":0.99967414},"labels":[],"label_agreement":null},{"id":"W1677029478","doi":"10.1109/newcas.2004.1359034","title":"Q-factor estimation of fabricated MEMS parallel-plate variable capacitors in MUMPs","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advanced MEMS and NEMS Technologies","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Dalhousie University","funders":"","keywords":"Capacitor; Capacitance; Microelectromechanical systems; Variable capacitor; Variable (mathematics); Quality (philosophy); Q factor; Relation (database); Electronic engineering; Computer science; Materials science; Electrical engineering; Optoelectronics; Engineering; Physics; Voltage; Mathematics","score_opus":0.02322253326729424,"score_gpt":0.24248898716207937,"score_spread":0.21926645389478513,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1677029478","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9767426,0.0035430307,0.01587377,0.00012355778,0.0010936388,0.000843061,0.00016521938,0.00050776073,0.0011073233],"genre_scores_gemma":[0.99887353,0.00034118327,0.00021805693,0.00002261419,0.00014626975,0.000064274696,0.000015407813,0.00006783559,0.00025081114],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9978781,0.00003171683,0.00075086585,0.0003870407,0.0003444546,0.00060782285],"domain_scores_gemma":[0.9989104,0.00015944123,0.00018806981,0.00052344764,0.00009247774,0.00012616525],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00030400173,0.0004335137,0.0006348344,0.000268673,0.00015655335,0.00006248515,0.00031569126,0.00032515658,0.0000120419445],"category_scores_gemma":[0.00006015561,0.00032699393,0.00007160389,0.0007173993,0.00017261185,0.00032101403,0.00002354405,0.00052527804,0.000024108494],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000025727559,0.00008721949,0.00012567162,0.00015863604,0.000067386725,0.000020374231,0.0012892219,0.9812494,0.004158887,0.0014328369,0.0002461689,0.011138478],"study_design_scores_gemma":[0.072123714,0.006811885,0.06549416,0.04721853,0.0016277124,0.0041186376,0.13099745,0.3717461,0.09273311,0.10231802,0.07487234,0.029938351],"about_ca_topic_score_codex":0.0006382965,"about_ca_topic_score_gemma":0.00015241758,"teacher_disagreement_score":0.60950327,"about_ca_system_score_codex":0.00017873888,"about_ca_system_score_gemma":0.00005134618,"threshold_uncertainty_score":0.9999182},"labels":[],"label_agreement":null},{"id":"W1783434861","doi":"10.1109/newcas.2004.1359114","title":"A tool for automatic watermarking of IP designs","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advanced Steganography and Watermarking Techniques","field":"Computer Science","cited_by":7,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Digital watermarking; Computer science; Watermark; Reuse; Block (permutation group theory); Intellectual property; Process (computing); Set (abstract data type); Embedded system; Computer engineering; Computer security; Software engineering; Programming language; Engineering; Operating system; Embedding; Artificial intelligence","score_opus":0.04211683829480876,"score_gpt":0.27895649021276525,"score_spread":0.2368396519179565,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1783434861","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.21842517,0.0018316186,0.77454615,0.0007308968,0.0011131387,0.002138425,0.000104157494,0.0006315559,0.0004788869],"genre_scores_gemma":[0.99682313,0.000048449747,0.0021158904,0.00025043532,0.0002668477,0.00018329403,0.000006257921,0.000044481767,0.00026120557],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99704546,0.00020120117,0.0008538292,0.0006477254,0.0005010928,0.00075066654],"domain_scores_gemma":[0.997818,0.00038863232,0.00042016472,0.00097675,0.00023736592,0.00015910082],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0011273611,0.00046289235,0.0006484398,0.00026862713,0.00057082024,0.0002572453,0.0010628994,0.00019830964,0.0000021369522],"category_scores_gemma":[0.000043010594,0.00031584047,0.00022920397,0.00055680226,0.0002132722,0.0004604338,0.000087205255,0.00029057873,0.000006088584],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00036659322,0.0016374012,0.0026272184,0.0026726564,0.0009414176,0.00025505567,0.03700626,0.12458395,0.0044992305,0.11564932,0.0054588257,0.7043021],"study_design_scores_gemma":[0.04651665,0.015162619,0.026166199,0.05632238,0.0020048772,0.008604242,0.021100791,0.32778633,0.06407089,0.311696,0.096746154,0.023822874],"about_ca_topic_score_codex":0.00011461942,"about_ca_topic_score_gemma":0.000015039451,"teacher_disagreement_score":0.778398,"about_ca_system_score_codex":0.00008202303,"about_ca_system_score_gemma":0.00011645878,"threshold_uncertainty_score":0.99992937},"labels":[],"label_agreement":null},{"id":"W1835309263","doi":"10.1109/newcas.2004.1359089","title":"A novel gain boosting technique for design of low power narrow-band RFCMOS LNAs","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":10,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Cascode; Noise figure; Amplifier; Power gain; Electronic engineering; Boosting (machine learning); High-gain antenna; Electrical engineering; Low-noise amplifier; Negative resistance; Power consumption; Power (physics); Engineering; Computer science; Physics; CMOS; Voltage","score_opus":0.03491547597863705,"score_gpt":0.247766979857027,"score_spread":0.21285150387838997,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1835309263","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0430072,0.012544681,0.92413497,0.00027332566,0.0025109195,0.007844853,0.0009828121,0.00090544997,0.0077958163],"genre_scores_gemma":[0.9978925,0.000053389267,0.00021659177,0.000107433276,0.00042007538,0.0005734562,0.000020449233,0.00022454608,0.00049154396],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.996221,0.00017504029,0.0012348848,0.0006904148,0.0005982359,0.0010803974],"domain_scores_gemma":[0.99746937,0.00063204736,0.00032754356,0.00085214275,0.00040729743,0.0003116057],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0015541957,0.00080560945,0.0009812472,0.0003345837,0.00037843655,0.00017135254,0.00063505326,0.0005111825,0.00001765216],"category_scores_gemma":[0.00017704627,0.00063366664,0.00022811229,0.0007189413,0.00026644827,0.00032952084,0.000005838324,0.00071720127,0.000022248358],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000075085154,0.00019411375,0.000033889006,0.00045334056,0.000236253,0.000042241827,0.002762795,0.8283214,0.1618307,0.001392503,0.00304626,0.0016114487],"study_design_scores_gemma":[0.038041774,0.008305843,0.00095814187,0.045891933,0.0019784046,0.013145527,0.048776492,0.08306969,0.7177501,0.010692861,0.012595011,0.018794252],"about_ca_topic_score_codex":0.00021595065,"about_ca_topic_score_gemma":0.000027759617,"teacher_disagreement_score":0.9548853,"about_ca_system_score_codex":0.00037979198,"about_ca_system_score_gemma":0.00023973943,"threshold_uncertainty_score":0.99961144},"labels":[],"label_agreement":null},{"id":"W1842616663","doi":"10.1109/newcas.2004.1359015","title":"SynAbs: model reduction tool for verilog verification","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Formal Methods in Verification","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Model checking; Reduction (mathematics); Computer science; Partial order reduction; State space; Verilog; Formal verification; State (computer science); Programming language; Functional verification; Algorithm; Theoretical computer science; Computer engineering; Embedded system; Field-programmable gate array; Mathematics","score_opus":0.05677783964006631,"score_gpt":0.30082139843976896,"score_spread":0.24404355879970266,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1842616663","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06802859,0.0012596596,0.92399234,0.0009670809,0.002731713,0.0018140202,0.00009494507,0.0003352983,0.00077636],"genre_scores_gemma":[0.98900115,0.00009579155,0.008197846,0.00019100404,0.0007843918,0.00035677085,0.000024733197,0.000056349643,0.0012919308],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9968202,0.00023295218,0.00079632446,0.00089851953,0.0005921611,0.00065985497],"domain_scores_gemma":[0.99750525,0.00014321583,0.00042256928,0.0013421915,0.0004001899,0.00018658939],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017273474,0.00043192017,0.0004456685,0.00019542211,0.0007813823,0.00043089324,0.00094417884,0.0002699794,0.0000024500257],"category_scores_gemma":[0.00013312748,0.00033889254,0.00014139796,0.00059853133,0.00018446815,0.0010641487,0.000053204858,0.0003601917,0.000054451426],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00016934231,0.00039275113,0.00002973696,0.00023045829,0.000110217174,0.000007729786,0.008141961,0.69440603,0.0019261774,0.18630956,0.0034919889,0.104784034],"study_design_scores_gemma":[0.0056281122,0.0012728157,0.0014205333,0.001527453,0.00023093361,0.0013751454,0.0072139287,0.9386115,0.0028345261,0.021508139,0.015297654,0.0030792498],"about_ca_topic_score_codex":0.000085834145,"about_ca_topic_score_gemma":0.0000065902,"teacher_disagreement_score":0.9209726,"about_ca_system_score_codex":0.00028252747,"about_ca_system_score_gemma":0.00022411066,"threshold_uncertainty_score":0.9999063},"labels":[],"label_agreement":null},{"id":"W1850516958","doi":"10.1109/newcas.2004.1359002","title":"Technology portable delay model for DSM CMOS inverters","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"CMOS; Inverter; Semiconductor device modeling; Range (aeronautics); Electronic engineering; Computer science; Electrical engineering; Engineering; Voltage","score_opus":0.02465329950880999,"score_gpt":0.23402607301570724,"score_spread":0.20937277350689726,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1850516958","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.66753924,0.014220139,0.29966637,0.0015331466,0.0051443223,0.0048255073,0.0007263032,0.0023265905,0.0040183817],"genre_scores_gemma":[0.9959108,0.00022821985,0.00012795882,0.0002940964,0.0004972474,0.00033101562,0.000027492795,0.00018754389,0.0023955812],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9967637,0.000044561246,0.0008486663,0.0006565481,0.0004727482,0.0012137432],"domain_scores_gemma":[0.99830943,0.00011485668,0.00016965152,0.0008945798,0.00020963604,0.00030184255],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00059547945,0.0006953101,0.0007733595,0.000421323,0.0005125252,0.00018013027,0.0006234664,0.0005093568,0.000011742125],"category_scores_gemma":[0.000028101553,0.0005364404,0.00015400222,0.00074142235,0.00022707552,0.00047268343,0.000034759287,0.0006265312,0.00011600717],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000037832273,0.00009249481,0.00019739056,0.00020721175,0.000178508,0.000033139084,0.0017046661,0.9724088,0.00043368732,0.0017881901,0.010433782,0.012484341],"study_design_scores_gemma":[0.0052420744,0.00047516462,0.00011759998,0.0014528203,0.00027205964,0.0007488368,0.004923118,0.9614398,0.0009453538,0.0019774686,0.020074109,0.002331616],"about_ca_topic_score_codex":0.00010082976,"about_ca_topic_score_gemma":0.00015243705,"teacher_disagreement_score":0.3283716,"about_ca_system_score_codex":0.000281286,"about_ca_system_score_gemma":0.00016148703,"threshold_uncertainty_score":0.9997087},"labels":[],"label_agreement":null},{"id":"W1860659301","doi":"10.1109/newcas.2004.1359074","title":"A high speed 512-bit modular multiplier for a RSA chip","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Cryptography and Residue Arithmetic","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Modular exponentiation; Computer science; Encryption; Arithmetic; Multiplier (economics); Modular design; Chip; Modular arithmetic; Binary number; Parallel computing; Exponentiation; Cryptography; Computer hardware; Algorithm; Public-key cryptography; Mathematics","score_opus":0.02642108040271294,"score_gpt":0.2502967153229758,"score_spread":0.22387563492026288,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1860659301","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.70155174,0.011269274,0.2693599,0.0054871733,0.0054339045,0.00466734,0.00040547,0.00075447164,0.001070768],"genre_scores_gemma":[0.9962607,0.000099167606,0.00055237423,0.0005840703,0.0010905641,0.00011495396,0.000016188009,0.00007009294,0.0012119063],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9959364,0.00021133966,0.00082312047,0.0011340141,0.00076595787,0.0011291837],"domain_scores_gemma":[0.99717593,0.00039596367,0.0003299021,0.0013529038,0.00030182782,0.00044348525],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0010108721,0.0006632489,0.0007834823,0.0003423748,0.001001154,0.00061303197,0.0012738965,0.00031769965,0.000008484159],"category_scores_gemma":[0.00006237559,0.00045881936,0.00034888138,0.0009878412,0.00028969249,0.00048735863,0.000111775764,0.0005291807,0.00007439879],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005170312,0.0028071345,0.0014785844,0.00090529805,0.0013976156,0.00053101464,0.024865342,0.5829934,0.0023746707,0.20438372,0.010302497,0.16744372],"study_design_scores_gemma":[0.11234773,0.012540105,0.071042426,0.019382313,0.0027627228,0.010529244,0.042397223,0.29884368,0.0064413333,0.14365825,0.2519981,0.02805685],"about_ca_topic_score_codex":0.00065484404,"about_ca_topic_score_gemma":0.00016972945,"teacher_disagreement_score":0.29470897,"about_ca_system_score_codex":0.00010169968,"about_ca_system_score_gemma":0.00017557551,"threshold_uncertainty_score":0.9997864},"labels":[],"label_agreement":null},{"id":"W1864353221","doi":"10.1109/newcas.2004.1359104","title":"Built-in self-test design of motion estimation computing array","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":12,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"Harbin Institute of Technology","keywords":"Verilog; VHDL; Computer science; Field-programmable gate array; Encoder; Hardware description language; Motion estimation; Reliability (semiconductor); Embedded system; Computer architecture; Coding (social sciences); Built-in self-test; Logic simulation; Logic synthesis; Computer hardware; Computer engineering; Logic gate; Algorithm","score_opus":0.036977770844582855,"score_gpt":0.2645118536684934,"score_spread":0.22753408282391052,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1864353221","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.10105906,0.0010548227,0.8953428,0.00041011794,0.00065567024,0.0007819375,0.000016664162,0.00026733402,0.00041159318],"genre_scores_gemma":[0.9986891,0.000030754545,0.00070243265,0.00011945935,0.00030994718,0.000017631768,0.0000059060444,0.00003648625,0.00008829531],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99659693,0.00033801503,0.0009851286,0.0007224877,0.0006437621,0.00071367656],"domain_scores_gemma":[0.99747646,0.0008107532,0.00052710285,0.00074150687,0.00024796734,0.00019620231],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017933137,0.0004345821,0.0006044411,0.0003074703,0.0004507904,0.00028566265,0.0008328013,0.00019235676,0.0000021280105],"category_scores_gemma":[0.00020162006,0.00034256038,0.00010240285,0.0010446629,0.000114810275,0.0005931386,0.0000548182,0.00044598785,0.00003220806],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000032157013,0.00047040798,0.0034884312,0.00016778651,0.000043619395,0.000054646523,0.006295895,0.85334194,0.00082532124,0.0032018938,0.00013053913,0.13197629],"study_design_scores_gemma":[0.0048923385,0.0009666912,0.019192003,0.00569135,0.00012347776,0.0012100891,0.0044573005,0.95676553,0.0010312183,0.0033862342,0.00023012524,0.0020536159],"about_ca_topic_score_codex":0.00048624686,"about_ca_topic_score_gemma":0.0000651905,"teacher_disagreement_score":0.89763004,"about_ca_system_score_codex":0.00017721432,"about_ca_system_score_gemma":0.00019227937,"threshold_uncertainty_score":0.99990267},"labels":[],"label_agreement":null},{"id":"W1881977259","doi":"10.1109/newcas.2004.1359098","title":"Characterization of stress induced defects in deep sub-micron MOSFETS","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Semiconductor materials and devices","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Materials science; Optoelectronics; Characterization (materials science); Parasitic extraction; Channel (broadcasting); CMOS; Gate oxide; Stress (linguistics); Breakdown voltage; MOSFET; Threshold voltage; Voltage; Electrical engineering; Metal gate; Power MOSFET; Logic gate; Electronic engineering; Transistor; Engineering; Nanotechnology","score_opus":0.021378867755769474,"score_gpt":0.22976082959279026,"score_spread":0.2083819618370208,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1881977259","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.995287,0.0019046307,0.00015505447,0.000039847866,0.0014443739,0.0006068717,0.00016968974,0.0001243167,0.0002682367],"genre_scores_gemma":[0.9991145,0.00022857888,0.0000015625213,0.00005249359,0.00040107532,0.000037929396,0.00005304755,0.00007273333,0.00003808411],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99800044,0.000115262614,0.0007099049,0.0003619477,0.00031207793,0.00050038664],"domain_scores_gemma":[0.99908423,0.000081250924,0.0001887597,0.00040482337,0.000102836,0.00013808633],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00035147555,0.00039669656,0.0005837224,0.0002026669,0.00011037923,0.00012544119,0.0002532414,0.00025079213,0.000014299187],"category_scores_gemma":[0.000017863273,0.0003100353,0.000068635614,0.0003925602,0.00006542286,0.00030487,0.000021328935,0.00027314934,0.000025884694],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000063462554,0.00021508375,0.0031272694,0.00072171143,0.00010574279,0.000042688098,0.0056147263,0.115894385,0.8676739,0.00035414615,0.000052566586,0.006134324],"study_design_scores_gemma":[0.014815468,0.001165551,0.17064461,0.015424822,0.00045152497,0.00071062555,0.022902366,0.011051508,0.75326043,0.0006012123,0.0027189637,0.006252914],"about_ca_topic_score_codex":0.00036743795,"about_ca_topic_score_gemma":0.0005101305,"teacher_disagreement_score":0.16751733,"about_ca_system_score_codex":0.000109448796,"about_ca_system_score_gemma":0.00004614485,"threshold_uncertainty_score":0.99993515},"labels":[],"label_agreement":null},{"id":"W1890393032","doi":"10.1109/newcas.2004.1359111","title":"A fast adaptive heuristic for FPGA placement","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Guelph","funders":"","keywords":"Field-programmable gate array; Computer science; Simulated annealing; Heuristic; Computation; Routing (electronic design automation); Placement; Compiler; Compile time; Parallel computing; Convergence (economics); Embedded system; Computer engineering; Algorithm; Physical design; Artificial intelligence; Circuit design","score_opus":0.033041792017859124,"score_gpt":0.2513717674783745,"score_spread":0.21832997546051536,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1890393032","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13727434,0.025951393,0.79801995,0.00093466975,0.005765771,0.010171524,0.0023575777,0.0035053436,0.016019434],"genre_scores_gemma":[0.99655867,0.00019462692,0.00008661805,0.00016260987,0.00089335005,0.0004181162,0.00002762846,0.00013419533,0.0015241926],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99741685,0.0000895297,0.0006779446,0.0005338523,0.00044277133,0.0008390397],"domain_scores_gemma":[0.9985884,0.00024674152,0.0001384217,0.0005663969,0.00017672463,0.00028331732],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00057652453,0.0005967291,0.00063892745,0.00018543913,0.00042340826,0.00019247872,0.00037547344,0.00026357247,0.000016712092],"category_scores_gemma":[0.00002983054,0.00044874498,0.00016612907,0.00032235103,0.00014245923,0.0002005595,0.000025199954,0.00043793352,0.00006543215],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003056313,0.00047982202,0.00009406762,0.0007452911,0.00066779007,0.00012446869,0.009412989,0.8551292,0.0007451864,0.0070708706,0.04494499,0.08027971],"study_design_scores_gemma":[0.056610808,0.017622873,0.003909463,0.03016131,0.003716472,0.0058059883,0.17568752,0.27120775,0.014070414,0.02194221,0.371578,0.027687168],"about_ca_topic_score_codex":0.00012257554,"about_ca_topic_score_gemma":0.00008670638,"teacher_disagreement_score":0.85928434,"about_ca_system_score_codex":0.0002464924,"about_ca_system_score_gemma":0.00007713465,"threshold_uncertainty_score":0.99979645},"labels":[],"label_agreement":null},{"id":"W1890580590","doi":"10.1109/newcas.2004.1359009","title":"New VLSI design of a max-log-MAP decoder","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advanced Wireless Communication Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Very-large-scale integration; Computer science; Soft-decision decoder; Application-specific integrated circuit; Pipeline (software); Decoding methods; Transmission (telecommunications); Algorithm; Parallel computing; Computer hardware; Embedded system; Telecommunications","score_opus":0.03526731413074038,"score_gpt":0.2647236799502228,"score_spread":0.2294563658194824,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1890580590","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.019589212,0.018434213,0.9551655,0.00059794326,0.001019357,0.0018121975,0.000121960475,0.0011109051,0.0021487195],"genre_scores_gemma":[0.9958346,0.00078910124,0.0014603032,0.00010557598,0.000322587,0.000088984125,0.000012463546,0.0001287893,0.0012575863],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99755526,0.00017480412,0.0008286395,0.00039774802,0.00045004892,0.0005935244],"domain_scores_gemma":[0.997856,0.0003098681,0.00022700206,0.001159343,0.00017932865,0.00026841633],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005393502,0.0004971452,0.00065820664,0.00021399808,0.000245278,0.00009540583,0.00071826205,0.0002666807,0.000029288796],"category_scores_gemma":[0.000035720986,0.0003934261,0.00011541164,0.00046715778,0.00017225936,0.00031500033,0.000050746934,0.0005400893,0.000062147694],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00003736153,0.000096611264,0.0000784875,0.00016527195,0.00012942687,0.000015682757,0.0020988192,0.93759286,0.0010048511,0.0025543086,0.0073176436,0.048908655],"study_design_scores_gemma":[0.044514578,0.0059786206,0.0068091857,0.042165674,0.0022284791,0.0049644164,0.065400384,0.24500282,0.071901776,0.05747413,0.42630127,0.027258666],"about_ca_topic_score_codex":0.0002435905,"about_ca_topic_score_gemma":0.00008072959,"teacher_disagreement_score":0.9762454,"about_ca_system_score_codex":0.0001690323,"about_ca_system_score_gemma":0.00012459433,"threshold_uncertainty_score":0.99985176},"labels":[],"label_agreement":null},{"id":"W1908083067","doi":"10.1109/newcas.2004.1359086","title":"A precision CMOS analog cubing circuit","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":14,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"CMOS; Centroid; Computer science; Voltage; Power (physics); Electronic circuit; Electronic engineering; Electrical engineering; Engineering; Physics","score_opus":0.030716310601193564,"score_gpt":0.23959075584210396,"score_spread":0.2088744452409104,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1908083067","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.4932736,0.053808734,0.38985026,0.00032510303,0.008515814,0.0048733875,0.0007599849,0.0028065625,0.045786586],"genre_scores_gemma":[0.9958844,0.00042370372,0.0000039179567,0.00025646386,0.0012835357,0.00010029222,0.000032675107,0.0001778399,0.0018371531],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99567086,0.00024890946,0.0010629625,0.00085395685,0.00089474506,0.001268588],"domain_scores_gemma":[0.99767864,0.00037786298,0.00021474181,0.00095068105,0.00022706525,0.000551025],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0011441861,0.0008569702,0.0009563396,0.0003581556,0.00074075354,0.00035866373,0.0006766572,0.00045441661,0.000057582518],"category_scores_gemma":[0.00006876027,0.0006557082,0.00027363223,0.0008538025,0.00023423329,0.0004459399,0.000036693655,0.0009683539,0.00038328397],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008847652,0.0003717785,0.0006244408,0.0004724596,0.0006547835,0.00046495494,0.007555122,0.8225047,0.0021015287,0.021054007,0.016850697,0.12725705],"study_design_scores_gemma":[0.06507583,0.009010616,0.031218603,0.04840244,0.0060303197,0.024256684,0.12745692,0.071193814,0.0072059957,0.107369676,0.45930263,0.043476455],"about_ca_topic_score_codex":0.00033866125,"about_ca_topic_score_gemma":0.00016110475,"teacher_disagreement_score":0.7513109,"about_ca_system_score_codex":0.0003317788,"about_ca_system_score_gemma":0.00014560885,"threshold_uncertainty_score":0.99958944},"labels":[],"label_agreement":null},{"id":"W1912648079","doi":"10.1109/newcas.2004.1359046","title":"A worst-case circuit delay verification technique considerino power grid voltage variations","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"","keywords":"Static timing analysis; Computer science; Benchmark (surveying); Delay calculation; Very-large-scale integration; Logic gate; Process (computing); Power (physics); Electronic engineering; Circuit extraction; Physical design; Asynchronous circuit; Circuit design; Electronic circuit; Voltage; Propagation delay; Equivalent circuit; Algorithm; Electrical engineering; Synchronous circuit; Engineering; Embedded system; Clock signal","score_opus":0.0241833421204715,"score_gpt":0.23210419303665142,"score_spread":0.20792085091617993,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1912648079","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.47779262,0.008554286,0.48114464,0.0007841221,0.009299844,0.007470767,0.0012938909,0.0031730135,0.010486836],"genre_scores_gemma":[0.99761415,0.000120008226,0.00006887022,0.00017628398,0.0007661076,0.00044467777,0.00004258446,0.00017849836,0.0005888407],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.996472,0.00014564396,0.0010524857,0.0007342375,0.00061115535,0.0009844569],"domain_scores_gemma":[0.9976158,0.00026157458,0.00024506683,0.0011986217,0.00028122184,0.00039772305],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0009846273,0.0007579749,0.00069420453,0.00039757203,0.000744202,0.00035780435,0.00046000187,0.00045617484,0.000066194276],"category_scores_gemma":[0.00005788885,0.0006227217,0.00016067424,0.00093379803,0.00023039641,0.0006328713,0.000034572913,0.0008659863,0.00030582125],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00015507615,0.0010833702,0.0010250423,0.0009365929,0.0012150533,0.003901808,0.022677427,0.8737885,0.014177155,0.034096353,0.027444089,0.019499565],"study_design_scores_gemma":[0.04901515,0.006244757,0.017877644,0.022511382,0.0043943753,0.19907591,0.081845455,0.113516875,0.019393513,0.017000414,0.43045938,0.038665153],"about_ca_topic_score_codex":0.0003005847,"about_ca_topic_score_gemma":0.00014723389,"teacher_disagreement_score":0.7602716,"about_ca_system_score_codex":0.0004046676,"about_ca_system_score_gemma":0.00018428973,"threshold_uncertainty_score":0.9996224},"labels":[],"label_agreement":null},{"id":"W1919335306","doi":"10.1109/newcas.2004.1359028","title":"Speech recognition for game control","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Speech and Audio Processing","field":"Computer Science","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université du Québec à Montréal","funders":"","keywords":"Computer science; Microcontroller; Mobile device; Embedded system; Architecture; Reduced instruction set computing; Instruction set; Computer architecture; Computer hardware; Operating system","score_opus":0.039218423085071896,"score_gpt":0.26741630572092945,"score_spread":0.22819788263585755,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1919335306","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.28989556,0.01062857,0.6764087,0.008451205,0.0052208,0.0041018897,0.0004858338,0.00089662615,0.0039107786],"genre_scores_gemma":[0.99503124,0.000072971554,0.0005533995,0.0014745885,0.0013920424,0.00011169863,0.000015723403,0.00005514642,0.001293189],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.9967931,0.00015404225,0.00068865984,0.0008516771,0.0005985439,0.0009140026],"domain_scores_gemma":[0.99780077,0.00037668948,0.00036119833,0.0007218068,0.00041366357,0.00032586974],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0010696701,0.00048496225,0.00059255434,0.00019206356,0.00061649515,0.0007383556,0.0008140229,0.00023274918,0.0000093492],"category_scores_gemma":[0.00010732684,0.0003496416,0.00017887505,0.00055675575,0.00015159707,0.000789406,0.000041444637,0.00039570386,0.00015711735],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020964726,0.0005692804,0.00033406666,0.0003435235,0.00025834513,0.00016139641,0.0042248066,0.018277414,0.0013222197,0.0021532772,0.007533065,0.96461296],"study_design_scores_gemma":[0.14387003,0.01312664,0.012908473,0.033633035,0.0024809747,0.022951087,0.045290597,0.0780663,0.067578465,0.17458925,0.37711236,0.028392792],"about_ca_topic_score_codex":0.00011890424,"about_ca_topic_score_gemma":0.00007510103,"teacher_disagreement_score":0.93622017,"about_ca_system_score_codex":0.000108285254,"about_ca_system_score_gemma":0.00022387036,"threshold_uncertainty_score":0.9998956},"labels":[],"label_agreement":null},{"id":"W1923175529","doi":"10.1109/newcas.2004.1359103","title":"Towards software model checking using MDGs","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Formal Methods in Verification","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Model checking; Programming language; Java; Software engineering; Software; Schema (genetic algorithms); Metamodeling; Theoretical computer science; Machine learning","score_opus":0.08429744369017628,"score_gpt":0.31436829529378046,"score_spread":0.2300708516036042,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1923175529","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.084429905,0.00236913,0.9085743,0.00039522166,0.002197662,0.0007504017,0.000052344763,0.00037966183,0.0008513757],"genre_scores_gemma":[0.97115684,0.00007788777,0.02642333,0.0005535729,0.0008638769,0.00005490846,0.0000068084,0.000082888444,0.0007799086],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99602824,0.00030819708,0.0008684666,0.0009358667,0.0009354151,0.0009237947],"domain_scores_gemma":[0.9972456,0.00012959645,0.00044365882,0.0013945531,0.0004574455,0.00032911138],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017971497,0.0005617867,0.0006019944,0.00024165018,0.00089283497,0.00061086897,0.0013882805,0.00029933103,0.0000045863526],"category_scores_gemma":[0.00020158834,0.00042455562,0.00016216408,0.00086612906,0.00022256226,0.0010962756,0.00016297067,0.00062653417,0.0000501768],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000275601,0.00017466072,0.00015306594,0.0001262052,0.000072662624,0.000034520817,0.006476995,0.8776554,0.00024497366,0.026748898,0.00044606786,0.08783899],"study_design_scores_gemma":[0.0024538648,0.00031559987,0.0009506414,0.0020687692,0.00012665895,0.0010336117,0.0033674052,0.97573936,0.0007452846,0.0074076406,0.0036358961,0.002155269],"about_ca_topic_score_codex":0.00041980363,"about_ca_topic_score_gemma":0.00003066791,"teacher_disagreement_score":0.8867269,"about_ca_system_score_codex":0.00033710685,"about_ca_system_score_gemma":0.00039165764,"threshold_uncertainty_score":0.99982065},"labels":[],"label_agreement":null},{"id":"W1933168821","doi":"10.1109/newcas.2004.1359093","title":"Circuit simulation of S-parameter based interconnects via passive macromodels","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Electromagnetic Compatibility and Noise Suppression","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Passivity; Computer science; Compensation (psychology); Algorithm; Electronic engineering; Engineering; Electrical engineering","score_opus":0.02564126696578464,"score_gpt":0.24615092472130906,"score_spread":0.22050965775552442,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1933168821","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9516205,0.0017279903,0.043814603,0.00013587477,0.00079398,0.0008983625,0.00011421056,0.00020649146,0.00068794907],"genre_scores_gemma":[0.99932915,0.000024169285,0.000016130636,0.00009530969,0.00025607293,0.0000460292,0.000024264915,0.000072168834,0.0001367025],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9974081,0.00019654723,0.00080507813,0.0004953409,0.00049615785,0.00059878227],"domain_scores_gemma":[0.9980188,0.00066845765,0.00018767387,0.00070526067,0.00020415043,0.0002156809],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00039798013,0.0004792102,0.00064554263,0.00020342765,0.00021901492,0.00009235801,0.00033010403,0.00026108607,0.00005710271],"category_scores_gemma":[0.00006395668,0.00036675733,0.00016489146,0.0004033223,0.00016006283,0.0002412195,0.00002417619,0.00047972295,0.000030084746],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0000561836,0.00014573602,0.00009249379,0.00023702178,0.000073967814,0.000015988591,0.0015379005,0.9771804,0.0027489136,0.00018254262,0.00019162285,0.017537184],"study_design_scores_gemma":[0.004018145,0.0010185551,0.0014212931,0.0030582512,0.00021887734,0.00012765406,0.0013801192,0.9766213,0.0069851824,0.0028339261,0.0008768619,0.0014397792],"about_ca_topic_score_codex":0.00021051416,"about_ca_topic_score_gemma":0.00013373078,"teacher_disagreement_score":0.047708612,"about_ca_system_score_codex":0.00014735828,"about_ca_system_score_gemma":0.00007128966,"threshold_uncertainty_score":0.99987847},"labels":[],"label_agreement":null},{"id":"W1942862422","doi":"10.1109/newcas.2004.1359051","title":"An embedded DRAM for MDLNS FIR filter","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Digital Filter Design and Implementation","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Dram; CAS latency; Universal memory; Computer science; Capacitance; Capacitor; Electronic engineering; Electrical engineering; Filter (signal processing); Embedded system; Static random-access memory; Dynamic random-access memory; Voltage; Computer hardware; Engineering; Memory controller; Semiconductor memory; Computer memory; Physics; Memory refresh","score_opus":0.052171064421662826,"score_gpt":0.3038007150743288,"score_spread":0.251629650652666,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1942862422","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.19042552,0.001587638,0.7900326,0.0030455082,0.003992708,0.004286586,0.00076270226,0.0007665446,0.0051001837],"genre_scores_gemma":[0.99513334,0.000020466467,0.00033936338,0.0012143498,0.0007742554,0.00017091981,0.000063578904,0.000055416953,0.0022283192],"study_design_codex":"design_other","study_design_gemma":"not_applicable","domain_scores_codex":[0.99681664,0.00017276143,0.0007157381,0.0008572553,0.0005889139,0.00084868335],"domain_scores_gemma":[0.9977996,0.00023036588,0.00026639592,0.0010637644,0.00026161672,0.00037826304],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.0007331147,0.0004840293,0.00047671085,0.00018282005,0.0006029244,0.0012205817,0.0010661669,0.00016027506,0.0000145563],"category_scores_gemma":[0.000032126503,0.0003517877,0.00015730124,0.0004670536,0.00012300027,0.0015509218,0.00005733978,0.00024598103,0.00009015164],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00040438608,0.0027092018,0.0007554885,0.0005965862,0.0006458415,0.00020330375,0.038906563,0.093762316,0.0033355725,0.14999014,0.08453899,0.6241516],"study_design_scores_gemma":[0.0592067,0.022762429,0.018794507,0.008026741,0.001029548,0.005178299,0.07350421,0.23553894,0.008194024,0.08588489,0.46208525,0.01979445],"about_ca_topic_score_codex":0.00014966929,"about_ca_topic_score_gemma":0.00008746617,"teacher_disagreement_score":0.8047078,"about_ca_system_score_codex":0.00011440995,"about_ca_system_score_gemma":0.00016590355,"threshold_uncertainty_score":0.9998934},"labels":[],"label_agreement":null},{"id":"W1944977865","doi":"10.1109/newcas.2004.1359059","title":"A novel technique to enhance the open loop gain of CMOS folded cascode OTA","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Dalhousie University","funders":"","keywords":"Phase margin; Cascode; CMOS; Operational transconductance amplifier; Transconductance; Open-loop gain; Operational amplifier; Amplifier; Biasing; Electronic engineering; Automatic gain control; Electrical engineering; Physics; Voltage; Transistor; Engineering","score_opus":0.03316195073960377,"score_gpt":0.2784224050697654,"score_spread":0.24526045433016164,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1944977865","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.070284165,0.0076554636,0.9022023,0.0005308418,0.0014631017,0.0067670397,0.00064545084,0.00045949206,0.009992138],"genre_scores_gemma":[0.9961904,0.00010879784,0.000028631115,0.00041425606,0.00043882942,0.00042211975,0.000011259991,0.00012753042,0.0022581315],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9967468,0.00019698686,0.0009511932,0.0006429714,0.0005888038,0.0008732836],"domain_scores_gemma":[0.99778974,0.00031721476,0.00022723261,0.0010867391,0.00023912637,0.00033996426],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0015438247,0.0006332313,0.000872085,0.0001867057,0.0004516886,0.00026340995,0.0013580647,0.00029032855,0.00002312298],"category_scores_gemma":[0.0000700426,0.00041794643,0.00017007839,0.0008500896,0.00021105986,0.00032231206,0.000092961236,0.00065189204,0.00007543826],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00021574466,0.0006925472,0.000106093416,0.00065844535,0.0007932975,0.00016303931,0.011488562,0.8203872,0.061914664,0.027989456,0.019448001,0.05614295],"study_design_scores_gemma":[0.04412654,0.012831514,0.0060538226,0.07006159,0.0051760767,0.020052504,0.164659,0.03332549,0.2915514,0.035001907,0.27947688,0.03768328],"about_ca_topic_score_codex":0.0016430308,"about_ca_topic_score_gemma":0.00073989935,"teacher_disagreement_score":0.9259063,"about_ca_system_score_codex":0.00020107969,"about_ca_system_score_gemma":0.00017707687,"threshold_uncertainty_score":0.99982727},"labels":[],"label_agreement":null},{"id":"W1946142907","doi":"10.1109/newcas.2004.1359056","title":"Asynchronous ADC/microprocessor interface","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Interfacing; Asynchronous communication; Microprocessor; Interface (matter); Computer science; Chip; Embedded system; Computer hardware; Sampling (signal processing); Front and back ends; Operating system; Telecommunications; Detector","score_opus":0.020662347490645494,"score_gpt":0.23842915230089848,"score_spread":0.21776680481025298,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1946142907","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.45357242,0.076507054,0.4357272,0.0004034899,0.0061692945,0.0029518188,0.0006065408,0.0020931412,0.021969026],"genre_scores_gemma":[0.99631935,0.00038246537,0.000005922166,0.00022944015,0.0010440163,0.00007834969,0.000017377395,0.00016414259,0.0017589198],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99668926,0.00015124795,0.0008264053,0.00068987394,0.0005589506,0.0010842513],"domain_scores_gemma":[0.9982917,0.00019455241,0.0001718044,0.00071451865,0.00020367834,0.000423747],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006800383,0.0007595986,0.0007957018,0.00021669533,0.00051983027,0.00030023034,0.0006074453,0.00037218828,0.00005474642],"category_scores_gemma":[0.00003666377,0.00057396205,0.00018312843,0.0005434113,0.00025891518,0.00032862453,0.000031266827,0.0008697717,0.0004918809],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009652023,0.00035234555,0.00019103225,0.0007019259,0.000615914,0.00028033234,0.008449613,0.8900485,0.003068232,0.00791486,0.016824875,0.07145586],"study_design_scores_gemma":[0.056774564,0.00954614,0.008032786,0.03784167,0.004671415,0.025118941,0.19201069,0.037823655,0.03254428,0.03405618,0.5224983,0.039081387],"about_ca_topic_score_codex":0.0002944313,"about_ca_topic_score_gemma":0.00017528232,"teacher_disagreement_score":0.8522248,"about_ca_system_score_codex":0.00029383507,"about_ca_system_score_gemma":0.00014395764,"threshold_uncertainty_score":0.99967116},"labels":[],"label_agreement":null},{"id":"W2097232115","doi":"10.1109/newcas.2004.1359116","title":"Carry free, bit parallel approximate squarers with linear complexity and constant delay","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Parameterized complexity; Constant (computer programming); Function (biology); Boolean function; Bit (key); Computer science; Simple (philosophy); Algorithm; Mathematics; Lookup table; Arithmetic","score_opus":0.04791621092080614,"score_gpt":0.2789545173268937,"score_spread":0.23103830640608755,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2097232115","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.08656843,0.0066705695,0.89711213,0.0037354943,0.0013035599,0.0017713277,0.00032791216,0.00045203653,0.0020585451],"genre_scores_gemma":[0.9805051,0.00022469627,0.016943092,0.00092871103,0.0006479557,0.000089991314,0.000011038277,0.00008414334,0.00056528964],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9961339,0.0004007454,0.0007032584,0.0010414058,0.0007715645,0.0009490998],"domain_scores_gemma":[0.9973027,0.0003503959,0.0003353701,0.0012025856,0.00024601552,0.0005629022],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0010520173,0.0006310709,0.0008496477,0.00015311503,0.00079863204,0.00047990697,0.000981874,0.00019536428,0.0000064730784],"category_scores_gemma":[0.000046797762,0.00038888695,0.000109970904,0.0007415326,0.0007705793,0.00045473452,0.00017114369,0.00062315044,0.000020155161],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00083037926,0.0024552974,0.004852893,0.0012079021,0.0014344611,0.0024164089,0.025229191,0.20331292,0.00034343707,0.36794704,0.0052168537,0.38475323],"study_design_scores_gemma":[0.064077586,0.014303264,0.015827488,0.015026317,0.0013824058,0.025800405,0.062761866,0.57150733,0.00053032715,0.11673041,0.09066595,0.02138667],"about_ca_topic_score_codex":0.00091210235,"about_ca_topic_score_gemma":0.00013967938,"teacher_disagreement_score":0.89393663,"about_ca_system_score_codex":0.000092778806,"about_ca_system_score_gemma":0.00018128207,"threshold_uncertainty_score":0.9998563},"labels":[],"label_agreement":null},{"id":"W2097670457","doi":"10.1109/newcas.2004.1359023","title":"Automatic synthesis from high level ASM to VHDL: a case study","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Montréal","funders":"","keywords":"Computer science; High-level synthesis; VHDL; Programming language; Computer architecture; Embedded system; Field-programmable gate array","score_opus":0.06198810978827832,"score_gpt":0.2907050788340988,"score_spread":0.22871696904582048,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2097670457","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9140014,0.0011676998,0.07598232,0.0010843927,0.0017974993,0.0039216713,0.0002987695,0.001278192,0.0004680328],"genre_scores_gemma":[0.99652076,0.000011911462,0.0008265312,0.00042586873,0.00073557487,0.0006351669,0.0000038294024,0.000115074865,0.0007252913],"study_design_codex":"design_other","study_design_gemma":"qualitative","domain_scores_codex":[0.99327976,0.0011161919,0.0014864776,0.001607307,0.0013545323,0.0011557115],"domain_scores_gemma":[0.9945406,0.0011748559,0.0005155049,0.0027014595,0.00037800134,0.00068961194],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.002194851,0.00094232545,0.0013030604,0.0004924929,0.0009316431,0.0010262466,0.0020024632,0.00034578633,0.000020371517],"category_scores_gemma":[0.00019041746,0.00068854296,0.00020185346,0.001299894,0.00014821951,0.00074912905,0.00025975212,0.000658771,0.00030912744],"study_design_candidate":"qualitative","study_design_consensus":null,"about_ca_topic_candidate":true,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002200916,0.009083553,0.00472294,0.0010124907,0.003292524,0.048607733,0.23227607,0.07311925,0.0017118211,0.023428917,0.046780758,0.5557439],"study_design_scores_gemma":[0.035809454,0.01883362,0.03422957,0.043451693,0.00396705,0.12612036,0.55667186,0.09817822,0.0089096455,0.021697672,0.016789488,0.035341367],"about_ca_topic_score_codex":0.017381152,"about_ca_topic_score_gemma":0.0019016906,"teacher_disagreement_score":0.5204025,"about_ca_system_score_codex":0.00040474677,"about_ca_system_score_gemma":0.00029668678,"threshold_uncertainty_score":0.9995566},"labels":[],"label_agreement":null},{"id":"W2100260603","doi":"10.1109/newcas.2004.1359109","title":"An integrated inductorless quadrature voltage controlled oscillator design in a 47GHz SiGe process","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"dBc; Inductor; CMOS; Phase noise; Electrical engineering; Transistor; Voltage; Materials science; Quadrature (astronomy); Electronic engineering; Optoelectronics; Engineering","score_opus":0.026110023367147975,"score_gpt":0.2571441912775563,"score_spread":0.23103416791040832,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2100260603","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.92478985,0.021068988,0.03564432,0.00026440018,0.00433389,0.0073786383,0.0006004225,0.0017102502,0.0042092423],"genre_scores_gemma":[0.9978206,0.00015196732,0.000012292484,0.00019152602,0.0006931642,0.00043867016,0.000048605576,0.00024416807,0.0003990142],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9945316,0.00063806894,0.0014761353,0.0010477047,0.00089212065,0.0014144101],"domain_scores_gemma":[0.99716926,0.0004014871,0.00030192637,0.0010988413,0.0004480411,0.00058043987],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0017090846,0.0011929871,0.0016344476,0.0006161583,0.00037500166,0.00050900434,0.0009831162,0.0008384336,0.00003707862],"category_scores_gemma":[0.00015705945,0.0008404827,0.00019177447,0.0017825566,0.00028518974,0.0008114766,0.0000054583434,0.0018602728,0.00007658335],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003145553,0.00036755862,0.00033408342,0.00021532526,0.00029265555,0.00035453067,0.008167645,0.9748028,0.0062601813,0.0010473733,0.0013094306,0.0065338956],"study_design_scores_gemma":[0.15570928,0.009380738,0.009449588,0.03953058,0.002762642,0.009396322,0.29984882,0.37917158,0.0284391,0.0135509465,0.019025302,0.0337351],"about_ca_topic_score_codex":0.00067745085,"about_ca_topic_score_gemma":0.00057147787,"teacher_disagreement_score":0.5956312,"about_ca_system_score_codex":0.0007002834,"about_ca_system_score_gemma":0.00048962806,"threshold_uncertainty_score":0.9994046},"labels":[],"label_agreement":null},{"id":"W2103799265","doi":"10.1109/newcas.2004.1359003","title":"A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advancements in Semiconductor Devices and Circuit Design","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"CMOS; Logic gate; Transistor; Computer science; Electronic engineering; Topology (electrical circuits); Series (stratigraphy); Algorithm; Electrical engineering; Engineering; Voltage","score_opus":0.047390459493608386,"score_gpt":0.2655859688484093,"score_spread":0.21819550935480092,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2103799265","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.7562822,0.017860351,0.21796575,0.00026079162,0.0012709098,0.0036145423,0.00095501327,0.00097172806,0.00081870466],"genre_scores_gemma":[0.9984043,0.0005323352,0.00025716858,0.00009202919,0.00014424139,0.00020569745,0.000038495695,0.000110143534,0.00021553859],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997357,0.00005769127,0.00093021203,0.00048151115,0.0003853285,0.00078823586],"domain_scores_gemma":[0.99848217,0.00023764936,0.0002731472,0.0006475072,0.00023023265,0.00012932054],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00041540156,0.00056231016,0.000812516,0.00020276464,0.00029180822,0.000103998136,0.0005285416,0.00024891863,0.000010784584],"category_scores_gemma":[0.00003680738,0.00042810632,0.0001447773,0.00038432732,0.00027398305,0.00030492258,0.000032098247,0.00036013252,0.000013640843],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000065740605,0.000113323884,0.00010337714,0.0005966651,0.00023890563,0.000009323502,0.0023466146,0.95360386,0.007016394,0.0025588816,0.00066612614,0.032680765],"study_design_scores_gemma":[0.022400575,0.0019716334,0.0004139397,0.005856944,0.0012937655,0.0008503159,0.07386443,0.82536304,0.016498432,0.02021051,0.024436552,0.0068398463],"about_ca_topic_score_codex":0.00007741455,"about_ca_topic_score_gemma":0.000093592455,"teacher_disagreement_score":0.24212216,"about_ca_system_score_codex":0.00017716983,"about_ca_system_score_gemma":0.00006042445,"threshold_uncertainty_score":0.9998171},"labels":[],"label_agreement":null},{"id":"W2108930304","doi":"10.1109/newcas.2004.1359017","title":"Formal verification of a bus structure modeled in SystemC","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Formal Methods in Verification","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"SystemC; Computer science; Formal verification; Programming language; Debugging; Model checking; Verilog; Electronic system-level design and verification; Functional verification; Abstraction; Intelligent verification; Embedded system; Hardware description language; Code (set theory); Reduction (mathematics); Software; Software development; Software construction","score_opus":0.035279528500329616,"score_gpt":0.27794382237141607,"score_spread":0.24266429387108646,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2108930304","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.6290711,0.0029267545,0.3628887,0.00037466467,0.0018031358,0.0016827768,0.00012881572,0.00017780505,0.00094623864],"genre_scores_gemma":[0.9979474,0.000053427,0.0013992348,0.00008624158,0.00023048339,0.000063073305,0.0000109637285,0.000032984608,0.0001762056],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9964872,0.00041042583,0.0010611387,0.00066675094,0.0007140296,0.0006604484],"domain_scores_gemma":[0.99759406,0.0001422019,0.00055591506,0.0012389155,0.00029619946,0.00017271214],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0014489425,0.00040659652,0.00061354873,0.00031257598,0.00029003405,0.00019385222,0.0010767762,0.00028073628,0.0000036970828],"category_scores_gemma":[0.000081395825,0.0002996831,0.000098818884,0.001024744,0.00016186845,0.0010428483,0.000073624506,0.00046799026,0.000017316672],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00019207533,0.0004617499,0.0010378389,0.00074360747,0.00012157091,0.000039364848,0.017730989,0.70586187,0.0023134407,0.20818593,0.00022904546,0.0630825],"study_design_scores_gemma":[0.018431604,0.0025785014,0.04585485,0.010516702,0.000313812,0.003117271,0.027053786,0.8569281,0.008148957,0.015657729,0.0053977347,0.006000954],"about_ca_topic_score_codex":0.00048008797,"about_ca_topic_score_gemma":0.00013519912,"teacher_disagreement_score":0.36887628,"about_ca_system_score_codex":0.00022055898,"about_ca_system_score_gemma":0.00019900584,"threshold_uncertainty_score":0.9999455},"labels":[],"label_agreement":null},{"id":"W2109371939","doi":"10.1109/newcas.2004.1359084","title":"Cache coherence support in a split-transaction bus for prototyping of system-on-chip multiprocessors","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Queen's University","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Computer science; Cache coherence; Bus sniffing; MESI protocol; System bus; Embedded system; Cache; VHDL; Control bus; Back-side bus; Address bus; Local bus; Computer hardware; Cache algorithms; Operating system; CPU cache; Field-programmable gate array","score_opus":0.03652958269455215,"score_gpt":0.2806579422214046,"score_spread":0.24412835952685247,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2109371939","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13236505,0.0014299477,0.8574442,0.0005263633,0.0010127305,0.0051549505,0.000101454454,0.0006193148,0.0013459593],"genre_scores_gemma":[0.9980266,0.00003591176,0.0009305484,0.000110271925,0.00017269085,0.000368572,0.000008669129,0.000036568123,0.00031017806],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99708056,0.00020583611,0.00090281526,0.0007255072,0.00049748115,0.00058781885],"domain_scores_gemma":[0.9981071,0.0002867982,0.00045835256,0.0006616834,0.00032745497,0.00015861665],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00133664,0.00040441536,0.0006127867,0.00029739883,0.00034814363,0.00018380988,0.0007625878,0.00022395224,0.0000015555288],"category_scores_gemma":[0.000049785478,0.00030658089,0.00012087404,0.0007622664,0.00011679448,0.00032886735,0.000029589386,0.00036734063,0.000009612107],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0002610386,0.00061655894,0.0006287881,0.0015386175,0.00009550213,0.00003947558,0.010048765,0.9219112,0.00016751183,0.013730762,0.00037793798,0.05058386],"study_design_scores_gemma":[0.022616955,0.0066587296,0.00707575,0.033795025,0.0002748226,0.0016920327,0.020591367,0.8824855,0.007239481,0.0031697378,0.008083629,0.006316973],"about_ca_topic_score_codex":0.00043729192,"about_ca_topic_score_gemma":0.0000887216,"teacher_disagreement_score":0.86566156,"about_ca_system_score_codex":0.00017780306,"about_ca_system_score_gemma":0.00023431698,"threshold_uncertainty_score":0.9999386},"labels":[],"label_agreement":null},{"id":"W2120021615","doi":"10.1109/newcas.2004.1359071","title":"A 0.18μm CMOS fully differential tran-simpedance amplifier for optical receiver","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Transimpedance amplifier; CMOS; Bandwidth (computing); Differential amplifier; Physics; Electrical impedance; Electrical engineering; Low-noise amplifier; Electronic engineering; Optoelectronics; Amplifier; Computer science; Engineering; Telecommunications","score_opus":0.03077441961767251,"score_gpt":0.24879769167073654,"score_spread":0.21802327205306402,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2120021615","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.77150494,0.015118565,0.16686988,0.0011654682,0.010635623,0.0070596784,0.0017283246,0.0019362576,0.023981238],"genre_scores_gemma":[0.9958256,0.0001977198,0.000026123991,0.00017350404,0.0015937292,0.00036674127,0.000046718076,0.000215631,0.0015542617],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99593544,0.00013505995,0.0010389743,0.00085732905,0.00069180137,0.0013414004],"domain_scores_gemma":[0.99776876,0.00040378838,0.0001619867,0.00088971225,0.00028658868,0.0004891468],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00056410336,0.0008864791,0.0009961702,0.00022061284,0.0005010872,0.00036991903,0.0006739386,0.0005312681,0.00005711769],"category_scores_gemma":[0.00007889318,0.00066868315,0.0003089112,0.0005296171,0.00031071666,0.00036814006,0.0000064150945,0.00091296417,0.00013716589],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00050266023,0.0007948235,0.00030655126,0.0011694558,0.0015736844,0.0003161034,0.009860727,0.7891186,0.018379794,0.03495555,0.032817956,0.110204086],"study_design_scores_gemma":[0.11919465,0.014405576,0.019765459,0.03883089,0.0090305805,0.019397639,0.08166478,0.17673692,0.06293917,0.049418595,0.35776457,0.05085116],"about_ca_topic_score_codex":0.00014195453,"about_ca_topic_score_gemma":0.00012752753,"teacher_disagreement_score":0.6123817,"about_ca_system_score_codex":0.00038702122,"about_ca_system_score_gemma":0.00016158087,"threshold_uncertainty_score":0.99957645},"labels":[],"label_agreement":null},{"id":"W2129114152","doi":"10.1109/newcas.2004.1359102","title":"A user-configurable framework for testing prototype system-on-chip implementations","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Queen's University","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Embedded system; Implementation; System on a chip; Computer architecture; Software; Microprocessor; Field-programmable gate array; Multiprocessing; Operating system; Software engineering","score_opus":0.06377102180019302,"score_gpt":0.31562784459159565,"score_spread":0.25185682279140265,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2129114152","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.021382371,0.0015179408,0.9549366,0.001422729,0.002366836,0.011404808,0.00036413217,0.0017874917,0.004817056],"genre_scores_gemma":[0.99040556,0.000010955294,0.004789639,0.0004717173,0.001034747,0.0022475321,0.000014346181,0.00011741269,0.00090807315],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.994873,0.00045886662,0.0013069891,0.0012256533,0.000908605,0.0012269063],"domain_scores_gemma":[0.9949663,0.0016145363,0.00070766424,0.0016929229,0.00062817364,0.00039038554],"candidate_categories":["metaepi_narrow","sts"],"consensus_categories":[],"category_scores_codex":[0.0020974858,0.00074528245,0.00087074685,0.00034497728,0.0013912943,0.0009576975,0.0015094142,0.00037174384,0.000005741417],"category_scores_gemma":[0.00029700517,0.0005535202,0.00020648156,0.0011671006,0.0001499764,0.0006171226,0.00007973872,0.0006909528,0.00009904584],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":"theoretical_or_conceptual","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018149141,0.00064349757,0.0008535484,0.0015489224,0.00039609656,0.00014380146,0.009689036,0.036163196,0.00079847773,0.913465,0.009268236,0.026848648],"study_design_scores_gemma":[0.046619564,0.039125293,0.006567682,0.14292559,0.0021017967,0.015968831,0.15629338,0.15594064,0.01860426,0.21929117,0.16534895,0.031212855],"about_ca_topic_score_codex":0.00063223403,"about_ca_topic_score_gemma":0.000074679396,"teacher_disagreement_score":0.9690232,"about_ca_system_score_codex":0.00039635846,"about_ca_system_score_gemma":0.0003962509,"threshold_uncertainty_score":0.99990875},"labels":[],"label_agreement":null},{"id":"W2132805517","doi":"10.1109/newcas.2004.1359100","title":"Design of reconfigurable general finite field multiplier in GF[2/sup m/]","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Coding theory and cryptography","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Lethbridge","funders":"","keywords":"Multiplier (economics); Finite field; Very-large-scale integration; Computer science; Mathematics; Arithmetic; Embedded system; Discrete mathematics","score_opus":0.03683872581728505,"score_gpt":0.2530160978105393,"score_spread":0.21617737199325426,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2132805517","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.3924382,0.0060986103,0.589098,0.001740814,0.0024834233,0.002163881,0.00008147315,0.00033144894,0.0055641886],"genre_scores_gemma":[0.99806917,0.000108860506,0.00024880565,0.0004631545,0.00026517166,0.00005444703,0.000003171299,0.000029704268,0.00075754646],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99697906,0.00044276443,0.00077543507,0.0006857883,0.00042537478,0.000691599],"domain_scores_gemma":[0.99756604,0.0008468948,0.00027578138,0.0009618427,0.00015183566,0.00019757333],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0014817786,0.00041388912,0.00058722444,0.00032649533,0.00030728962,0.00021284887,0.0009833449,0.00023324545,0.000023098175],"category_scores_gemma":[0.00007886348,0.00030970693,0.0001454082,0.00093790854,0.00015435471,0.00041681927,0.000055194698,0.00048979884,0.00003581297],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00018978269,0.00044591542,0.0009895933,0.000109912115,0.000113710536,0.00009971961,0.008764726,0.9019553,0.00050954975,0.028539684,0.0012997945,0.056982335],"study_design_scores_gemma":[0.048008624,0.011995387,0.013941137,0.019287713,0.00064830336,0.0030808882,0.031560324,0.6474853,0.01476709,0.15681274,0.036551505,0.01586096],"about_ca_topic_score_codex":0.00040594043,"about_ca_topic_score_gemma":0.00007863933,"teacher_disagreement_score":0.60563093,"about_ca_system_score_codex":0.000057549983,"about_ca_system_score_gemma":0.00012614822,"threshold_uncertainty_score":0.9999355},"labels":[],"label_agreement":null},{"id":"W2154466711","doi":"10.1109/newcas.2004.1359107","title":"Shunt-peaking of MCML gates using active inductors","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Inductor; Shunt (medical); Resistor; CMOS; Electronic engineering; Electronic circuit; Logic gate; Electrical engineering; Computer science; Materials science; Engineering; Voltage; Medicine","score_opus":0.04037178147363803,"score_gpt":0.25619306790189134,"score_spread":0.21582128642825332,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2154466711","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9789822,0.0070204297,0.0023477606,0.000093226394,0.0024522394,0.0010577162,0.00027631983,0.0003966307,0.007373441],"genre_scores_gemma":[0.9987145,0.0001264285,0.000010384491,0.0000586851,0.0006930728,0.000037845297,0.000015430069,0.00016442938,0.0001791998],"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99657387,0.00020670432,0.0010126998,0.000594041,0.00067088427,0.0009417991],"domain_scores_gemma":[0.99809474,0.0002535711,0.0003145539,0.0007532898,0.00029162917,0.00029221395],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00059627957,0.0007254745,0.000900939,0.00036685643,0.00036217747,0.00015400474,0.000553636,0.00040197873,0.000031759468],"category_scores_gemma":[0.00007176159,0.00055824895,0.00018932146,0.0009166775,0.000316777,0.0005056486,0.000009375127,0.0008814492,0.000034659046],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000041881045,0.00015128325,0.0005296519,0.0002999337,0.0005475385,0.000102467915,0.008338827,0.9550008,0.017887756,0.0025074966,0.0005932354,0.013999113],"study_design_scores_gemma":[0.03365022,0.004670951,0.018811442,0.062197983,0.0049762265,0.014909276,0.3323466,0.119525425,0.33671632,0.014785415,0.028792156,0.028617999],"about_ca_topic_score_codex":0.0011119675,"about_ca_topic_score_gemma":0.00012432259,"teacher_disagreement_score":0.8354754,"about_ca_system_score_codex":0.0005096375,"about_ca_system_score_gemma":0.00019067863,"threshold_uncertainty_score":0.9996869},"labels":[],"label_agreement":null},{"id":"W2157627782","doi":"10.1109/newcas.2004.1359062","title":"A novel asynchronous wrapper using 1-of-4 data encoding and single-track handshaking","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Concordia University","funders":"","keywords":"Handshaking; Asynchronous communication; Computer science; Encoding (memory); Throughput; Asynchronous system; Asynchronous circuit; Protocol (science); Embedded system; Computer architecture; Synchronization (alternating current); Computer network; Clock signal; Channel (broadcasting); Wireless; Synchronous circuit; Operating system","score_opus":0.07835245238350412,"score_gpt":0.2736662163467105,"score_spread":0.19531376396320638,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2157627782","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.9330811,0.013644294,0.048511855,0.00009347558,0.0017682946,0.0009821368,0.00039824587,0.00033565893,0.001184931],"genre_scores_gemma":[0.998403,0.0002297308,0.00028710955,0.00005921196,0.000759544,0.000015079504,0.000026525606,0.00013762325,0.00008215534],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9968572,0.00007558312,0.0009004264,0.0007243844,0.0005716212,0.00087075],"domain_scores_gemma":[0.9980318,0.00022005722,0.00024731868,0.0011003214,0.00013714998,0.0002633788],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008932166,0.00062622386,0.0007735796,0.00028676036,0.00046205206,0.00030310868,0.0006693118,0.00028487638,0.000011428635],"category_scores_gemma":[0.000037116897,0.0004944634,0.00007807485,0.00057774247,0.00026822925,0.0009872388,0.00010932936,0.00054887286,0.00001889822],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008339921,0.00042231914,0.0014250011,0.0011295577,0.0005332183,0.000102761056,0.009583891,0.8990813,0.039891742,0.00061720464,0.0006881859,0.046441406],"study_design_scores_gemma":[0.027135247,0.0022944438,0.006841358,0.035361353,0.0022199517,0.011536369,0.04118183,0.82364494,0.012787669,0.00044023793,0.024052793,0.012503802],"about_ca_topic_score_codex":0.00031774704,"about_ca_topic_score_gemma":0.0001307167,"teacher_disagreement_score":0.07543636,"about_ca_system_score_codex":0.0002069394,"about_ca_system_score_gemma":0.00011749617,"threshold_uncertainty_score":0.9997507},"labels":[],"label_agreement":null},{"id":"W2162743530","doi":"10.1109/newcas.2004.1359057","title":"Synchronous to asynchronous conversion using GasP control","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McGill University","funders":"","keywords":"Datapath; Asynchronous communication; Computer science; Asynchronous circuit; Electronic circuit; Sequential logic; Synchronous circuit; Clock signal; Logic synthesis; Logic gate; Parallel computing; Algorithm; Engineering; Electrical engineering; Computer network; Jitter","score_opus":0.01810573390262057,"score_gpt":0.23097876398173414,"score_spread":0.21287303007911357,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2162743530","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.92483103,0.0064440696,0.059298962,0.00033365702,0.004315769,0.0022429044,0.00023928453,0.00074011594,0.0015542345],"genre_scores_gemma":[0.9976404,0.00012252876,0.00004838571,0.0004069261,0.0012167149,0.00006790733,0.000012037802,0.00017957442,0.00030557244],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99628234,0.00015369106,0.00086168724,0.0007068508,0.00072477333,0.001270683],"domain_scores_gemma":[0.99796593,0.00019652695,0.00016715871,0.0008842115,0.00020700926,0.0005791529],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007296889,0.0007930718,0.00089175825,0.00034458115,0.0006342614,0.00029856252,0.00055902207,0.00034737907,0.00004936958],"category_scores_gemma":[0.000030140343,0.0006224539,0.00016146865,0.00067659444,0.00018069464,0.00047094323,0.00003909393,0.0006430967,0.0005344905],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00007448492,0.00011193801,0.00041920214,0.00021232555,0.00019569538,0.00011941335,0.00244142,0.98645484,0.0013641787,0.00017741219,0.0023268631,0.0061021973],"study_design_scores_gemma":[0.061963715,0.007260159,0.014663306,0.022186782,0.0030069402,0.010897903,0.045517012,0.6901027,0.008780944,0.0005624932,0.11306963,0.021988409],"about_ca_topic_score_codex":0.0004412385,"about_ca_topic_score_gemma":0.00008067179,"teacher_disagreement_score":0.29635215,"about_ca_system_score_codex":0.00073720765,"about_ca_system_score_gemma":0.00018490269,"threshold_uncertainty_score":0.9996227},"labels":[],"label_agreement":null},{"id":"W2163435175","doi":"10.1109/newcas.2004.1359045","title":"Low-energy design of a 3G-compliant turbo decoder","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Advanced Wireless Communication Techniques","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Waterloo","funders":"","keywords":"Turbo code; Turbo equalizer; Computer science; Turbo; Soft-decision decoder; Throughput; VHDL; CMOS; Serial concatenated convolutional codes; Power (physics); Electronic engineering; Efficient energy use; Real-time computing; Decoding methods; Computer hardware; Wireless; Electrical engineering; Algorithm; Telecommunications; Low-density parity-check code; Engineering; Concatenated error correction code; Field-programmable gate array; Block code; Physics","score_opus":0.033578937584217726,"score_gpt":0.25662214212341966,"score_spread":0.22304320453920193,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2163435175","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.06400462,0.020101812,0.9081674,0.00040945338,0.00106749,0.0015303424,0.0002075001,0.0013289207,0.003182438],"genre_scores_gemma":[0.9975922,0.0009968077,0.00037752173,0.000121711,0.00021412897,0.00012933291,0.000013507695,0.000121026635,0.00043377728],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997546,0.00019090947,0.0008421993,0.0003996131,0.00043355304,0.0005876786],"domain_scores_gemma":[0.9979067,0.00030061216,0.00022950984,0.0011459108,0.00020966907,0.00020759554],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00046837755,0.00049782684,0.0006636179,0.00021065515,0.00026382267,0.00008603044,0.0006810046,0.00023945094,0.000015315174],"category_scores_gemma":[0.000029101107,0.00038687699,0.00011743328,0.00048626566,0.00022428966,0.00026815687,0.000049159702,0.0004417349,0.000026226653],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000036163256,0.00015719018,0.000031290125,0.00014494805,0.00011522511,0.000018132238,0.0012882722,0.96140254,0.0016048905,0.0031853395,0.0015354047,0.03048059],"study_design_scores_gemma":[0.029648626,0.0044162027,0.0057583842,0.041791875,0.0013555585,0.004866662,0.046882197,0.53485763,0.15811116,0.042109698,0.108558424,0.021643583],"about_ca_topic_score_codex":0.00020552502,"about_ca_topic_score_gemma":0.00007335015,"teacher_disagreement_score":0.93358755,"about_ca_system_score_codex":0.00016919077,"about_ca_system_score_gemma":0.00007323134,"threshold_uncertainty_score":0.9998583},"labels":[],"label_agreement":null},{"id":"W2166419724","doi":"10.1109/newcas.2004.1358997","title":"An investigation into transistor-based adiabatic logic styles","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":8,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Carleton University","funders":"","keywords":"Adiabatic process; Pass transistor logic; Transistor; CMOS; Logic gate; Adiabatic circuit; Electronic engineering; Power (physics); Computer science; Logic family; Electrical engineering; Logic synthesis; Engineering; Physics; Voltage","score_opus":0.023731547665809153,"score_gpt":0.23670882979141789,"score_spread":0.21297728212560874,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2166419724","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.97736436,0.005298924,0.01248481,0.00050126517,0.0015160976,0.0012260677,0.000099966644,0.00080655224,0.000701981],"genre_scores_gemma":[0.9982389,0.00008374173,0.00008387525,0.00038274325,0.00068636617,0.000117001255,0.000053924647,0.0001387535,0.00021470238],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99695647,0.00022893233,0.0007934458,0.0006025149,0.0006363585,0.00078227837],"domain_scores_gemma":[0.9982218,0.00016944311,0.0001525697,0.00082847034,0.00015947237,0.0004682105],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007710184,0.00066130084,0.00063653954,0.0003210767,0.0005086596,0.00026747535,0.00050298014,0.0003266784,0.000027542806],"category_scores_gemma":[0.000021595086,0.0005048598,0.00012193507,0.00067847274,0.00029282828,0.00062075333,0.000008534472,0.0005676384,0.000131484],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000032827917,0.00012661253,0.00064980215,0.00036145543,0.000093712675,0.00003826902,0.0065116985,0.98114663,0.0016508986,0.0009346363,0.0011469951,0.007306476],"study_design_scores_gemma":[0.038855102,0.008551754,0.041385222,0.019401839,0.0024479337,0.0015755307,0.08479634,0.7256826,0.014796884,0.008768515,0.032501508,0.02123678],"about_ca_topic_score_codex":0.00041939685,"about_ca_topic_score_gemma":0.0004606417,"teacher_disagreement_score":0.25546402,"about_ca_system_score_codex":0.0003523722,"about_ca_system_score_gemma":0.00018419283,"threshold_uncertainty_score":0.9997403},"labels":[],"label_agreement":null},{"id":"W2170518693","doi":"10.1109/newcas.2004.1359065","title":"On low power shift register hardware realizations for convolutional encoders and decoders","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Shift register; Computer science; Encoder; Convolutional code; Decoding methods; Field-programmable gate array; Computer hardware; Coding (social sciences); Dissipation; Power (physics); Linear feedback shift register; Algorithm; Parallel computing; Electronic engineering; Chip; Engineering; Mathematics; Telecommunications","score_opus":0.03053235459895815,"score_gpt":0.27730021329306664,"score_spread":0.2467678586941085,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2170518693","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07869459,0.002274572,0.90338403,0.006108234,0.0026921465,0.002574288,0.0003177674,0.00091635715,0.0030379966],"genre_scores_gemma":[0.996294,0.000053800002,0.00038084565,0.001210912,0.00023763246,0.00016020627,0.00002103745,0.00006158587,0.0015799628],"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9970311,0.00019753791,0.0006249887,0.00084974285,0.0005906767,0.0007059903],"domain_scores_gemma":[0.9975091,0.0006195855,0.0003183947,0.0009436459,0.0003130372,0.0002962303],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008950531,0.0004896704,0.0004855082,0.00025482758,0.0008943583,0.00044664912,0.000744191,0.00026141934,0.0000063560074],"category_scores_gemma":[0.00017557609,0.00037964128,0.00013889912,0.00044938992,0.00028265498,0.0004778526,0.00008095633,0.00041307847,0.000021153588],"study_design_candidate":"theoretical_or_conceptual","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00046796774,0.0014513141,0.0025600698,0.0007126197,0.0005791293,0.00016586894,0.054067947,0.21804653,0.00017595227,0.5809033,0.10763513,0.033234194],"study_design_scores_gemma":[0.051244315,0.016900206,0.032543086,0.042985477,0.0013870155,0.008927217,0.08439589,0.24846298,0.0017284455,0.24613169,0.23814249,0.02715118],"about_ca_topic_score_codex":0.00028373455,"about_ca_topic_score_gemma":0.00033043613,"teacher_disagreement_score":0.91759944,"about_ca_system_score_codex":0.00019977536,"about_ca_system_score_gemma":0.00023070128,"threshold_uncertainty_score":0.99986553},"labels":[],"label_agreement":null},{"id":"W2171681271","doi":"10.1109/newcas.2004.1359092","title":"Leap-frog-based synthesis of CMOS micropower nth-order log-domain filters","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":6,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Dalhousie University","funders":"","keywords":"Chebyshev filter; CMOS; Micropower; Realization (probability); Filter (signal processing); Sensitivity (control systems); Topology (electrical circuits); Integrator; Network synthesis filters; Mathematics; Prototype filter; Computer science; Electronic engineering; Algorithm; Control theory (sociology); Filter design; Engineering; Physics; Mathematical analysis; Artificial intelligence; Combinatorics; Telecommunications; Statistics; Bandwidth (computing)","score_opus":0.01839409892984005,"score_gpt":0.22515945138095994,"score_spread":0.20676535245111988,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2171681271","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.51994455,0.029772528,0.4195947,0.0007108146,0.005251133,0.004023016,0.0017967604,0.0013500223,0.017556444],"genre_scores_gemma":[0.99806213,0.00012977135,0.000025744492,0.00027282033,0.00047787087,0.00009358195,0.000025003803,0.00016604544,0.0007470302],"study_design_codex":"simulation_or_modeling","study_design_gemma":"not_applicable","domain_scores_codex":[0.99631774,0.00027853064,0.0010382538,0.0006671125,0.0006727827,0.0010255912],"domain_scores_gemma":[0.99769324,0.00052118255,0.00026122952,0.00088102353,0.0002685575,0.0003747656],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008888114,0.000779387,0.0010421241,0.00031891753,0.0003740634,0.00014297929,0.0005954683,0.00040277737,0.00009206123],"category_scores_gemma":[0.00007328272,0.0006023298,0.00028425409,0.0007070823,0.00042042756,0.00021732393,0.000022598042,0.0006207632,0.00016361354],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00017307857,0.000534265,0.00053103955,0.00083882216,0.00075994176,0.00025622593,0.0032452976,0.94661415,0.00530077,0.0044074515,0.014198526,0.023140453],"study_design_scores_gemma":[0.07934528,0.010172771,0.0153955165,0.067840375,0.009209236,0.008830425,0.22251761,0.05176806,0.11210037,0.022389332,0.3511567,0.049274318],"about_ca_topic_score_codex":0.00038372524,"about_ca_topic_score_gemma":0.00016876,"teacher_disagreement_score":0.8948461,"about_ca_system_score_codex":0.00023390807,"about_ca_system_score_gemma":0.0001904755,"threshold_uncertainty_score":0.9996428},"labels":[],"label_agreement":null},{"id":"W2172219312","doi":"10.1109/newcas.2004.1359038","title":"Performance of probabilistic approaches to Steiner tree problem","year":2004,"lang":"en","type":"article","venue":"The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Steiner tree problem; Heuristics; Computer science; Probabilistic logic; Heuristic; Class (philosophy); Tree (set theory); Mathematical optimization; Automation; Theoretical computer science; Algorithm; Artificial intelligence; Mathematics; Engineering; Combinatorics","score_opus":0.06073061505041603,"score_gpt":0.22675602689848376,"score_spread":0.16602541184806774,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2172219312","genre_codex":"empirical","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":"empirical","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.97115266,0.0034281958,0.0075213914,0.00035318307,0.00064224587,0.0029482616,0.00016045863,0.0007664237,0.013027194],"genre_scores_gemma":[0.9980541,0.00008924251,0.00011695108,0.00005310967,0.00036618445,0.00021980295,0.000010054516,0.000095271134,0.0009952743],"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99761003,0.000084659485,0.00074234273,0.00045379557,0.00046813465,0.00064100605],"domain_scores_gemma":[0.99876577,0.00009740206,0.0001295134,0.000641472,0.00011708262,0.0002487402],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006191143,0.000495669,0.0006378069,0.00021164585,0.00019732738,0.000097081625,0.00042639798,0.00022040664,0.000008465794],"category_scores_gemma":[0.000018980445,0.00034907417,0.00010529983,0.00055120024,0.00014681295,0.00022153929,0.0000314193,0.0003842362,0.00004389082],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00009242236,0.00032635464,0.00096827256,0.0014802628,0.00020471169,0.000022720631,0.006452213,0.8958222,0.0012719458,0.003160803,0.0037849748,0.08641311],"study_design_scores_gemma":[0.041193116,0.028592017,0.051316313,0.073999055,0.0038989196,0.007091,0.07382948,0.4837556,0.046845697,0.012780179,0.13883004,0.037868608],"about_ca_topic_score_codex":0.00009615313,"about_ca_topic_score_gemma":0.00008290565,"teacher_disagreement_score":0.41206664,"about_ca_system_score_codex":0.0001340469,"about_ca_system_score_gemma":0.00006622601,"threshold_uncertainty_score":0.9998961},"labels":[],"label_agreement":null}]}