{"meta":{"query_hash":"60a25c24dffa","filters":{"venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology"},"cohort_total":21,"direct_labels_cover":0,"predictions_cover":21,"exported":21,"export_cap":100000,"truncated":false,"label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12"},"permalink":"https://metacan.xera.ac/q/60a25c24dffa","api":"https://metacan.xera.ac/api/v1/cohort?venue=The+Journal+of+VLSI+Signal+Processing+Systems+for+Signal+Image+and+Video+Technology"},"results":[{"id":"W1505157853","doi":"10.1023/a:1020268902913","title":"Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation","year":2002,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Digital Filter Design and Implementation","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada","funders":"","keywords":"Polyphase system; Field-programmable gate array; Bandwidth (computing); Electronic engineering; Computer science; Demodulation; Gate array; Finite impulse response; Digital signal processing; Digital filter; Computer hardware; Engineering; Telecommunications","score_opus":0.026122823913564533,"score_gpt":0.2593217240537918,"score_spread":0.23319890014022726,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1505157853","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017210662,0.0017898327,0.97926134,0.00089872815,0.000099903256,0.0005963135,0.000012374963,0.00007252041,0.000058351066],"genre_scores_gemma":[0.9597953,0.000016955708,0.039628245,0.00018368795,0.00017213025,0.00004853244,0.000007537896,0.000020420897,0.00012716845],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984241,0.00007753397,0.0006538837,0.00022939914,0.00027558595,0.00033947662],"domain_scores_gemma":[0.998324,0.00019416757,0.00069838075,0.00019377253,0.00052229996,0.00006741511],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000987295,0.00021595476,0.00033768508,0.0004326678,0.00037050477,0.00041382347,0.00065708277,0.00014551709,0.0000035275407],"category_scores_gemma":[0.00003398029,0.00014515826,0.00007993984,0.00044840362,0.00012851188,0.001536897,0.00004605982,0.00022025354,0.0000011860803],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00053262076,0.00044970328,0.00012757794,0.0015161892,0.00016969226,0.000010806906,0.00091445685,0.0030846733,0.19740647,0.0040319893,0.009390692,0.78236514],"study_design_scores_gemma":[0.0021890728,0.0019820984,0.000032092754,0.00023504415,0.0000972373,0.0004499821,0.00021115494,0.929402,0.061613128,0.002646933,0.000867424,0.0002738626],"about_ca_topic_score_codex":0.0000033127144,"about_ca_topic_score_gemma":1.917331e-7,"teacher_disagreement_score":0.94258463,"about_ca_system_score_codex":0.000041112482,"about_ca_system_score_gemma":0.0000601856,"threshold_uncertainty_score":0.59193826},"labels":[],"label_agreement":null},{"id":"W1510840923","doi":"10.1023/a:1015397423173","title":"A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation","year":2002,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Advanced Image and Video Retrieval Techniques","field":"Computer Science","cited_by":17,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"U.S. Department of Energy","keywords":"Computer science; Adder; Image warping; Mobile device; Affine transformation; MPEG-4; Architecture; CMOS; Computer architecture; Computer hardware; Latency (audio); Embedded system; Electronic engineering; Artificial intelligence; Coding (social sciences); Engineering","score_opus":0.016188339075876777,"score_gpt":0.26896069261079664,"score_spread":0.25277235353491984,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1510840923","genre_codex":"methods","genre_gemma":"methods","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":"methods","domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0003662825,0.015040741,0.9789088,0.004651,0.000032998392,0.0008265263,0.000013800527,0.0001362945,0.000023561994],"genre_scores_gemma":[0.4856248,0.0010015445,0.5126761,0.00019679924,0.00022262063,0.00014345637,0.0000019628546,0.00003338483,0.00009933839],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99852,0.00006593719,0.00065737247,0.00022874738,0.0002170911,0.0003108353],"domain_scores_gemma":[0.99807,0.00040821236,0.0006135162,0.0002589813,0.00057380775,0.00007545428],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0010181214,0.00022387685,0.0004019244,0.00037182114,0.00039495045,0.00020749606,0.0008252697,0.00016363588,0.0000013772886],"category_scores_gemma":[0.00013199639,0.00014852684,0.00008598953,0.0003989752,0.00023209017,0.0010363526,0.0000909253,0.00031329138,4.0450144e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00008371575,0.00005578401,0.000003070771,0.00029418594,0.000041654755,0.0000040438445,0.0009330428,0.00007695225,0.025052419,0.0013350123,0.000778915,0.9713412],"study_design_scores_gemma":[0.0044082464,0.0033205487,0.000013611009,0.00081258354,0.0002057586,0.0039632353,0.0008197156,0.7874882,0.06130371,0.11588934,0.021173673,0.0006013461],"about_ca_topic_score_codex":0.0000042197566,"about_ca_topic_score_gemma":8.663298e-7,"teacher_disagreement_score":0.97073984,"about_ca_system_score_codex":0.00002854117,"about_ca_system_score_gemma":0.000034018645,"threshold_uncertainty_score":0.6056749},"labels":[],"label_agreement":null},{"id":"W1516483814","doi":"10.1023/a:1008140025773","title":"A Low Power Approach to Floating Point Adder Design for DSP Applications","year":2001,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Royal Military College of Canada; Concordia University","funders":"","keywords":"Adder; Computer science; Latency (audio); Critical path method; Low latency (capital markets); Logic gate; Parallel computing; Electronic engineering; Arithmetic; Algorithm; Mathematics; Engineering; Telecommunications; Computer network","score_opus":0.013983587780079791,"score_gpt":0.24149312523165986,"score_spread":0.22750953745158006,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1516483814","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0076593896,0.0051080794,0.98442227,0.00030221295,0.00011123021,0.0019254169,0.000011743897,0.00024196126,0.00021768764],"genre_scores_gemma":[0.9465551,0.00009060176,0.05233141,0.00008507893,0.00033991775,0.00041379328,0.000002487208,0.00010461949,0.0000769945],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99780816,0.00007289013,0.0009592938,0.00026231603,0.00028108252,0.00061627786],"domain_scores_gemma":[0.99814016,0.00039994018,0.00040671646,0.00025979584,0.00064442167,0.0001489717],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0020933838,0.000363135,0.00059970265,0.0006368607,0.00044074294,0.00019199538,0.00064354663,0.00025561103,0.0000057973807],"category_scores_gemma":[0.00007261432,0.00026418298,0.00011908894,0.0007666152,0.00016381795,0.0005822463,0.000050951796,0.0004356913,0.000006747195],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00083508034,0.000365518,0.000050334234,0.0024075813,0.000644504,0.000018549368,0.0028316071,0.11877436,0.7541247,0.0009181845,0.014810444,0.10421911],"study_design_scores_gemma":[0.004701375,0.0034415578,0.000020466396,0.0019968227,0.0008465595,0.005093849,0.008035155,0.7746785,0.17017174,0.0058502574,0.023482356,0.0016813548],"about_ca_topic_score_codex":0.0000029902699,"about_ca_topic_score_gemma":4.1477355e-7,"teacher_disagreement_score":0.9388957,"about_ca_system_score_codex":0.00011003059,"about_ca_system_score_gemma":0.0001060789,"threshold_uncertainty_score":0.99998105},"labels":[],"label_agreement":null},{"id":"W1543526270","doi":"10.1023/a:1021145919099","title":"Energy Efficient Adiabatic Multiplier-Accumulator Design","year":2003,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Adiabatic process; Adiabatic circuit; Dissipation; Binary number; Computer science; Electronic engineering; Logic gate; Physics; Topology (electrical circuits); Mathematics; Logic synthesis; Arithmetic; Algorithm; Electrical engineering; Engineering; Logic family; Quantum mechanics","score_opus":0.012608334509384917,"score_gpt":0.22877716644755614,"score_spread":0.2161688319381712,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1543526270","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.050483473,0.02593764,0.9224335,0.00006740164,0.00034059005,0.00043080826,0.0000047572203,0.00020741246,0.00009441043],"genre_scores_gemma":[0.99295676,0.00027530483,0.006358759,0.00003551741,0.0001682695,0.000050808576,7.271028e-7,0.00009362654,0.0000602122],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99760985,0.00019271439,0.0009999856,0.0002205848,0.0003536016,0.0006232464],"domain_scores_gemma":[0.99819565,0.00050065527,0.0004793246,0.00024933764,0.00042775852,0.00014725667],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.002055655,0.00040453934,0.0006651737,0.00064650737,0.00035159974,0.00015769296,0.0005178328,0.00028909385,0.000012519314],"category_scores_gemma":[0.00009647876,0.0002828885,0.00011339594,0.0006305505,0.00028785865,0.00037654318,0.00003243515,0.00046423828,0.0000065804907],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00030007435,0.00018194935,0.000083640094,0.0012316678,0.00054266443,0.000075897115,0.0010350774,0.31807074,0.6219754,0.0011336553,0.0040452024,0.051324],"study_design_scores_gemma":[0.0018951045,0.0009197833,0.0000069760627,0.00072736706,0.00034238628,0.0016853244,0.0009415921,0.7729429,0.21385093,0.0010858518,0.0050320025,0.00056979933],"about_ca_topic_score_codex":0.0000050793396,"about_ca_topic_score_gemma":6.032764e-7,"teacher_disagreement_score":0.9424733,"about_ca_system_score_codex":0.00012563968,"about_ca_system_score_gemma":0.0001548016,"threshold_uncertainty_score":0.99996233},"labels":[],"label_agreement":null},{"id":"W1587360322","doi":"10.1023/a:1022236132192","title":"Fast Fourier Transforms Using the Complex Logarithmic Number System","year":2003,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":8,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"Ryerson University","keywords":"Logarithm; Fast Fourier transform; Arithmetic; Computer science; Point (geometry); Algorithm; Adder; Multiplication (music); Mathematics; Geometry; Telecommunications; Combinatorics","score_opus":0.029849803841538305,"score_gpt":0.3035803363279219,"score_spread":0.2737305324863836,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1587360322","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.004817691,0.0029712787,0.9903384,0.0009411137,0.0002383414,0.0004411091,0.0000042499505,0.000082097315,0.00016574498],"genre_scores_gemma":[0.83756435,0.000030184954,0.16201851,0.000103343664,0.00019006376,0.000015896352,1.9767691e-7,0.000028236882,0.000049229453],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99741906,0.00047118397,0.0008991279,0.00026778967,0.00042088717,0.00052194565],"domain_scores_gemma":[0.997705,0.00047585877,0.00082478684,0.0003097605,0.0005745556,0.000110046196],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0036482955,0.00029455998,0.000618434,0.00020146147,0.00083546364,0.00039382983,0.0011832464,0.00017806614,0.0000050835292],"category_scores_gemma":[0.000067994544,0.00014971272,0.00016061512,0.00075912755,0.00046786983,0.0006526276,0.00008376161,0.0005671256,0.0000023921245],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00023045372,0.00028582208,0.00023883917,0.0016188251,0.00055805704,0.00019624675,0.0024306201,0.0015576304,0.24037533,0.06787271,0.0007945967,0.6838409],"study_design_scores_gemma":[0.002572853,0.0012297885,0.000023160366,0.0014051534,0.00044230564,0.02816281,0.008641158,0.8928662,0.024564624,0.028720608,0.01054215,0.0008292188],"about_ca_topic_score_codex":0.000022615264,"about_ca_topic_score_gemma":5.789144e-7,"teacher_disagreement_score":0.89130855,"about_ca_system_score_codex":0.000079528596,"about_ca_system_score_gemma":0.00018046008,"threshold_uncertainty_score":0.6425795},"labels":[],"label_agreement":null},{"id":"W1681298107","doi":"10.1023/a:1008135917341","title":"Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors","year":2001,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":2,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"McMaster University","keywords":"Computer science; Video decoder; Cache; Computer hardware; Bandwidth (computing); Software; Data compression; Embedded system; High memory; MPEG-4; Decoding methods; Parallel computing; Operating system; Computer network; Telecommunications; Coding (social sciences)","score_opus":0.02298798773144987,"score_gpt":0.28647604528673687,"score_spread":0.263488057555287,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1681298107","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.09218698,0.011956874,0.8929968,0.001929133,0.00011397862,0.0006116713,0.000010498869,0.00015064796,0.000043401138],"genre_scores_gemma":[0.99044305,0.0004035612,0.00897423,0.00003676719,0.00005077818,0.000029669278,8.109094e-7,0.000020125317,0.000040999847],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99780786,0.00009596954,0.0010259872,0.0002905277,0.00039045056,0.00038918553],"domain_scores_gemma":[0.9971367,0.00042403137,0.0011925292,0.00025707527,0.0009113154,0.000078347024],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0018530036,0.00027316896,0.0006161785,0.0006132675,0.0004805919,0.00019412741,0.0010465446,0.00025319084,0.0000016826551],"category_scores_gemma":[0.00012338813,0.00017375086,0.00011047254,0.000575013,0.00041398528,0.000664964,0.0001594103,0.00035610705,5.0271956e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0012285435,0.0005241368,0.00021739508,0.0023288787,0.00024182364,0.000027467384,0.00460709,0.005527699,0.43743113,0.005520542,0.0020868941,0.5402584],"study_design_scores_gemma":[0.0033564009,0.0031321421,0.000051067513,0.0027259008,0.0001829901,0.0019282149,0.0050327047,0.70037204,0.25862473,0.018462176,0.0055961427,0.00053552183],"about_ca_topic_score_codex":0.000006786409,"about_ca_topic_score_gemma":6.0159266e-7,"teacher_disagreement_score":0.89825606,"about_ca_system_score_codex":0.00003148082,"about_ca_system_score_gemma":0.00010599803,"threshold_uncertainty_score":0.70853543},"labels":[],"label_agreement":null},{"id":"W1975304868","doi":"10.1023/b:vlsi.0000017006.75431.c7","title":"A Low Power Architecture for HASM Motion Tracking","year":2004,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Affine transformation; Motion estimation; Motion compensation; Motion vector; Mesh networking; Computer vision; Mathematics","score_opus":0.016404825659260543,"score_gpt":0.2644000435190492,"score_spread":0.24799521785978867,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1975304868","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.017402316,0.0065668775,0.9691742,0.0058952975,0.00018085646,0.00046899193,0.000004079942,0.00028853834,0.00001880607],"genre_scores_gemma":[0.9747623,0.000049661026,0.024868343,0.00010478635,0.00011644413,0.000045441633,4.431693e-7,0.000024316661,0.00002822988],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9981682,0.0000717497,0.00071195356,0.0003028587,0.0003011266,0.0004441112],"domain_scores_gemma":[0.99778354,0.00030976904,0.00084929005,0.0003083848,0.0006806244,0.000068412985],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0014732464,0.00026815414,0.00048548286,0.0005911546,0.0005981074,0.0003739543,0.0013985418,0.0002763969,9.1388193e-7],"category_scores_gemma":[0.00019767476,0.00017053222,0.00015466881,0.0005144958,0.00029405332,0.00067846663,0.00016929366,0.0005319434,9.764912e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00022044752,0.00017215814,0.000015530017,0.00052431726,0.00010444596,0.000029210101,0.0011955397,0.0037620459,0.29997885,0.008846325,0.00072941574,0.6844217],"study_design_scores_gemma":[0.004513336,0.0042628967,0.000029070497,0.0036319983,0.0001936345,0.0052484353,0.0026234337,0.03158733,0.60976803,0.33381027,0.0035486293,0.00078294805],"about_ca_topic_score_codex":0.0000063620773,"about_ca_topic_score_gemma":0.000001327488,"teacher_disagreement_score":0.95736,"about_ca_system_score_codex":0.00006476709,"about_ca_system_score_gemma":0.00015454635,"threshold_uncertainty_score":0.69541025},"labels":[],"label_agreement":null},{"id":"W1987430645","doi":"10.1007/s11265-007-0051-z","title":"Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems","year":2007,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Wireless Communication Networks Research","field":"Computer Science","cited_by":7,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université du Québec à Trois-Rivières","funders":"National Science Council","keywords":"Computer science; Field-programmable gate array; Multipath propagation; Digital signal processing; Fast Fourier transform; Asynchronous communication; Real-time computing; Channel (broadcasting); Computer hardware; Embedded system; Algorithm; Computer network","score_opus":0.020159054167742937,"score_gpt":0.32338417952512594,"score_spread":0.303225125357383,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1987430645","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.13460775,0.0033170711,0.86087656,0.0005465577,0.00004522522,0.00054585905,0.0000033873976,0.00004048218,0.000017098608],"genre_scores_gemma":[0.990178,0.00013664602,0.009565727,0.0000123591535,0.000047861646,0.000026609092,0.0000022223574,0.00001765793,0.000012930074],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9976579,0.0002939631,0.0010690785,0.0002041331,0.00040878088,0.00036617002],"domain_scores_gemma":[0.99703985,0.0007506241,0.0011202134,0.0002927075,0.00072005333,0.00007653413],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0057066404,0.00017736007,0.00044294898,0.00084579934,0.00022060628,0.00016866704,0.0008238007,0.00016044028,0.0000011877115],"category_scores_gemma":[0.00006686125,0.00013002689,0.00004267071,0.0007714875,0.00025688187,0.0007930064,0.00016041788,0.0003246525,5.4736836e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00049744773,0.00027575484,0.0009689497,0.0016327063,0.00012601897,0.00004415334,0.0030519802,0.030938162,0.58361375,0.00202214,0.0002728534,0.37655607],"study_design_scores_gemma":[0.0014132858,0.0006024885,0.00044401136,0.0007956941,0.00002890538,0.00026418254,0.0015861582,0.9649928,0.028927736,0.0007601571,0.000028545153,0.00015603816],"about_ca_topic_score_codex":0.00021299915,"about_ca_topic_score_gemma":0.000015156524,"teacher_disagreement_score":0.9340546,"about_ca_system_score_codex":0.00008428197,"about_ca_system_score_gemma":0.00018109653,"threshold_uncertainty_score":0.5302343},"labels":[],"label_agreement":null},{"id":"W1990583874","doi":"10.1007/s11265-006-5919-9","title":"Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters","year":2006,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Advanced Algorithms and Applications","field":"Engineering","cited_by":27,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Ottawa","funders":"","keywords":"Computer science; Resampling; Mechanism (biology); Speedup; Particle filter; Parallel computing; Auxiliary particle filter; Algorithm; Filter (signal processing); Artificial intelligence; Physics; Kalman filter; Ensemble Kalman filter; Computer vision","score_opus":0.016992363777027886,"score_gpt":0.2817532261074687,"score_spread":0.2647608623304408,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1990583874","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07693595,0.0027268005,0.9195404,0.00018527362,0.00003173426,0.0005130585,0.000012990126,0.00005184594,0.0000019119952],"genre_scores_gemma":[0.9378519,0.00007047237,0.06188122,0.0000081102,0.00008607315,0.000059310903,0.0000022130334,0.000024478659,0.000016239874],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99904126,0.00002051995,0.0005277864,0.00010031836,0.00009610821,0.00021398994],"domain_scores_gemma":[0.9990956,0.00021221803,0.0003217349,0.0000730846,0.00026664775,0.000030715426],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005408461,0.00012746523,0.00026206783,0.00012062667,0.00018326013,0.000043764954,0.00012583032,0.00007299409,0.0000018195333],"category_scores_gemma":[0.000008062252,0.000096063224,0.000032485314,0.0001579968,0.00009293663,0.00023333536,0.000016003598,0.00010344628,1.4317376e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00012735161,0.000028531447,0.000017507831,0.00038555686,0.00007834565,0.0000014154612,0.00022929654,0.039420206,0.9113104,0.0144561445,0.0002361493,0.033709094],"study_design_scores_gemma":[0.0018981767,0.00071980275,0.000036623136,0.00022852249,0.00021173304,0.00017245943,0.0029621576,0.28577405,0.625147,0.08250981,0.00011227228,0.00022737878],"about_ca_topic_score_codex":0.00003249135,"about_ca_topic_score_gemma":0.0000016210402,"teacher_disagreement_score":0.8609159,"about_ca_system_score_codex":0.000022488626,"about_ca_system_score_gemma":0.00002374386,"threshold_uncertainty_score":0.39173448},"labels":[],"label_agreement":null},{"id":"W1997343952","doi":"10.1007/s11265-005-4161-1","title":"A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices","year":2005,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"","keywords":"Computer science; Block (permutation group theory); Encoder; Pixel; Computer hardware; Frame (networking); Motion estimation; Block size; Architecture; CMOS; Clock rate; Frame rate; Process (computing); Embedded system; Real-time computing; Electronic engineering; Artificial intelligence; Engineering; Telecommunications","score_opus":0.011298658641158279,"score_gpt":0.2661542212039765,"score_spread":0.25485556256281827,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W1997343952","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.005410129,0.011815663,0.9778252,0.0038277423,0.000030266467,0.0008182753,0.000007675371,0.00023661721,0.000028397286],"genre_scores_gemma":[0.86856866,0.000035041816,0.1306733,0.00013956241,0.00016965644,0.00033272945,0.0000012573281,0.00001893151,0.000060884595],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9984743,0.00006340976,0.0005781468,0.0002734699,0.00028899492,0.00032167646],"domain_scores_gemma":[0.99754983,0.0005877069,0.0007808583,0.00025437775,0.00076411036,0.00006313499],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00093123765,0.00022682542,0.00040078533,0.000450224,0.0006007264,0.00025286732,0.0012685742,0.00015848243,0.0000012209341],"category_scores_gemma":[0.000030265905,0.00013482066,0.00008320336,0.0004905098,0.00033548335,0.00050005515,0.00013853825,0.00036312608,0.0000012360166],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00020931677,0.0001483004,0.00003658794,0.0004883252,0.00013854077,0.0000053402255,0.0006280841,0.04074743,0.016098578,0.004366665,0.0016896813,0.93544316],"study_design_scores_gemma":[0.005548966,0.00651888,0.000034581524,0.0023218528,0.00049395964,0.007798278,0.006216439,0.70309746,0.070165865,0.10200677,0.09447481,0.0013221427],"about_ca_topic_score_codex":0.000003059917,"about_ca_topic_score_gemma":0.000002668,"teacher_disagreement_score":0.934121,"about_ca_system_score_codex":0.000036101253,"about_ca_system_score_gemma":0.0001821063,"threshold_uncertainty_score":0.5497827},"labels":[],"label_agreement":null},{"id":"W2000095678","doi":"10.1007/s11265-007-0050-0","title":"A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration","year":2007,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"CCD and CMOS Imaging Sensors","field":"Engineering","cited_by":5,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Computer science; Instruction set; Video processing; Overhead (engineering); Flexibility (engineering); Computer architecture; Set (abstract data type); Application-specific instruction-set processor; Embedded system; Hardware acceleration; Parallel computing; Computer hardware; Computer engineering; Field-programmable gate array; Programming language","score_opus":0.025740946474339395,"score_gpt":0.26060544659333723,"score_spread":0.23486450011899784,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2000095678","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012942912,0.010793702,0.97445184,0.0001518562,0.00011219197,0.0012343858,0.000012431391,0.00025135503,0.000049310573],"genre_scores_gemma":[0.9406715,0.00011059461,0.0583302,0.000038270544,0.0005785924,0.00014671267,0.000007748873,0.00009189695,0.000024458508],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.997709,0.000035851433,0.0011078906,0.000296998,0.00031664284,0.00053363794],"domain_scores_gemma":[0.9976991,0.0003062542,0.0007278362,0.00018055669,0.0009860409,0.00010024496],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0024997036,0.00036338542,0.00054450444,0.0005842849,0.00058480445,0.00030608726,0.00047612574,0.00024511942,0.0000013156495],"category_scores_gemma":[0.000053199976,0.00027575364,0.000101806254,0.0007862427,0.0002808863,0.0008026196,0.000022947544,0.00047673917,8.285001e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005508583,0.000113152295,0.000035332883,0.0019787548,0.000119849225,0.0000032842122,0.0010455842,0.019157475,0.69872713,0.00031557286,0.00093375065,0.27701923],"study_design_scores_gemma":[0.003720966,0.000660761,0.00003199216,0.0007811136,0.0003392841,0.0036103104,0.005669246,0.792689,0.1808732,0.0028774983,0.007925138,0.0008214739],"about_ca_topic_score_codex":0.0000043578093,"about_ca_topic_score_gemma":0.0000012104027,"teacher_disagreement_score":0.9277286,"about_ca_system_score_codex":0.000110386034,"about_ca_system_score_gemma":0.000110518675,"threshold_uncertainty_score":0.9999695},"labels":[],"label_agreement":null},{"id":"W2005671325","doi":"10.1007/s11265-006-0030-9","title":"On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC","year":2007,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":15,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Computer science; Field-programmable gate array; Encoder; Quantization (signal processing); Computer hardware; Pixel; MPEG-4; Discrete cosine transform; Embedded system; Coding (social sciences); Virtex; Algorithm; Artificial intelligence; Image (mathematics)","score_opus":0.025192159654209026,"score_gpt":0.31428201495344343,"score_spread":0.2890898552992344,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2005671325","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.04958229,0.0037778642,0.9448623,0.0011506216,0.00008746606,0.0004141953,0.000008844847,0.00009936511,0.000017071116],"genre_scores_gemma":[0.98409486,0.00008895951,0.015647896,0.000050856415,0.000046862748,0.000020922143,9.4372183e-7,0.000013397059,0.000035321766],"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.9984624,0.000051460298,0.0007568434,0.00020560916,0.0002370299,0.00028665387],"domain_scores_gemma":[0.9974202,0.000771316,0.000935528,0.00020227108,0.00062253565,0.000048144757],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.001993602,0.000173581,0.00037625694,0.00060143945,0.0004160794,0.00012640997,0.0006717923,0.00015364308,0.0000010790295],"category_scores_gemma":[0.00019239231,0.00011577187,0.000070934904,0.00042910987,0.00023805087,0.00037614335,0.00012415786,0.0002260724,1.8654445e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0005157194,0.00018540281,0.00037206395,0.00085681595,0.00017466635,0.000013033823,0.001217143,0.0006210778,0.23760074,0.046048712,0.0032909536,0.70910364],"study_design_scores_gemma":[0.0046341177,0.007932967,0.00018309677,0.0028730289,0.00034489352,0.0014366792,0.008840714,0.16964409,0.63559854,0.16484673,0.0029430273,0.0007221167],"about_ca_topic_score_codex":0.000008244872,"about_ca_topic_score_gemma":0.0000022864212,"teacher_disagreement_score":0.93451256,"about_ca_system_score_codex":0.00002461275,"about_ca_system_score_gemma":0.00007996426,"threshold_uncertainty_score":0.47210398},"labels":[],"label_agreement":null},{"id":"W2013346672","doi":"10.1023/b:vlsi.0000042493.11467.64","title":"A Pipeline Architecture for Processing of DNA Microarrays Images","year":2004,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Gene expression and cancer classification","field":"Biochemistry, Genetics and Molecular Biology","cited_by":9,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Pipeline (software); DNA microarray; Computer science; Architecture; Computational biology; Computer architecture; Biology; Geography; Genetics; Operating system; Gene; Gene expression","score_opus":0.010518680667881801,"score_gpt":0.2675127534273182,"score_spread":0.25699407275943636,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2013346672","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.07827195,0.022391085,0.89720833,0.0015263971,0.00006233152,0.00046949787,0.000022604796,0.000015448633,0.000032380063],"genre_scores_gemma":[0.9927432,0.00018551965,0.006452322,0.00008150449,0.00031783464,0.000042651332,0.000008135974,0.000032540338,0.00013630479],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99868125,0.0000533679,0.00063930394,0.00021854222,0.0001566249,0.0002509141],"domain_scores_gemma":[0.9980191,0.00003980078,0.0009237905,0.00016309092,0.0007964404,0.000057791294],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00083709916,0.00019881784,0.0003549878,0.00023433848,0.00021778024,0.00005340825,0.00036999892,0.0002205663,0.0000011723594],"category_scores_gemma":[0.000097221164,0.00013217276,0.00011921837,0.00021148687,0.00032555955,0.000024034536,0.000049637463,0.00018652227,1.6711176e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000519328,0.000061428706,0.00001588149,0.00051191705,0.000036565638,9.73124e-7,0.00015413895,0.00037339953,0.9504966,0.000031747662,0.0012696572,0.046528373],"study_design_scores_gemma":[0.0017859505,0.001078216,0.000010348757,0.0005881779,0.00013376001,0.00047705128,0.001282493,0.00038194653,0.9838616,0.0025626284,0.0076624122,0.0001754011],"about_ca_topic_score_codex":0.000004584062,"about_ca_topic_score_gemma":0.0000021084331,"teacher_disagreement_score":0.91447127,"about_ca_system_score_codex":0.00001992777,"about_ca_system_score_gemma":0.00028228405,"threshold_uncertainty_score":0.53898484},"labels":[],"label_agreement":null},{"id":"W2013392609","doi":"10.1023/b:vlsi.0000047274.68702.8d","title":"Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders","year":2004,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Coding theory and cryptography","field":"Computer Science","cited_by":56,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Toronto; McGill University","funders":"","keywords":"Very-large-scale integration; Reed–Solomon error correction; Interpolation (computer graphics); Computer science; Parallel computing; Soft-decision decoder; Arithmetic; Algorithm; Decoding methods; Mathematics; Linear code; Embedded system; Artificial intelligence; Block code","score_opus":0.011656878434417484,"score_gpt":0.2669418569395721,"score_spread":0.25528497850515464,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2013392609","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.012392029,0.0037077558,0.9802096,0.0027876762,0.00023474543,0.0005116317,0.000007499454,0.0001289251,0.000020159341],"genre_scores_gemma":[0.91614,0.000015894182,0.08343261,0.00020301576,0.00014670042,0.000027386275,0.0000010917347,0.000024713323,0.000008546893],"study_design_codex":"design_other","study_design_gemma":"theoretical_or_conceptual","domain_scores_codex":[0.9980795,0.00011004101,0.0007725446,0.00030758767,0.00031588328,0.00041446305],"domain_scores_gemma":[0.9974059,0.000744087,0.00081520394,0.00029055594,0.0006424668,0.00010178471],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0023658688,0.00027941613,0.00048067517,0.0007722377,0.0005601922,0.0003207804,0.0012304084,0.00022908002,0.0000018898926],"category_scores_gemma":[0.00020808815,0.00018627598,0.00023384074,0.00068363437,0.00033454693,0.0005314896,0.00011060582,0.0004358609,7.936837e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0020269311,0.00024267579,0.00006187366,0.0006960259,0.00020828786,0.000032120955,0.0021967269,0.0077957558,0.14205275,0.013502228,0.00066260045,0.830522],"study_design_scores_gemma":[0.0060989894,0.005880684,0.000020355392,0.0031548624,0.0003276431,0.0020502945,0.0016662051,0.21474983,0.052596517,0.71001565,0.0026435289,0.0007954644],"about_ca_topic_score_codex":0.0000111664895,"about_ca_topic_score_gemma":0.000008580078,"teacher_disagreement_score":0.90374804,"about_ca_system_score_codex":0.000057617173,"about_ca_system_score_gemma":0.00029966913,"threshold_uncertainty_score":0.75961137},"labels":[],"label_agreement":null},{"id":"W2017264709","doi":"10.1007/s11265-006-0001-1","title":"Buffer and Register Allocation for Memory Space Optimization","year":2007,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":3,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Université de Montréal; Université du Québec à Montréal; Polytechnique Montréal","funders":"","keywords":"Register allocation; Computer science; Translation lookaside buffer; Cache; Write buffer; Processor register; Parallel computing; CPU cache; Unix; Memory hierarchy; Operating system; Cache algorithms; Memory address; Physical address; Semiconductor memory","score_opus":0.015495876634167604,"score_gpt":0.27785053230130624,"score_spread":0.2623546556671386,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2017264709","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0017273559,0.0053285924,0.99015427,0.002072173,0.00008215024,0.00044631472,9.96656e-7,0.00013153136,0.00005660779],"genre_scores_gemma":[0.7304905,0.0001304366,0.26893806,0.00012089231,0.00014655702,0.000013633853,0.000001055236,0.000017810613,0.00014105947],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9986906,0.00007249855,0.00058779115,0.0002066363,0.0001800137,0.00026244303],"domain_scores_gemma":[0.99778074,0.00039081712,0.00077213586,0.00016908729,0.0008335762,0.00005362727],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0031236645,0.00016543429,0.00029839342,0.00039545883,0.00036269077,0.00022456038,0.00047707837,0.00016523509,4.9920317e-7],"category_scores_gemma":[0.00011150365,0.00011736718,0.000049601316,0.00032141423,0.0001804003,0.000595558,0.00008465056,0.00018684825,1.7302102e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0015511255,0.00040638426,0.00025766835,0.0026837855,0.00040262015,0.00004375702,0.005481868,0.13034175,0.15658201,0.03466812,0.013962008,0.6536189],"study_design_scores_gemma":[0.0010193479,0.0009091093,0.000012092684,0.00042628733,0.00008264882,0.00094700727,0.000498776,0.9606548,0.027398597,0.006598897,0.00119919,0.0002532412],"about_ca_topic_score_codex":0.0000060855714,"about_ca_topic_score_gemma":8.2717594e-7,"teacher_disagreement_score":0.830313,"about_ca_system_score_codex":0.000035556473,"about_ca_system_score_gemma":0.00007674466,"threshold_uncertainty_score":0.47860947},"labels":[],"label_agreement":null},{"id":"W2023426888","doi":"10.1007/s11265-005-4841-x","title":"Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey","year":2005,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":34,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"McMaster University","funders":"","keywords":"Control reconfiguration; Digital signal processing; Computer science; Embedded system; Throughput; Power consumption; Signal processing; Digital signal processor; Real-time computing; Computer hardware; Computer architecture; Power (physics); Telecommunications","score_opus":0.021779155849940418,"score_gpt":0.27980409704848547,"score_spread":0.258024941198545,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2023426888","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0010885564,0.031374756,0.963485,0.0007001884,0.00008265948,0.0025554986,0.000059980386,0.00045813093,0.00019523299],"genre_scores_gemma":[0.9828892,0.00012209426,0.014867805,0.000076065626,0.0006850095,0.00065405853,0.000010238791,0.000093447605,0.0006021173],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9953588,0.00038940046,0.0021065879,0.0006457018,0.0006350305,0.00086445565],"domain_scores_gemma":[0.9927682,0.0013626114,0.0025745088,0.0005423164,0.002547782,0.0002045785],"candidate_categories":["metaepi_narrow","scholarly_communication"],"consensus_categories":[],"category_scores_codex":[0.007117412,0.00056438195,0.001185908,0.00088028214,0.0008868828,0.0017649364,0.0023536019,0.00047759755,0.0000034332213],"category_scores_gemma":[0.00016847912,0.00041353132,0.00021073566,0.0010858971,0.00041609356,0.0030511892,0.00014816508,0.0006219749,0.000012770031],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0006976008,0.00054323574,0.00020170107,0.0041061863,0.00045822054,0.000024655908,0.0013157092,0.001418251,0.19716053,0.0034100218,0.014765927,0.775898],"study_design_scores_gemma":[0.003347512,0.0036394252,0.000018295863,0.0047698906,0.0003727709,0.0072332732,0.0016330825,0.87676275,0.044948783,0.012970453,0.042494036,0.0018097176],"about_ca_topic_score_codex":0.0000371574,"about_ca_topic_score_gemma":0.0000031263642,"teacher_disagreement_score":0.9818006,"about_ca_system_score_codex":0.00021791375,"about_ca_system_score_gemma":0.0005918538,"threshold_uncertainty_score":0.9998317},"labels":[],"label_agreement":null},{"id":"W2091831372","doi":"10.1007/s11265-005-5268-0","title":"An Efficient Architecture for a Lifted 2D Biorthogonal DWT","year":2005,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Advanced Data Compression Techniques","field":"Computer Science","cited_by":12,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Transpose; Parallel computing; Biorthogonal system; Wavelet; Lifting scheme; Architecture; Signal processing; Discrete wavelet transform; Second-generation wavelet transform; Algorithm; Factoring; Wavelet transform; Image processing; Digital signal processing; Computer hardware; Image (mathematics); Artificial intelligence","score_opus":0.012348886256349627,"score_gpt":0.29195555628600695,"score_spread":0.27960667002965733,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2091831372","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.011166726,0.006314889,0.9790827,0.0023429298,0.0000804424,0.0006988875,0.000028594808,0.0002736268,0.000011197081],"genre_scores_gemma":[0.7732522,0.000028284703,0.22612268,0.00018625922,0.00028822818,0.0000633364,0.0000027987026,0.00002890807,0.000027289409],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99774045,0.0001535392,0.0008739789,0.00037567518,0.00037097686,0.0004853728],"domain_scores_gemma":[0.997147,0.00044691793,0.001016381,0.000446876,0.000798545,0.00014423383],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.001853788,0.0003044818,0.0005268974,0.00061613665,0.0005096262,0.0002744497,0.0017952675,0.00021771275,0.0000019675954],"category_scores_gemma":[0.000105100975,0.0001946539,0.000121953904,0.0005069722,0.00031840548,0.00082682597,0.00020564326,0.0004920116,9.597749e-7],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00039130868,0.000246828,0.000020555475,0.00027908388,0.00006550742,0.000015069129,0.00054161565,0.005675417,0.44084963,0.0035506347,0.0016004061,0.54676396],"study_design_scores_gemma":[0.0022375942,0.003572087,0.000018965244,0.0010331229,0.00015902742,0.003531943,0.00051798485,0.71652275,0.22138412,0.031928286,0.018403763,0.00069034443],"about_ca_topic_score_codex":0.0000028809231,"about_ca_topic_score_gemma":0.0000013560209,"teacher_disagreement_score":0.7620855,"about_ca_system_score_codex":0.00005268728,"about_ca_system_score_gemma":0.0001757674,"threshold_uncertainty_score":0.79377556},"labels":[],"label_agreement":null},{"id":"W2102792919","doi":"10.1023/a:1022869805515","title":"Modeling of the Coding Gain of Joint Coding for Multi-Program Video Transmission","year":2003,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":2,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"Communications Research Centre Canada","funders":"","keywords":"Computer science; Constant bitrate; Coding (social sciences); Statistical time division multiplexing; Multiplexing; Channel code; Variable-length code; Context-adaptive binary arithmetic coding; Channel (broadcasting); Coding gain; Bit rate; Theoretical computer science; Algorithm; Real-time computing; Decoding methods; Data compression; Variable bitrate; Computer network; Telecommunications; Statistics; Mathematics","score_opus":0.05072885929433482,"score_gpt":0.301342746853878,"score_spread":0.25061388755954317,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2102792919","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.018247943,0.008488171,0.9715786,0.0006751385,0.00013849403,0.0007204217,0.0000036029717,0.00012956813,0.000018080043],"genre_scores_gemma":[0.9269641,0.00018719623,0.07270702,0.000021778056,0.00002919792,0.000045281497,1.8351234e-7,0.000022145716,0.000023078699],"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9974391,0.00021184357,0.001285763,0.00028072082,0.00037245644,0.0004101341],"domain_scores_gemma":[0.9969641,0.000374274,0.0013372377,0.0003786983,0.0008860387,0.00005963673],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.002979655,0.00026913028,0.00071724737,0.00045635557,0.0005330552,0.00011942982,0.0014308698,0.00025886227,8.5947363e-7],"category_scores_gemma":[0.00036943142,0.00015374749,0.0002598229,0.00065457245,0.00037152186,0.00041910325,0.00016886048,0.0004613479,1.07383954e-7],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00014397963,0.00022866667,0.000044075794,0.001471076,0.00011773737,0.0000037933269,0.0010310345,0.008635275,0.7511115,0.008762313,0.00017324841,0.22827731],"study_design_scores_gemma":[0.00095820904,0.0006242038,0.0000018340571,0.0019637914,0.00008828782,0.00024376978,0.0014406143,0.66273266,0.3240154,0.007599592,0.00017900536,0.00015260231],"about_ca_topic_score_codex":0.00001109177,"about_ca_topic_score_gemma":6.2841116e-7,"teacher_disagreement_score":0.9087162,"about_ca_system_score_codex":0.000038714796,"about_ca_system_score_gemma":0.00019521575,"threshold_uncertainty_score":0.6269641},"labels":[],"label_agreement":null},{"id":"W2121208961","doi":"10.1023/a:1015385120447","title":"A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming","year":2002,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Digital Filter Design and Implementation","field":"Computer Science","cited_by":12,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Windsor","funders":"","keywords":"Constant (computer programming); Computer science; Multiplication (music); Genetic programming; Digital signal processing; Parallel computing; Algorithm; Mathematics; Computer hardware; Programming language; Artificial intelligence","score_opus":0.02961118696753076,"score_gpt":0.3054483298543305,"score_spread":0.2758371428867997,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2121208961","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.015297229,0.0030885744,0.9803795,0.00045821126,0.000045986202,0.00068237487,0.00003128603,0.000013891556,0.0000029195226],"genre_scores_gemma":[0.96202576,0.00003278489,0.037838817,0.0000132542555,0.000035647194,0.000022701535,0.0000034633506,0.0000121482,0.000015398795],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.9985305,0.000056316363,0.0008177608,0.0001335993,0.00024277286,0.0002190687],"domain_scores_gemma":[0.9981991,0.00032311928,0.000990419,0.0001234078,0.0003269327,0.000037003938],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00058104,0.00013378453,0.0002808975,0.00029059945,0.0001461502,0.00020527947,0.00051266135,0.000060386665,0.000002126883],"category_scores_gemma":[0.000025278487,0.00008737051,0.00007036668,0.000401193,0.00010513905,0.0010810537,0.00006777833,0.00010813987,8.210076e-8],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.000019876621,0.00005198765,0.00012922255,0.00013021675,0.000034419845,0.0000011263985,0.0009636988,0.00010064941,0.057255913,0.0000698155,0.00049511547,0.940748],"study_design_scores_gemma":[0.0034650771,0.0029270358,0.0001296834,0.0010481266,0.00023408147,0.0004774391,0.00950622,0.7988845,0.17880683,0.003357574,0.0008290658,0.0003343887],"about_ca_topic_score_codex":0.00004634141,"about_ca_topic_score_gemma":0.0000029176585,"teacher_disagreement_score":0.9467285,"about_ca_system_score_codex":0.000037658425,"about_ca_system_score_gemma":0.00006615104,"threshold_uncertainty_score":0.3562866},"labels":[],"label_agreement":null},{"id":"W2137933077","doi":"10.1007/s11265-005-4840-y","title":"IEEE-Compliant IDCT on FPGA-Augmented TriMedia","year":2005,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":4,"is_retracted":false,"has_abstract":false,"route_ca_aff":true,"route_ca_fund":false,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"University of Victoria","funders":"","keywords":"Field-programmable gate array; Computer science; Control reconfiguration; Decoding methods; Parallel computing; Computation; Computer architecture; Scheme (mathematics); Embedded system; Computer hardware; Algorithm; Mathematics","score_opus":0.023469186407768464,"score_gpt":0.29062560529653053,"score_spread":0.26715641888876207,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2137933077","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"methods","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.0077847955,0.008522491,0.9788157,0.003238808,0.00024333154,0.00078522053,0.0000056684235,0.00036093508,0.00024309478],"genre_scores_gemma":[0.9799198,0.00010781947,0.01881264,0.00027562698,0.0005498953,0.000054175318,6.217727e-7,0.00004408929,0.00023534469],"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","domain_scores_codex":[0.99667543,0.00035021693,0.0013616305,0.00039860082,0.00061511854,0.00059899886],"domain_scores_gemma":[0.99643767,0.0006385398,0.0014741077,0.000501843,0.0007933409,0.0001545034],"candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0036568574,0.00040593575,0.0008056759,0.0008883809,0.00043838323,0.00035373963,0.0019357149,0.00030470802,0.000004308803],"category_scores_gemma":[0.00010149399,0.00026576736,0.00017067637,0.0007354013,0.00032806752,0.0010400387,0.00013145787,0.0007245165,0.000014590055],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.00043996712,0.0003595997,0.000029127557,0.00056704984,0.00025981935,0.00011454499,0.0013129757,0.00040137648,0.60579276,0.004531313,0.022768352,0.36342314],"study_design_scores_gemma":[0.0036876833,0.006269539,0.000020651347,0.0035924823,0.0002923678,0.008619334,0.0011616311,0.16955753,0.77233785,0.0141081,0.019226389,0.001126439],"about_ca_topic_score_codex":0.00001237537,"about_ca_topic_score_gemma":0.000001734624,"teacher_disagreement_score":0.972135,"about_ca_system_score_codex":0.00015459953,"about_ca_system_score_gemma":0.0002327988,"threshold_uncertainty_score":0.99997944},"labels":[],"label_agreement":null},{"id":"W2165989566","doi":"10.1007/s11265-006-0022-9","title":"Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse","year":2007,"lang":"en","type":"article","venue":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","topic":"Video Coding and Compression Technologies","field":"Computer Science","cited_by":1,"is_retracted":false,"has_abstract":false,"route_ca_aff":false,"route_ca_fund":true,"route_ca_venue":false,"route_about_ca":false,"ca_institutions":"","funders":"University of Calgary","keywords":"Computer science; Discrete cosine transform; Hardware acceleration; Embedded system; Efficient energy use; Energy consumption; Very-large-scale integration; Obstacle; Computer hardware; Abstraction; Energy (signal processing); Computer architecture; Computer engineering; Field-programmable gate array; Artificial intelligence; Electrical engineering; Image (mathematics); Engineering","score_opus":0.025908373840917792,"score_gpt":0.27427146137749026,"score_spread":0.24836308753657246,"validation_status":"score_only:v0-immature-baseline","prediction":{"id":"W2165989566","genre_codex":"methods","genre_gemma":"empirical","domain_codex":null,"domain_gemma":null,"model_version":"codex-gemma-dda1882f352a","genre_candidate":"empirical","genre_consensus":null,"domain_candidate":null,"domain_consensus":null,"prediction_status":"machine_predicted_unvalidated","genre_scores_codex":[0.025841938,0.027683465,0.9431062,0.002584253,0.00021358184,0.00036707753,0.0000043574523,0.00018140291,0.000017744625],"genre_scores_gemma":[0.9954738,0.0002999213,0.0037705072,0.00016851551,0.00013632486,0.000036303834,2.6824682e-7,0.000020512447,0.00009383286],"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","domain_scores_codex":[0.99812245,0.00007637751,0.00071205414,0.00029227903,0.0003170419,0.00047979705],"domain_scores_gemma":[0.99714166,0.0010287806,0.00078566547,0.00029259012,0.0006645953,0.000086736145],"candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0029110482,0.0002634072,0.00042454057,0.00047659775,0.00095299823,0.0003498997,0.0014752032,0.00023057584,0.0000010301997],"category_scores_gemma":[0.0001775725,0.0001428832,0.0001062743,0.0005778203,0.00033231216,0.00041369768,0.0003408482,0.00040220437,5.597802e-7],"study_design_candidate":"design_other","study_design_consensus":null,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_system_candidate":false,"about_ca_system_consensus":false,"study_design_scores_codex":[0.0003677676,0.00012225621,0.000053088912,0.00045952125,0.00020101135,0.000040204657,0.0010449222,0.0014988346,0.11159996,0.017584873,0.0051672435,0.86186033],"study_design_scores_gemma":[0.0017781903,0.0015221778,0.000026396634,0.0009260362,0.00021225524,0.0018613844,0.004741071,0.75005835,0.21256572,0.01376375,0.012048212,0.00049647316],"about_ca_topic_score_codex":0.000009255217,"about_ca_topic_score_gemma":0.0000029677676,"teacher_disagreement_score":0.96963185,"about_ca_system_score_codex":0.00004147657,"about_ca_system_score_gemma":0.00012087558,"threshold_uncertainty_score":0.7329788},"labels":[],"label_agreement":null}]}