{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":3,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":3,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"8bd72d0a35d3","filters":{"venue":"Circuits and Systems"}},"results":[{"id":"W2147083707","doi":"10.4236/cs.2014.512030","title":"CFOA Based Low Pass and High Pass Ladder Filter—A New Configuration","year":2014,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":13,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Campbell Scientific (Canada)","funders":"","keywords":"High-pass filter; Low-pass filter; Filter (signal processing); Current-feedback operational amplifier; Active filter; Capacitor-input filter; Signal-flow graph; Voltage-controlled filter; Filter design; Engineering; Electronic engineering; Control theory (sociology); Computer science; Operational amplifier; Amplifier; Electrical engineering; Voltage; Artificial intelligence; CMOS","authors":[{"name":"Praween K. Sinha","is_ca":false},{"name":"Akshay Saini","is_ca":false},{"name":"Pranav Kumar","is_ca":false},{"name":"Sumit Mishra","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01262252594202346,"gpt":0.1802083163722476,"spread":0.1675857904302241,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002278671,0.0001819706,0.0002813824,0.00006804714,0.00008661461,0.0001615011,0.00006784966,0.0001314324,0.00003522359],"category_scores_gemma":[0.00002171599,0.0001658185,0.00003058806,0.00007290181,0.00002891024,0.0001140933,0.000004764371,0.0001135496,0.000031666],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00002055427,"about_ca_system_score_gemma":0.00002273041,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001567063,"about_ca_topic_score_gemma":0.00001454635,"domain_scores_codex":[0.9990819,0.00007005993,0.0002442209,0.0002233692,0.0001420654,0.00023844],"domain_scores_gemma":[0.9994456,0.0001052223,0.00004160613,0.0001778003,0.00004006286,0.0001897298],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00001958713,0.00009308159,0.006874351,0.00391779,0.0004948495,0.00007457982,0.002224525,0.02974662,0.1535846,0.4437319,0.1121536,0.2470846],"study_design_scores_gemma":[0.009876567,0.0008698318,0.06865193,0.001978842,0.0004536439,0.0002679548,0.001024786,0.700564,0.01001805,0.009707695,0.1924556,0.004131099],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.04378401,0.001867696,0.9444647,0.00002879299,0.0008640492,0.0003410531,0.00002031381,0.0002645186,0.008364883],"genre_scores_gemma":[0.998684,0.00002416155,0.000003034719,0.00009874802,0.0004032803,0.00001765219,0.00002712648,0.00003107169,0.0007108474],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9549001,"threshold_uncertainty_score":0.6761883,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2028312043","doi":"10.4236/cs.2015.61002","title":"A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop","year":2015,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":2,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Carleton University","funders":"","keywords":"Jitter; Control theory (sociology); Offset (computer science); Phase-locked loop; Charge pump; Loop gain; Delay-locked loop; Phase frequency detector; Detector; Voltage; Electronic engineering; Materials science; Engineering; Electrical engineering; Computer science; Capacitor","authors":[{"name":"Xinjie Wang","is_ca":true},{"name":"T. Kwaśniewski","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.06926467194022638,"gpt":0.303271157622975,"spread":0.2340064856827486,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001891322,0.0001104729,0.0001665121,0.0000780485,0.00005824739,0.00003427367,0.00006799434,0.0000813597,6.558897e-7],"category_scores_gemma":[0.00005169501,0.00009919798,0.00001802398,0.00008539792,0.00003131326,0.0001239381,0.00001298269,0.00007090669,0.000002482927],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00005891167,"about_ca_system_score_gemma":0.00000951371,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000007189467,"about_ca_topic_score_gemma":5.17089e-7,"domain_scores_codex":[0.9993889,0.000009641119,0.0002063179,0.0001401175,0.00007964886,0.0001754007],"domain_scores_gemma":[0.9996805,0.00002205308,0.00003859822,0.000148384,0.00005547352,0.00005505699],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00006413096,0.0002877015,0.0004462721,0.00334102,0.0003656805,0.00003529602,0.003925585,0.03235032,0.3628165,0.009649223,0.03549351,0.5512248],"study_design_scores_gemma":[0.009339878,0.001107272,0.00001956223,0.0009132707,0.0001340206,0.0006211692,0.01840951,0.7486262,0.06257571,0.007042186,0.1496368,0.001574489],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1907256,0.00177197,0.8035161,0.0000235489,0.00117058,0.001433603,0.00006476843,0.0007838482,0.0005098885],"genre_scores_gemma":[0.9982746,0.00004454477,0.0008570145,0.00000387926,0.0000745192,0.0005293658,0.00002201848,0.00002215283,0.0001718783],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.807549,"threshold_uncertainty_score":0.4045176,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2044990188","doi":"10.4236/cs.2011.24050","title":"Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution","year":2011,"lang":"en","type":"article","venue":"Circuits and Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Simon Fraser University","funders":"","keywords":"Vernier scale; Time-to-digital converter; CMOS; Electronic engineering; Detector; Dynamic range; Resolution (logic); Phase detector; Dead time; Delay calculation; Computer science; Electrical engineering; Engineering; Physics; Propagation delay; Voltage; Optics; Telecommunications; Jitter","authors":[{"name":"Chin-Hsin Lin","is_ca":true},{"name":"M. Syrzycki","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02293154224121226,"gpt":0.1817303548176828,"spread":0.1587988125764705,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00005455322,0.0001457611,0.0001738411,0.00006575313,0.00004940409,0.00006340398,0.0000990362,0.00007904592,0.00005145307],"category_scores_gemma":[0.000007538802,0.0001165376,0.00001586001,0.00008691265,0.00005186418,0.0002238913,0.00002784735,0.00007432017,0.0005525604],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00004276556,"about_ca_system_score_gemma":0.000004418579,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000004165917,"about_ca_topic_score_gemma":6.466626e-7,"domain_scores_codex":[0.9993131,0.000006573692,0.0001602872,0.0001780317,0.0001058443,0.0002361557],"domain_scores_gemma":[0.9996678,0.00001196658,0.00002944712,0.000197441,0.00003006849,0.00006328256],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"not_applicable","study_design_scores_codex":[0.0003108563,0.0007103219,0.01702509,0.002659435,0.002019933,0.0008989825,0.012092,0.02366545,0.2808549,0.006154159,0.04502812,0.6085807],"study_design_scores_gemma":[0.004148211,0.0026929,0.003777533,0.001879817,0.0001663261,0.0005331226,0.001847643,0.3638809,0.02631718,0.0003691996,0.5904013,0.003985864],"study_design_candidate":"not_applicable","study_design_consensus":null,"genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.8670633,0.001005134,0.03853289,0.00001053005,0.0003988225,0.0009004633,0.0001163041,0.001447093,0.09052545],"genre_scores_gemma":[0.9952707,0.000007420891,0.00003615132,0.000009780644,0.00003451346,0.00003219442,0.000009417944,0.00002967635,0.004570131],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.6045948,"threshold_uncertainty_score":0.710223,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}