{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":232,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":232,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"5ac9c1114ec6","filters":{"venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"}},"results":[{"id":"W2113645429","doi":"10.1109/tvlsi.2004.824300","title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":416,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Lookup table; Field-programmable gate array; Computer science; Parallel computing; Benchmark (surveying); Cluster (spacecraft); Cluster analysis; Context (archaeology); Logic block; Logic synthesis; Logic gate; Algorithm; Computer hardware; Artificial intelligence","authors":[{"name":"Elias Ahmed","is_ca":true},{"name":"Jonathan Rose","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.00342918692884033,"gpt":0.1893602428445608,"spread":0.1859310559157205,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004436456,0.000228378,0.0002665369,0.00009492645,0.0002649678,0.00007927288,0.00008768544,0.00016533,0.000003692598],"category_scores_gemma":[0.000008536133,0.0001602757,0.00007365141,0.0001310869,0.00007100977,0.0002062305,0.000001268916,0.0003049282,0.00001071094],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001169603,"about_ca_system_score_gemma":0.000009163139,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00004184917,"about_ca_topic_score_gemma":0.000201096,"domain_scores_codex":[0.9989735,0.0001012393,0.0003209293,0.0001997548,0.0001880616,0.0002164471],"domain_scores_gemma":[0.9993083,0.0002723569,0.00005392138,0.0002519274,0.00004940851,0.00006403861],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.002809599,0.0006852028,0.002699005,0.004624898,0.0009759672,0.00002393651,0.009603751,0.2574735,0.404028,0.0006478162,0.002380759,0.3140476],"study_design_scores_gemma":[0.001468877,0.00109782,0.001236086,0.0006231469,0.00008238578,0.00007234038,0.0002705002,0.07715348,0.9172012,0.00002866854,0.0004184428,0.0003470868],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.616466,0.000178067,0.3819433,0.00002549095,0.0004823825,0.0004678368,0.00001791062,0.0001737772,0.0002452389],"genre_scores_gemma":[0.9991997,0.000339894,0.0001172456,0.00001993033,0.00004174826,0.000104121,0.000002114485,0.00002935458,0.0001459042],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.5131732,"threshold_uncertainty_score":0.6535851,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2578985517","doi":"10.1109/tvlsi.2016.2643639","title":"Design of Power and Area Efficient Approximate Multipliers","year":2017,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":393,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada; University of Saskatchewan","keywords":"Multiplier (economics); Approximation error; Lagrange multiplier; Approximation algorithm; Approximation theory; Computer science; Mathematics; Stochastic computing; Mathematical optimization; Algorithm; Arithmetic; Computation","authors":[{"name":"Seok‐Bum Ko","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01452232133591159,"gpt":0.2168836869960683,"spread":0.2023613656601568,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005098407,0.0003410648,0.0004200828,0.0002959998,0.0004633869,0.0002053862,0.0002922233,0.0002222357,0.00004186101],"category_scores_gemma":[0.00001181586,0.0003050297,0.0001017888,0.0001529939,0.0001260665,0.0004419081,0.00000241767,0.0003245571,0.00005531077],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001551356,"about_ca_system_score_gemma":0.00003426509,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003788497,"about_ca_topic_score_gemma":0.00002377651,"domain_scores_codex":[0.9982672,0.00007865659,0.0005500609,0.0003435023,0.0003740189,0.0003865144],"domain_scores_gemma":[0.9986906,0.0000960769,0.0001649391,0.0007558634,0.0001566843,0.0001358355],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001146772,0.0002206716,0.00006663552,0.0002079382,0.0001419779,0.00000562109,0.002331915,0.9388934,0.05565817,0.00007262798,0.0004387299,0.001847646],"study_design_scores_gemma":[0.0009330002,0.0001236348,0.0001799693,0.0003059511,0.00004731027,0.00001736722,0.0007290464,0.885793,0.111358,0.000004391062,0.0001840162,0.0003242455],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1480978,0.0001220377,0.8474805,0.00001501533,0.002494266,0.0007327283,0.0001006537,0.0002550334,0.000701901],"genre_scores_gemma":[0.998154,0.00007380031,0.001201094,0.000008342405,0.0000347901,0.0001662039,0.00000561641,0.00006264407,0.0002935031],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8500562,"threshold_uncertainty_score":0.9999402,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2145787620","doi":"10.1109/tvlsi.2003.819320","title":"A model for battery lifetime analysis for organizing applications on a pocket computer","year":2003,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Advanced Battery Technologies Research","field":"Engineering","cited_by":213,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Victoria","funders":"","keywords":"Battery (electricity); Maximization; Computer science; Computation; Lithium-ion battery; Simulation; Reliability engineering; Automotive engineering; Engineering; Power (physics); Algorithm","authors":[{"name":"Daler Rakhmatov","is_ca":true},{"name":"Sarma Vrudhula","is_ca":false},{"name":"Deborah A. Wallach","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02406220966830701,"gpt":0.2673917669405593,"spread":0.2433295572722523,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003267021,0.000344243,0.0004654632,0.0008446675,0.0003736251,0.0001372368,0.0002843963,0.0002765569,0.00003489566],"category_scores_gemma":[0.00001665659,0.0003381845,0.000336906,0.001059268,0.00004129147,0.0002730774,0.000001728394,0.0003808748,0.00007385711],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0004042108,"about_ca_system_score_gemma":0.00004063831,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000003711921,"about_ca_topic_score_gemma":0.00008007115,"domain_scores_codex":[0.9980133,0.00005993914,0.0005648904,0.0005261856,0.0003017877,0.00053395],"domain_scores_gemma":[0.9985024,0.0003765886,0.00007883423,0.0006655173,0.0002671829,0.0001094603],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003595706,0.0001781503,0.00001226721,0.0001141337,0.000364516,4.108363e-7,0.0001654402,0.9906267,0.004280231,0.0004756752,0.001095598,0.002650954],"study_design_scores_gemma":[0.0005957178,0.0001232795,0.000006192692,0.00005943913,0.0001473965,0.000004592185,0.0003182917,0.9749635,0.02052547,0.0001399628,0.002788074,0.0003280239],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.004469241,0.00005512928,0.9909304,0.00009360188,0.000498986,0.002136036,0.0008738032,0.0008275107,0.000115256],"genre_scores_gemma":[0.9721573,0.00002595489,0.02237784,0.0001243637,0.00008574081,0.00424698,0.0001156095,0.0001009743,0.0007652292],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9685526,"threshold_uncertainty_score":0.999907,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2158959564","doi":"10.1109/tvlsi.2003.810787","title":"A digitally programmable delay element: design and analysis","year":2003,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":168,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Delay calculation; Group delay and phase delay; Elmore delay; Delay-locked loop; Computer science; Electronic engineering; Propagation delay; Digital delay line; Electronic circuit; Static timing analysis; Delay line oscillator; Control theory (sociology); Engineering; Electrical engineering; Digital signal processing; Digital signal; Telecommunications; Phase-locked loop; Control (management)","authors":[{"name":"Mohammad Maymandi‐Nejad","is_ca":true},{"name":"Manoj Sachdev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01251244688518255,"gpt":0.2259897415152469,"spread":0.2134772946300644,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0002874028,0.0002710735,0.0003194159,0.0003990229,0.0002122989,0.0001832524,0.0001224933,0.0001565656,0.00004786517],"category_scores_gemma":[0.000008450117,0.0002414315,0.0001258048,0.0007998784,0.00004889865,0.0004569827,9.958108e-7,0.0002464277,0.00003073796],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001431059,"about_ca_system_score_gemma":0.00001656809,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00001051727,"about_ca_topic_score_gemma":0.00007711173,"domain_scores_codex":[0.998566,0.00007271043,0.0004333182,0.0003140349,0.0002462491,0.0003677325],"domain_scores_gemma":[0.99938,0.0000701387,0.00006007245,0.0003306712,0.00008079899,0.0000783292],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003378388,0.0002698556,0.0001836887,0.00008748646,0.001024419,0.000009120276,0.0003943233,0.9711168,0.001490174,0.001065107,0.000332872,0.02399236],"study_design_scores_gemma":[0.001216814,0.000403905,0.000041954,0.0001678435,0.0006896083,0.00004320667,0.003074315,0.898975,0.06816996,0.0003666552,0.02595359,0.0008971713],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01080405,0.0003473234,0.9856802,0.00001057874,0.0006213541,0.0005971813,0.00007173591,0.000763119,0.001104427],"genre_scores_gemma":[0.9907349,0.0002048717,0.007581547,0.00001267415,0.00001347195,0.0003983798,0.00001702279,0.00003336766,0.001003748],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9799309,"threshold_uncertainty_score":0.9845291,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2000956074","doi":"10.1109/tvlsi.2012.2232321","title":"Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function","year":2014,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Neural Networks and Applications","field":"Computer Science","cited_by":160,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Windsor","funders":"","keywords":"Hyperbolic function; Activation function; Sigmoid function; Artificial neural network; Very-large-scale integration; Tangent; Nonlinear system; Computer science; Adder; Function (biology); Transfer function; Function approximation; Inverse trigonometric functions; Algorithm; Mathematics; Topology (electrical circuits); Mathematical analysis; Artificial intelligence; Engineering; Telecommunications","authors":[{"name":"Babak Zamanlooy","is_ca":true},{"name":"Mitra Mirhassani","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.009279577385021536,"gpt":0.2313607662454921,"spread":0.2220811888604706,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004001316,0.0002975537,0.0003138626,0.0002498987,0.000419894,0.0001882422,0.0003379679,0.0001327262,0.00002764134],"category_scores_gemma":[0.000002330854,0.0002440493,0.0001447455,0.0009095986,0.00004785878,0.0004212606,0.000004619331,0.0003052888,0.00001871034],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001419508,"about_ca_system_score_gemma":0.00004136428,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001889441,"about_ca_topic_score_gemma":0.0003197594,"domain_scores_codex":[0.997632,0.0002354123,0.0006400481,0.0005653971,0.0005469699,0.0003801399],"domain_scores_gemma":[0.9984094,0.0001358328,0.0003725067,0.0006448627,0.0003069752,0.0001304248],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00008143992,0.0003016111,0.00007518414,0.00002954727,0.00004733856,3.782001e-7,0.0003860986,0.9444061,0.005163615,0.003601542,0.000250295,0.04565684],"study_design_scores_gemma":[0.0007968833,0.0005431972,0.0009688488,0.00008913482,0.00005446231,0.00001120029,0.0005163764,0.9823036,0.01380553,0.00002339476,0.0006269031,0.0002604209],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1613812,0.00002323783,0.8361398,0.0002539535,0.00109484,0.0007674756,0.00001940387,0.0001919128,0.0001282212],"genre_scores_gemma":[0.9981862,0.00001040341,0.0008732773,0.0001729487,0.0002076577,0.0003643768,0.00003363548,0.00002851216,0.0001229359],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8368051,"threshold_uncertainty_score":0.995204,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2980235527","doi":"10.1109/tvlsi.2019.2940943","title":"Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers","year":2019,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":147,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"MNIST database; Computer science; Artificial neural network; Convolutional neural network; Noise (video); Multiplication (music); Artificial intelligence; Efficient energy use; Computer engineering; Deep neural networks; Machine learning; Algorithm; Mathematics","authors":[{"name":"Mohammad Saeed Ansari","is_ca":true},{"name":"Vojtěch Mrázek","is_ca":false},{"name":"B.F. Cockburn","is_ca":true},{"name":"Lukáš Sekanina","is_ca":false},{"name":"Zdeněk Vašíček","is_ca":false},{"name":"Jie Han","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.009042114404894398,"gpt":0.2074460499332867,"spread":0.1984039355283924,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.000429684,0.0003116255,0.0003539986,0.0002129483,0.0002609814,0.0001445178,0.0002347296,0.0001838725,0.00002417062],"category_scores_gemma":[0.000009434496,0.0002359498,0.0001181437,0.0004561433,0.00006752156,0.0006568336,0.000003025173,0.000486251,0.00001400319],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001502957,"about_ca_system_score_gemma":0.00002895373,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001072694,"about_ca_topic_score_gemma":0.00003764263,"domain_scores_codex":[0.9982796,0.0001003292,0.0005722405,0.0003178527,0.0003179752,0.0004119756],"domain_scores_gemma":[0.9989727,0.0001966548,0.0001463404,0.0004735264,0.000129108,0.00008164537],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003300012,0.00004654426,0.0001356588,0.0002003782,0.00004335812,9.069994e-7,0.0009980409,0.961917,0.03339337,0.00001626003,0.00002905582,0.003186452],"study_design_scores_gemma":[0.0005628258,0.00006895765,0.00005253799,0.0001869545,0.00004660006,0.00002261646,0.001472808,0.9722354,0.0250579,7.412006e-7,0.00004928291,0.0002434244],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.4105749,0.0002024511,0.5860934,0.000005825746,0.002241462,0.0006274537,0.00003799919,0.0001591979,0.00005735827],"genre_scores_gemma":[0.999318,0.00004233012,0.000309237,0.00001668111,0.00008317886,0.00006703111,0.00000759861,0.00006042117,0.00009552107],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.5887432,"threshold_uncertainty_score":0.9621754,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W1978112103","doi":"10.1109/tvlsi.2014.2334642","title":"A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique","year":2014,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":140,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"McGill University","funders":"","keywords":"CMOS; Low-noise amplifier; Wideband; Electrical engineering; Amplifier; Electronic engineering; Noise figure; Bandwidth (computing); Integrated circuit design; Biasing; Physics; Computer science; Voltage; Engineering; Telecommunications","authors":[{"name":"Mahdi Parvizi","is_ca":true},{"name":"Karim Allidina","is_ca":true},{"name":"Mourad N. El-Gamal","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01107317284142998,"gpt":0.2092329269637931,"spread":0.1981597541223631,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001217025,0.0008137118,0.0007847244,0.0007403506,0.0003953897,0.0003537667,0.000527372,0.0007339107,0.0001496523],"category_scores_gemma":[0.00005074257,0.0007748698,0.0003731836,0.0009985572,0.0001190421,0.0008201019,3.716065e-7,0.001197678,0.0005647603],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0007351555,"about_ca_system_score_gemma":0.0001131375,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001519684,"about_ca_topic_score_gemma":0.0001790628,"domain_scores_codex":[0.9959053,0.0005203261,0.001196904,0.0007849286,0.0006947049,0.0008978465],"domain_scores_gemma":[0.9976025,0.0004449111,0.0001691366,0.00107725,0.0003538986,0.0003523339],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.00005638507,0.0002301252,0.00000868412,0.0002102357,0.0001470415,0.00001453907,0.0004878314,0.2104881,0.7803562,0.0002924279,0.004100733,0.003607626],"study_design_scores_gemma":[0.0007356464,0.0002102543,0.00001209199,0.0008542613,0.00009325139,0.000130773,0.0003227415,0.09673119,0.8979462,0.0001779712,0.001959302,0.0008263607],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.006769244,0.0001556279,0.9774247,0.00002428916,0.003787175,0.002062387,0.0002146252,0.001770959,0.007791008],"genre_scores_gemma":[0.995884,0.0001432677,0.0004384507,0.00009970352,0.0002624056,0.001827546,0.00004239722,0.0002244379,0.001077786],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9891148,"threshold_uncertainty_score":0.9994702,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2953289753","doi":"10.1109/tvlsi.2019.2922999","title":"Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA","year":2019,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptography and Data Security","field":"Computer Science","cited_by":135,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":false,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"","funders":"Engineering and Physical Sciences Research Council; Fundamental Research Funds for the Central Universities; Government of Jiangsu Province; Six Talent Peaks Project in Jiangsu Province; Queen's University; National Natural Science Foundation of China; Queen's University Belfast","keywords":"Field-programmable gate array; Computer science; Lattice-based cryptography; Speedup; Cryptography; Multiplication (music); Throughput; Parallel computing; Computer hardware; Algorithm; Mathematics; Quantum; Quantum cryptography; Physics; Quantum information","authors":[{"name":"Weiqiang Liu","is_ca":false},{"name":"Sailong Fan","is_ca":false},{"name":"Ayesha Khalid","is_ca":false},{"name":"Ciara Rafferty","is_ca":false},{"name":"Máire O׳Neill","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01530187227589272,"gpt":0.2526773690943855,"spread":0.2373754968184928,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007250784,0.0004522478,0.0005245042,0.0008156427,0.0005188521,0.0005644463,0.0008030182,0.0003006015,0.00007002998],"category_scores_gemma":[0.00001541612,0.0004155508,0.0006348644,0.000874128,0.0000632966,0.001154642,0.000003342539,0.0005034633,0.0002961204],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001888733,"about_ca_system_score_gemma":0.0001415453,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001321385,"about_ca_topic_score_gemma":0.0000845449,"domain_scores_codex":[0.9968672,0.0002941359,0.0007383978,0.0009494527,0.0006021056,0.000548699],"domain_scores_gemma":[0.9971329,0.0006088483,0.0003094582,0.001382519,0.0003199916,0.0002462777],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.01255665,0.01822642,0.001159773,0.001627647,0.001660573,0.0000166227,0.006851999,0.6371203,0.06504135,0.1593687,0.0474494,0.04892059],"study_design_scores_gemma":[0.00741486,0.00110766,0.0004202501,0.0004501579,0.0000853384,0.000009000726,0.0004237392,0.924354,0.05082706,0.0002548856,0.01375015,0.0009029206],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01734722,0.00005487313,0.9745495,0.0003712027,0.003402894,0.002337891,0.0007983184,0.0005110459,0.0006270375],"genre_scores_gemma":[0.9787369,0.00001410481,0.01994868,0.0004232383,0.0001655683,0.0004162811,0.0001593581,0.00004024956,0.00009556167],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9613897,"threshold_uncertainty_score":0.9998296,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W1988102072","doi":"10.1109/92.994977","title":"Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies","year":2002,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":134,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Domino logic; Domino; Cascode; CMOS; Electronic engineering; Standby power; Computer science; Logic gate; Overhead (engineering); Dynamic demand; Engineering; Reliability (semiconductor); Dynamic logic (digital electronics); Pass transistor logic; Electrical engineering; Power (physics); Voltage; Transistor; Logic synthesis; Logic family","authors":[{"name":"Mohab Anis","is_ca":true},{"name":"M.W. Allam","is_ca":false},{"name":"M.I. Elmasry","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.007794041568643099,"gpt":0.1937992313350795,"spread":0.1860051897664364,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002732305,0.0005041767,0.000512893,0.0005733584,0.000432546,0.000208028,0.0002766532,0.0003981828,0.0000516554],"category_scores_gemma":[0.000007457863,0.0004515764,0.0001952955,0.0005147711,0.0001183622,0.0004058939,0.000002759711,0.0003986958,0.00008835244],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0003487942,"about_ca_system_score_gemma":0.00001827548,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003243046,"about_ca_topic_score_gemma":0.0002244076,"domain_scores_codex":[0.9976727,0.00006416005,0.0007049645,0.0005388454,0.0004039,0.0006154336],"domain_scores_gemma":[0.9989127,0.0001564192,0.00009856527,0.0005602214,0.0001556147,0.0001164606],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001260689,0.0008289635,0.0000296555,0.0007078312,0.0003476731,0.00001359091,0.002173436,0.8507745,0.05221055,0.000794113,0.003870112,0.08812346],"study_design_scores_gemma":[0.0009845241,0.0001736651,0.00001349831,0.0003067612,0.0000688213,0.00004084578,0.001738007,0.9495854,0.04295013,0.00001443901,0.00362433,0.0004995825],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.09284844,0.001258276,0.9001518,0.0001127987,0.002165659,0.000955171,0.0003528055,0.001710938,0.0004440812],"genre_scores_gemma":[0.9965761,0.000399022,0.0007284237,0.00002636376,0.00006523253,0.0009665401,0.00002171918,0.0001014467,0.001115182],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9037277,"threshold_uncertainty_score":0.9997936,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2105551687","doi":"10.1109/tvlsi.2005.850098","title":"Global passivity enforcement algorithm for macromodels of interconnect subnetworks characterized by tabulated data","year":2005,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Electrostatic Discharge in Electronics","field":"Engineering","cited_by":126,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Carleton University","funders":"","keywords":"Passivity; Interconnection; Computer science; Enforcement; Transient (computer programming); Algorithm; Control theory (sociology); Electronic engineering; Engineering; Computer network; Electrical engineering; Artificial intelligence; Control (management)","authors":[{"name":"D. Saraswat","is_ca":true},{"name":"Ramachandra Achar","is_ca":true},{"name":"M. Nakhla","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01215667967682705,"gpt":0.2488577853227062,"spread":0.2367011056458792,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005855538,0.0004302971,0.0005924419,0.0001330738,0.0001518585,0.0001182111,0.0005125429,0.0002754107,0.0001100915],"category_scores_gemma":[0.000006089657,0.0004277197,0.000182592,0.0003937199,0.00004292197,0.0007919689,0.000004402339,0.000361408,0.00002262337],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0006547112,"about_ca_system_score_gemma":0.00007870545,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00008707164,"about_ca_topic_score_gemma":0.000620519,"domain_scores_codex":[0.9972843,0.000114434,0.0009882963,0.0005108174,0.0004075896,0.0006945922],"domain_scores_gemma":[0.9985301,0.0001357424,0.0001944958,0.0007970068,0.0002031608,0.0001394294],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0004852198,0.00176897,0.00001387501,0.0006311756,0.001566765,0.00000380115,0.00109477,0.4304393,0.06645644,0.0009647292,0.01459707,0.4819779],"study_design_scores_gemma":[0.001297141,0.0002104865,0.000001397844,0.0001788139,0.0001088602,0.00001597512,0.0001438489,0.942058,0.04381673,0.00003210049,0.01176664,0.0003700347],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01681298,0.0005174667,0.9722923,0.0000465832,0.001427528,0.001491909,0.006886529,0.0003533204,0.0001713862],"genre_scores_gemma":[0.9944158,0.0002439252,0.002746516,0.00004666784,0.000187195,0.00053207,0.00137511,0.00007626749,0.0003764984],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9776028,"threshold_uncertainty_score":0.9998175,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2141825982","doi":"10.1109/tvlsi.2005.853609","title":"MOS current mode circuits: analysis, design, and variability","year":2005,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":125,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Electronic circuit; Electronic engineering; CMOS; Current-mode logic; Computer science; Integrated circuit design; Circuit design; Logic gate; Integrated circuit; Engineering; Electrical engineering","authors":[{"name":"Hossam Hassan","is_ca":true},{"name":"Mohab Anis","is_ca":true},{"name":"M. Elmasry","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01535185714347722,"gpt":0.2385529517374107,"spread":0.2232010945939334,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008271689,0.000378232,0.0005261353,0.00045696,0.0002618152,0.0001529367,0.0001721966,0.0002292685,0.0001053012],"category_scores_gemma":[0.00000952096,0.0003602605,0.0002581571,0.0007568079,0.00006349655,0.0004831828,8.743457e-7,0.0005118472,0.0001009488],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0003583716,"about_ca_system_score_gemma":0.00005069988,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006781413,"about_ca_topic_score_gemma":0.0002470705,"domain_scores_codex":[0.9976576,0.0003630224,0.0006810391,0.0004940256,0.0003792863,0.0004250475],"domain_scores_gemma":[0.9988763,0.0002055993,0.0000791432,0.0004598793,0.0001585754,0.0002204877],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00001900184,0.0002628026,0.00004272375,0.0000974654,0.0004594949,0.000001847221,0.0008174598,0.9644158,0.005184389,0.0009807805,0.0006290648,0.0270892],"study_design_scores_gemma":[0.0005551419,0.00007108489,0.00008319062,0.0001076344,0.0006039041,0.00001633889,0.0003280359,0.984489,0.01064765,0.0002046135,0.002403246,0.0004901923],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.006956469,0.000723111,0.9893837,0.00001131477,0.001084307,0.0006404402,0.0002065048,0.0004786911,0.0005154791],"genre_scores_gemma":[0.9988247,0.0002201062,0.0001834046,0.00002668951,0.0001690965,0.0002371954,0.00003526622,0.00004464902,0.0002588661],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9918683,"threshold_uncertainty_score":0.999885,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2806161090","doi":"10.1109/tvlsi.2018.2834499","title":"Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review","year":2018,"lang":"en","type":"review","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Silicon Carbide Semiconductor Technologies","field":"Engineering","cited_by":120,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"Polytechnique Montréal","funders":"Natural Sciences and Engineering Research Council of Canada; Airbus","keywords":"Electronics; Automotive industry; Silicon carbide; Reliability (semiconductor); Engineering physics; Aerospace; Gallium nitride; Materials science; Computer science; Electrical engineering; Systems engineering; Nanotechnology; Engineering; Aerospace engineering; Power (physics)","authors":[{"name":"Ahmad Hassan","is_ca":true},{"name":"Yvon Savaria","is_ca":true},{"name":"Mohamad Sawan","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02612958261445177,"gpt":0.2801043522608521,"spread":0.2539747696464004,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005726459,0.0007814774,0.001609758,0.0005202512,0.0002447909,0.0001362549,0.0004207304,0.0005826156,0.00004126826],"category_scores_gemma":[0.0000212561,0.000717954,0.0005658615,0.0004489536,0.0001052045,0.0002823295,0.000005054285,0.0008676606,0.0001199577],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0008727633,"about_ca_system_score_gemma":0.0000796732,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000007457691,"about_ca_topic_score_gemma":0.00003422461,"domain_scores_codex":[0.9969164,0.0001275692,0.001275068,0.0007907325,0.0003022383,0.0005879716],"domain_scores_gemma":[0.9982715,0.0002368905,0.0003129581,0.0009595186,0.0001068269,0.0001122769],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"not_applicable","study_design_scores_codex":[0.000005543127,0.0000917704,1.896081e-7,0.05085019,0.0005970201,0.000001327709,0.0001212642,0.000229829,0.0003309262,0.0002035258,0.004188839,0.9433796],"study_design_scores_gemma":[0.0002184713,0.00008136757,3.612396e-8,0.02781544,0.0009176888,0.00007806245,0.0002854521,0.006147467,0.0007622864,0.00003563921,0.9629502,0.0007078672],"study_design_candidate":"not_applicable","study_design_consensus":null,"genre_codex":"review","genre_gemma":"review","genre_scores_codex":[0.000005446911,0.6665573,0.328257,0.00001982361,0.0007971001,0.003242099,0.0003914677,0.0006757815,0.0000540956],"genre_scores_gemma":[0.0004441288,0.9896114,0.0003668055,0.00003858978,0.000179276,0.008691935,0.0001657065,0.0001913726,0.0003107573],"genre_candidate":"review","genre_consensus":"review","teacher_disagreement_score":0.9587614,"threshold_uncertainty_score":0.9995272,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2019828391","doi":"10.1109/tvlsi.2003.816139","title":"Low-leakage asymmetric-cell SRAM","year":2003,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":105,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Leakage (economics); Static random-access memory; Leakage power; Sense amplifier; Degradation (telecommunications); Computer science; Electronic engineering; Transistor; Electrical engineering; Engineering; Semiconductor memory; Computer hardware; Voltage","authors":[{"name":"Navid Azizi","is_ca":true},{"name":"Farid N. Najm","is_ca":true},{"name":"Andreas Moshovos","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.006963472649608291,"gpt":0.1959009477767522,"spread":0.1889374751271439,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0006144618,0.0005535858,0.0005191425,0.0008273274,0.0003404069,0.0002505005,0.0003136488,0.0004077979,0.0002689043],"category_scores_gemma":[0.00001354535,0.00053171,0.0002805584,0.001368165,0.00004803497,0.0008449867,0.000001048141,0.000781063,0.001843007],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0005098179,"about_ca_system_score_gemma":0.0000730124,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0000398356,"about_ca_topic_score_gemma":0.0001003606,"domain_scores_codex":[0.9970357,0.0002138989,0.0008425274,0.0005220466,0.0006499615,0.0007358011],"domain_scores_gemma":[0.99854,0.000161757,0.0001083919,0.0007521544,0.0001838434,0.0002538336],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0001082193,0.001911414,0.0001337078,0.0009977157,0.000378233,0.00005698477,0.002906579,0.8969299,0.06631158,0.001123649,0.01939228,0.009749786],"study_design_scores_gemma":[0.002075016,0.0003072796,0.00005359309,0.0003690975,0.0001157089,0.00006981706,0.001682589,0.2772976,0.6872496,0.00001895153,0.02959576,0.001165023],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.06539812,0.0003610571,0.9040891,0.00001521796,0.008318684,0.0008251905,0.0001471032,0.001048131,0.01979742],"genre_scores_gemma":[0.9944505,0.0001373097,0.000628509,0.00005995234,0.0001556118,0.0002875428,0.00002312824,0.0001426971,0.004114748],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9290524,"threshold_uncertainty_score":0.9997134,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2169957670","doi":"10.1109/tvlsi.2009.2031651","title":"A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptographic Implementations and Security","field":"Computer Science","cited_by":104,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Western University","funders":"National Institute of Standards and Technology","keywords":"Advanced Encryption Standard; Fault injection; Encryption; Computer science; Overhead (engineering); Inverse; AES implementations; Fault detection and isolation; Embedded system; Fault (geology); Algorithm; Error detection and correction; Computer engineering; Parallel computing; Cryptography; Mathematics; Software; Artificial intelligence","authors":[{"name":"Mehran Mozaffari Kermani","is_ca":true},{"name":"Arash Reyhani-Masoleh","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01471307471530304,"gpt":0.2676813202781219,"spread":0.2529682455628188,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["sts"],"consensus_categories":[],"category_scores_codex":[0.0005158991,0.0002686276,0.0002677064,0.0003008034,0.001315398,0.0003927873,0.0003875297,0.000160859,0.00001457229],"category_scores_gemma":[0.000005250015,0.0002087881,0.0001925532,0.0007510131,0.00003652619,0.001169517,0.000002694903,0.0003311211,0.000008889521],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002139472,"about_ca_system_score_gemma":0.0000614941,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00009323114,"about_ca_topic_score_gemma":0.0003687559,"domain_scores_codex":[0.9979777,0.0001182855,0.0005863702,0.0004591512,0.0004740973,0.0003844053],"domain_scores_gemma":[0.9986237,0.000159571,0.0002123816,0.0005507338,0.0003706902,0.00008287091],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.001309704,0.001272653,0.00008548937,0.0002279669,0.0003577234,0.000005632277,0.008668175,0.2282371,0.2549356,0.01844544,0.0004969483,0.4859576],"study_design_scores_gemma":[0.001297183,0.0006648546,0.000256625,0.0001326725,0.00004726879,0.00002565278,0.0005490607,0.8607133,0.1338172,0.0002522809,0.001933253,0.0003106922],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2575313,0.00006848671,0.7390504,0.0002938171,0.001936491,0.0008466478,0.00007500483,0.0001716544,0.00002614126],"genre_scores_gemma":[0.9866848,0.00008398071,0.01262255,0.00017961,0.0001281284,0.0002074704,0.00001622407,0.00001402823,0.00006323365],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7291535,"threshold_uncertainty_score":0.9999847,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2094621017","doi":"10.1109/tvlsi.2011.2109404","title":"Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron","year":2011,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":102,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Windsor","funders":"","keywords":"Sigmoid function; NMOS logic; PMOS logic; Activation function; CMOS; Computer science; Electronic engineering; Artificial neural network; Voltage; Transistor; Electrical engineering; Artificial intelligence; Engineering","authors":[{"name":"Golnar Khodabandehloo","is_ca":true},{"name":"Mitra Mirhassani","is_ca":true},{"name":"Majid Ahmadi","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.03233366874871141,"gpt":0.2463742559712598,"spread":0.2140405872225484,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003051282,0.0002694336,0.000335429,0.0003423977,0.0001431247,0.00003513938,0.0001618258,0.0001644865,0.0002165115],"category_scores_gemma":[0.000004606399,0.0002646307,0.0001641461,0.0004525267,0.00004432526,0.0003341396,7.616535e-7,0.0002869636,0.00006155505],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000137866,"about_ca_system_score_gemma":0.00005420214,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0005435373,"about_ca_topic_score_gemma":0.0009430244,"domain_scores_codex":[0.9983469,0.0001067176,0.0006281258,0.0002938848,0.0003115243,0.0003128113],"domain_scores_gemma":[0.9991938,0.0000668314,0.0001190983,0.000294807,0.0002186301,0.0001067739],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0006989223,0.002027198,0.0007900183,0.0008532104,0.001086568,0.0000370109,0.01440276,0.1133907,0.8233919,0.01446569,0.005464497,0.02339157],"study_design_scores_gemma":[0.005824924,0.002588931,0.007313975,0.0007793851,0.0007402472,0.0001203197,0.0199803,0.1444523,0.8132351,0.0002996205,0.002626101,0.002038836],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.07429507,0.00009770182,0.9210676,0.000002340699,0.001774879,0.0004270536,0.0002369719,0.0002332377,0.001865151],"genre_scores_gemma":[0.9992129,0.00004127732,0.000119786,0.00002124274,0.00007968265,0.0000766399,0.00003566382,0.00005008618,0.0003627673],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9249178,"threshold_uncertainty_score":0.9999806,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2122084979","doi":"10.1109/tvlsi.2008.2010941","title":"Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":99,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"St. Francis Xavier University","funders":"","keywords":"Dynamic voltage scaling; Scheduling (production processes); Computer science; Voltage; Energy consumption; Dissipation; Leakage (economics); Algorithm; Electronic engineering; Mathematical optimization; Electrical engineering; Engineering; Mathematics; Physics","authors":[{"name":"Meikang Qiu","is_ca":false},{"name":"Laurence T. Yang","is_ca":true},{"name":"Zili Shao","is_ca":false},{"name":"Edwin H.‐M. Sha","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.006269244762138148,"gpt":0.2193619970504954,"spread":0.2130927522883573,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000300452,0.0002941937,0.0003100743,0.000322378,0.0004309241,0.0004304344,0.0002269095,0.0001677602,0.000006913201],"category_scores_gemma":[0.000005749032,0.0002563213,0.00005436089,0.0004171259,0.00005141104,0.0007076585,0.000004181496,0.0001943401,0.000006984631],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001244256,"about_ca_system_score_gemma":0.00005898307,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006872941,"about_ca_topic_score_gemma":0.00004613689,"domain_scores_codex":[0.9981434,0.0001639615,0.0004358835,0.0005985855,0.0003601948,0.000298019],"domain_scores_gemma":[0.9990005,0.00009739646,0.0001910016,0.0004024058,0.0001668897,0.0001417833],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0002199221,0.001105448,0.00007002012,0.0001081973,0.000151752,0.0000345858,0.003537774,0.8606358,0.02941036,0.006980943,0.0007249871,0.09702018],"study_design_scores_gemma":[0.0005222441,0.0003938276,0.00007712816,0.0002289367,0.00002229468,0.00005083117,0.0001715523,0.9924211,0.005539522,0.00009249663,0.0001737534,0.0003062946],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01050507,0.0001190745,0.9876094,0.0001920427,0.0002417544,0.0002942089,0.00001476313,0.0006365476,0.0003871596],"genre_scores_gemma":[0.9580803,0.0002240923,0.03992903,0.0001216282,0.00002550635,0.0000422376,0.00001760153,0.00002073796,0.001538847],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9476804,"threshold_uncertainty_score":0.9999889,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2794935685","doi":"10.1109/tvlsi.2018.2812214","title":"Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences","year":2018,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":91,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada; China Scholarship Council","keywords":"Stochastic computing; Sobol sequence; Computer science; Parallel computing; Random number generation; Electronic circuit; Algorithm; Efficient energy use; Binary number; Computation; Pseudorandom number generator; Mathematics; Monte Carlo method; Arithmetic; Engineering; Statistics","authors":[{"name":"Siting Liu","is_ca":true},{"name":"Jie Han","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.04107774159824099,"gpt":0.277744882069191,"spread":0.23666714047095,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007352582,0.000427333,0.0004263234,0.0005636933,0.0007709105,0.000458168,0.0009416764,0.0002634978,0.00003121351],"category_scores_gemma":[0.00002413797,0.0003962029,0.0002301161,0.001005637,0.0001632324,0.0007009186,0.000009777355,0.0004130371,0.0001106414],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0004945837,"about_ca_system_score_gemma":0.0002402233,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0007220802,"about_ca_topic_score_gemma":0.0004979547,"domain_scores_codex":[0.9965594,0.0003582097,0.000744114,0.0008947377,0.0008122633,0.0006312086],"domain_scores_gemma":[0.9978437,0.0001839254,0.0003017115,0.000915472,0.0005573556,0.000197818],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001168196,0.001903595,0.00003216496,0.0001823016,0.0002905217,0.00006333121,0.02109242,0.8373386,0.07136745,0.02003462,0.001556198,0.04602195],"study_design_scores_gemma":[0.0002924754,0.0003044961,0.000007499521,0.000401992,0.00003206401,0.0001585786,0.0007630585,0.9627333,0.03439787,0.000232784,0.0002146245,0.0004612614],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01572081,0.00008633168,0.9754093,0.0001090073,0.006289106,0.0005098537,0.00003396978,0.001244099,0.0005974809],"genre_scores_gemma":[0.9904293,0.000006652902,0.008475357,0.0001526763,0.0002773032,0.0001782964,0.000003914405,0.00004102335,0.0004354744],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9747085,"threshold_uncertainty_score":0.999849,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2085540322","doi":"10.1109/tvlsi.2011.2158595","title":"Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis","year":2011,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptography and Residue Arithmetic","field":"Computer Science","cited_by":79,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"Western University","funders":"Division of Electrical, Communications and Cyber Systems; CMC Microsystems","keywords":"Elliptic curve cryptography; Hessian matrix; Lookup table; Elliptic curve point multiplication; Multiplication (music); Elliptic curve; Binary number; Edwards curve; Mathematics; Computer science; Parallel computing; Arithmetic; Algorithm; Applied mathematics; Combinatorics; Schoof's algorithm; Pure mathematics; Encryption; Public-key cryptography","authors":[{"name":"Reza Azarderakhsh","is_ca":true},{"name":"Arash Reyhani-Masoleh","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02770676403880055,"gpt":0.2670120190335478,"spread":0.2393052549947472,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0005001448,0.0002623208,0.0003114582,0.0005873707,0.0004694387,0.00008950717,0.0002998187,0.0001181298,0.00005707434],"category_scores_gemma":[0.000005514912,0.0002251235,0.0002033452,0.0007085874,0.00009593721,0.0003027206,0.000006426014,0.0002143946,0.00001210417],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00008899107,"about_ca_system_score_gemma":0.00006382837,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0008598232,"about_ca_topic_score_gemma":0.0002656477,"domain_scores_codex":[0.9977809,0.0003108757,0.0006703339,0.0004976201,0.0004261829,0.0003140764],"domain_scores_gemma":[0.998749,0.00008703457,0.0002572644,0.0005732175,0.0001878912,0.0001456348],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.002153405,0.02330417,0.006368637,0.004670491,0.002639809,0.0001140152,0.1040554,0.3802366,0.2420561,0.07565103,0.004158005,0.1545924],"study_design_scores_gemma":[0.002767296,0.0009724105,0.01292809,0.001521981,0.0002279663,0.0001040364,0.003037572,0.7878017,0.1893399,0.0001390118,0.0002752506,0.0008847645],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1769188,0.0001553065,0.8207852,0.0002228509,0.0007911043,0.0006040579,0.0001363876,0.000106753,0.0002795411],"genre_scores_gemma":[0.9890704,0.00008748692,0.01046739,0.000122063,0.00003376208,0.0001360343,0.00001293953,0.00001903541,0.00005090099],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8121516,"threshold_uncertainty_score":0.9180269,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2164095419","doi":"10.1109/tvlsi.2006.878259","title":"Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":77,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Polytechnique Montréal; STMicroelectronics (Canada)","funders":"","keywords":"Computer science; Multiprocessing; Interoperability; Encoder; Computer architecture; Scheduling (production processes); Programming paradigm; Embedded system; Symmetric multiprocessor system; Operating system; Programming language","authors":[{"name":"Pierre Paulin","is_ca":true},{"name":"Chuck Pilkington","is_ca":true},{"name":"M. Langevin","is_ca":true},{"name":"Essaid Bensoudane","is_ca":true},{"name":"D. Lyonnard","is_ca":true},{"name":"Olivier Benny","is_ca":true},{"name":"Bruno Lavigueur","is_ca":true},{"name":"David Lo","is_ca":true},{"name":"Giovanni Beltrame","is_ca":true},{"name":"Vincent Gagné","is_ca":true},{"name":"Gabriela Nicolescu","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02133919429732502,"gpt":0.2389249474259229,"spread":0.2175857531285978,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007152344,0.0003898106,0.0004783841,0.0003220657,0.0006826567,0.0006998303,0.0003826239,0.0002681072,0.000003157995],"category_scores_gemma":[0.000003973166,0.000349289,0.0001898493,0.0005111849,0.00003424339,0.0008378191,0.000006063966,0.000293558,0.00002410317],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001831588,"about_ca_system_score_gemma":0.00005332835,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0002996399,"about_ca_topic_score_gemma":0.001364845,"domain_scores_codex":[0.9972279,0.0000663394,0.0008343387,0.0007965852,0.0004186042,0.0006562101],"domain_scores_gemma":[0.9986421,0.0002144055,0.0002276996,0.0004407745,0.0002855808,0.0001893996],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0002627714,0.0004895213,0.00001504875,0.0001994693,0.0001040276,0.00000400845,0.005638584,0.8833098,0.001363318,0.01181123,0.001889181,0.09491301],"study_design_scores_gemma":[0.001182311,0.000169612,0.000007850529,0.0002550395,0.00002180319,0.00002790186,0.0008951481,0.9895676,0.001071023,0.0003162976,0.006071656,0.0004136914],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.003644323,0.0001312242,0.9893429,0.0001325827,0.003538559,0.002281964,0.00003939295,0.0004327762,0.0004562521],"genre_scores_gemma":[0.9667255,0.000008390126,0.02940504,0.0001204476,0.0006500797,0.002044878,0.00001959597,0.00004410433,0.000981996],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9630811,"threshold_uncertainty_score":0.9998959,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2159795949","doi":"10.1109/tvlsi.2008.2004592","title":"Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Interconnection Networks and Systems","field":"Computer Science","cited_by":77,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Network topology; Computer science; Throughput; Network on a chip; Process (computing); Logical topology; Topology (electrical circuits); Distributed computing; Embedded system; Computer network; Engineering; Wireless","authors":[{"name":"Victor Dumitriu","is_ca":true},{"name":"Gul N. Khan","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01744174013809855,"gpt":0.2473134310673228,"spread":0.2298716909292242,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006152204,0.0002938031,0.0004875873,0.0004696749,0.0006993838,0.0003208009,0.0002705505,0.0002590515,0.000020817],"category_scores_gemma":[0.000006828789,0.0002585771,0.000223786,0.0009191916,0.00004069268,0.0009231854,0.00000238336,0.0002436544,0.00002018028],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001720374,"about_ca_system_score_gemma":0.00004601902,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001226313,"about_ca_topic_score_gemma":0.0004560659,"domain_scores_codex":[0.9976705,0.0002182624,0.000714001,0.000676202,0.0003200198,0.0004009937],"domain_scores_gemma":[0.9986106,0.000109276,0.0002291447,0.0005471754,0.0003948161,0.0001089507],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0005755635,0.002235478,0.001040259,0.0002693125,0.002366845,0.00001549631,0.01362798,0.6255014,0.02509073,0.1981828,0.009149095,0.121945],"study_design_scores_gemma":[0.0006959622,0.0006235566,0.0004292002,0.00005056776,0.0001198554,0.00003218637,0.0003629831,0.9863317,0.009449356,0.00007242313,0.00153088,0.000301345],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1072724,0.0000854009,0.8867025,0.0004562047,0.004436585,0.0006096995,0.00005674502,0.0002016316,0.0001788299],"genre_scores_gemma":[0.9947218,0.00006036766,0.002840964,0.0003371885,0.0003951016,0.0001939924,0.00005296882,0.00001429938,0.001383359],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8874493,"threshold_uncertainty_score":0.9999866,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3000160544","doi":"10.1109/tvlsi.2019.2961602","title":"Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks","year":2020,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Advanced Neural Network Applications","field":"Computer Science","cited_by":75,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Saskatchewan","funders":"Korea Evaluation Institute of Industrial Technology","keywords":"STRIDE; Convolutional neural network; Kernel (algebra); Computer science; Speedup; Digital signal processing; Convolution (computer science); Algorithm; Computational complexity theory; Parallel computing; Field-programmable gate array; Mathematics; Artificial neural network; Artificial intelligence; Embedded system; Computer hardware; Discrete mathematics","authors":[{"name":"Juan Yépez","is_ca":true},{"name":"Seok‐Bum Ko","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.0222694878945663,"gpt":0.2494657186137322,"spread":0.2271962307191659,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0001857038,0.0002989581,0.00032023,0.0001148052,0.0005823812,0.0002474945,0.0004476439,0.0001552123,0.00000917463],"category_scores_gemma":[0.00001168712,0.0002864779,0.0001703032,0.0006380267,0.00008253085,0.0008379674,0.00000662996,0.0003912981,0.0000219731],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00008898417,"about_ca_system_score_gemma":0.00004399776,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0000144285,"about_ca_topic_score_gemma":0.00005136632,"domain_scores_codex":[0.9978681,0.0001200109,0.0005424081,0.0007138326,0.0003203893,0.0004353259],"domain_scores_gemma":[0.9985716,0.0003374897,0.0001764893,0.0004179725,0.0002110532,0.0002854054],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0002145511,0.0003115688,0.00007904003,0.00008095978,0.0001045008,0.00000572333,0.0008836568,0.9272639,0.002958929,0.02326371,0.005674338,0.03915919],"study_design_scores_gemma":[0.0007776443,0.000210351,0.00004989386,0.00003428329,0.00002416469,0.00003072263,0.0001658531,0.9916965,0.001368862,0.0001518917,0.005210837,0.0002789491],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.003346482,0.0002538788,0.9909786,0.002305422,0.00132311,0.001145845,0.0001691069,0.0004201838,0.00005738092],"genre_scores_gemma":[0.9916961,0.00005157355,0.006147469,0.000898082,0.0003599858,0.0005743826,0.00003588934,0.0000296971,0.000206836],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9883496,"threshold_uncertainty_score":0.9999588,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2089389313","doi":"10.1109/tvlsi.2008.917552","title":"A Compact and Accurate Gaussian Variate Generator","year":2008,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Image and Signal Denoising Methods","field":"Computer Science","cited_by":74,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Alberta","funders":"","keywords":"Datapath; Field-programmable gate array; Algorithm; Gaussian; Computer science; Logarithm; Chip; CMOS; Block (permutation group theory); Range (aeronautics); Parallel computing; Computer hardware; Mathematics; Electronic engineering; Engineering","authors":[{"name":"Amirhossein Alimohammad","is_ca":true},{"name":"Saeed Fouladi Fard","is_ca":true},{"name":"B.F. Cockburn","is_ca":true},{"name":"Christian Schlegel","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.03029089301513507,"gpt":0.2725454127132645,"spread":0.2422545196981295,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006882872,0.0003172677,0.0003979915,0.0003160377,0.0007811247,0.0004424946,0.0003966552,0.0001698743,0.00002994289],"category_scores_gemma":[0.00001134848,0.0002679193,0.0001530136,0.0005678527,0.0000755923,0.001146815,0.000002737614,0.000388569,0.000121639],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001092614,"about_ca_system_score_gemma":0.0001243848,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0002154895,"about_ca_topic_score_gemma":0.00006654301,"domain_scores_codex":[0.9974449,0.0005867613,0.0005320645,0.0005796387,0.0004392125,0.0004174514],"domain_scores_gemma":[0.9986638,0.0001656959,0.0001545316,0.0006021769,0.0001914802,0.0002222621],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.001773528,0.006815123,0.0008930329,0.0008446372,0.00182918,0.001941435,0.07017176,0.1188255,0.5541317,0.02846004,0.04018617,0.1741278],"study_design_scores_gemma":[0.003124771,0.0005517225,0.001352065,0.0003362028,0.00007507158,0.001213917,0.0004446481,0.8080024,0.1773124,0.0002456352,0.006246448,0.001094788],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.02439309,0.0001800597,0.9710024,0.0002646015,0.002488385,0.0003502844,0.00005106338,0.0002862729,0.0009838212],"genre_scores_gemma":[0.9904268,0.00007673449,0.006589429,0.0002848517,0.000154666,0.00004098022,0.00000550151,0.00002587503,0.002395136],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9660338,"threshold_uncertainty_score":0.9999773,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3208657910","doi":"10.1109/tvlsi.2022.3153605","title":"High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND","year":2022,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":70,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"McGill University","funders":"","keywords":"Computer science; Decoding methods; Code word; Code (set theory); Latency (audio); Code rate; Throughput; Algorithm; Parallel computing; Computer engineering; Wireless; Telecommunications","authors":[{"name":"Syed Mohsin Abbas","is_ca":true},{"name":"Thibaud Tonnellier","is_ca":true},{"name":"Furkan Ercan","is_ca":false},{"name":"Marwan Jalaleddine","is_ca":true},{"name":"Warren J. Gross","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01031769425105502,"gpt":0.2336148887118031,"spread":0.2232971944607481,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001160247,0.000383959,0.0004579852,0.0004280249,0.001258094,0.0002686956,0.0006569368,0.0001648254,0.00002064357],"category_scores_gemma":[0.00003391377,0.0003592487,0.0002296286,0.0008595667,0.00007732811,0.0003047096,0.00002148863,0.0006021128,0.00000439768],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0003796408,"about_ca_system_score_gemma":0.0001283528,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0006137872,"about_ca_topic_score_gemma":0.0008225232,"domain_scores_codex":[0.9965828,0.000546483,0.0006814579,0.001032059,0.0006668756,0.0004903443],"domain_scores_gemma":[0.9979073,0.0004395067,0.0002462777,0.0009744642,0.0002883549,0.0001440817],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0008404796,0.003038716,0.00007124,0.0004266524,0.0002141217,0.00002215247,0.01304262,0.850485,0.01596251,0.01700107,0.008525762,0.09036972],"study_design_scores_gemma":[0.002010392,0.001632356,0.00005728824,0.0002108475,0.00007062007,0.0001743772,0.001171645,0.9122598,0.05312929,0.001787518,0.0265089,0.0009869899],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.03909138,0.000120072,0.9534881,0.0006518039,0.004400669,0.0009014436,0.0002749571,0.0009343918,0.0001372032],"genre_scores_gemma":[0.9833176,0.00001496062,0.01417022,0.0002028966,0.00008622857,0.001086857,0.00002530616,0.00004383269,0.001052171],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9442261,"threshold_uncertainty_score":0.999886,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2023777102","doi":"10.1109/tvlsi.2005.863187","title":"Design and verification of SystemC transaction-level models","year":2006,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":69,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Concordia University","funders":"","keywords":"SystemC; Computer science; Transaction-level modeling; Correctness; Abstract state machines; Electronic system-level design and verification; Programming language; Formal verification; Embedded system; High-level synthesis; Unified Modeling Language; Computer architecture; Finite-state machine; Software; Field-programmable gate array","authors":[{"name":"A. Habibi","is_ca":true},{"name":"Sofiène Tahar","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.03567468190291152,"gpt":0.2447658100817937,"spread":0.2090911281788822,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001341959,0.0004058236,0.000583462,0.0006033402,0.0003247278,0.0002721446,0.000559891,0.0003543151,0.000007927328],"category_scores_gemma":[0.000004521644,0.0003852557,0.000184145,0.0007238924,0.0000800722,0.001670812,0.000002387612,0.0003304398,0.00002611767],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002648319,"about_ca_system_score_gemma":0.0001256782,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0006045938,"about_ca_topic_score_gemma":0.000122105,"domain_scores_codex":[0.9961482,0.0007399499,0.001223965,0.0007567463,0.0007353908,0.0003958067],"domain_scores_gemma":[0.9977034,0.0002839435,0.0004498818,0.0009658901,0.0004779033,0.0001189824],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0003517562,0.002209817,0.00002728422,0.00142185,0.0003349256,0.00002172567,0.007393227,0.5560619,0.3202549,0.09073006,0.003123417,0.01806922],"study_design_scores_gemma":[0.0005537731,0.0002269164,0.00001957145,0.0004622905,0.00004228301,0.00009016822,0.000460043,0.7848968,0.2118848,0.0008760301,0.0001102772,0.0003770841],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.002333856,0.0002756285,0.9930466,0.00007037371,0.001281523,0.001555975,0.00008681145,0.0006442216,0.0007050334],"genre_scores_gemma":[0.9649462,0.00004546397,0.03344304,0.0000215066,0.00006617677,0.0005062369,0.00000990646,0.00004254228,0.0009189722],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9626123,"threshold_uncertainty_score":0.9998599,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3103728101","doi":"10.1109/tvlsi.2020.3033928","title":"Area-Efficient Nano-AES Implementation for Internet-of-Things Devices","year":2020,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptographic Implementations and Security","field":"Computer Science","cited_by":66,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Saskatchewan","funders":"Natural Sciences and Engineering Research Council of Canada; University of Saskatchewan","keywords":"Datapath; Computer science; Encryption; Advanced Encryption Standard; Byte; Cryptosystem; Cryptography; Application-specific integrated circuit; Embedded system; Field-programmable gate array; Shift register; Computer hardware; Computer network","authors":[{"name":"Karim Shahbazi","is_ca":true},{"name":"Seok‐Bum Ko","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02994524984239608,"gpt":0.2884923201032786,"spread":0.2585470702608825,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004755853,0.0002565076,0.0003388186,0.0003078385,0.0003054281,0.0002859878,0.0005020112,0.0001027263,0.00007273133],"category_scores_gemma":[0.000009310471,0.0002437343,0.0002899084,0.000729926,0.00004288797,0.0007448082,0.000006517188,0.0001780049,0.00001752055],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00009554225,"about_ca_system_score_gemma":0.00009020208,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0003530924,"about_ca_topic_score_gemma":0.0004382913,"domain_scores_codex":[0.9976203,0.0001383064,0.000866236,0.000549246,0.0004778551,0.0003480338],"domain_scores_gemma":[0.9986255,0.0001823315,0.0003385987,0.0003319677,0.0003733331,0.0001483307],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0009203083,0.004414215,0.00133486,0.002167046,0.001445116,0.00001526297,0.2246292,0.03628359,0.1022322,0.2372187,0.01414927,0.3751902],"study_design_scores_gemma":[0.001665407,0.0007218224,0.0001083499,0.0001534845,0.0000740721,0.00000989394,0.009623338,0.8925051,0.0886218,0.0001332446,0.005960663,0.0004228051],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.06178371,0.00006735449,0.9345753,0.0006246599,0.001411241,0.001105722,0.0001689495,0.0001810114,0.00008204018],"genre_scores_gemma":[0.9910471,0.00001276184,0.00800166,0.0004135133,0.00005466986,0.0003494072,0.00005939515,0.00001974436,0.00004170883],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9292634,"threshold_uncertainty_score":0.9939198,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2900500071","doi":"10.1109/tvlsi.2018.2877438","title":"Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration","year":2018,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Physical Unclonable Functions (PUFs) and Hardware Security","field":"Computer Science","cited_by":62,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Simon Fraser University","funders":"National Science Foundation","keywords":"Field-programmable gate array; Physical unclonable function; Computer science; Key generation; Embedded system; Overhead (engineering); Key (lock); Encryption; Virtex; Computer hardware; Cryptography; Advanced Encryption Standard; Algorithm; Computer network","authors":[{"name":"Mohammad Usmani","is_ca":false},{"name":"Shahrzad Keshavarz","is_ca":false},{"name":"Eric Matthews","is_ca":true},{"name":"Lesley Shannon","is_ca":true},{"name":"Russel Tessier","is_ca":false},{"name":"Daniel Holcomb","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02984465471118834,"gpt":0.2623921777810458,"spread":0.2325475230698575,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007220739,0.0003794294,0.0003958129,0.0006014086,0.0007763235,0.0005115197,0.0004317058,0.0002474668,0.0001007465],"category_scores_gemma":[0.0000200768,0.0003619289,0.0002057471,0.00122416,0.0001001914,0.0007770014,0.000004765237,0.0004528102,0.0003484452],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0006132991,"about_ca_system_score_gemma":0.0002996972,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0006088456,"about_ca_topic_score_gemma":0.001903924,"domain_scores_codex":[0.9966606,0.0004681445,0.0007795852,0.0008376334,0.0007308893,0.0005231092],"domain_scores_gemma":[0.9980258,0.0001175953,0.0002260766,0.00077411,0.0006787828,0.0001776065],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001417702,0.002064961,0.00003213725,0.00008788358,0.00005934385,0.00001101959,0.003706003,0.8637492,0.1152052,0.008467351,0.0006344911,0.005840689],"study_design_scores_gemma":[0.0007806577,0.0002490271,0.00006664517,0.0001416515,0.00002512772,0.00001227563,0.0002753591,0.9278219,0.06841812,0.00004145424,0.001814229,0.0003535261],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1782659,0.00003891306,0.8164396,0.0002189441,0.003455418,0.000645819,0.0000584458,0.0002411037,0.0006358874],"genre_scores_gemma":[0.9962329,0.000003961175,0.002466213,0.0002731929,0.0005389251,0.0001520307,0.0000437536,0.00002855913,0.0002604352],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.817967,"threshold_uncertainty_score":0.9998833,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2078731783","doi":"10.1109/tvlsi.2014.2375640","title":"Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves","year":2015,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptography and Residue Arithmetic","field":"Computer Science","cited_by":61,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Saskatchewan","funders":"","keywords":"NIST; Elliptic curve cryptography; Field-programmable gate array; Computer science; Elliptic curve point multiplication; Elliptic curve; Scalability; Parallel computing; Hessian form of an elliptic curve; Scalar multiplication; Schoof's algorithm; Embedded system; Arithmetic; Mathematics; Encryption; Public-key cryptography; Operating system","authors":[{"name":"K.C. Cinnati Loi","is_ca":true},{"name":"Seok‐Bum Ko","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02465452726244105,"gpt":0.2566337248512674,"spread":0.2319791975888263,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.00129691,0.0004470015,0.0005766052,0.0004532396,0.0005823627,0.0005883661,0.0008636894,0.0002652735,0.00001789405],"category_scores_gemma":[0.00003792711,0.0003770857,0.0003752293,0.001123923,0.00009534824,0.00103522,0.000006386144,0.0003872937,0.0002386672],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002207142,"about_ca_system_score_gemma":0.0002861462,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001517188,"about_ca_topic_score_gemma":0.0002547865,"domain_scores_codex":[0.9964343,0.0003358822,0.000875412,0.0008588593,0.0008297568,0.0006657992],"domain_scores_gemma":[0.9972858,0.0002569111,0.0003022363,0.0009244134,0.0008568582,0.0003737797],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"not_applicable","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.004261544,0.0350242,0.00214786,0.03292779,0.005574689,0.0002829154,0.06203163,0.2098692,0.04398873,0.134712,0.320912,0.1482674],"study_design_scores_gemma":[0.007168159,0.002608053,0.0001576015,0.006388092,0.0004204801,0.0003922097,0.005061499,0.7289105,0.1757696,0.001515479,0.06879968,0.002808644],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.003275986,0.001413147,0.9865239,0.000672339,0.004782426,0.001896689,0.0001607019,0.0005524121,0.0007224021],"genre_scores_gemma":[0.9901062,0.00009924568,0.005280228,0.0002130723,0.0002166967,0.001074083,0.00002923784,0.00005173837,0.002929478],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9868302,"threshold_uncertainty_score":0.9998681,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2120872844","doi":"10.1109/tvlsi.2002.808429","title":"A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops","year":2002,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":52,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Low voltage; Low-power electronics; FLOPS; Dissipation; Dual (grammatical number); Power (physics); Power–delay product; Electronic engineering; Voltage; Energy consumption; Enhanced Data Rates for GSM Evolution; Figure of merit; Electrical engineering; Computer science; Power consumption; Engineering; Telecommunications; Physics; Parallel computing; Transistor","authors":[{"name":"Wai Man Chung","is_ca":true},{"name":"Tien-Yu Lo","is_ca":true},{"name":"Manoj Sachdev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01391084861325538,"gpt":0.2242007784440364,"spread":0.210289929830781,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow","insufficient_payload"],"consensus_categories":[],"category_scores_codex":[0.0004439456,0.0006294403,0.001275219,0.001607001,0.0002757802,0.0001540865,0.0003350324,0.0003922099,0.001144392],"category_scores_gemma":[0.000008582588,0.0005932394,0.0006165264,0.002984575,0.0001195185,0.000868054,0.000002556691,0.000657349,0.0006641421],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0004382292,"about_ca_system_score_gemma":0.00003630939,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006769998,"about_ca_topic_score_gemma":0.0003799632,"domain_scores_codex":[0.9964124,0.0001979855,0.001344037,0.0005959389,0.0007985174,0.0006511512],"domain_scores_gemma":[0.9980041,0.0002310843,0.0002417938,0.0009066898,0.0003814953,0.0002347796],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001560641,0.001428021,0.0001271877,0.0003961645,0.003902654,0.0000282559,0.01364814,0.8956366,0.07647932,0.000201328,0.006891722,0.001104595],"study_design_scores_gemma":[0.001192444,0.0001903207,0.0003167206,0.0003807426,0.0006742173,0.00001262866,0.001977021,0.8659087,0.1270756,0.000003292385,0.001556886,0.0007114374],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.3638091,0.0003887944,0.6276585,0.00001538433,0.002927423,0.0007858317,0.0006313975,0.0005623224,0.003221246],"genre_scores_gemma":[0.9972066,0.0001347603,0.000186396,0.00002873353,0.00009731786,0.0002653094,0.00006615126,0.00007564948,0.001939053],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.6333975,"threshold_uncertainty_score":0.9997687,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2137663768","doi":"10.1109/tvlsi.2009.2017443","title":"Low-Power Programmable FPGA Routing Circuitry","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":51,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Sleep mode; Routing (electronic design automation); Computer science; Power analysis; Embedded system; Dynamic demand; Power (physics); Electronic engineering; Engineering; Power consumption; Cryptography","authors":[{"name":"Jason H. Anderson","is_ca":true},{"name":"Farid N. Najm","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.00788344337603655,"gpt":0.2079548589754282,"spread":0.2000714155993916,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0005739273,0.0005669998,0.0005429775,0.0004592809,0.0004316262,0.0003722858,0.0003573724,0.0004064664,0.0001729674],"category_scores_gemma":[0.000008128112,0.0005477713,0.0002846193,0.0008605732,0.00004772799,0.001116334,0.000001211461,0.0008351222,0.0007041591],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000529139,"about_ca_system_score_gemma":0.00007131976,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003309025,"about_ca_topic_score_gemma":0.00006755987,"domain_scores_codex":[0.9968594,0.0001179138,0.000917459,0.0005550043,0.0006495293,0.0009006742],"domain_scores_gemma":[0.9986315,0.0000758298,0.000123882,0.0007256072,0.0001999416,0.0002432254],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001925752,0.001859661,0.0001271345,0.0005044029,0.000475211,0.00007559078,0.006770252,0.8102872,0.09640977,0.0007679367,0.008671015,0.07385918],"study_design_scores_gemma":[0.002641543,0.0008306343,0.000376658,0.001493146,0.0001668299,0.0001609402,0.002841636,0.6488512,0.3294766,0.00006275997,0.01112804,0.001970061],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.119179,0.0002075641,0.8669939,0.00005793198,0.005456157,0.001065637,0.00008684267,0.001869421,0.005083532],"genre_scores_gemma":[0.9972965,0.00005594019,0.0003752823,0.0001007208,0.0002457608,0.0002327459,0.00002490454,0.0001057684,0.001562406],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8781174,"threshold_uncertainty_score":0.9996974,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2145473619","doi":"10.1109/tvlsi.2007.902204","title":"Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies","year":2007,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Radio Frequency Integrated Circuit Design","field":"Engineering","cited_by":50,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Advanced Micro Devices (Canada)","funders":"","keywords":"Inductor; CMOS; Electronic engineering; Voltage regulator; Process (computing); Macro; Engineering; Voltage; Computer science; Electrical engineering","authors":[{"name":"Jaeseo Lee","is_ca":true},{"name":"G. Hatcher","is_ca":false},{"name":"Lieven Vandenberghe","is_ca":false},{"name":"Chih-Kong Ken Yang","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.0221140530623207,"gpt":0.2692550045741708,"spread":0.2471409515118501,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.003588461,0.0005035566,0.0005872234,0.00094091,0.0002461178,0.0001034204,0.0003943801,0.000598134,0.00003849879],"category_scores_gemma":[0.0001261102,0.0004604314,0.0002738356,0.00122749,0.00007665881,0.0006283966,3.05682e-7,0.0006375362,0.00002399362],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.001058567,"about_ca_system_score_gemma":0.0002116683,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00007458314,"about_ca_topic_score_gemma":0.0004244857,"domain_scores_codex":[0.9962754,0.0001674547,0.001262569,0.0005150891,0.001164232,0.0006152631],"domain_scores_gemma":[0.9970896,0.0002458286,0.0002567534,0.0006277458,0.001681028,0.00009904195],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0001458741,0.0003415712,0.0000374155,0.0004352788,0.0005067051,0.000003594138,0.001849443,0.5417196,0.3355716,0.0007850669,0.0005867076,0.1180172],"study_design_scores_gemma":[0.0007882728,0.0001468271,0.00001488695,0.0004832181,0.0002229806,0.00002590988,0.006497809,0.3693514,0.6214923,0.0004324097,0.0001982182,0.0003457153],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1345092,0.000456324,0.8562998,0.00002186682,0.002763793,0.002218066,0.0001976584,0.00141123,0.002122104],"genre_scores_gemma":[0.9982016,0.00003212003,0.0003768007,0.000007630165,0.00007900873,0.001035252,0.00004125981,0.0001103626,0.0001159799],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8636924,"threshold_uncertainty_score":0.9997848,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2121169595","doi":"10.1109/tvlsi.2004.826204","title":"A low-power reduced swing global clocking methodology","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":50,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Swing; Clock network; CMOS; Power (physics); Clock gating; Electronic engineering; Computer science; Electrical engineering; Engineering; Electronic circuit; Synchronous circuit; Clock signal; Physics","authors":[{"name":"Farhad Haj Ali Asgari","is_ca":true},{"name":"Manoj Sachdev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02117802753230498,"gpt":0.2565472739598578,"spread":0.2353692464275529,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008243823,0.0005554712,0.000634225,0.0003941519,0.0003807849,0.0001972292,0.0003598593,0.0004803301,0.0001120669],"category_scores_gemma":[0.00002020737,0.000543612,0.0003067983,0.0009332842,0.00007003404,0.0008331105,0.000002624756,0.0007172275,0.0004985538],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.001266125,"about_ca_system_score_gemma":0.0001236025,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001453807,"about_ca_topic_score_gemma":0.0003084394,"domain_scores_codex":[0.9968731,0.0002655685,0.0009276803,0.0005897366,0.0005435825,0.0008003582],"domain_scores_gemma":[0.9986596,0.0001438206,0.0001240753,0.0006619475,0.000187834,0.0002227022],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0001335326,0.0003446018,0.00002803499,0.0002063056,0.0003028387,0.00003760952,0.003091182,0.8844135,0.104383,0.0009081888,0.0006250511,0.00552616],"study_design_scores_gemma":[0.005216067,0.0006855981,0.0003895428,0.002001356,0.0002859082,0.0005318446,0.005331376,0.1502448,0.8288834,0.0003629256,0.003784781,0.002282362],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2286126,0.000183306,0.7592192,0.00005901307,0.008436636,0.0005715954,0.0001067572,0.001004484,0.001806415],"genre_scores_gemma":[0.9952199,0.00005532794,0.003814784,0.00008652855,0.0002425433,0.0002438188,0.00001858161,0.0001015308,0.0002169206],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7666073,"threshold_uncertainty_score":0.9997016,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W1969775274","doi":"10.1109/tvlsi.2007.893584","title":"Segmented Virtual Ground Architecture for Low-Power Embedded SRAM","year":2007,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":48,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Static random-access memory; Dynamic demand; Computer science; Dissipation; Low-power electronics; Electronic engineering; Dynamic voltage scaling; Power consumption; Power (physics); Soft error; Energy consumption; Embedded system; Engineering; Electrical engineering; Computer hardware","authors":[{"name":"Mohammad Sharifkhani","is_ca":true},{"name":"Manoj Sachdev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.006939423437098234,"gpt":0.2207381096543361,"spread":0.2137986862172379,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008105796,0.0005868186,0.0005355948,0.000649008,0.0003895383,0.0002141973,0.0003240634,0.0004542676,0.000140187],"category_scores_gemma":[0.00001097312,0.0005459401,0.0003366399,0.0006534471,0.00007071891,0.0006232921,0.000001730391,0.0007135142,0.0002517095],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0005258194,"about_ca_system_score_gemma":0.0000553501,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00002990731,"about_ca_topic_score_gemma":0.0004188062,"domain_scores_codex":[0.9969522,0.00008652287,0.0009498958,0.0005437221,0.0006006219,0.0008669811],"domain_scores_gemma":[0.9984935,0.000271447,0.0001202708,0.0006276007,0.000232052,0.0002551184],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0009295346,0.0009965217,0.00002462273,0.0005528858,0.0006840738,0.0000285253,0.008312282,0.8267799,0.1363058,0.0005653474,0.008331043,0.01648952],"study_design_scores_gemma":[0.005881758,0.001444516,0.0002023806,0.001084478,0.0002501922,0.0001546525,0.007836437,0.5683416,0.3883422,0.00005837267,0.02421983,0.0021836],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1707919,0.00009055915,0.818688,0.00002636263,0.006974209,0.001349575,0.000304846,0.000916237,0.0008583264],"genre_scores_gemma":[0.9958581,0.00001806832,0.00122291,0.0000972389,0.0003305852,0.0004042599,0.00008345593,0.0001572915,0.001828114],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8250662,"threshold_uncertainty_score":0.9996992,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2147506855","doi":"10.1109/tvlsi.2004.827562","title":"Design of FPGA interconnect for multilevel metallization","year":2004,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":46,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":false,"ca_fund":false,"ca_venue":false,"about_ca":true},"ca_institutions":"","funders":"","keywords":"Field-programmable gate array; Interconnection; Routing (electronic design automation); Computer science; Exploit; Gate array; Topology (electrical circuits); Embedded system; Arity; Engineering; Electrical engineering; Computer network","authors":[{"name":"André DeHon","is_ca":false},{"name":"Raphael Rubin","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02608449495973388,"gpt":0.2430953538035635,"spread":0.2170108588438296,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000406704,0.0002837694,0.0003864524,0.0003592941,0.0001216209,0.00006068171,0.0001754339,0.0002430416,0.00003083204],"category_scores_gemma":[0.00001272679,0.0002685078,0.0002019671,0.0002587142,0.00003248055,0.0004162453,6.639965e-7,0.0002023586,0.000025315],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002407581,"about_ca_system_score_gemma":0.00004032351,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00004942511,"about_ca_topic_score_gemma":0.00006440005,"domain_scores_codex":[0.9985057,0.00008191293,0.0006367796,0.0002692127,0.0002318444,0.0002745783],"domain_scores_gemma":[0.9991547,0.0001443897,0.00009978491,0.0003058866,0.0002210239,0.00007418889],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0000814575,0.0002517651,9.002772e-7,0.0002440966,0.0001500662,0.000001244233,0.001276405,0.8364415,0.1505422,0.0005731606,0.000289169,0.0101481],"study_design_scores_gemma":[0.0008163942,0.0002560478,0.000003148309,0.0003271569,0.000067606,0.00001057652,0.0004035889,0.3509498,0.6463414,0.0002260902,0.0003403086,0.0002579143],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.003089458,0.00015201,0.9929678,0.0000149154,0.001377831,0.001362783,0.0002057504,0.0006711695,0.0001582983],"genre_scores_gemma":[0.9870596,0.00009342236,0.01180598,0.00001929951,0.00006540944,0.0006438149,0.00003356506,0.0000710527,0.0002078669],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9839701,"threshold_uncertainty_score":0.9999767,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2148701953","doi":"10.1109/tvlsi.2008.2001237","title":"GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering","year":2008,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":45,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of British Columbia","funders":"","keywords":"Glitch; Lookup table; Field-programmable gate array; Routing (electronic design automation); Computer science; Programmable logic array; Logic synthesis; Critical path method; Retiming; Logic gate; Dynamic demand; Electronic engineering; Delay calculation; Programmable logic device; Macrocell array; Power (physics); Embedded system; Logic family; Parallel computing; Engineering; Propagation delay; Algorithm; CMOS","authors":[{"name":"Julien Lamoureux","is_ca":true},{"name":"Guy Lemieux","is_ca":true},{"name":"Steven J. E. Wilton","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01044319176882217,"gpt":0.2132663811452761,"spread":0.202823189376454,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000257114,0.0004210435,0.0004387822,0.0003741806,0.0002618287,0.0001029743,0.0001766814,0.000273232,0.00007884316],"category_scores_gemma":[0.000005130384,0.0004198783,0.0001062204,0.0005409225,0.00006638434,0.001044913,0.000002598325,0.0004116067,0.00009978229],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0005695916,"about_ca_system_score_gemma":0.00004142068,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00009919948,"about_ca_topic_score_gemma":0.0003298721,"domain_scores_codex":[0.9977351,0.000115282,0.0007698281,0.0004648938,0.0004190075,0.0004959247],"domain_scores_gemma":[0.9992002,0.00008120065,0.00008369544,0.0004396169,0.00008435134,0.0001109642],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001702225,0.0006454716,0.0004753003,0.0004849111,0.0002054947,0.00006911636,0.02197913,0.9289181,0.04246278,0.0001908491,0.001710553,0.002688092],"study_design_scores_gemma":[0.001959452,0.0001933167,0.000912639,0.0007242974,0.00004598672,0.0001736718,0.003087613,0.9383929,0.05050428,0.00002353915,0.003121272,0.0008609893],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.3969113,0.0003140624,0.5989017,0.00003265998,0.002249439,0.0005490343,0.0000844438,0.0003236619,0.0006336779],"genre_scores_gemma":[0.9976783,0.0005589919,0.0007459277,0.00004130781,0.00005813478,0.0002787615,0.0000333505,0.00008605063,0.0005191502],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.600767,"threshold_uncertainty_score":0.9998253,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2087866481","doi":"10.1109/tvlsi.2007.893659","title":"On Concurrent Detection of Errors in Polynomial Basis Multiplication","year":2007,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptographic Implementations and Security","field":"Computer Science","cited_by":45,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"Division of Materials Research","keywords":"Parity bit; Error detection and correction; Parity (physics); Arithmetic; Multiplier (economics); Binary number; Computer science; Algorithm; Multiplication (music); Standard basis; Overhead (engineering); Mathematics; Discrete mathematics; Combinatorics","authors":[{"name":"Siavash Bayat-Sarmadi","is_ca":true},{"name":"M.A. Hasan","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01640876264141811,"gpt":0.2793068406043503,"spread":0.2628980779629322,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.001065486,0.0002238622,0.0002716212,0.0009358138,0.0002322771,0.00009340329,0.0002940505,0.0001596199,0.00002504529],"category_scores_gemma":[0.00001469102,0.0002179017,0.0001839345,0.001118968,0.00005688842,0.0005213526,0.00000274995,0.0003291662,0.0000242092],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0003095733,"about_ca_system_score_gemma":0.00005858845,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0007922189,"about_ca_topic_score_gemma":0.007065519,"domain_scores_codex":[0.9976577,0.0002034564,0.0008576217,0.0004677095,0.000477674,0.0003358397],"domain_scores_gemma":[0.9986846,0.0002677609,0.0002629861,0.0004803214,0.0002028162,0.0001014653],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.001225038,0.009203581,0.001797734,0.0003972407,0.0003406659,0.00002376586,0.03234235,0.05052274,0.2151899,0.04707886,0.001261827,0.6406164],"study_design_scores_gemma":[0.004643961,0.001067166,0.007621754,0.0004862382,0.00005236368,0.00003368695,0.005723525,0.4228456,0.5544986,0.0002691558,0.001897064,0.0008608657],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2975577,0.00002849478,0.7000208,0.0000527813,0.001569262,0.0004950963,0.00005544362,0.00008250478,0.0001379206],"genre_scores_gemma":[0.9989421,0.00001899042,0.0007564495,0.0000465767,0.00004255884,0.000115243,0.00001418042,0.00001386936,0.00004997797],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7013845,"threshold_uncertainty_score":0.8885772,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2955242165","doi":"10.1109/tvlsi.2019.2920152","title":"An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing","year":2019,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":44,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Alberta","funders":"Natural Sciences and Engineering Research Council of Canada","keywords":"Computer science; Recurrent neural network; Stochastic computing; Energy consumption; Artificial neural network; Noise (video); Binary number; Computer engineering; Efficient energy use; Artificial intelligence; Arithmetic; Engineering","authors":[{"name":"Yidong Liu","is_ca":true},{"name":"Leibo Liu","is_ca":false},{"name":"Fabrizio Lombardi","is_ca":false},{"name":"Jie Han","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01557487133214182,"gpt":0.2586968472504028,"spread":0.2431219759182609,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0007629694,0.0003787536,0.0004314357,0.0003176804,0.0005355185,0.0004607518,0.0005184661,0.0001777371,0.000008092135],"category_scores_gemma":[0.000005634274,0.0003575198,0.0001420062,0.0006468535,0.00004395144,0.0005643151,0.00001070901,0.0004869666,0.0000168409],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002608449,"about_ca_system_score_gemma":0.00007670084,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000280858,"about_ca_topic_score_gemma":0.0001712782,"domain_scores_codex":[0.9969745,0.0004318955,0.0006544276,0.0008373985,0.0005370371,0.0005647262],"domain_scores_gemma":[0.9982945,0.0002069959,0.000272328,0.0007979221,0.0002361492,0.0001921453],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0000258526,0.0002178862,0.00005320085,0.00002849169,0.00001833346,0.000003182899,0.001220754,0.9835959,0.003179525,0.0006114187,0.00003481017,0.01101064],"study_design_scores_gemma":[0.0003341616,0.0003006308,0.00006306237,0.000501068,0.00002301662,0.00009978279,0.0003759779,0.9958606,0.001992664,0.00002818387,0.00004472413,0.0003760716],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.300942,0.00009838574,0.6928686,0.00002721243,0.005008162,0.0004215177,0.00001140332,0.0005756264,0.00004703558],"genre_scores_gemma":[0.9929335,0.000003824568,0.00663345,0.00009633548,0.0001889223,0.00003532516,0.000005701881,0.00003931575,0.00006368203],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.6919914,"threshold_uncertainty_score":0.9998877,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3130406170","doi":"10.1109/tvlsi.2021.3058509","title":"An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Cryptography and Residue Arithmetic","field":"Computer Science","cited_by":44,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Windsor","funders":"FedDev Ontario","keywords":"Operand; Elliptic curve cryptography; Field-programmable gate array; Cryptography; Computer science; Multiplier (economics); Finite field; Public-key cryptography; Key (lock); Gate array; Multiplication (music); Computer hardware; Parallel computing; Arithmetic; Embedded system; Algorithm; Mathematics; Encryption","authors":[{"name":"Moslem Heidarpur","is_ca":true},{"name":"Mitra Mirhassani","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01139373177462619,"gpt":0.2656827451022813,"spread":0.2542890133276551,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000436974,0.0002758103,0.0002969211,0.0003382325,0.0005576254,0.0004871788,0.0003712134,0.0001831616,0.00004810644],"category_scores_gemma":[0.00002626447,0.0002536055,0.000207481,0.0005921908,0.00004123836,0.0003840995,0.000004905179,0.0002372376,0.00001388006],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00008008845,"about_ca_system_score_gemma":0.0001204007,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000203707,"about_ca_topic_score_gemma":0.0009179431,"domain_scores_codex":[0.9977322,0.0002351547,0.0005257549,0.0006919457,0.0004329145,0.0003820732],"domain_scores_gemma":[0.9978386,0.0006487622,0.0001443257,0.0008436994,0.0003521243,0.0001724873],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0007759809,0.005349018,0.0007314351,0.0006963031,0.0004855776,0.00007232682,0.008086715,0.7412124,0.1004885,0.03146782,0.00283669,0.1077972],"study_design_scores_gemma":[0.002939749,0.0005518546,0.000375035,0.0001246455,0.00006254007,0.00001272464,0.001854235,0.8118347,0.1808144,0.0001732652,0.0008716258,0.0003852377],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.07102909,0.0001068681,0.92506,0.0006319211,0.001957934,0.0007299738,0.0002661364,0.0001794847,0.00003862035],"genre_scores_gemma":[0.9872531,0.00001666614,0.01191918,0.0003405588,0.00008843066,0.0002004735,0.00006047147,0.00002276416,0.000098378],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.916224,"threshold_uncertainty_score":0.9999916,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2064187704","doi":"10.1109/tvlsi.2011.2160001","title":"Exploiting Process Variability in Voltage/Frequency Control","year":2011,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":42,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Frequency scaling; Chip; Throughput; Computer science; Voltage; Multi-core processor; Multiprocessing; Power (physics); Dram; Dynamic demand; Embedded system; Electronic engineering; Parallel computing; Electrical engineering; Computer hardware; Engineering; Telecommunications; Physics","authors":[{"name":"Sebastian Herbert","is_ca":false},{"name":"Siddharth Garg","is_ca":true},{"name":"Diana Marculescu","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01427299725690723,"gpt":0.2107434303360679,"spread":0.1964704330791607,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001277704,0.0004311122,0.0005092555,0.0004591902,0.000191273,0.00009428392,0.0003129973,0.0003164484,0.0002481541],"category_scores_gemma":[0.00002683354,0.0004142115,0.0001536727,0.000706408,0.00005670727,0.001222552,8.485846e-7,0.0007186192,0.0002322962],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0004720787,"about_ca_system_score_gemma":0.00007650176,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0002408629,"about_ca_topic_score_gemma":0.000439445,"domain_scores_codex":[0.9972597,0.0002328808,0.0009741512,0.0004957938,0.0004247934,0.0006126456],"domain_scores_gemma":[0.9988054,0.0001658011,0.0001122114,0.000554027,0.0002081273,0.0001544546],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0009999309,0.00542911,0.01762106,0.004385418,0.001053507,0.000188214,0.07315668,0.6901758,0.1616257,0.003079798,0.001149125,0.04113562],"study_design_scores_gemma":[0.002935334,0.0002647051,0.001327826,0.0008744012,0.00010523,0.00004642799,0.003724765,0.8820319,0.1070108,0.0003350175,0.0001815762,0.001161925],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1922471,0.00005666681,0.7992783,0.000008018234,0.002797377,0.0008920754,0.0001101025,0.0006696059,0.003940748],"genre_scores_gemma":[0.9984049,0.00002212082,0.0003540122,0.00003126698,0.0001244002,0.0008022154,0.00001105908,0.00008511052,0.0001649826],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8061578,"threshold_uncertainty_score":0.999831,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3164065772","doi":"10.1109/tvlsi.2021.3072866","title":"Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":42,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Polytechnique Montréal","funders":"","keywords":"Computer science; Low-density parity-check code; Field-programmable gate array; Computer hardware; Embedded system; Gate array; Scheduling (production processes); Parallel computing; Computer architecture; Decoding methods; Algorithm; Engineering","authors":[{"name":"Jérémy Nadal","is_ca":true},{"name":"Amer Baghdadi","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01427380275155997,"gpt":0.2541533053275753,"spread":0.2398795025760153,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006850181,0.00037514,0.000411318,0.0003223839,0.0005652748,0.0005356739,0.0004783014,0.0002634552,0.00004040494],"category_scores_gemma":[0.00004221313,0.0003531475,0.000198562,0.0007540173,0.00005473315,0.0007035817,0.00001029433,0.0007405487,0.00005660731],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001658245,"about_ca_system_score_gemma":0.0001542257,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00014098,"about_ca_topic_score_gemma":0.000634959,"domain_scores_codex":[0.9970512,0.0004115911,0.0006331698,0.0008735617,0.0005189136,0.0005115466],"domain_scores_gemma":[0.9982048,0.0002688566,0.0001886542,0.0007998647,0.0003538835,0.0001839135],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0004845869,0.004312512,0.00125938,0.001505657,0.0009960057,0.000568446,0.04831785,0.3336917,0.2453638,0.01954251,0.03228638,0.3116711],"study_design_scores_gemma":[0.001505793,0.0004281678,0.0001820128,0.001180713,0.00008989223,0.0008243474,0.003279213,0.5154331,0.4574109,0.001793174,0.01630721,0.001565487],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.009580839,0.0004892956,0.9836606,0.0005675682,0.002611829,0.0004317167,0.00003344435,0.001220503,0.001404197],"genre_scores_gemma":[0.9471171,0.00007749262,0.04943842,0.0002964573,0.0001332653,0.0001854779,0.0000135922,0.00004369295,0.002694425],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.9375364,"threshold_uncertainty_score":0.9998921,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2040579262","doi":"10.1109/tvlsi.2007.891085","title":"Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels","year":2007,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Electromagnetic Compatibility and Noise Suppression","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"Carleton University","funders":"University of Ottawa","keywords":"Passivity; Signal integrity; Computer science; Very-large-scale integration; Electronic engineering; Reciprocal; Overhead (engineering); Power integrity; Computer engineering; Embedded system; Engineering; Interconnection; Electrical engineering","authors":[{"name":"D. Saraswat","is_ca":true},{"name":"Ramachandra Achar","is_ca":true},{"name":"M. Nakhla","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.008621508935274247,"gpt":0.2236688288724724,"spread":0.2150473199371981,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008090524,0.0003538339,0.0003948847,0.0002382679,0.0003318267,0.0001415323,0.000130308,0.0002423641,0.00004650202],"category_scores_gemma":[0.000008575515,0.0003024199,0.00008907507,0.0003196295,0.00004206605,0.0004094556,0.000001913841,0.0003564313,0.0000143063],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002834313,"about_ca_system_score_gemma":0.00003440774,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001421226,"about_ca_topic_score_gemma":0.001486259,"domain_scores_codex":[0.9979066,0.0001018528,0.000640625,0.000475251,0.0003493453,0.000526309],"domain_scores_gemma":[0.9988355,0.0002044428,0.0001033756,0.0004192229,0.0002674831,0.0001699863],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00397923,0.002805097,0.0002909662,0.004295608,0.000870239,0.00002317318,0.01323072,0.6467816,0.251726,0.004849117,0.002142163,0.0690061],"study_design_scores_gemma":[0.00160986,0.0007557417,0.00008764658,0.0005391307,0.00008012314,0.00004541458,0.001770132,0.928561,0.06405406,0.00002726324,0.002031274,0.0004383956],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2559053,0.0001960142,0.7407368,0.00001992226,0.001154203,0.001224698,0.0001440711,0.0002505235,0.0003684721],"genre_scores_gemma":[0.9982056,0.00005600396,0.0005886077,0.00001903616,0.0001123087,0.0004743625,0.00007702859,0.00005641978,0.0004106269],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7423003,"threshold_uncertainty_score":0.9999428,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W1967779689","doi":"10.1109/tvlsi.2012.2198501","title":"Analysis and Design of On-Chip Decoupling Capacitors","year":2012,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"CMOS; NMOS logic; Capacitor; Electronic engineering; Chip; Decoupling capacitor; Decoupling (probability); Computer science; Integrated circuit design; Leakage (economics); Engineering; Electrical engineering; Transistor; Control engineering; Voltage","authors":[{"name":"Tasreen Charania","is_ca":true},{"name":"A. Opal","is_ca":true},{"name":"Manoj Sachdev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01463663006793878,"gpt":0.2187772200034506,"spread":0.2041405899355118,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006826389,0.0003353095,0.0004995391,0.0008781497,0.0001899893,0.00007220998,0.0001439916,0.0002300109,0.0000667537],"category_scores_gemma":[0.000007635281,0.0003043989,0.0001919339,0.0009453805,0.00005226918,0.0006266549,8.334335e-7,0.0003610183,0.00008103147],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002004144,"about_ca_system_score_gemma":0.00002173761,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00007316668,"about_ca_topic_score_gemma":0.00007383306,"domain_scores_codex":[0.9981453,0.000119557,0.0006219178,0.0002666012,0.0003978119,0.0004488013],"domain_scores_gemma":[0.9989514,0.00023679,0.0001060955,0.0004179906,0.0001042451,0.0001835226],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00006702517,0.0002331908,0.00177251,0.0001456009,0.0007404853,0.00000123976,0.00255158,0.9753988,0.01699473,0.00006848395,0.0002430231,0.001783373],"study_design_scores_gemma":[0.0005658467,0.0001691607,0.0009715272,0.0002099525,0.0005174521,0.00001184601,0.00118045,0.8202901,0.1754036,0.000004144837,0.0002091552,0.0004667217],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2869871,0.0001922387,0.7099963,0.000005195622,0.002016898,0.0003371183,0.00006713219,0.0002014707,0.0001964805],"genre_scores_gemma":[0.9983837,0.0001056418,0.0009694003,0.00001357678,0.0001579221,0.0001275188,0.00001087901,0.00005664689,0.0001747258],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7113966,"threshold_uncertainty_score":0.9999408,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2167801005","doi":"10.1109/tvlsi.2009.2032288","title":"Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Electromagnetic Compatibility and Noise Suppression","field":"Engineering","cited_by":41,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Western University","funders":"","keywords":"RLC circuit; Inductance; Spice; Crosstalk; Topology (electrical circuits); Electronic engineering; Transmission line; Capacitance; Electric power transmission; Network topology; Elmore delay; Mathematics; Computer science; Control theory (sociology); Propagation delay; Algorithm; Delay calculation; Engineering; Physics; Capacitor; Voltage; Telecommunications; Electrical engineering","authors":[{"name":"Sourajeet Roy","is_ca":true},{"name":"Anestis Dounavis","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01459827999181807,"gpt":0.2364976944954219,"spread":0.2218994145036038,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003272346,0.0002704265,0.0003494985,0.0003161916,0.0002600891,0.00008759479,0.0001191461,0.0001800231,0.0000411667],"category_scores_gemma":[0.00001494374,0.0002593045,0.0001348294,0.0003507372,0.00004020252,0.0001986595,0.00000159713,0.0003372847,0.000007535846],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001635053,"about_ca_system_score_gemma":0.00003935019,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001251446,"about_ca_topic_score_gemma":0.0002954014,"domain_scores_codex":[0.9982682,0.0001157081,0.0006704108,0.0003247181,0.0002976785,0.0003232743],"domain_scores_gemma":[0.9991596,0.0001498949,0.00007495937,0.0003375396,0.0001625229,0.000115483],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003949192,0.0001706194,0.00000346445,0.0000670763,0.00002796606,0.000001739397,0.001306337,0.9123804,0.08396785,0.0001413675,0.000009762925,0.001883931],"study_design_scores_gemma":[0.0004802557,0.0002251802,0.00001472256,0.0004278497,0.00005639161,0.00002972783,0.0005738081,0.9643742,0.03350579,0.00007285488,0.000009707958,0.0002294615],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.5002525,0.0002547495,0.4985549,0.00001224504,0.0004124657,0.0002475291,0.00004016945,0.0001133403,0.0001121184],"genre_scores_gemma":[0.9990307,0.00002459872,0.0007716694,0.00001635354,0.00004265102,0.00002699331,0.00001212445,0.00002807349,0.00004683693],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.4987782,"threshold_uncertainty_score":0.9999859,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2808558511","doi":"10.1109/tvlsi.2018.2838591","title":"A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS","year":2018,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Error Correcting Code Techniques","field":"Computer Science","cited_by":40,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Computer science; Decoding methods; Low-density parity-check code; Clock rate; CMOS; Chip; Node (physics); Scalability; Parallel computing; Computer hardware; Algorithm; Electronic engineering; Physics; Engineering; Telecommunications","authors":[{"name":"Mario Milicevic","is_ca":true},{"name":"P.G. Gulak","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01655553026681414,"gpt":0.2663288758883945,"spread":0.2497733456215804,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001183646,0.0005564096,0.0006558668,0.0007675229,0.0005322876,0.0005979594,0.000929085,0.0003837903,0.00004780673],"category_scores_gemma":[0.00004197494,0.0004699556,0.0002248678,0.001292688,0.0001422652,0.001325305,0.00001183791,0.0009220684,0.0001485611],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0005322928,"about_ca_system_score_gemma":0.0001944841,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0006425153,"about_ca_topic_score_gemma":0.007260681,"domain_scores_codex":[0.9957851,0.0006099325,0.001055936,0.001102943,0.0007130514,0.0007330195],"domain_scores_gemma":[0.9973946,0.0002517377,0.0003869996,0.00126282,0.0005092953,0.0001945394],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.005902596,0.02596508,0.01698864,0.001847547,0.001991824,0.001376452,0.2266404,0.03720916,0.4040764,0.005396944,0.0141719,0.258433],"study_design_scores_gemma":[0.002253214,0.0008152825,0.0004255965,0.00150074,0.00004077512,0.0001442264,0.001820849,0.9175996,0.07370488,0.00005699995,0.0008139907,0.0008238426],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.0638935,0.00004145284,0.9302518,0.0002020343,0.002653232,0.001091088,0.00002802462,0.001222119,0.0006167859],"genre_scores_gemma":[0.9415843,0.000009024648,0.05634911,0.0002231698,0.0001233005,0.0004543183,0.000005300992,0.00007035868,0.001181085],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8803905,"threshold_uncertainty_score":0.9997752,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2073321629","doi":"10.1109/tvlsi.2013.2255071","title":"Incremental Trace-Buffer Insertion for FPGA Debug","year":2013,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":39,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of British Columbia","funders":"","keywords":"Debugging; Computer science; TRACE (psycholinguistics); Field-programmable gate array; Embedded system; Routing (electronic design automation); Tracing; Background debug mode interface; Observability; Computer hardware; Process (computing); Parallel computing","authors":[{"name":"Eddie Hung","is_ca":true},{"name":"Steven J. E. Wilton","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02087027236584845,"gpt":0.2391193351511538,"spread":0.2182490627853053,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004913478,0.0003091481,0.0003165575,0.0003082766,0.000610195,0.0005548352,0.0004921294,0.0001938663,0.00006628906],"category_scores_gemma":[0.00001881381,0.0002771881,0.0002466992,0.0004739412,0.00003585505,0.001710908,0.000003128472,0.000306949,0.0003418765],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002464865,"about_ca_system_score_gemma":0.00008052067,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0004609003,"about_ca_topic_score_gemma":0.0003224138,"domain_scores_codex":[0.9976341,0.000172318,0.0006516535,0.000592983,0.0004501335,0.0004988796],"domain_scores_gemma":[0.9985943,0.0002020547,0.000179637,0.0005115364,0.0003373393,0.0001751052],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003646873,0.002884595,0.000708113,0.0004655226,0.0003678299,0.000014397,0.00679134,0.01898849,0.2671748,0.005977203,0.01310947,0.6834818],"study_design_scores_gemma":[0.001760546,0.0005332947,0.001010018,0.0004298539,0.0000577302,0.00008695228,0.001573644,0.8990889,0.0917405,0.0004063016,0.002520234,0.0007920585],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.07624967,0.00007672492,0.9189278,0.0003119841,0.002318508,0.001091809,0.00004947738,0.0004479722,0.0005260321],"genre_scores_gemma":[0.9964185,0.000009569852,0.001270751,0.0002378278,0.0001884858,0.0007773797,0.00001699799,0.00003096827,0.001049511],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9201688,"threshold_uncertainty_score":0.9999681,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2354420835","doi":"10.1109/tvlsi.2016.2558105","title":"5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications","year":2016,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Advancements in PLL and VCO Technologies","field":"Engineering","cited_by":39,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Calgary","funders":"Natural Sciences and Engineering Research Council of Canada; Canada Research Chairs; Alberta Innovates - Technology Futures; CMC Microsystems; University of Calgary","keywords":"Effective number of bits; Flash ADC; CMOS; Dynamic range; Successive approximation ADC; Comparator; Electronic engineering; Nyquist frequency; Spurious-free dynamic range; Nyquist rate; Analog-to-digital converter; Calibration; Oversampling; Computer science; Voltage; Electrical engineering; Physics; Sampling (signal processing); Engineering; Detector; Bandwidth (computing); Telecommunications","authors":[{"name":"Yongsheng Xu","is_ca":true},{"name":"Ge Wu","is_ca":true},{"name":"Leonid Belostotski","is_ca":true},{"name":"J.W. Haslett","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.00800949869732335,"gpt":0.2199419210098973,"spread":0.2119324223125739,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0002189499,0.0003307813,0.0003655445,0.0004061809,0.0001670728,0.00006111336,0.0002955221,0.0002330837,0.0001106561],"category_scores_gemma":[0.000007961503,0.0002675028,0.0001747397,0.0003296262,0.00007444176,0.0003854655,0.00000164152,0.0002485001,0.0002370217],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0004822373,"about_ca_system_score_gemma":0.00004079179,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00001486174,"about_ca_topic_score_gemma":0.0001446481,"domain_scores_codex":[0.9982815,0.00004377658,0.0006178074,0.0004109711,0.0001968878,0.0004490222],"domain_scores_gemma":[0.9989948,0.000209062,0.00009339943,0.0005214737,0.0001038113,0.00007744859],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.0005192642,0.001648468,0.0004031308,0.0006193364,0.0004682104,0.000006266581,0.0006693854,0.3684086,0.1442472,0.001905469,0.006124507,0.4749801],"study_design_scores_gemma":[0.006932415,0.0005819618,0.00009129597,0.0015169,0.0001320789,0.00001732447,0.001935455,0.3809012,0.4120833,0.0002678622,0.1940479,0.001492355],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.006380375,0.00009355236,0.9890409,0.0001370053,0.0009506964,0.001550442,0.00054278,0.000840639,0.0004636516],"genre_scores_gemma":[0.9880382,0.00003060661,0.00533384,0.00002288867,0.0001012142,0.004110496,0.00004075855,0.00006740227,0.002254629],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.983707,"threshold_uncertainty_score":0.9999777,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3131053867","doi":"10.1109/tvlsi.2021.3056243","title":"Machine-Learning-Based Self-Tunable Design of Approximate Computing","year":2021,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":38,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Benchmark (surveying); Overhead (engineering); Computer engineering; Set (abstract data type); Energy consumption; Efficient energy use; Software; Reduction (mathematics); Constraint (computer-aided design); Embedded system","authors":[{"name":"Mahmoud Masadeh","is_ca":true},{"name":"Osman Hasan","is_ca":true},{"name":"Sofiène Tahar","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01037863767093995,"gpt":0.2039752414382916,"spread":0.1935966037673516,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0006932399,0.0004084198,0.0005499586,0.0003678477,0.0003057501,0.0001419488,0.0002247568,0.0002604712,0.0001214723],"category_scores_gemma":[0.00001244508,0.0004076431,0.0002111671,0.0008192809,0.00003594956,0.0004026258,0.000001985258,0.0006511025,0.0001170347],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0003013134,"about_ca_system_score_gemma":0.0001343135,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00004630893,"about_ca_topic_score_gemma":0.00003937692,"domain_scores_codex":[0.9973828,0.0003554384,0.0008198861,0.0004199269,0.000506451,0.0005154986],"domain_scores_gemma":[0.9986597,0.0002448577,0.0001553087,0.000490333,0.0003158067,0.0001339662],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003707494,0.0002555777,0.00005441043,0.0003956855,0.0001231074,0.0000119263,0.0007409664,0.9780357,0.01942753,0.00004268547,0.0002423503,0.0006329094],"study_design_scores_gemma":[0.0007796399,0.0001105464,0.00001117058,0.0003023036,0.00006226372,0.00002330904,0.0004376285,0.7846966,0.2124367,0.000004180386,0.0008303061,0.0003053475],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01531512,0.00039593,0.9795733,0.00001858474,0.002309672,0.0005892807,0.00008765938,0.001060667,0.0006497996],"genre_scores_gemma":[0.9925044,0.00007778765,0.006564966,0.00002699185,0.00008172441,0.00009822102,0.00004835062,0.0001060561,0.0004915062],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9771893,"threshold_uncertainty_score":0.9998375,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2000410358","doi":"10.1109/tvlsi.2007.893580","title":"A New Single-Ended SRAM Cell With Write-Assist","year":2007,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":38,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"Simon Fraser University","funders":"Natural Sciences and Engineering Research Council of Canada; CMC Microsystems","keywords":"Static random-access memory; NMOS logic; Leakage (economics); Computer science; Leakage power; Random access memory; Memory cell; Read-write memory; Electronic engineering; Computer hardware; Electrical engineering; Voltage; Transistor; Engineering","authors":[{"name":"Richard F. Hobson","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.008651370039534095,"gpt":0.19577098013293,"spread":0.1871196100933959,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000484837,0.000532625,0.0004713192,0.0005762468,0.0002945646,0.0002665429,0.0002875255,0.0003433676,0.0001494606],"category_scores_gemma":[0.000002888473,0.0004682106,0.0001847461,0.0009011151,0.00004971833,0.000811299,0.000001206767,0.0006838457,0.0004835674],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0005944544,"about_ca_system_score_gemma":0.00009460846,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001568947,"about_ca_topic_score_gemma":0.001411466,"domain_scores_codex":[0.9972454,0.00007245605,0.0007799125,0.0004883332,0.0006679927,0.000745857],"domain_scores_gemma":[0.9986049,0.0001299046,0.0001175398,0.0006354086,0.0001718942,0.0003403868],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.001226565,0.002402392,0.000490098,0.00111552,0.0007365823,0.0001860909,0.008332321,0.6620467,0.2539299,0.000496014,0.02697306,0.04206481],"study_design_scores_gemma":[0.004771628,0.001231733,0.0004943801,0.00107721,0.0002773059,0.0002164597,0.004240966,0.2057294,0.7526845,0.00001807031,0.02729608,0.001962243],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.06818354,0.0001820849,0.9175504,0.00003047213,0.003641966,0.0006974463,0.00007547648,0.001065593,0.008572995],"genre_scores_gemma":[0.9917344,0.00002064203,0.003006074,0.00004751042,0.0002838699,0.00008619694,0.0000284562,0.0001315409,0.004661282],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9235509,"threshold_uncertainty_score":0.999777,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2044605272","doi":"10.1109/tvlsi.2012.2202409","title":"Scalable Signal Selection for Post-Silicon Debug","year":2012,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":36,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of British Columbia","funders":"","keywords":"Observability; Computer science; Scalability; Debugging; Benchmark (surveying); Computer engineering; Metric (unit); Theoretical computer science; Embedded system; Algorithm; Engineering; Mathematics","authors":[{"name":"Eddie Hung","is_ca":true},{"name":"Steven J. E. Wilton","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.0193880468798241,"gpt":0.2453616756555041,"spread":0.22597362877568,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008739501,0.0003126925,0.0003284123,0.0003504689,0.0007730436,0.0003572703,0.0003996113,0.0002234633,0.00004848588],"category_scores_gemma":[0.0000228775,0.0002894179,0.0002576489,0.0006683501,0.00003165529,0.00187128,0.000002676821,0.0003453896,0.0001921095],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000258289,"about_ca_system_score_gemma":0.0001155672,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0002418426,"about_ca_topic_score_gemma":0.0002746817,"domain_scores_codex":[0.9975541,0.000198424,0.0005730491,0.0005107186,0.0004299243,0.0007337561],"domain_scores_gemma":[0.9984512,0.000280678,0.0001872031,0.0003830007,0.0004534886,0.0002443991],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00009816766,0.005197495,0.004680297,0.000730684,0.0005423803,0.000006837733,0.01108022,0.05728142,0.429925,0.01885926,0.008127489,0.4634708],"study_design_scores_gemma":[0.001071155,0.0005241543,0.0003590315,0.0002856698,0.00007403067,0.0001632876,0.0008990592,0.8661344,0.1256741,0.00009590021,0.0040262,0.0006930275],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.02812446,0.0001435425,0.966628,0.0001442115,0.003024542,0.000690942,0.00006983296,0.0005481806,0.0006263289],"genre_scores_gemma":[0.9960983,0.00000642487,0.001314385,0.0002195103,0.0004365639,0.0003183342,0.00002006867,0.00003411594,0.001552268],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9679739,"threshold_uncertainty_score":0.9999558,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2117439128","doi":"10.1109/tvlsi.2002.1043339","title":"An ultra-fast instruction set simulator","year":2002,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":34,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Workstation; Host (biology); Instruction set; Interface (matter); Code (set theory); Computer architecture; Set (abstract data type); Parallel computing; Operating system; Embedded system; Programming language","authors":[{"name":"Jianwen Zhu","is_ca":true},{"name":"Daniel D. Gajski","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01833145711488193,"gpt":0.2518577246971913,"spread":0.2335262675823094,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004095919,0.0003352152,0.0003249547,0.0004533722,0.0005994764,0.0005410674,0.0006633533,0.0002573797,0.00008413433],"category_scores_gemma":[0.000008228824,0.0003202374,0.0001715241,0.0008008627,0.00005027421,0.001536563,0.000001824986,0.0004202797,0.0002076241],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001933355,"about_ca_system_score_gemma":0.0000340379,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00007676925,"about_ca_topic_score_gemma":0.00005545286,"domain_scores_codex":[0.9973848,0.0003476224,0.0006403493,0.0006901636,0.0005306971,0.0004063868],"domain_scores_gemma":[0.9982822,0.0000860688,0.0002134613,0.0009157778,0.0002933544,0.0002091701],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003485539,0.0009103249,0.00005905309,0.00004924928,0.00006661833,0.000009410302,0.004387795,0.9475794,0.004617144,0.002189453,0.003031703,0.03706503],"study_design_scores_gemma":[0.0005501508,0.0002571682,0.00002124661,0.00009591504,0.0000133593,0.00006067185,0.0003125635,0.9677834,0.02855843,0.00004928901,0.001942519,0.0003552912],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01464334,0.00005117411,0.9791957,0.0001251738,0.002607666,0.0004431584,0.00005882938,0.001564427,0.001310548],"genre_scores_gemma":[0.9902837,0.00004752353,0.008145599,0.0001633887,0.000162471,0.00008363212,0.00001775795,0.00003160326,0.001064288],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9756404,"threshold_uncertainty_score":0.999925,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W2089902593","doi":"10.1109/tvlsi.2008.2003004","title":"Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns","year":2009,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Numerical Methods and Algorithms","field":"Computer Science","cited_by":33,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"McMaster University","funders":"","keywords":"Multiplication (music); Adder; Constant (computer programming); Computer science; Heuristic; Algorithm; Multiplication algorithm; Arithmetic; Divide and conquer algorithms; Parallel computing; Mathematics; Combinatorics; Artificial intelligence; Binary number","authors":[{"name":"Jason Thong","is_ca":true},{"name":"Nicola Nicolici","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01695558374234841,"gpt":0.2549822595759776,"spread":0.2380266758336292,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0004731781,0.0003420482,0.0003809612,0.0003278212,0.0003873824,0.0004627125,0.0004614163,0.0001604929,0.00003573461],"category_scores_gemma":[0.00002340101,0.0002934628,0.0002345869,0.0006749728,0.00004498462,0.0004190225,0.000002519656,0.0003571719,0.0002026023],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000351106,"about_ca_system_score_gemma":0.00006881002,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003291374,"about_ca_topic_score_gemma":0.000007111143,"domain_scores_codex":[0.9971622,0.0003242235,0.000637602,0.0007435359,0.0006781152,0.0004543314],"domain_scores_gemma":[0.9982004,0.0003269382,0.0002286117,0.0008115939,0.0002287868,0.0002036885],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0001459705,0.005379008,0.00002317556,0.00006371966,0.00006061966,0.00002488199,0.001229178,0.4090156,0.07730369,0.002563481,0.0003631538,0.5038275],"study_design_scores_gemma":[0.0006280579,0.000534347,0.00009957854,0.0003311429,0.00001342141,0.00001107203,0.0001447354,0.9630525,0.03375278,0.00004770381,0.001040825,0.0003438982],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.008184424,0.00001746831,0.9872344,0.0006149078,0.001539018,0.0006661225,0.0001183148,0.000438996,0.001186402],"genre_scores_gemma":[0.9851284,0.000004044664,0.01363817,0.0005821388,0.0001032942,0.00009050081,0.00001489692,0.00002075937,0.0004177922],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.976944,"threshold_uncertainty_score":0.9999518,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}