{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":5,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":5,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"cf0a2144a34f","filters":{"venue":"Modeling of systems and processes"}},"results":[{"id":"W4380610161","doi":"10.12737/2219-0767-2023-16-2-85-93","title":"Routing buses impact analysis on the results on modeling standard digital cell on CMOS 28 nm","year":2023,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Netlist; Routing (electronic design automation); Standard cell; Standard deviation; Set (abstract data type); Computer science; Simulation; CMOS; Real-time computing; Algorithm; Electronic engineering; Embedded system; Statistics; Integrated circuit; Engineering; Mathematics","authors":[{"name":"Sergey Il'in","is_ca":true},{"name":"Dmitriy Kopeykin","is_ca":true},{"name":"О.В. Ласточкин","is_ca":true},{"name":"Irina N. Polunina","is_ca":true},{"name":"Dmitriy Shipicin","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.03323241672115342,"gpt":0.2527429747662627,"spread":0.2195105580451093,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0004865174,0.0002383727,0.0003834162,0.0003075544,0.0001410405,0.0002220878,0.0001573396,0.00009281759,0.000001047027],"category_scores_gemma":[0.0001382597,0.0001546448,0.0001012533,0.0007606387,0.00001382037,0.000142735,0.00002150831,0.0001710845,0.000005245739],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00004166786,"about_ca_system_score_gemma":0.00003278951,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001210204,"about_ca_topic_score_gemma":0.000004516229,"domain_scores_codex":[0.9986498,0.00002064089,0.0004485293,0.0002683718,0.0003455559,0.0002671403],"domain_scores_gemma":[0.9991909,0.0002469918,0.00008133408,0.0002746866,0.0001496069,0.00005652832],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00007127799,0.00001174752,0.00005717012,0.0003735542,0.000114477,0.000002343822,0.000629043,0.9979525,0.0001512115,0.00005224446,0.0001598178,0.0004245679],"study_design_scores_gemma":[0.0001455405,0.0002077399,0.000002641963,0.000619892,0.0000569059,7.297368e-7,0.0005964933,0.9961092,0.001857739,0.0002000646,0.00001976222,0.0001832219],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.8964126,0.0006543014,0.09715021,0.00004189029,0.00007091572,0.0003012966,0.0002926904,0.0007054153,0.004370653],"genre_scores_gemma":[0.9994091,0.0003308633,0.00003477749,0.000008778537,0.00007838746,0.00002589931,0.00002574822,0.0000412088,0.00004518194],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.1029965,"threshold_uncertainty_score":0.630623,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4411541241","doi":"10.12737/2219-0767-2025-62-70","title":"Architecture of a test structure for verification of libraries of standard elements in silicon based on a pipeline-distribution approach","year":2025,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"Radiation Effects in Electronics","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Pipeline (software); Computer science; Standard cell; Multiplexer; CMOS; Computer engineering; Computer architecture; Electronic engineering; Integrated circuit; Engineering; Programming language; Multiplexing; Operating system","authors":[{"name":"S. V. Gavrilov","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.00708928536043458,"gpt":0.2189952973093175,"spread":0.2119060119488829,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001586102,0.00008182054,0.0002495128,0.000117195,0.00001184196,0.000006240633,0.00006252868,0.00006832139,2.106065e-7],"category_scores_gemma":[0.0002113092,0.00007510372,0.00001770554,0.000247509,0.00001982339,0.0000447885,0.00000391942,0.00005504072,2.432255e-9],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00002349359,"about_ca_system_score_gemma":0.0001163787,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00001910741,"about_ca_topic_score_gemma":0.000006160633,"domain_scores_codex":[0.9993041,0.00001317018,0.000401999,0.0000962909,0.0001072275,0.00007723261],"domain_scores_gemma":[0.9994546,0.0001422995,0.0001285568,0.0001022784,0.0001635286,0.000008764896],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00009271195,0.00002654957,0.0005876858,0.01505024,0.00001273595,8.566242e-9,0.0001789817,0.9775585,0.004971064,0.0006119639,0.00001176634,0.0008978217],"study_design_scores_gemma":[0.0004456442,0.0001125761,0.00004300907,0.0005884834,0.00001525998,1.056939e-7,0.00007890293,0.9523243,0.04575589,0.00056474,0.00002420472,0.00004684749],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.441792,0.001891311,0.5553012,0.000009618481,0.00003002642,0.0004291406,0.0004845786,0.00001489248,0.00004716399],"genre_scores_gemma":[0.998441,0.00002242411,0.001390506,0.000001253745,0.000008048708,0.00003014049,0.00009673892,0.000008007059,0.000001830358],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.556649,"threshold_uncertainty_score":0.3062641,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4408662702","doi":"10.12737/2219-0767-2025-44-51","title":"A set-theoretic model of a test structure for verifying in silicon libraries of standard digital elements","year":2025,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Set (abstract data type); Computer science; Test (biology); Programming language; Geology","authors":[{"name":"Sergey Il'in","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02561653560717215,"gpt":0.2522305017189199,"spread":0.2266139661117477,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001473848,0.00008980078,0.0002883337,0.0001228869,0.00003714559,0.00007966279,0.0002218782,0.00004216807,1.046524e-7],"category_scores_gemma":[0.0002824225,0.0000776834,0.000021662,0.0002572876,0.00003918978,0.0003849858,0.00006776615,0.00004068098,6.329496e-9],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000006999834,"about_ca_system_score_gemma":0.0002427592,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00002512047,"about_ca_topic_score_gemma":0.000004610003,"domain_scores_codex":[0.9991239,0.000006579619,0.00044608,0.0001797573,0.0001238278,0.0001199014],"domain_scores_gemma":[0.9992911,0.0001712879,0.0001692089,0.0001235773,0.0002272386,0.00001755704],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00002392445,0.00008238348,0.05822172,0.04002962,0.00006540188,0.000001042697,0.009224814,0.7836378,0.009865886,0.08047941,0.00001168951,0.01835632],"study_design_scores_gemma":[0.0002838979,0.0000709196,0.000007149372,0.001419002,0.000006939522,7.919409e-7,0.0003599758,0.9629661,0.002831702,0.03198674,0.000001556953,0.00006523276],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.4398803,0.001458965,0.5582812,0.00001561335,0.00002228351,0.0001465703,0.00009174299,0.00001351616,0.00008982258],"genre_scores_gemma":[0.9984211,0.00001869395,0.001524742,0.000004862978,0.000005948937,0.000008601995,0.000002943166,0.000004615495,0.000008548196],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.5585408,"threshold_uncertainty_score":0.3167837,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4411985875","doi":"10.12737/2219-0767-2025-18-2-62-70","title":"Architecture of a test structure for verification of libraries of standard elements in silicon based on a pipeline-distribution approach","year":2025,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"Radiation Effects in Electronics","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Pipeline (software); Architecture; Computer science; Test (biology); Distribution (mathematics); Computer architecture; Programming language; Mathematics; Geology; Geography; Archaeology","authors":[{"name":"Sergey Il'in","is_ca":true},{"name":"S. V. Gavrilov","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.00708928536043458,"gpt":0.2189952973093175,"spread":0.2119060119488829,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001586102,0.00008182054,0.0002495128,0.000117195,0.00001184196,0.000006240633,0.00006252868,0.00006832139,2.106065e-7],"category_scores_gemma":[0.0002113092,0.00007510372,0.00001770554,0.000247509,0.00001982339,0.0000447885,0.00000391942,0.00005504072,2.432255e-9],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00002349359,"about_ca_system_score_gemma":0.0001163787,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00001910741,"about_ca_topic_score_gemma":0.000006160633,"domain_scores_codex":[0.9993041,0.00001317018,0.000401999,0.0000962909,0.0001072275,0.00007723261],"domain_scores_gemma":[0.9994546,0.0001422995,0.0001285568,0.0001022784,0.0001635286,0.000008764896],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00009271195,0.00002654957,0.0005876858,0.01505024,0.00001273595,8.566242e-9,0.0001789817,0.9775585,0.004971064,0.0006119639,0.00001176634,0.0008978217],"study_design_scores_gemma":[0.0004456442,0.0001125761,0.00004300907,0.0005884834,0.00001525998,1.056939e-7,0.00007890293,0.9523243,0.04575589,0.00056474,0.00002420472,0.00004684749],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.441792,0.001891311,0.5553012,0.000009618481,0.00003002642,0.0004291406,0.0004845786,0.00001489248,0.00004716399],"genre_scores_gemma":[0.998441,0.00002242411,0.001390506,0.000001253745,0.000008048708,0.00003014049,0.00009673892,0.000008007059,0.000001830358],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.556649,"threshold_uncertainty_score":0.3062641,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4380610092","doi":"10.12737/2219-0767-2023-16-2-93-100","title":"Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures","year":2023,"lang":"en","type":"article","venue":"Modeling of systems and processes","topic":"Advancements in Semiconductor Devices and Circuit Design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Mitel (Canada)","funders":"","keywords":"Transconductance; Transistor; CMOS; Voltage; Materials science; Threshold voltage; Scalability; Optoelectronics; Electronic engineering; Electrical engineering; Computer science; Engineering","authors":[{"name":"Andrey Osykin","is_ca":false},{"name":"А.Г. Потупчик","is_ca":true},{"name":"Kirill A. Panyshev","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.04766088655271161,"gpt":0.2478000312167696,"spread":0.200139144664058,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001341945,0.0001128494,0.0002202279,0.00006121724,0.00005475092,0.00001240331,0.0001560317,0.00006276101,9.988078e-7],"category_scores_gemma":[0.00002408849,0.00008435542,0.00003033864,0.0002012428,0.00003259593,0.00009786917,0.00004141189,0.00008691251,8.066734e-7],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00002275864,"about_ca_system_score_gemma":0.00003533901,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006840492,"about_ca_topic_score_gemma":0.0001121687,"domain_scores_codex":[0.9992403,0.00001230766,0.0003118961,0.0001396452,0.0001425652,0.0001532583],"domain_scores_gemma":[0.999619,0.0000328364,0.00005707908,0.0001956732,0.000071389,0.00002403795],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.000003814333,0.000006296257,0.001046369,0.001745716,0.0000176607,4.313369e-7,0.001127752,0.9631508,0.0325469,0.0001889879,0.0001375203,0.00002775378],"study_design_scores_gemma":[0.0001636369,0.00001022687,0.00002560301,0.0004587693,0.0000123629,0.000002932957,0.0004323228,0.9926954,0.004432012,0.001549181,0.00009761654,0.0001199231],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.9857276,0.009402467,0.004048233,0.00001048778,0.0002419521,0.0001932791,0.00004006919,0.00006496612,0.0002709279],"genre_scores_gemma":[0.998504,0.001208573,0.00003703944,0.000005418693,0.00002855613,0.00002612122,0.000003567018,0.00001919595,0.0001674795],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.02954461,"threshold_uncertainty_score":0.3439914,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}