{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":6,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":6,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"0a973c333757","filters":{"venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)"}},"results":[{"id":"W3145549985","doi":"10.1109/dac.2003.1218834","title":"A static pattern-independent technique for power grid voltage integrity verification","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":18,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Computer science; Power grid; Grid; Voltage; Power (physics); Electrical engineering; Engineering; Mathematics","authors":[{"name":"D. Kuoroussis","is_ca":true},{"name":"Farid N. Najm","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.0271399639559795,"gpt":0.2421491316090504,"spread":0.2150091676530709,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001172887,0.0007275544,0.0006058707,0.0004499841,0.0002357894,0.0004547694,0.0007357398,0.0004951356,0.000189801],"category_scores_gemma":[0.0004679625,0.0007609791,0.0001187831,0.000938353,0.000117045,0.001742644,0.00003829092,0.0006056763,0.000629024],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.001099386,"about_ca_system_score_gemma":0.0005510154,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003466297,"about_ca_topic_score_gemma":0.000004936009,"domain_scores_codex":[0.9964865,0.00003123664,0.001028223,0.000804257,0.0007321796,0.0009175353],"domain_scores_gemma":[0.9966663,0.00008886561,0.0003749424,0.0004220902,0.002162083,0.0002856995],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.00009514097,0.0002986815,0.0003972163,0.00135999,0.000157697,0.000008491084,0.003486071,0.003265466,0.9535223,0.004913864,0.02667944,0.005815628],"study_design_scores_gemma":[0.002114995,0.0005354087,0.001223273,0.0006299552,0.0001080775,0.0000558136,0.0004608995,0.3399855,0.6482085,0.002454261,0.002724999,0.001498297],"study_design_candidate":"bench_or_experimental","study_design_consensus":"bench_or_experimental","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.03987284,0.00002346264,0.9513423,0.0001612658,0.001573463,0.00395498,0.00008638595,0.001940453,0.001044829],"genre_scores_gemma":[0.8541473,0.000125418,0.1417721,0.0002036539,0.0002415512,0.003072813,0.0001043684,0.0001714223,0.0001614119],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.8142744,"threshold_uncertainty_score":0.9994841,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4242199054","doi":"10.1109/dac.2003.1219139","title":"Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":8,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Die (integrated circuit); Power grid; Voltage; Voltage drop; Leakage (economics); Grid; Leakage power; Computer science; Environmental science; Electrical engineering; Electronic engineering; Power (physics); Engineering; Mechanical engineering; Transistor; Mathematics; Physics","authors":[{"name":"I.A. Ferzli","is_ca":true},{"name":"F.N. Najm","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.04336309476274766,"gpt":0.2768579591042649,"spread":0.2334948643415173,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001083393,0.0004865301,0.0005696337,0.0003686567,0.000414645,0.000648261,0.0009067028,0.0002394479,0.0000550343],"category_scores_gemma":[0.003579263,0.0005101042,0.00006633244,0.001357066,0.000159503,0.002524362,0.0000904011,0.0003715674,0.0001886299],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002658146,"about_ca_system_score_gemma":0.001890733,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006436903,"about_ca_topic_score_gemma":0.000004226885,"domain_scores_codex":[0.9962776,0.00005571871,0.001174711,0.0009046469,0.0009178118,0.0006694875],"domain_scores_gemma":[0.9948177,0.0002440175,0.0009950149,0.0003585251,0.003296547,0.0002882295],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00001444224,0.0007614215,0.001315241,0.001099159,0.0001861885,0.00006550364,0.02116596,0.02305749,0.4583035,0.4648322,0.000981571,0.02821738],"study_design_scores_gemma":[0.0008951657,0.000289608,0.001413572,0.000466407,0.00005325373,0.00008124857,0.0003291184,0.9052488,0.07152152,0.0190288,0.00001240483,0.0006601551],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.06606331,0.000009906051,0.9295933,0.0002110088,0.00074117,0.0008062128,0.00001796981,0.0008594083,0.001697778],"genre_scores_gemma":[0.7828525,0.000005610358,0.2167129,0.0001399323,0.00008444015,0.0001056885,0.00001900787,0.00003541877,0.00004453176],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.8821912,"threshold_uncertainty_score":0.9997351,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4252940155","doi":"10.1109/dac.2003.1219000","title":"Model order reduction of nonuniform transmission lines using integrated congruence transform","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Model Reduction and Neural Networks","field":"Physics and Astronomy","cited_by":1,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Carleton University","funders":"","keywords":"Orthonormal basis; Basis function; Algorithm; Computer science; Congruence (geometry); Model order reduction; Orthogonal basis; Basis (linear algebra); Mathematics; Orthonormality; Topology (electrical circuits); Mathematical optimization; Projection (relational algebra); Mathematical analysis","authors":[{"name":"E. Gad","is_ca":true},{"name":"M. Nakhla","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.05159047128044988,"gpt":0.2770223753109597,"spread":0.2254319040305098,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0003116285,0.0004448018,0.0004723283,0.000211208,0.0002433768,0.0001459807,0.0002957401,0.0002064585,0.0002997549],"category_scores_gemma":[0.00002830572,0.0004096593,0.000113492,0.00111519,0.0001710879,0.001274747,0.00001276347,0.0003309842,0.00002831031],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001551979,"about_ca_system_score_gemma":0.0009526831,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0002026941,"about_ca_topic_score_gemma":0.000001188365,"domain_scores_codex":[0.9977059,0.00002386452,0.0008200134,0.0005450864,0.000433854,0.0004713336],"domain_scores_gemma":[0.9961365,0.00001540176,0.000470616,0.0001574667,0.003006232,0.000213801],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.000206618,0.0003479421,0.00006955594,0.0001742347,0.00008235123,5.511022e-7,0.002387718,0.1658706,0.7794983,0.01428869,0.0007691504,0.0363043],"study_design_scores_gemma":[0.0008351383,0.0000925815,0.00000852366,0.0002931855,0.0000627578,0.00001122036,0.000485827,0.7775123,0.2163204,0.003891624,0.0001266004,0.0003599126],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2324076,0.00001188446,0.7641481,0.0001974844,0.0003530587,0.0007931273,0.0000186227,0.0001831505,0.001887078],"genre_scores_gemma":[0.8474504,0.00007187571,0.151481,0.00003233366,0.000205627,0.00007420363,0.00005465229,0.0000454461,0.0005843876],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.6150429,"threshold_uncertainty_score":0.9998356,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4229722470","doi":"10.1109/dac.2003.1219088","title":"Synthesizing optimal filters for crosstalk-cancellation for high-speed buses","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of British Columbia","funders":"","keywords":"Crosstalk; Computer science; Electronic engineering; Performance metric; Speedup; Bandwidth (computing); Computer engineering; Algorithm; Telecommunications; Parallel computing; Engineering","authors":[{"name":"Jiaying Ren","is_ca":true},{"name":"M. Greenstreet","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.03113258825884511,"gpt":0.23741667127861,"spread":0.2062840830197649,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000761458,0.000738688,0.0006738235,0.000392948,0.0004355415,0.0006960941,0.0005808417,0.0004018462,0.00008532433],"category_scores_gemma":[0.0006478658,0.0008042605,0.0001402898,0.0008025121,0.0001493052,0.002072552,0.00002793067,0.0002287907,0.0001834088],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0008121258,"about_ca_system_score_gemma":0.0004633979,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00002224759,"about_ca_topic_score_gemma":0.000003333284,"domain_scores_codex":[0.9965935,0.00001707227,0.0009715432,0.0007930681,0.0005350886,0.001089694],"domain_scores_gemma":[0.9966623,0.0002432258,0.0003920926,0.0002929724,0.002159995,0.0002494173],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0003800876,0.000137648,0.0001305187,0.001697855,0.0002360112,0.000002521375,0.003647939,0.2292647,0.7316993,0.008068583,0.01782108,0.006913775],"study_design_scores_gemma":[0.001983096,0.000304773,0.0002269523,0.0003493081,0.00009980831,0.00001142342,0.0001945627,0.6107948,0.3829285,0.0007636724,0.001462464,0.0008806038],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2249045,0.00005619256,0.7677401,0.0001414342,0.00158409,0.003224154,0.00009205544,0.001809572,0.0004479686],"genre_scores_gemma":[0.6781061,0.0001134096,0.3196125,0.00009449341,0.000456582,0.0009944037,0.00008227603,0.0001852424,0.000354942],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.4532017,"threshold_uncertainty_score":0.9994408,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4244938795","doi":"10.1109/dac.2003.1219137","title":"Design of a 17-million gate network processor using a design factory","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":false,"ca_fund":false,"ca_venue":false,"about_ca":true},"ca_institutions":"","funders":"","keywords":"Factory (object-oriented programming); Computer science; Network processor; Computer network; Programming language","authors":[{"name":"G.-E. Descamps","is_ca":false},{"name":"S. Bagalkotkar","is_ca":false},{"name":"S. Ganesan","is_ca":false},{"name":"S. Iyengar","is_ca":false},{"name":"A. Pirson","is_ca":false}],"retraction":null,"screen_n_in":null,"score":{"opus":0.08659970242603296,"gpt":0.2826864506209027,"spread":0.1960867481948697,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.003841568,0.001029888,0.001212255,0.0007107625,0.0004619302,0.0008168868,0.002524805,0.0006651587,0.00004545152],"category_scores_gemma":[0.0009088943,0.001043136,0.0001635568,0.003514142,0.0002749424,0.003606816,0.0002163036,0.0005211868,0.0001558279],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0008770456,"about_ca_system_score_gemma":0.003095183,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00006593804,"about_ca_topic_score_gemma":0.000001540465,"domain_scores_codex":[0.9931157,0.0003879166,0.001901667,0.001603076,0.001536545,0.001455072],"domain_scores_gemma":[0.9909618,0.0003291145,0.002087966,0.0008220287,0.005369129,0.0004298913],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0002343016,0.0005012637,0.0001428505,0.001006813,0.0002232245,0.00003856445,0.008870601,0.1249578,0.8289344,0.01641973,0.01479449,0.00387602],"study_design_scores_gemma":[0.0009161667,0.0006522014,0.00004345249,0.001208718,0.00006909372,0.0001192759,0.0001151324,0.7280889,0.2548965,0.01279048,0.00006881161,0.001031304],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"methods","genre_scores_codex":[0.003927921,0.0001649182,0.9879499,0.00009538727,0.0006842845,0.004261413,0.000005702103,0.002327523,0.0005829722],"genre_scores_gemma":[0.2687608,0.0001034737,0.7298859,0.00019593,0.0002179545,0.0005129004,0.000005259976,0.0001015274,0.0002162286],"genre_candidate":"methods","genre_consensus":"methods","teacher_disagreement_score":0.6031311,"threshold_uncertainty_score":0.9992019,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4234208104","doi":"10.1109/dac.2003.1219120","title":"A retargetable microarchitecture simulator","year":2004,"lang":"en","type":"article","venue":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","topic":"Parallel Computing and Optimization Techniques","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Toronto","funders":"","keywords":"Microarchitecture; Computer science; Computer architecture; Microprocessor; Instruction set; Embedded system; Branch predictor; Computer architecture simulator; Parallel computing","authors":[{"name":"Wai Sum Mong","is_ca":true},{"name":"Jianwen Zhu","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.02517826436919297,"gpt":0.2462476084909273,"spread":0.2210693441217343,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.0008806436,0.0005427969,0.0005070047,0.0003752751,0.0004197482,0.001014308,0.001653181,0.0003184066,0.00005752216],"category_scores_gemma":[0.0006136057,0.0005383024,0.0001084932,0.001761412,0.0001285586,0.001470711,0.0001817455,0.0003868665,0.0004740947],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002880136,"about_ca_system_score_gemma":0.0009029842,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.00003043915,"about_ca_topic_score_gemma":0.000001223342,"domain_scores_codex":[0.996654,0.00007158465,0.0007349473,0.00104857,0.000679365,0.0008115444],"domain_scores_gemma":[0.9960234,0.00007425956,0.0005231845,0.0005089873,0.002565284,0.0003049058],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.000172112,0.001231538,0.001038588,0.0008154906,0.0003222217,0.00005773628,0.01572034,0.3032709,0.3283406,0.2258003,0.09089945,0.03233066],"study_design_scores_gemma":[0.0008511831,0.0002018395,0.0001241588,0.0001896285,0.00001976182,0.00005366963,0.00003063614,0.902366,0.083953,0.008905694,0.002571303,0.0007331708],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"methods","genre_scores_codex":[0.008059493,0.00005914251,0.9831364,0.0007991446,0.0005522295,0.0009557066,0.000004778369,0.003219303,0.003213843],"genre_scores_gemma":[0.2638443,0.00006150243,0.7342675,0.0007059887,0.0001511978,0.0001035453,0.00001140272,0.00004153897,0.0008129345],"genre_candidate":"methods","genre_consensus":"methods","teacher_disagreement_score":0.599095,"threshold_uncertainty_score":0.9997069,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}