{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":2,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":2,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"34e9ba243374","filters":{"venue":"Proceedings EURO-DAC '92: European Design Automation Conference"}},"results":[{"id":"W4251343752","doi":"10.1109/eurdac.1992.246230","title":"Routing algorithms for multi-chip modules","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":4,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"Concordia University","funders":"","keywords":"Computer science; Static routing; Routing (electronic design automation); Link-state routing protocol; Equal-cost multi-path routing; Policy-based routing; Placement; Multipath routing; Dynamic Source Routing; Destination-Sequenced Distance Vector routing; Algorithm; Channel (broadcasting); Distributed computing; Computer network; Physical design; Routing protocol; Embedded system; Circuit design","authors":[{"name":"Jens Lienig","is_ca":true},{"name":"K. Thulasiraman","is_ca":true},{"name":"M.N.S. Swamy","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.09028723337086844,"gpt":0.2670350396055092,"spread":0.1767478062346408,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001383099,0.0004759351,0.0003530021,0.0002519419,0.0002551022,0.0004429237,0.0004551071,0.0001121616,0.00004869201],"category_scores_gemma":[0.0006581701,0.0005035179,0.000115379,0.0003502943,0.00006469727,0.0006432746,0.00004424214,0.0002933585,0.0001515338],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00008525833,"about_ca_system_score_gemma":0.000037529,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000001320461,"about_ca_topic_score_gemma":1.71671e-7,"domain_scores_codex":[0.9977682,0.0001091661,0.0006575508,0.000558199,0.0002927806,0.0006140866],"domain_scores_gemma":[0.9988188,0.0001148846,0.0002054774,0.0002138178,0.000465266,0.0001817681],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00005419539,0.0003368364,0.001086227,0.001337025,0.0002506475,0.00003624826,0.006226004,0.002768036,0.6313299,0.08424545,0.02633399,0.2459955],"study_design_scores_gemma":[0.0008185328,0.0001536699,0.001244666,0.0002118624,0.00004705815,0.00003990903,0.0001658829,0.857233,0.1334475,0.001254344,0.004583997,0.0007996366],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.004865196,0.000116575,0.9669573,0.00002956732,0.0002266903,0.001056279,0.00001364828,0.004125399,0.02260932],"genre_scores_gemma":[0.6970292,0.00006620241,0.302134,0.0000681003,0.00009829121,0.00009929937,0.00001108463,0.0001527475,0.0003411185],"genre_candidate":"methods","genre_consensus":null,"teacher_disagreement_score":0.8544649,"threshold_uncertainty_score":0.9997417,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W4229764280","doi":"10.1109/eurdac.1992.246233","title":"Efficient constrained encoding for VLSI sequential logic synthesis","year":2003,"lang":"en","type":"article","venue":"Proceedings EURO-DAC '92: European Design Automation Conference","topic":"VLSI and FPGA Design Techniques","field":"Engineering","cited_by":1,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"University of Waterloo","funders":"","keywords":"Encoding (memory); Heuristic; Computer science; Asynchronous communication; Sequential logic; Variety (cybernetics); Algorithm; State (computer science); Theoretical computer science; Parallel computing; Arithmetic; Logic gate; Artificial intelligence; Mathematics","authors":[{"name":"C.-J. Shi","is_ca":true},{"name":"J.A. Brzozowski","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.05243470574356956,"gpt":0.2420089333845209,"spread":0.1895742276409513,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001613084,0.0004830196,0.0003977186,0.0003200073,0.0002611978,0.0004186027,0.0004448027,0.0001206232,0.000190495],"category_scores_gemma":[0.001131376,0.000499812,0.0001416377,0.0003899197,0.0001234,0.0002462581,0.00004137014,0.0002526892,0.0001577399],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001233939,"about_ca_system_score_gemma":0.00007377194,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":6.731334e-7,"about_ca_topic_score_gemma":7.862756e-8,"domain_scores_codex":[0.9976103,0.0001519801,0.0006905721,0.0005716435,0.0003455477,0.0006299796],"domain_scores_gemma":[0.9986477,0.0002881817,0.0002193617,0.0002038033,0.0004489029,0.0001920629],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"bench_or_experimental","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003657662,0.0001105655,0.00008138765,0.0005913998,0.0001049568,0.00002564911,0.00125629,0.005774688,0.8844253,0.08482236,0.006158582,0.01661221],"study_design_scores_gemma":[0.0007462182,0.0002273334,0.0001937079,0.0003839615,0.0001338072,0.000113007,0.0002543913,0.5136487,0.4769101,0.002327241,0.003911695,0.001149817],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.01141618,0.00007436498,0.878756,0.00006083336,0.0002703803,0.001208788,0.00002079442,0.003544891,0.1046477],"genre_scores_gemma":[0.9393107,0.0000420941,0.05999976,0.00008691075,0.00009962438,0.000173097,0.000007168368,0.0001317064,0.0001489059],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.9278945,"threshold_uncertainty_score":0.9997454,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}