{"meta":{"page":1,"per_page":50,"max_per_page":100,"total":3,"total_is_capped":false,"direct_labels_cover":0,"predictions_cover":3,"direct_label_status":"direct model label, unvalidated","prediction_status":"machine_predicted_unvalidated (Codex and Gemma teacher distillation)","score_status":"score_only:v0-immature-baseline (scores rank; they never assert a category)","snapshot":{"source":"OpenAlex, pinned release, all 482 partitions","release":"2026-06-24","frame_built":"2026-07-12","author_layer_release":"2026-06-26"},"query_hash":"85c6ca2a43f1","filters":{"venue":"SYNCHROINFO JOURNAL"}},"results":[{"id":"W4317415683","doi":"10.36724/2664-066x-2021-7-4-7-11","title":"A 36 MW, 13 B, 2.1 MS/S MULTI-BIT DS ADC IN 0.18 M DIGITAL CMOS PROCESS USING AN EFFICIENT TOP-DOWN DESIGN METHODOLOGY","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":true,"ca_venue":false,"about_ca":false},"ca_institutions":"McGill University","funders":"CMC Microsystems","keywords":"CMOS; Block (permutation group theory); Capacitor; Dynamic range; Switched capacitor; Electronic engineering; Nyquist–Shannon sampling theorem; Computer science; 12-bit; Decimation; Integrated circuit design; Nyquist rate; Electrical engineering; Engineering; Telecommunications; Mathematics; Sampling (signal processing); Bandwidth (computing); Voltage","authors":[{"name":"Mona Safi-Harb","is_ca":true},{"name":"Gordon W. Roberts","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.1007972913452806,"gpt":0.315108126470356,"spread":0.2143108351250754,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.001184785,0.0003668374,0.0005517432,0.0003384551,0.0002042309,0.0003124971,0.000336359,0.0002330105,0.000424516],"category_scores_gemma":[0.0002991183,0.0003635795,0.0001746117,0.0005931258,0.00008204863,0.0004348075,0.00003165476,0.0008513011,0.00009549598],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.000310863,"about_ca_system_score_gemma":0.0005101963,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0000206007,"about_ca_topic_score_gemma":0.00002791162,"domain_scores_codex":[0.9973816,0.0003681016,0.0007242091,0.000359384,0.0003768583,0.000789832],"domain_scores_gemma":[0.9987258,0.0002649419,0.00013595,0.000282058,0.0002255985,0.000365634],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00004866419,0.0001889073,0.0008417704,0.000101805,0.0001178999,0.00146056,0.002365293,0.9683048,0.0184758,0.0001496712,0.0001765502,0.00776832],"study_design_scores_gemma":[0.003745653,0.0003873528,0.001585917,0.0005417367,0.0001682539,0.01194908,0.004507234,0.94355,0.0283539,0.003068399,0.0006776107,0.001464871],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2122637,0.001122315,0.7845176,0.000004480019,0.0004211362,0.0001719909,0.00001214779,0.0001081138,0.001378577],"genre_scores_gemma":[0.9882814,0.00005161874,0.01110033,0.00005850883,0.0003376878,0.000008376101,0.000009814567,0.00007749496,0.00007477104],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.7760177,"threshold_uncertainty_score":0.9998816,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3206782637","doi":"10.36724/2664-066x-2021-7-3-31-35","title":"A 19 MW, 12.5 B, 2.1 MS/S SINGLE-BIT DS ADC IN 0.18 MM DIGITAL CMOS PROCESS","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"Analog and Mixed-Signal Circuit Design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"McGill University","funders":"","keywords":"Oversampling; CMOS; Delta-sigma modulation; Computer science; Bandwidth (computing); Electronic engineering; Effective number of bits; Switched capacitor; Electrical engineering; Low-power electronics; Dissipation; Dynamic range; Voltage; Power (physics); Capacitor; Engineering; Physics; Telecommunications; Power consumption","authors":[{"name":"Mona Safi-Harb","is_ca":true},{"name":"Gordon W. Roberts","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01805950254111605,"gpt":0.2218679147422079,"spread":0.2038084122010919,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":["metaepi_narrow"],"consensus_categories":[],"category_scores_codex":[0.000259577,0.000287726,0.0003676242,0.0002188577,0.0001216673,0.0004090111,0.000268426,0.0001551288,0.0007838322],"category_scores_gemma":[0.0001736317,0.000290178,0.0001754403,0.0004291303,0.00005406225,0.0005741013,0.00002878072,0.0007488237,0.000187792],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002899081,"about_ca_system_score_gemma":0.0002981097,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000005205664,"about_ca_topic_score_gemma":0.00002255753,"domain_scores_codex":[0.9981221,0.00004134331,0.000568688,0.00023347,0.0004183595,0.000616041],"domain_scores_gemma":[0.9991466,0.0000818169,0.00008848162,0.000213322,0.0001316002,0.0003381914],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"not_applicable","study_design_scores_codex":[0.0003397503,0.001864094,0.06203214,0.003044804,0.002069907,0.03916227,0.01872518,0.2067604,0.1100364,0.006926203,0.1419863,0.4070526],"study_design_scores_gemma":[0.03530337,0.00363219,0.02628344,0.01030712,0.001104292,0.1337572,0.02600983,0.08043642,0.1418415,0.1684799,0.3566351,0.01620962],"study_design_candidate":"not_applicable","study_design_consensus":null,"genre_codex":"empirical","genre_gemma":"empirical","genre_scores_codex":[0.4661869,0.009235521,0.2208544,0.000134546,0.001905999,0.0004338593,0.00007161789,0.0006532504,0.3005239],"genre_scores_gemma":[0.9981368,0.0001068836,0.00007406644,0.000109628,0.00061763,0.0000073297,0.00001598354,0.0000627239,0.0008689158],"genre_candidate":"empirical","genre_consensus":"empirical","teacher_disagreement_score":0.53195,"threshold_uncertainty_score":0.9999551,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null},{"id":"W3207568191","doi":"10.36724/2664-066x-2021-7-3-27-30","title":"TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS","year":2021,"lang":"en","type":"article","venue":"SYNCHROINFO JOURNAL","topic":"VLSI and Analog Circuit Testing","field":"Computer Science","cited_by":0,"is_retracted":false,"has_abstract":true,"routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false},"ca_institutions":"McGill University","funders":"","keywords":"Electronic engineering; Mixed-signal integrated circuit; Computer science; Electronics; Automatic test equipment; Integrated circuit; Engineering; Electrical engineering","authors":[{"name":"Chris Taillefer","is_ca":true},{"name":"Gordon W. Roberts","is_ca":true}],"retraction":null,"screen_n_in":null,"score":{"opus":0.01598184289442005,"gpt":0.229053941566265,"spread":0.213072098671845,"validation_status":"score_only:v0-immature-baseline"},"prediction":{"model_version":"codex-gemma-dda1882f352a","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0003951925,0.0001983723,0.0002550787,0.0001176656,0.0003905479,0.0008085012,0.0008450503,0.00006821925,0.0004208412],"category_scores_gemma":[0.0004870979,0.0001843175,0.0002068169,0.0004718692,0.00008230588,0.0007603051,0.0002246667,0.0004992315,0.0006151777],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0001042267,"about_ca_system_score_gemma":0.0005086962,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.000002180737,"about_ca_topic_score_gemma":0.000002884275,"domain_scores_codex":[0.9981798,0.00005850489,0.0004416211,0.0003227707,0.0004699813,0.0005273424],"domain_scores_gemma":[0.9984167,0.0003476675,0.0002101223,0.0003790756,0.0003182632,0.0003281845],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.000001568842,0.000376069,0.01357282,0.00005732409,0.000191963,0.01039132,0.001909277,0.0005888417,0.07276575,0.003518446,0.05467713,0.8419495],"study_design_scores_gemma":[0.007732359,0.001798037,0.02887304,0.003105489,0.0002129564,0.1873888,0.002594148,0.6106495,0.05987072,0.03622936,0.05669646,0.004849066],"study_design_candidate":"design_other","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.1556931,0.001358835,0.756351,0.003178809,0.002456099,0.0001742212,0.00002000798,0.0007670697,0.08000089],"genre_scores_gemma":[0.9915674,0.00002355403,0.004687273,0.0007055109,0.0006321097,0.000001572407,0.000005212433,0.0000199511,0.002357366],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.8371004,"threshold_uncertainty_score":0.7907071,"prediction_status":"machine_predicted_unvalidated"},"labels":[],"label_agreement":null}]}