{"id":"W2119092821","doi":"10.1145/2366231.2337161","title":"RAIDR","year":2012,"lang":"en","type":"article","venue":"ACM SIGARCH Computer Architecture News","topic":"Advanced Data Storage Technologies","field":"Computer Science","cited_by":449,"is_retracted":false,"has_abstract":true,"ca_institutions":"","funders":"Army Research Office; Natural Sciences and Engineering Research Council of Canada; Samsung; National Science Foundation","keywords":"Dram; Memory controller; Computer science; Row; Dynamic random-access memory; CAS latency; Embedded system; Universal memory; Static random-access memory; Computer hardware; Overhead (engineering); Memory refresh; Controller (irrigation); Data retention; Semiconductor memory; Operating system; Computer memory","routes":{"ca_aff":false,"ca_fund":true,"ca_venue":false,"about_ca":false,"invisible_to_affiliation_only":true},"retraction":null,"screen":null,"machine_scores":{"provisional":true,"baseline":true,"maturity_gate_passed":false,"score_opus":0.01983698611201415,"score_gpt":0.2647596643035801,"score_spread":0.244922678191566,"validation_status":"score_only:v0-immature-baseline","note":"Baseline scores from an immature model (maturity gate not passed). Scores rank; they never assert a category."}}