{"id":"W2154900953","doi":"10.1109/fpl.2005.1515739","title":"A verilog RTL synthesis tool for heterogeneous FPGAs","year":2005,"lang":"en","type":"article","venue":"","topic":"Embedded Systems Design Techniques","field":"Computer Science","cited_by":43,"is_retracted":false,"has_abstract":true,"ca_institutions":"University of Toronto","funders":"","keywords":"Field-programmable gate array; Verilog; Computer science; Computer architecture; CAD; Routing (electronic design automation); Domain (mathematical analysis); Embedded system; Logic synthesis; Reconfigurable computing; Place and route; High-level synthesis; Architecture; Logic gate; Algorithm; Engineering; Engineering drawing","routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false,"invisible_to_affiliation_only":false},"retraction":null,"screen":null,"direct_labels":[],"prediction":{"model_version":"metacan-v3-hybrid-931329e0061c","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.001023094,0.00087325,0.000431048,0.0008996534,0.0004213194,0.0008684298,0.001240849,0.0005289322,0.01762368],"category_scores_gemma":[0.003049094,0.0006934264,0.0005739329,0.0004256926,0.0003807287,0.0008882602,0.0004971898,0.0009820482,0.003988622],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0007009412,"about_ca_system_score_gemma":0.001300787,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.001603636,"about_ca_topic_score_gemma":0.002394505,"domain_scores_codex":[0.9992551,0.0001627448,0.00008595258,0.00009445718,0.0003308212,0.00007090875],"domain_scores_gemma":[0.9988079,0.0006407826,0.0001023281,0.0001664334,0.000259868,0.00002267146],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"design_other","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.0005524875,0.0002052503,0.001368028,0.001494625,0.00006551657,0.0009672657,0.000377459,0.2461021,0.1064522,0.04894201,0.05171725,0.5417559],"study_design_scores_gemma":[0.0004031928,0.0004093285,0.0006165849,0.0002868134,0.00007471052,0.0008424209,0.00006382947,0.7439074,0.09927586,0.02287417,0.1311582,0.00008755001],"study_design_candidate":"simulation_or_modeling","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.004370101,0.0001273551,0.9623057,0.00009176919,0.00006057382,0.0001712822,0.0009916227,0.02474248,0.007139227],"genre_scores_gemma":[0.1426313,0.0004144324,0.8362873,0.0002974485,0.00004922279,0.0008702162,0.003582969,0.005573666,0.01029349],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.01762368,"threshold_uncertainty_score":0.0589571,"prediction_status":"machine_predicted_unvalidated"},"machine_scores":{"provisional":true,"baseline":true,"maturity_gate_passed":false,"score_opus":0.0205025177535854,"score_gpt":0.2614962953013756,"score_spread":0.2409937775477902,"validation_status":"score_only:v0-immature-baseline","note":"Baseline scores from an immature model (maturity gate not passed). Scores rank; they never assert a category."}}