{"id":"W2154990096","doi":"10.1109/tvlsi.2002.1043336","title":"Compatible cell connections for multifamily dynamic logic gates","year":2002,"lang":"en","type":"article","venue":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"ca_institutions":"Carleton University","funders":"","keywords":"Logic gate; Pass transistor logic; Logic family; Computer science; Logic optimization; Dynamic logic (digital electronics); Sequential logic; AND-OR-Invert; Logic synthesis; Set (abstract data type); Digital electronics; Electronic engineering; Electronic circuit; Algorithm; Engineering; Electrical engineering; Transistor; Voltage","routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false,"invisible_to_affiliation_only":false},"retraction":null,"screen":null,"direct_labels":[],"prediction":{"model_version":"metacan-v3-hybrid-931329e0061c","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.00009757861,0.0002399961,0.0001252861,0.0004384506,0.0004653388,0.000566229,0.0005092949,0.0004270273,0.003878676],"category_scores_gemma":[0.0006535533,0.0001298023,0.0001897163,0.0003549981,0.0003752502,0.0009296028,0.000399764,0.0003256437,0.000613987],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.0002668122,"about_ca_system_score_gemma":0.0001532295,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.0001604627,"about_ca_topic_score_gemma":0.00053126,"domain_scores_codex":[0.9998341,0.00001947105,0.00001241728,0.00003276646,0.00008146457,0.0000198387],"domain_scores_gemma":[0.9998363,0.00004908942,0.0000310306,0.0000335483,0.00003569683,0.00001442198],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"theoretical_or_conceptual","study_design_gemma":"bench_or_experimental","study_design_scores_codex":[0.00007189428,0.00003802151,0.000556246,0.0001160042,0.000009845165,0.0003754614,0.0001918322,0.01692839,0.1380444,0.732297,0.001610101,0.1097607],"study_design_scores_gemma":[0.00004825135,0.0003162879,0.000912013,0.00005180812,0.00003517153,0.00151703,0.0001573596,0.168052,0.1264847,0.6129247,0.08945187,0.00004882128],"study_design_candidate":"bench_or_experimental","study_design_consensus":null,"genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.2392224,0.0008032685,0.6974464,0.0003280202,0.0002043879,0.0001782193,0.0002398436,0.0005310202,0.06104639],"genre_scores_gemma":[0.815801,0.0005305479,0.1757386,0.0001292443,0.00004122789,0.0001780848,0.0002001223,0.00006056403,0.007320551],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.003878676,"threshold_uncertainty_score":0.01297551,"prediction_status":"machine_predicted_unvalidated"},"machine_scores":{"provisional":true,"baseline":true,"maturity_gate_passed":false,"score_opus":0.01649407453907798,"score_gpt":0.2170100173016759,"score_spread":0.2005159427625979,"validation_status":"score_only:v0-immature-baseline","note":"Baseline scores from an immature model (maturity gate not passed). Scores rank; they never assert a category."}}