{"id":"W4243911862","doi":"10.32920/ryerson.14645664","title":"On-chip interconnects modeling and timing driven buffer insertion","year":2021,"lang":"en","type":"preprint","venue":"","topic":"Low-power high-performance VLSI design","field":"Engineering","cited_by":0,"is_retracted":false,"has_abstract":true,"ca_institutions":"Toronto Metropolitan University","funders":"","keywords":"Interconnection; Very-large-scale integration; Electronic engineering; RLC circuit; Chip; Computer science; Spice; Electronic circuit; Equivalent circuit; Overhead (engineering); Representation (politics); Topology (electrical circuits); Electrical engineering; Engineering; Voltage; Telecommunications; Capacitor","routes":{"ca_aff":true,"ca_fund":false,"ca_venue":false,"about_ca":false,"invisible_to_affiliation_only":false},"retraction":null,"screen":null,"direct_labels":[],"prediction":{"model_version":"metacan-v3-hybrid-931329e0061c","candidate_categories":[],"consensus_categories":[],"category_scores_codex":[0.0001530378,0.000516841,0.0002876467,0.0003506371,0.0002254408,0.0006602813,0.001116583,0.0007167496,0.002026655],"category_scores_gemma":[0.0004128646,0.0002111376,0.0005079783,0.0003230861,0.0002242852,0.0007652179,0.0003256205,0.0004576264,0.0006232095],"about_ca_system_candidate":false,"about_ca_system_consensus":false,"about_ca_system_score_codex":0.00072666,"about_ca_system_score_gemma":0.0006795142,"about_ca_topic_candidate":false,"about_ca_topic_consensus":false,"about_ca_topic_score_codex":0.003024197,"about_ca_topic_score_gemma":0.002468713,"domain_scores_codex":[0.9998564,0.00003144003,0.000004799346,0.00002704207,0.00005804271,0.0000222749],"domain_scores_gemma":[0.99989,0.00002552903,0.00002410139,0.00002752743,0.00002887922,0.000004073724],"domain_codex":null,"domain_gemma":null,"domain_candidate":null,"domain_consensus":null,"study_design_codex":"simulation_or_modeling","study_design_gemma":"simulation_or_modeling","study_design_scores_codex":[0.00003897418,0.00003740145,0.0003482724,0.0001034745,0.00001555987,0.0001865096,0.00007258284,0.9048308,0.05133769,0.02597123,0.000776085,0.0162813],"study_design_scores_gemma":[0.000002036268,0.00003369027,0.00008902211,0.000006166137,0.000007250963,0.00004050909,0.000007478137,0.9894089,0.006982689,0.001261271,0.002157056,0.000003938977],"study_design_candidate":"simulation_or_modeling","study_design_consensus":"simulation_or_modeling","genre_codex":"methods","genre_gemma":"empirical","genre_scores_codex":[0.08888271,0.0008768245,0.8766086,0.0001902314,0.0001003082,0.00009917022,0.0003040911,0.001670594,0.03126751],"genre_scores_gemma":[0.8895431,0.001410626,0.09039167,0.0000819243,0.00004227487,0.0001301722,0.0003418227,0.0002446277,0.01781378],"genre_candidate":"empirical","genre_consensus":null,"teacher_disagreement_score":0.003024197,"threshold_uncertainty_score":0.00677979,"prediction_status":"machine_predicted_unvalidated"},"machine_scores":{"provisional":true,"baseline":true,"maturity_gate_passed":false,"score_opus":0.0245830528316695,"score_gpt":0.2216295372490922,"score_spread":0.1970464844174227,"validation_status":"score_only:v0-immature-baseline","note":"Baseline scores from an immature model (maturity gate not passed). Scores rank; they never assert a category."}}