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CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture

2021· preprint· en· 0 citations· W3090302053 sur OpenAlex· 10.1109/tcsi.2021.3066967

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Le tri à trois modèles

les 1 000 travaux triés →

Les trois modèles l'ont jugé hors champ.

strate : aff_core · poids de sondage : 5595.24 (l'échantillon est stratifié ; tout taux calculé sans le poids est faux)
Claude Opus 4.8OUT
genre : empirical
porte sur le Canada: non
confiance: high

Hardware architecture for convolutional neural network acceleration.

GPT-5.6 (high)OUT
genre : empirical
porte sur le Canada: non
confiance: high

The paper develops a neural-network hardware accelerator rather than studying research practice.

Grok 4.5OUT
genre : empirical
porte sur le Canada: non
confiance: high

Hardware architecture for CNN acceleration, computer engineering domain work.

Résumé

Convolutional Neural Networks (CNNs) have proven to be extremely accurate for image recognition, even outperforming human recognition capability. When deployed on battery-powered mobile devices, efficient computer architectures are required to enable fast and energy-efficient computation of costly convolution operations. Despite recent advances in hardware accelerator design for CNNs, two major problems have not yet been addressed effectively, particularly when the convolution layers have highly diverse structures: (1) minimizing energy-hungry off-chip DRAM data movements; (2) maximizing the utilization factor of processing resources to perform convolutions. This work thus proposes an energy-efficient architecture equipped with several optimized dataflows to support the structural diversity of modern CNNs. The proposed approach is evaluated on convolutional layers of VGGNet-16 and ResNet-50. Results show that the architecture achieves a Processing Element (PE) utilization factor of 98% for the majority of 3×3 and 1×1 convolutional layers, while limiting latency to 396.9 ms and 92.7 ms when performing convolutional layers of VGGNet-16 and ResNet-50, respectively. In addition, the proposed architecture benefits from the structured sparsity in ResNet-50 to reduce the latency to 42.5 ms when half of the channels are pruned.

Conservé avec la notice de tri, où il sert de preuve aux étiquettes ci-dessus.

La notice

Revue
IEEE Transactions on Circuits and Systems I Regular Papers
Thématique
Advanced Neural Network Applications
Domaine
Computer Science
Établissements canadiens
Polytechnique Montréal
Organismes subventionnaires
Natural Sciences and Engineering Research Council of Canada
Mots-clés
Computer scienceConvolutional neural networkDramConvolution (computer science)ArchitectureLatency (audio)ComputationEfficient energy useComputer architectureComputer engineeringResidual neural networkEmbedded systemParallel computingComputer hardwareArtificial intelligenceAlgorithmArtificial neural networkTelecommunications
Résumé présent dans OpenAlex
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