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Record W2113541291 · doi:10.1109/esscirc.2007.4430359

A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology

2007· article· en· W2113541291 on OpenAlex

Why this work is in the frame

A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.

affAt least one author lists a Canadian institution in the pinned OpenAlex snapshot.

Bibliographic record

VenueProceedings of ESSCIRC · 2007
Typearticle
Languageen
FieldEngineering
TopicAdvancements in PLL and VCO Technologies
Canadian institutionsSTMicroelectronics (Canada)
Fundersnot available
KeywordsSerDesCMOSJitterElectronic engineeringComputer scienceElectrical engineeringEngineering

Abstract

fetched live from OpenAlex

A low-jitter and low-power clocking strategy targeting a high-density multi-channel SerDes application is presented. A cascaded PLL architecture was devised in order to simultaneously meet the jitter generation requirements and distribute multiple clock phases to each transceiver segment. Multiple clock phases are generated and distributed to transceivers by a synchronized oscillator array (SOA), formed by multiple closed-loop ring oscillators (located in each transceiver segment). Each individual delay element is connected in parallel with its counterparts located in other segments of the array. The synchronized oscillator array spans the entire length of the SerDes macro, thus eliminating the need for expensive high-speed clock drivers. It is part of a wide-bandwidth PLL, which tracks a low-jitter clock generated from an on-chip wide-tuning range LC-PLL, locked to a low cost external reference. The long-term jitter measured at the output of a transmitter is approximately 0.33 ps rms. Integrated in STMicroelectronics’ standard LP 65nm CMOS process, the power consumption of the clock circuits in a 4 channel SerDes is 168mW from a 1.2V supply.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Bench or experimental · Consensus signal: Bench or experimental
GenreCandidate signal: Empirical · Consensus signal: Empirical
Teacher disagreement score0.181
Threshold uncertainty score0.726

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.001
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0000.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.014
GPT teacher head0.261
Teacher spread0.247 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it