A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology
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Bibliographic record
Abstract
A low-jitter and low-power clocking strategy targeting a high-density multi-channel SerDes application is presented. A cascaded PLL architecture was devised in order to simultaneously meet the jitter generation requirements and distribute multiple clock phases to each transceiver segment. Multiple clock phases are generated and distributed to transceivers by a synchronized oscillator array (SOA), formed by multiple closed-loop ring oscillators (located in each transceiver segment). Each individual delay element is connected in parallel with its counterparts located in other segments of the array. The synchronized oscillator array spans the entire length of the SerDes macro, thus eliminating the need for expensive high-speed clock drivers. It is part of a wide-bandwidth PLL, which tracks a low-jitter clock generated from an on-chip wide-tuning range LC-PLL, locked to a low cost external reference. The long-term jitter measured at the output of a transmitter is approximately 0.33 ps rms. Integrated in STMicroelectronics’ standard LP 65nm CMOS process, the power consumption of the clock circuits in a 4 channel SerDes is 168mW from a 1.2V supply.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.001 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it