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Record W2147671664 · doi:10.1109/cse.2009.493

Run-Time Component Relocation in Partially-Reconfigurable FPGAs

2009· article· en· W2147671664 on OpenAlex

Why this work is in the frame

A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.

affAt least one author lists a Canadian institution in the pinned OpenAlex snapshot.
fundA Canadian funder is recorded on the work.

Bibliographic record

Venuenot available
Typearticle
Languageen
FieldComputer Science
TopicEmbedded Systems Design Techniques
Canadian institutionsToronto Metropolitan University
FundersNatural Sciences and Engineering Research Council of CanadaCMC Microsystems
KeywordsComputer scienceRelocationControl reconfigurationComponent (thermodynamics)Field-programmable gate arrayEmbedded systemOverhead (engineering)VirtualizationChipStatic timing analysisComputer architectureOperating systemCloud computing

Abstract

fetched live from OpenAlex

The concept of hardware resource virtualization which was initiated in virtual memory organization has recently expanded towards virtualization of computing resources in partially reconfigurable FPGAs. However, this kind of resource virtualization requires mechanisms for flexible allocation/relocation of components associated with data execution processes. The ability for on-chip component relocation will allow cost efficient multi-task/multi-modal operations in FPGAs by run-time architecture-to-task optimization. On-chip component relocation would also allow hardware fault mitigation and even dynamic self-restoration of FPGA systems. Therefore, the goal of the presented research was to investigate the feasibilityof on-chip component relocation in partially reconfigurable FPGAs. In this proof-of-concept research phase we have analyzed structural requirements of target FPGAs as well as design constraints for the components suitable for on-chiprelocation. As a result, the possibility for run-time relocation of components associated with video-processing applications has been proven. Architectural requirements and component design constraints have been determined. It is shown that the hardware overhead required for performing the relocation procedure is negligible compared to the total amount of FPGA resources. In addition, the component relocation time has been measured according to slot size. It is two orders of magnitude less than the reconfiguration time for the entire target FPGA, which allows quite rapid mode switching or circuit restoration.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.001
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Bench or experimental · Consensus signal: none
GenreCandidate signal: Empirical · Consensus signal: none
Teacher disagreement score0.934
Threshold uncertainty score0.580

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0010.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.000
Science and technology studies0.0000.000
Scholarly communication0.0000.001
Open science0.0010.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.015
GPT teacher head0.246
Teacher spread0.231 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Quick stats

Citations4
Published2009
Admission routes2
Has abstractyes

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