Hardware Emulation for Real-Time Power System Simulation
Why this work is in the frame
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Bibliographic record
Abstract
The classical approach used to implement digital real-time power system simulators (DRTPSS) consists in modeling the power system network and devices in software, and using numerical integration techniques and parallel processors to solve the resulting equations. This approach has many advantages, but it is subjected to the processor-memory hardware paradigm and the inter-processor communication overhead. The latter imposes a minimum time step that cannot be much decreased even when using higher performance processors. Typically, the minimum time step reported in the literature is around 20 μs [6]. This paper presents a new approach to design and implement high-performance DRTPSS that consists in modeling the power system network and devices directly in VLSI hardware. The network topology and device models are described in a hardware description language (HDL) and mapped to a programmable device (FPGA) by using automatic synthesis tools. The simulation runs directly in hardware resulting in very short simulation time steps. Indeed, the initial results obtained and presented in this work show that time steps in the order of microseconds are possible.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it