Hardware-assisted fast routing for runtime reconfigurable computing
Why this work is in the frame
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Bibliographic record
Abstract
Reconfigurable devices, such as the Field Programmable Gate Array, offer 10–100× computational density and reduced latency compared to conventional processor solutions. Despite its advantages, however, use of reconfigurable computing remains limited, largely due to the lack of software expressibility and longevity across various generations of devices. SCORE is a stream-based computational model that virtualizes reconfigurable computing resources by segmenting computations into fixed-size “pages” and time-multiplexing the virtual pages on available hardware. Therefore, SCORE applications can scale up or down automatically to operate seamlessly with a wide variety of hardware sizes. To support the SCORE model, we provide details of SCOREμP—a micro-architecture that combines (1) a reconfigurable array for regular fine-grained computation and (2) a sequential processor to run the page scheduler and execute SCORE operators or other user applications that do not run efficiently in spatial implementations. To fully realize the benefits of rapid partial reconfiguration of field-programmable devices, the runtime system often needs to schedule computing tasks dynamically and generate instance-specific configurations, i.e., new graphs which must be routed during program execution. Consequently, route time can be a significant overhead cost, reducing the achievable net benefits of dynamic configuration generation. By adding hardware to accelerate routing, it is possible to (1) compute routes in one one-thousandth of the time required by a traditional software router; and (2) achieve routes that are within five percent of state-of-the-art offline routing algorithms for a sample set of application netlists, and within three percent for the Toronto Place and Route Benchmarks. Strategic use of parallelism can allow total route time to scale substantially less than linearly in graph size. The observed speedups vary from greater than 10× with modest hardware overhead, to greater than 1000× with full hardware assistance.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.001 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.001 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it