Interconnect Solutions for Virtualized Field-Programmable Gate Arrays
Bibliographic record
Abstract
Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA). One would like to virtualize FPGAs to share them between multiple users and to be able to allocate incoming tasks to FPGAs without interrupting their operation. To virtualize FPGAs, their complexities, such as board-specific system-level integration and tricky I/O timing closure problems should be abstracted away from users. To this end FPGA designers have proposed the shell concept which abstracts away the board-specific details from the user and provides an easy-to-use interface to the user application. In this paper, we create several shells using a wide variety of interconnect solutions and rigorously evaluate them in terms of accelerator frequency, usable bandwidth, area-efficiency, latency, wire demand, and FPGA routing congestion. We show that virtualization of four accelerators per chip with traditional bus-based FPGA interconnect costs an average frequency drop of 24%, increases the wire demand of the shell to 2.78X, and creates significant routing congestion. We also show that while FPGA-optimized soft network on chip interconnect solutions can mitigate the reduction in accelerator frequency, they exacerbate the wire demand and routing congestion problems and offer a lower usable bandwidth. Finally, we demonstrate that hard networks on chip are a superior interconnect solution for virtualized FPGAs in all of the aforementioned evaluation criteria making them well-suited to datacenteroptimized FPGAs.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.001 | 0.001 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.002 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".