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Record W3080620120 · doi:10.1109/cjece.2019.2962147

Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

2020· article· en· W3080620120 on OpenAlex

Why this work is in the frame

A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.

venuePublished in a venue whose home country is Canada.
no affNo Canadian affiliation: this work is invisible to an affiliation-only frame.
No Canadian affiliation. An affiliation-only frame, the usual design, would never have seen this work. It is one of the works that make the case for inverting the frame.

Bibliographic record

VenueCanadian Journal of Electrical and Computer Engineering · 2020
Typearticle
Languageen
FieldEngineering
TopicVLSI and FPGA Design Techniques
Canadian institutionsnot available
Fundersnot available
KeywordsFloorplanControl reconfigurationField-programmable gate arraySimulated annealingGate arrayComputer scienceBenchmark (surveying)Genetic algorithmEmbedded systemParallel computingAlgorithmComputer architectureComputer engineering

Abstract

fetched live from OpenAlex

Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Simulation or modeling · Consensus signal: Simulation or modeling
GenreCandidate signal: Empirical · Consensus signal: none
Teacher disagreement score0.761
Threshold uncertainty score0.388

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.000
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0000.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.004
GPT teacher head0.161
Teacher spread0.157 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it