Saras eVR STile - Demonstration of Next Generation Integrated Passives for Next Generation AI & HPC Power Delivery Network Designs
Why this work is in the frame
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Bibliographic record
Abstract
High-performance microprocessors and accelerators, integral to data centers, require power delivery networks capable of managing higher currents and power densities while operating at lower voltages. The surge in generative AI applications is reshaping the landscape of semiconductor hardware, necessitating advanced power delivery solutions to meet escalating demands for efficiency and performance. As AI workloads intensify, traditional power delivery methods struggle to provide the necessary energy without compromising spatial constraints on circuit boards. This paper addresses the critical challenges posed by embedded passive components, specifically capacitors and inductors, while demonstrating an embedded voltage regulation (eVR) STile™. We introduce an innovative approach that leverages embedded passive technology to enhance power efficiency. This paper will demonstrate the integration of capacitors and inductors directly into the package substrate to enable for the first time and subsequently vertical power delivery directly into the package substrate. This demonstration of highly integrated passive components serves to optimize the power delivery network through reduction in the power path length as well as leveraging high performance passive components. By addressing these power delivery challenges, we pave the way for the next generation of semiconductor hardware tailored to the demands of next generation AI applications. Ensuring optimal power signal integrity is vital for maintaining stable voltage delivery across a wide frequency range. A standard design methodology focuses on minimizing the impedance seen by the load’s input nodes, thereby reducing voltage ripple and droop during transient events. STile technology improves performance by embedding high capacitance density capacitors close to the load and combining them with complimentary inductors to, significantly reduce parasitics and optimize space for both VPD and embedded voltage regulation (eVR) solutions. This paper will demonstrate the ability to integrate these passive components specifically designed to support integrated voltage regulation inside of the package. This paper will show configurations of passive components that support a variety of different domains for traditional high performance computing die. This paper will also demonstrate the superior performance capable of being achieved as compared to traditional power delivery network’s. These traditional power delivery networks perform the voltage conversion from 48V to POL (Point of Load) voltages in discrete and bulky modules on the periphery of the printed circuit board. These modules combine the use of inductors, capacitors and actives however, are significantly far away from the load that efficiency of the network becomes a problem. To minimize I²R losses, efficient power delivery demands higher voltages and low current levels at the package substrate level. While conventional power regulator topologies typically utilize inductors to achieve high conversion efficiencies, integrating inductors onto the die can complicate design and elevate costs. The STile technology provides a groundbreaking solution by enabling the co-location of inductors and capacitors within a customizable three-terminal LC passive module (patent pending) embedded in the core substrate. This integration allows for precise alignment with processor power domains, significantly reducing the need for lateral metal routing. Additionally, the flexible layout of the LC passive modules supports multiple power domains, facilitating interleaved multiphase outputs and innovative configurations such as sharing output capacitors among several inductors. By addressing these design challenges, eVR STile technology significantly enhances power delivery efficiency while meeting the stringent demands of next-generation semiconductor applications. This paper emphasizes the development of advanced, highly integrated capacitor and inductor solutions that deliver superior performance for next-generation power delivery systems. By leveraging STile technology, we illustrate how embedding capacitors and inductors within the substrate not only enhances power signal integrity and minimizes parasitics but also optimizes space for embedded voltage regulation (eVR). This innovative platform enables the creation of custom eVR designs tailored to specific application requirements, significantly improving efficiency in high-performance computing environments. Through our findings, we highlight the transformative potential of these embedded passive components in addressing the power delivery challenges faced by next generation artificial intelligence chips.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.001 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it