Formal Methods in Automated Design Debugging

The relentless growth in size and complexity of semiconductor devices over the last decades continues to present new challenges to the electronic design community. Today, functional debugging is a bottleneck that jeopardizes the future growth of the industry as it can account for up to 30% of the overall design effort. To alleviate the manual debugging burden for industrial problems, scalable, practical and robust automated debugging solutions are required.\nThis dissertation presents novel techniques and methodologies to bridge the gap between\ncurrent capabilities of automated debuggers and the strict industry requirements. The contributions proposed leverage powerful advancements made in the formal method community, such as model checking and reasoning engines, to significantly ease the debugging effort.\nThe first contribution, abstraction and refinement, is a systematic methodology that reduces the complexity of debugging problems by abstracting irrelevant sections of the circuits under analysis. Powerful abstraction techniques are developed for netlists as well as hierarchical and\nmodular designs. Experiments demonstrate that an abstraction and refinement methodology\nrequires up to 200 times less run-time and 27 times less memory than a state-of-the-art debugger.\nThe second contribution, Bounded Model Debugging (BMD), is a debugging methodology\nbased on the observation that erroneous behaviour is more likely caused by errors excited temporally close to observation points. BMD systematically generates a series of consecutively larger yet more complete debugging problems to be solved. Experiments show the effectiveness of BMD as 93% of the large problems are solved with BMD versus 34% without BMD.\nA third contribution is an automated debugging formulation based on maximum satisfiability. The formulation is used to build a powerful two step, coarse and fine grained debugging framework providing up to 980 times performance improvements.\nThe final contribution of this thesis is a trace reduction technique that uses reachability analysis to identify the observed failure with fewer simulation events. Experiments demonstrate that many redundant state transitions can be removed resulting in traces with up to 100 times\nfewer events than the original.

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