In Situ Tuning of Switching Window in a Gate‐Controlled Bilayer Graphene‐Electrode Resistive Memory Device

A resistive random access memory (RRAM) device with a tunable switching window is demonstrated for the first time. The SET voltage can be continuously tuned from 0.27 to 4.5 V by electrical gating from −10 to +35 V. The gate-controlled bilayer graphene-electrode RRAM can function as 1D1R and potentially increase the RRAM density. Resistive random access memory (RRAM) is a well-known two-terminal nonvolatile memory.1-5 RRAM shows great promise as the next mainstream memory technology.6, 7 The ability to be fabricated as small as 5 nm,8, 9 having a simple structure,10 and demonstrated potential for 3D stacking11 make it attractive. For typical bipolar metal-oxide RRAM, the high resistance state (HRS) can be switched to the low resistance state (LRS) at a given SET voltage. This switching process involves the formation of conducting filaments (CFs) by oxygen vacancies induced by the applied electric field.12, 13 The LRS can also revert back to the HRS when the applied (negative) voltage reaches the RESET voltage. The reset process involves breaking of the CF as the oxygen ions migrate back and recombine with the oxygen vacancies.14 The SET window depends on the gap distance, the CF configuration (size), and the density of defects in the gap region. As a result, the SET window is fixed for traditional RRAM.15, 16 It is important to be able to tune the SET voltage to a reasonable value to match the system voltage. The SET voltage should not be too small. If the SET voltage is too small, it is highly possible that it will be SET accidentally by thermal fluctuation and therefore the retention time will be short. Moreover, changing the SET voltage to a higher value can protect the unselected cells in an array from being written. Therefore, only the selected cells with a lower SET voltage can be written and the gate can function as a selector and there is no half-select effect. A precise and broad switching window that can be electrically tuned allows a plethora of applications and therefore is highly desired for modern RRAMs. However, to date, in situ control of SET window in an RRAM device has never been realized. In recent years, the use of graphene as an electrode material has received a lot of attention in memory device applications. In 2010, Liu et al.17 reported bulk heterojunction polymer memory devices using reduced graphene oxide as electrodes. The memory device exhibited a high ON/OFF ratio (104–105) and a low switching threshold voltage (0.5–1.2 V), which were dependent on the sheet resistance of the rGO electrode. In 2011, Ji et al.18 used multilayer graphene electrodes to make flexible organic memory devices. Tian et al.19 and Qian et al.20 demonstrated that single-layer and multilayer graphene can reduce the power consumption of the memory due to the high resistance of graphene–oxide interface. In 2014, Tian et al.21 reported a laser-scribed graphene-HfOx memory device with low-cost and flexible feature. Although, the use of graphene in the RRAM device structure is currently the focus of intense study,22-24 the device structures reported previously were still two-terminal. Graphene is a tunable platform with a Fermi-level that can be shifted by electrical gating.25 In particular, for bilayer graphene (BLG), a vertical electrical field can induce a bandgap.26, 27 Here, we report the first gate-controlled graphene-electrode RRAM (GC-GRRAM) with a tunable SET window. The key to the advance presented here is to use BLG as the back-gate and induce a bandgap in it. This bandgap allows the electrical field (from the Si substrate) to penetrate into the resistive switching material. This enables control over the amount of oxygen ions and therefore provides the ability to tune the RRAM switching behavior. Figure 1a shows the schematic of the GC-GRRAM. The single-crystal BLG layer is first grown by chemical vapor deposition (CVD) with AB stacking orientation and without a rotation angle.28 In addition, single-crystal single-layer graphene (SLG) and trilayer graphene (TLG) are also synthesized (see Supporting Information, Figure S1 and S2) and employed for device fabrication as control samples. As shown in Figure 1b, three electron-beam patterning steps are used to define the graphene stripe, Al electrode and Au electrode, respectively. A unique aspect of this research is that no resistive switching oxide material deposition step is performed—the AlOx is formed by directly depositing Al on graphene followed by native oxidation. The 5 nm (Figure 1c,d) thick native oxide between Al and graphene serves as the resistive switching material. Figure 1e,f shows the surface morphology of the BLG and Al. The rough surface of the Al electrode indicates oxidization. In order to demonstrate the concept of GC-GRRAM, using BLG with bandgap opening29-31 is critical to let the gate-applied electrical field pass through.25 Figure 2a shows a transistor structure where the BLG is used. In addition, this structure employs both top and bottom gates. It is observed that the ON/OFF ratio can be tuned by the back gate. Using a back gate voltage of Vbg = −40 V, a larger ON/OFF ratio can be obtained (Figure 2b). This is direct evidence of bandgap opening in BLG, which is in agreement with the literature.32 The peaks in the resistance curves can be used to identify the charge neutral points (CNPs) as charge neutrality results in a maximum resistance. The deduced CNPs, in terms of the applied voltages (Vtg,Vbg), are plotted in Figure 2c. If there is no bandgap in the graphene, the Id–Vd curves should be linear (metal–metal contact). This is always observed in graphene. If there is a bandgap in graphene, the Id–Vd curves should be nonlinear (metal–semiconductor junction). Current saturation is observed in Figure 2d, which shows a typical rectifying behavior of a metal–semiconductor junction and indicates an appreciable bandgap opening in graphene at this bias condition. The back gate voltage combined with SiO2 only provides an electric field. The gate leakage from the SiO2 is less than 0.25 nA (Figure S3, Supporting Information) under Vbg = −40 V or 40 V. Figure 3a shows the device structure of the GC-GRRAM. As compared to other conventional RRAM devices, an additional gate is added underneath the BLG. This gate can be used to apply an electrical field through the BLG and change the oxygen ions density in the AlOx. The electric field from the gate serves two functions: changing the energy barrier for oxygen vacancy formation (and therefore makes it easier or harder for oxygen ions to be released from the oxide) and driving the oxygen ions to the top or the bottom electrode. Under zero applied gate voltage (Figure 3b), the AlOx shows switching behavior like a conventional RRAM. The resistance of LRS is not changed with the device area (Figure S4, Supporting Information) because of the localization of the CF. Moreover, the SET voltage decreases with temperature (Figure S5, Supporting Information), which indicates that the filament should be formed from oxygen vacancies. A forming step is required and the forming voltage is 3.7 V (Figure S6, Supporting Information) which is larger than ≈2.0 V SET voltage. The compliance current is set to be 0.1 μA to ensure enough switching cycles. When varying the compliance current, the RESET current increases with the compliance current and the LRS decreases with the compliance current (Figure S7, Supporting Information), which indicates that the LRS resistance can be modulated by the SET compliance current by controlling the filament size. Surprisingly, when a −35 V gate voltage is applied (Figure 3c), there is no SET window (Figure S8, Supporting Information); however, the RESET process works well. This may indicate a pre-SET process, where the HRS–LRS transition happens before the forward sweep, resulting in no observable SET window. More interestingly, when a +35 V gate voltage is applied (Figure 3d), a larger window with a larger SET voltage is obtained. The SET voltage and memory window can be tuned by the gate voltage (Figure 3e,f). The SET voltage under zero gate voltage is ≈2.0 V. When the gate voltage is 35 V, the SET voltage increases to ≈4.5 V. When the gate voltage is −10 V, the SET voltage decreases to ≈0.27 V (Figure S11, Supporting Information). When the gate voltage is lower than −10 V, there is no SET window, but the RESET window remains. Our control samples based on SLG and TLG do not show obvious difference on switching performance by changing the gate voltage (Figure 4 and Figure S12 and S13, Supporting Information). This demonstrates that using BLG with an induced bandgap is necessary for realizing a gate tunable RRAM. The low density of states in the SLG could also cause incomplete screening of the electric field.33 However, the low density of states (n ≈ 1012 cm−2) could only appear near the Dirac point. Weak gate tunability based on SLG was observed. The SET voltage could only be tuned within a limited range of 1.7–2.1 V (Figure 4b). Because of the nature of zero bandgap of SLG, the screening effect from such semimetal material is still very strong (Figure S20, Supporting Information). Meanwhile, due to the bandgap opening in BLG (Figure 4d), the screening effect for such semiconductor material is much weaker. As a result, the tunability for BLG is obvious (Figure 4e). We have also performed simulation for BLG-based RRAM, which is shown in Figure S17 (Supporting Information). It is obvious that the electrical field can pass through the BLG and affect the AlOx. For TLG, there is an overlap between the conduction band and the valence band (Figure 4g), which corresponds to a high density of states.34 The TLG screens the electrical field from the bottom gate. As a result, the electrical field cannot penetrate into the AlOx and there is no gate tunability. In addition, the device to device variation is small and the results are repeatable (Figure 4c,f,i). The ability to tune the HRS/LRS ratio by gate voltage (Figure 3b–d) can be explained by considering the superposition of electric fields. We hypothesize that this phenomenon should be attributed to the change in the amount of effective oxygen ions. Under a negative gate voltage, the oxygen vacancies would be attracted, resulting in the decrease of HRS (Table S2, Supporting Information) and the HRS/LRS ratio. Conversely, under a positive gate voltage, some oxygen ions would be influenced by the electric field, leading to the increase of the HRS and the HRS/LRS ratio. The voltage distribution for the AlOx in HRS is simulated. In the simulation the top voltage is fixed to −0.1 V to ensure the AlOx is in HRS. Under a gate voltage of −35 V, the simulation (Figure 5e) suggests the formation of a −2 V potential on the edge of the BLG. This means that even without the top electrode voltage, the device could be pre-SET by the gate voltage and the filament will most probably form at the edge of the BLG due to the largest potential difference. This also indicates that the electrical field could pass through the BLG and affect the AlOx. Since the BLG has resistance, there is a voltage drop along the BLG. The potential in the center of BLG decreases to −1 V (Figure S17, Supporting Information). Contrarily, under a gate voltage of +35 V, a 2 V and a 1 V potential is formed on the edge and the center of the BLG respectively (Vg = 35 V), which originates from a higher SET voltage. The filament will most probably form at the center of BLG. If Vg = 0 V, the filaments could be formed at random locations. The voltage distribution for the AlOx in LRS is also simulated (Figure S18, Supporting Information). Figure 5f shows the schematic SET window under different gate voltages. When the Vg is at −35 V, there is no SET window, which is in agreement with Figure 3c. The physical picture for the pre-SET process is shown in Figure S19 (Supporting Information). In a conventional RRAM array, a 1D1R structure can be used to read or write the cell. The diode functions as the selector. For 1D1R, suppressing the leakage current in 1D1R crossbar arrays has been a main challenge for high density RRAM development.36 Si-based diodes with high ON/OFF ratio and high current density typically require a high-temperature-doped poly-Si process37 and therefore is not very well suited for RRAM with many 3D layers. Our gate-controlled RRAM can be fabricated at a low temperature and the OFF current should be very low since the higher SET voltage maintains the LRS of the device, which could enable high density 3D stacking. Moreover, our gate-controlled RRAM is more compact than a 1D1R RRAM. The third terminal essentially serves as a selector. In summary, in situ tuning of switching window in a gate-controlled RRAM is demonstrated for the first time. Due to the unique bandgap opening property of BLG, the gate electrical field can affect the oxygen ions density in AlOx. The SET voltage and HRS/LRS ratio can be controlled by gating the AlOx between the “oxygen ions accumulated state” and the “oxygen ions depleted state.” Under a −35 V gate voltage, there is a preformed filament under an ultralow voltage with an HRS/LRS ratio of 103. Under a +35 V gate voltage, the SET voltage is 4.1 V with an HRS/LRS ratio of 105. The GC-GRRAM presented in this work can yield an adequate SET window suitable for practical applications. Graphene Growth and Transfer: Large hexagonal single-crystal few-layer graphene grains were grown by atmospheric pressure CVD of Ar-diluted methane (80 ppm) on 10 μm thick polycrystalline Cu foils. Prior to growth, the Cu foils were cleaned using acetone and isopropyl alcohol (IPA), followed by etching in acetic acid for 30 min to remove surface oxides. The Cu foils were then mounted in the CVD chamber and the furnace was heated to 1050 °C over 30 min, with constant flows of 300 sccm Ar and 15 sccm H2. After reaching 1050 °C, the Cu foils were annealed for 150 min without changing the gas flow. For graphene growth, 150 sccm methane mixed with the flows of 150 sccm Ar and of 15 sccm H2 was fed into the reaction chamber for 60 min to form SLG, BLG, and TLG. Following the growth, the Cu foils were moved to the cooling zone under the protection of Ar and H2. For the transfer process, the graphene sheets were first coated with a thin layer of poly(methyl methacrylate) (PMMA), followed by etching in HCl aqueous solution to remove the Cu. Then, the PMMA film, along with the attached graphene, was transferred onto a silicon substrate. Finally, the PMMA was removed using acetone and IPA. Device Fabrication: GC-GRRAM was made with e-beam lithography (EBL) and standard lift-off processes. First, the device region was isolated using O2 plasma. A 60 nm thick layer of Al was deposited by thermal evaporation and the substrate was encapsulated in a sealed chamber filled with high purity oxygen (>99.999%) at a pressure of 2 kg cm−2. External source/drain electrodes were made of Cr/Au (0.5/60 nm). For each EBL step, PMMA was spin-coated on the graphene film, followed by baking at 130 °C for 30 min. At this stage, the AlOx was not formed yet. The exposed PMMA was developed with methyl isobutyl ketone and IPA in a ratio of 3:8. The EBL was carried out using a scanning electron microscope (JSM-840A) equipped with an e-beam writer (Raith Elphy Quantum). Finally, after 24 h exposure to pure oxygen at room temperature, the Al electrodes were surrounded with a continuous ultrathin AlOx, which acted as the dielectric. H.T., H.Z., X.-F.W., and Q.-Y.X. contributed equally to this work. This work was supported by the National Natural Science Foundation of China (Grant No. 61434001, and 61574083), the National Key Project of Science and Technology (Grant No. 2011ZX02403-002) and 973 Program (Grant No. 2015CB352100). H.T. is thankful for receiving support from the Ministry of Education Scholarship of China. M.A.M. is thankful for receiving support from the postdoctoral fellowship (PDF) program of the Natural Sciences and Engineering Research Council of Canada (NSERC) and from the China Postdoctoral Science Foundation (CPSF). H.-Y.C. was supported in part by the Stanford School of Engineering China Research Exchange Program and the Intel Ph.D. Fellowship. H.-Y.C. and H.-S.P.W. were supported in part by the member companies of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI) industrial affiliate program. As a service to our authors and readers, this journal provides supporting information supplied by the authors. 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