Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs

Despite advances in register-transfer level (RTL) synthesis tools, the quality of synthesized netlists still relies on the RTL micro-architecture. This often causes timing violations to be addressed in the RTL, resulting in time-consuming modify-synthesize-analyze cycles. Recent approaches use machine learning (ML) to estimate timing metrics from an RTL. However, they do not target relevant metrics such as block-based arrival times (ATs) and slacks, essential for micro-architecture search. This paper introduces a novel approach called Fake Timer, which back-annotates realistic timing metrics from flattened synthesis to RTL blocks. Fake Timer inputs an RTL intermediate representation and propagates ML-predicted pin-to-pin delays to compute block-based ATs. These computed ATs do not consider cross-boundary optimizations possible during flattened synthesis. Thus, predicted delays are corrected and used to recompute realistic ATs, required ATs, and slacks. Experiments show that computed ATs at the design’s endpoints achieve a coefficient of determination $R^{2}$ of 95% and 85% regarding hierarchical and flattened synthesis results, respectively. Moreover, all the pin-to-pin delays are corrected to consider flattened results and obtain realistic timing metrics. Fake Timer back-annotates timing to RTL blocks, even if they no longer appear in the flattened netlist. In this way, timing-driven micro-architecture search is enabled at the early stages of the design flow.

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