Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams

A primary aim of Coarse-Grained Reconfigurable Arrays (CGRAs), compared to FPGAs, is to maximize the portion of the die used for computational resources, while minimizing the complexity of control and steering logic, leading to inherently constrained routing architectures. This challenge has compelled CAD developers to utilize exact solutions, such as integer linear programming (ILP), in formulating and solving the mapping problem. Those solutions have been shown not to scale, especially for larger devices with intricate architectural features, such as multiple contexts and optional pipeline registers. Even if an exact or a greedy approach yields a feasible solution, it often fails to optimize multifaceted objective criteria. In this work, we have devised a framework for systematically enumerating mapping solutions of a subject kernel on a target CGRA using Zero- Suppressed Binary Decision Diagrams (ZDDs). To effectively manage runtime, we developed a linear algorithm that retains the best$k$solutions at each stage of the mapping flow, where both the objective function and$k$are user defined. Experimental results on a diverse range of application kernels targeting two CGRA architectures show how we can enumerate hundreds of thousands of solutions within seconds. When compared against prior methodologies, and while generating dozens of solutions, our mapper exhibits a remarkable speed advantage, ranging from one to three orders of magnitude faster than exact and heuristic approaches. Notably, when allocated the same runtime as the fastest heuristic, our framework demonstrates its efficacy by generating an impressive 105 solutions.

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