Synthesis, design and test of reversible circuits employing classical techniques

Over the last few years, research on reversible logic emerged as an important topic in many directions starting from synthesis towards test, debugging and verification as well as arithmetic designs. The motivation behind reversible computation comes from low power dissipation and close relation to quantum circuits, which, in the near future, could become a competitor to current classical circuits. As reversible circuits are still relatively new, the biggest research impact is on synthesis of such circuits. In the first part of this thesis, we present a synthesis approach to realize large reversible circuits based on classical technology mapping. The irreversible nature of most of the original algorithms makes the synthesis of reversible circuits from irreversible specifications a challenging task. A large part of the existing algorithms, although optimized in garbage bits and gate counts, are restricted to small functions, while some approaches address large functions but are costly in terms of gate count, additional lines and quantum cost. A synthesis solution for large circuits with less quantum cost and garbage bits is presented in this thesis by avoiding permutation based reversible embedding.In addition, we present an indirect way of realizing arithmetic circuits avoiding the direct translation of classical truth table with better performance with respect to various reversible parameters. We develop an improved reversible controlled adder/subtractor with overflow detection to enhance reliability. We use this adder/subtractor module with slight modification to implement some complex designs such as reversible square-root circuit, comparator for signed numbers and finally a new integrated module of reversible arithmetic logic unit, which encapsulates most of the operations in classical realization with less number of control lines. This module intends to perform the basic mathematical operations of addition, subtraction with overflow detection, comparison, as well as logic operations AND, OR, XOR and some negated logical functions such as NAND, NOR and XNOR including implication. Thus our design is very efficient and versatile with less number of lines and quantum cost.Apart from synthesis and designs, testing must also be brought onboard to accommodate the reliable implementation of reversible logic. Our final part of the thesis addresses this issue. To date, most reversible circuit fault models include stuck-at-value, missing gate fault and control point faults of Toffoli network. Now-a-days, the synthesis process is not restricted to standard reversible gates, rather some designs especially arithmetic circuits include other gates. In such realization, failures can happen due to erroneous replacements or incorrect cascading of gates, which cannot be defined with existing fault model alone. Thus in this thesis, we present two fault models namely gate replacement fault and wire replacement fault which target circuits implemented using any reversible gate library. To test such faults, three testing schemes are proposed by adopting the conventional testing methods for irreversible circuits based on Boolean Satisfiability (SAT) formulation. In particular, a new Reversible Test Miter is constructed, which, along with backtracking, speed up detection gate and wire replacement faults with less memory. In addition, on a different study, the testing feature of modular reversible design is investigated and presented in this thesis showing that the same test set of basic block is applicable for cascaded design. We hope our effort on synthesis, design and test of reversible circuits will enrich their viable technological realization.

Récupéré en direct depuis OpenAlex et désinversé. Les résumés ne sont pas conservés dans cette base de données : les index inversés représentent 8,6 Go des 9,3 Go de texte de la base, et le serveur dispose de 13 Go libres.