An overview of technology, architecture and CAD tools for programmable logic devices
Why this work is in the frame
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Bibliographic record
Abstract
Before the advent of programmable logic devices (PLDs), most digital hardware designs included significant numbers of small-scale integrated (SSI) circuits that comprised basic logic gates and flip-flops. However, modem designs contain virtually none of these low-density parts, but instead are built from more complex devices that consist of an uncommitted array of logic gates and memory elements that can be configured by the user to implement different circuits. The term programmable logic device is not easy to define because the assortment of chips that fall within this broad category, namely any integrated circuit that is programmable by the end user and intended for implementing hardware, has grown very large over the past few years. In fact, even the relevant terminology has become nebulous because of rapid technology changes and the introduction of new innovative architectures. The purpose of this paper is to provide an overview of programmable logic devices in order to present the reader with a clear view of what is available on the market today. The fundamental technologies employed to manufacture PLDs are presented, after which for each of the three categories of chips, namely simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field-programmable gate arrays (FPGAs), the paper describes the most significant architectural features, examples of applications, and the CAD tool design now typically used when implementing circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it