A CMOS Integrated Linear Voltage-to-Pulse-Delay-Time Converter for Time Based Analog-to-Digital Converters
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Bibliographic record
Abstract
A novel 0.13mum CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC architecture uses current starved inverters where the inverter delay versus input voltage characteristic is linearized by using several parallel current starving devices with different gate bias voltages and different amounts of source degeneration. The VTC operates at a clock frequency of up to 500 MHz. Input voltage signals of up to 2 GHz can be converted to pulse time delays by using several VTC's in parallel. Since the voltage to time conversion is essentially done with a single inverter stage no sample-and-hold is needed for the input voltage. The VTC can be used in combination with a time-to-digital converter (TDC) to build a simple high speed, low power, time based analog-to-digital converter (ADC) that consumes very little chip area
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.001 | 0.002 |
Machine scores (provisional)
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Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
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