Adaptive Thread Management For Power, Temperature, And Reliability In Future Microprocessors
Bibliographic record
Abstract
With continued scaling of CMOS technology, power, thermal, and reliability issues threaten to significantly limit future performance improvements. The advent of microprocessors with multiple processing units creates a new opportunity to address these concerns through low-cost adaptive thread management techniques. In this dissertation we devise two types of dynamic management schemes, thread migration and power management, which leverage the inherent architectural characteristics of future microprocessors to dramatically mitigate thermal hotspots, variations, and hard faults. These techniques are applied both within the core, in clustered simultaneous multithreaded (SMT) architectures, and among the cores of unpredictably heterogeneous chip multiprocessors (CMPs). First, we investigate dynamic thermal management (DTM) in clustered SMT architectures. We propose novel thread migration algorithms that leverage the steering mechanism inherent in clustered architectures to cool hotspots more effectively than dynamic voltage and frequency scaling (DVFS) when executing thermally nonuniform workloads. In addition, we create a DTM mechanism that combines intelligent steering with DVFS power management to achieve efficient thermal control across all workloads. In future large-scale multi-core microprocessors, hard faults and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ among the cores in an unanticipated manner. Contemporary CMP thread managers are oblivious to this heterogeneity, resulting in significant performance losses and excess power dissipation. We develop operation system scheduling and global power management policies, which significantly reduce the loss in power-performance efficiency. We further explore the scalability of these algorithms to many-core architectures with four to two-hundred fifty-six cores and devise novel, scalable runtime management techniques which achieve high performance with low overhead.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.001 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".