Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters
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Bibliographic record
Abstract
SUMMARY A systolic architecture has recently been proposed for implementing two‐dimensional infinite impulse response (IIR) space–time beam plane‐wave filters at a throughput of one‐frame‐per‐clock–cycle for such applications as real‐time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M‐frames‐per‐clock‐cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look‐ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock‐cycle limit of the very large‐scale integration (VLSI) technology, thereby potentially allowing multi‐GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array‐based real‐time prototype is described, tested and verified for the two‐phase case ( M = 2) at a technology‐limited clock frequency of 50 MHz which corresponds to a throughput of 100 million‐frames‐per‐clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.
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Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.000 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
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Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
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