A Low-Complexity Dual-Voltage-Loop Digital Control Architecture With Dynamically Varying Voltage and Current References
Bibliographic record
Abstract
In this paper, a low-complexity dual-voltage-loop digital control architecture is presented for voltage regulators (VRs), delivering power to processors. The proposed digital control architecture uses low speed and less complex digital-to-analog converters instead of high-speed analog-to-digital converters, thus significantly reducing the system complexity and cost. In this control architecture, there are two voltage loops, and the voltage reference is dynamically generated to selectively track one of them, as compared to other control methods where the output voltage tracks the voltage reference. Moreover, a straightforward control law is used, which does not require any compensator, making the proposed digital architecture simple and easy to implement. The dual-voltage-loop architecture breaks dependence between the system transient response and the system control bandwidth. One voltage loop is designed for the stable system operation, and the other is dedicated for the load transient response. Thus, the digital controller can be designed in such a way that the VR operates at a relatively low switching frequency to reduce power losses, and at the same time, it is also able to provide fast transient response. The proposed small signal model reveals that the inner current loop is analog and the voltage loop is digital. The proposed controller thus can benefit from both: having valuable features of digital control but without limitations such as limit cycle, which is eliminated by the inherent dithering characteristic. Theoretical, simulation and experimental results prove the effective operation and excellent dynamic performance of the low-complexity digital controller, thus making it a valuable candidate for a high-volume, low-cost digital controller for processors' VRs.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.001 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.002 | 0.000 |
| Research integrity | 0.001 | 0.001 |
| Insufficient payload (model declined to judge) | 0.003 | 0.001 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".