STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing
Why this work is in the frame
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Bibliographic record
Abstract
The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35fJ read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it