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Record W2132001925 · doi:10.1177/0037549708091537

FPGA-based Ultra-Low Latency HIL Fault Testing of a Permanent Magnet Motor Drive using RT-LAB-XSG

2008· article· en· W2132001925 on OpenAlex

Why this work is in the frame

A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.

affAt least one author lists a Canadian institution in the pinned OpenAlex snapshot.

Bibliographic record

VenueSIMULATION · 2008
Typearticle
Languageen
FieldEngineering
TopicReal-time simulation and control systems
Canadian institutionsOpal-Rt Technologies (Canada)
Fundersnot available
KeywordsResolverField-programmable gate arrayComputer scienceHardware-in-the-loop simulationVHDLEncoderEmbedded systemReal-time simulationSimulationChip

Abstract

fetched live from OpenAlex

Presented is a real-time simulator of a permanent magnet synchronous motor (PMSM) drive implemented on an FPGA card. Real-time simulation of PMSM drives enables thorough testing of control strategies and software protection routines and therefore allows rapid deployment of vehicular or industrial applications. The proposed PMSM model is a phase domain model with sinusoidal flux induction. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented on an FPGA chip, without any VHDL coding, with the RT-LAB real-time simulation platform of Opal-RT Technologies using a Simulink blockset called Xilinx System Generator (XSG). The paper explains various aspects of the design of the motor drive models in fixed-point representation in XSG, as well as simulation validation against a standard PMSM drive model built in Simulink. The PMSM drive, along with a open-loop test source for the pulse width modulation, is coded for an FPGA card. The model has user-selectable dead time, modulation index, source angle offset, and frequency. The PMSM drive is completed with various encoder models (quadrature, Hall effects and resolver). The overall model compilation and simulation is entirely automated by RT-LAB. The drive can also run in a closed loop with a controller executing on a CPU of a real-time simulator. The phase-domain PMSM drive model runs with an equivalent 10 nanosecond time step (100 MHz FPGA card) and has a latency of 300 nanoseconds (PMSM machine and inverter). The motor drive is directly connected to digital inputs and analog outputs with 1 microsecond settling time on the FPGA card and has a resulting total hardware-in-the-loop latency of 1.3 microseconds.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Simulation or modeling · Consensus signal: Simulation or modeling
GenreCandidate signal: Empirical · Consensus signal: Empirical
Teacher disagreement score0.086
Threshold uncertainty score0.815

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.000
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0000.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.026
GPT teacher head0.237
Teacher spread0.212 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it