The gem5 simulator
Why is this work in the frame?
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Abstract
The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86). The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
The record
- Venue
- ACM SIGARCH Computer Architecture News
- Topic
- Parallel Computing and Optimization Techniques
- Field
- Computer Science
- Canadian institutions
- Advanced Micro Devices (Canada)
- Funders
- Türkiye Bilimsel ve Teknolojik Araştırma Kurumu
- Keywords
- x86Computer scienceARM architectureBootingOperating systemEmbedded systemSoftware
- Has abstract in OpenAlex
- yes