An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs
Bibliographic record
Abstract
Field programmable gate arrays (FPGAs) are commonly used as an inexpensive and flexible implementation platform for system-on-chip (SoC) designs. Now that FPGAs are large enough to implement SoCs, the reprogrammable fabric allows a different approach to the design process where on-chip computer aided design (CAD) tools can leverage reconfigurability to reduce design time. Statistics on commercial SoC designs suggest that 50% or more of design time may be spent on testing and verification due to design complexity. In previous work, we have proposed the systems integrating modules with predefined physical links (SIMPPL) SoC architectural framework to improve the design process. The defined communication links and protocols have been used to reduce integration time by an order of magnitude. In this paper, we propose an on-chip testbed that leverages both SIMPPL and an FPGApsilas reconfigurability to enable onchip testing and verification in real time using run time traffic patterns to reduce design time. The proposed testbed requires 331 LUTs and 224 flipflops for the Transmitter and 31 LUTs and 30 flipflops for the receiver. This testbed is able to generate a variety of possible run time traffic patterns that may be used to verify the operation of the CE.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".