Embedded memory in system-on-chip design: architecture and prototype implementation
Why this work is in the frame
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Bibliographic record
Abstract
Advances in microelectronics fabrication technology have created new opportunities for system designers to employ embedded DRAM in system-on-chip (SoC) designs. This paper discusses an embedded DRAM architecture and its prototype implementation. The architecture consists of multiple memory banks, each with a row buffer to hold a subset of recently-accessed rows. The memory banks use either contiguous or interleaved addressing, and the row buffer in each bank uses either direct-mapping or full-associativity to map rows from the DRAM array into the buffer. A write bypass feature is also supported for the row buffer. A prototype memory bank implementation has been developed in VHDL for a programmable logic chip using embedded SRAM memory blocks to emulate a DRAM array. A single 256/spl times/256 memory bank uses only 4% of the logic capacity of a Xilinx XCV2000E chip and 10% of the embedded memory. Operational results demonstrate the functionality of the implementation for read and write accesses.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it