Top-Gate Nanocrystalline Silicon Thin Film Transistors

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses.
\nIn our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity.
\nBased on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time.
\nQuantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric.
\nMaterial and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

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