Optimization techniques for distributed logic simulation

Gate level simulation is a necessary step to verify the correctness of a circuitdesign before fabrication. It is a very time-consuming application, especially in lightof current circuit sizes. Since circuits are continually growing in size and complexity,there is a need for more efficient simulation techniques to keep the circuit verificationtime acceptably small. The use of parallel or distributed simulation is such a technique.When executed on a network of workstations, distributed simulation is alsoa very cost-effective technique. This research focuses on optimization techniques forTime Warp based gate-level logic simulations. The techniques which are described inthis thesis are oriented towards distributed platforms. The first major contributionof this thesis was the creation of an object oriented distributed simulator, XTW. Ituses an optimistic synchronization algorithm and incorporates a number of knownoptimization techniques targeting different aspects of distributed logic simulation.XEQ, an O(1) event scheduling algorithm for this simulator was developed for usein XTW. XEQ enabled us to execute gate level simulations up to 9.4 times fasterthan the same simulator using a skip-list (O(lg n)) event queue. rb-messagea mechanism which reduces the cost of rollback in Time Warp was also developedfor use in XTW. Our experiments revealed that the rb-message mechanism reducedthe number of anti-messages sent in a Time Warp based logic simulation by 76%on average. Moreover, based on the observations that (1)not all circuits should besimulated in parallel and (2) different circuits achieve their best parallel simulationperformance with a different number of compute nodes, an algorithm that uses theK-NN machine learning algorithm was devised to determine the most effective softwareand hardware combination for a logic simulation. After an extensive trainingregime, it was shown to make a correct prediction 99% of the time on whether touse a parallel or sequential simulator. The predicted number of nodes to use on aparallel platform was shown to produce an average execution time which was notmore than 12% of the smallest execution time. The configuration which resulted inthe minimal execution time was picked 61% of the time. A final contribution of thisthesis is an effort to link together commercial single processor simulators making useof Verilog PLI.

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