InfiniBand-Based Real-Time Simulation of HVDC, STATCOM, and SVC Devices with Commercial-Off-The-Shelf PCs and FPGAs
Bibliographic record
Abstract
This paper presents a real-time simulator for large power networks based on commercial-off-the-shelf products and the RT-LAB platform developed by Opal-RT Technologies Inc. This platform uses Pentium-, Xeon-, or Opteron-based PCs (multi-CPUs and/or dual-core configurations) or even Xilinx FPGA cards for computational engines, and infiniband communication fabric for fast inter-PC communication. The real-time PCs run under well-known operating systems QNX or RedHawk Linux, while the main control interface is either Simulink software from MathWorks or Lab VIEW software from National Instruments. The paper demonstrates the real-time simulation of a complete, single-pole, 12-pulse, HVDC system on a 2.2 GHz, dual-CPU, dual-core, Opteron PC with an under 15-microsecond time step. Also demonstrated are real-time simulations of complex power system devices like SVCs, STATCOMs, and more general power systems like the Kundur network. The paper also discusses the latest advances in hardware-in-the-loop simulation, including directly programming devices like a PMSM drive in an FPGA card. This feature is enabled in RT-LAB with the Xilinx System Generator, a Simulink blockset. Such FPGA targeting diminishes further the leap between prototype and production-type controller systems because an FPGA card can implement rapid control functions along with fast protection systems, like IGBT-current protection, of a real controller
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.001 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.001 |
| Insufficient payload (model declined to judge) | 0.005 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".