An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology
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Bibliographic record
Abstract
In this paper, a low-leakage PMOS based transient clamp with a thyristor as a delay element in 65 nm general-purpose (GP) CMOS technology is presented. Simulation results show that the proposed clamp is capable of protecting the circuit core against ±1.5 kV HBM and ±125 V CDM ESD stress by limiting the voltage across it to less than 5 V. The proposed clamp was characterized over PVT conditions with 2200 different combinations to investigate the selectivity to power-on ramp rates. Extensive analysis and measurements demonstrate that the clamp is robust against false triggering and transient induced latch-up. Measurement results show that the clamp is capable of handling 3.82 A, while its leakage is only 494 pA at room temperature. HBM and CDM measurement results show that the proposed clamp passed +3.25 kV and -1.75 kV HBM stresses and +800 V and -550 V CDM stresses.
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Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.001 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
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Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
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