Verified Multicore Parallelism Using Atomic Verifiable Operations
Bibliographic record
Abstract
Michal Dobrogost, Christopher Kumar Anand, and Wolfram Kahl Department of Computing and Software, McMaster University, Hamilton, Ontario, Canada 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.1.1 Novelty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1.2 Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1.3 Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.1 Map Modification Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.2 Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.3 Disjoint Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.3 Background and Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.3.1 Concurrency Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.3.2 Motivating Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.3 Strictly Forward Inspection of Partial Order . . . . . . . . . . . 116 4.3.4 The Follows Map (Φ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.5 Φ Slices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3.6 Discussion of the Follows Map (Φ) . . . . . . . . . . . . . . . . . . . . . . 119 4.3.7 Merging Φ Slices to Strengthen Our Partial Order . . . . . 121 4.3.8 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.9 Verification Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4 The Loop AVOp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.4.1 Loop AVOp Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.2 Loop Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.5 Efficient Verification of Looping Programs . . . . . . . . . . . . . . . . . . . . . . 126 4.5.1 Locally Sequential Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.5.2 Bumping State to the Next Iteration via Λ . . . . . . . . . . . . . 127 4.5.3 Loop Short Circuit Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.4 Verifying Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.5.5 Verifier Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.6 Rewritable Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Architecture, 4.6.1 Motivating Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.6.2 The Rewrite Map: ρ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.6.3 Formulation of AVOps as Functions on the State . . . . . . . 136 4.6.4 Induced Rewrites and Rewriting AVOps . . . . . . . . . . . . . . . . 137 4.6.5 Short Circuit Theorem for Rewritable Loops . . . . . . . . . . . 138 4.6.6 Verifier Run Time on Rewritable Loops . . . . . . . . . . . . . . . . 140 4.6.7 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.7 Extension to Full AVOp Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.7.1 Extension of AVOp State and Hazard Checking . . . . . . . . 142 4.7.2 Extension of the Rewrite Map . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.7.3 Extension of Loops for Accessing Global Memory . . . . . . 146 4.7.4 Extension of Verification Algorithm . . . . . . . . . . . . . . . . . . . . . 147 4.8 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.8.1 Restricted Global Memory Access for Verification . . . . . . 147 4.8.2 Stronger Short Circuit Theorem for Rewritable Loops . 148 4.8.3 Breaking up AVOp Streams to Increase AVOp Feed Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.8.4 Verifying the Verifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.8.5 Modifications for Cached Memory Multicore Processors 149 4.8.6 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.8.7 Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Parallel computer architectures have now become almost universal, with even mobile phones containing dual core processors. Taking full advantage of the performance available in a computer system requires taking full advantage of the parallelism offered by that system. Opposed to the need for high performance is the need to verify the code’s requirements. Programming such architectures has long been recognized as a difficult task. Both requirements for performance and verifiability are difficult to attain.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.003 | 0.015 |
| Meta-epidemiology (narrow) | 0.001 | 0.001 |
| Meta-epidemiology (broad) | 0.001 | 0.001 |
| Bibliometrics | 0.001 | 0.001 |
| Science and technology studies | 0.001 | 0.003 |
| Scholarly communication | 0.003 | 0.005 |
| Open science | 0.002 | 0.005 |
| Research integrity | 0.001 | 0.003 |
| Insufficient payload (model declined to judge) | 0.010 | 0.002 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".