Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage
Bibliographic record
Abstract
With the end of Dennard scaling, FPGA power consumption has become a major concern. While FPGAs are conventionally supplied by a fixed supply voltage (Vdd), recent industrial (SmartVID) and academic solutions (dynamic voltage scaling) have shown significant power savings by scaling the FPGA Vdd on a chip-specific or chip-and application-specific basis. However, FPGAs have historically been designed for fixed-Vdd operation, which raises the question of whether we can design FPGA circuitry that is better suited for voltage scaling. In this work, we show that conventional LUTs are more sensitive to voltage than routing, so we design different LUT circuits that are more tolerant to voltage scaling. Compared to a conventional LUT, our fastest proposed LUT reduces the average critical path delay by 14% and 47% at nominal (0.8 V) Vdd and at reduced (0.6 V) Vdd, respectively. This significant reduction in delay comes at a cost of only 8% FPGA tile area increase. Our proposed LUT designs result in lower energy-delay and energy-delay^2 products at nominal Vdd and below.
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How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.001 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".