Bibliographic record
Abstract
Since the dawn of electronics, the energy efficiency of computation has been a driving force for change, motivating disruptive technology advances from vacuum tubes to discrete semiconductor devices to ultra-large-scale integrated circuits [1]. Modern society’s reliance on the electronics behind digital hardware will continue to grow, with accelerating demand for computing power driven by advances such as artificial intelligence and machine learning. Improving energy efficiency while maintaining functional density of integrated electronics is widely acknowledged as the most important technological challenge for electronics in the 21st century [2-7]. The thermodynamic limit to irreversible computation at room temperature is ~ kBT ln 2 = 18 meV per bit of information erasure, corresponding roughly to a limit of 18 meV per logical operation in a transistor based logic. By contrast, the energy consumed in a modern integrated circuit per logical operation is of the order 104-105 kBT ~ 0.6-6 keV, as a result of the energy consumed to transmit information between transistors by charging interconnect capacitance up to the operating voltage of the transistor. The mean energy consumed per transistor per clock-cycle in a digital circuit [7]: E = CV 2 [α + (I off/I on)β] where C ~ 10 fF is the average load capacitance dominated by interconnects, V ~ 1 V is the transistor operating voltage, α ~ 1% is the fraction of transistors that switch per clock-cycle, I on/I off ~ 106 is the on/off current ratio of the transistor, and β ~ 100-1000 is the ratio of clock period (~1 ns) to the intrinsic transistor switching delay time (~1 ps). Improving the energy efficiency of a transistor circuit can thus be achieved by reducing operating voltage V while maintaining the on/off current ratio I on/I off . Transistors are limited by the sub-threshold swing of current versus voltage, S = ∂VG/∂log(ID), which is typically subject to the thermionic limit ~(kT/e)×ln10 ≈ 60 mV/decade, although tunneling transistors can modestly surpass this limit but at the cost of a significant loss of current drive [2-7]. Switches with improved sub-threshold swing S are known as steep-slope devices. We propose a new approach to energy efficient electronics, consisting of nanomechanical suspended graphene steep-slope switches. The mechanical properties of graphene are ideally suited to nanoelectromechanical systems (NEMS). Graphene’s Young’s modulus Y ~ 1 TPa [8] is higher than any other material, but the atomic thinness of graphene t = 0.34 nm results in an elastic modulus for deflection of Ee = Et/(1−υ) ~ 400 N/m for an unstrained membrane. Graphene monolayers are the most flexible membranes known, and thus require less voltage than any other membrane for electrostatically actuated deflection. Adopting graphene as a membrane material can in principle achieve a ~10 fold reduction in operating voltage to ~0.1 V and thus a ~100 fold reduction in switching energy, as a direct result of suspended monolayer graphene’s uniquely low deflection modulus [9]. Experimental realization of such low-voltage operation poses challenges in device fabrication and scaling. References: [1] G. Moore, Electronics 38, 114 (1965). [2] A. M. Ionescu and H. Riel, Nature 479, 329 (2011). [3] A. Seabaugh, IEEE Spectrum (2013). [4] T. N. Theis and P. M. Solomon, Proc. IEEE 98, 2005 (2010). [5] V. Pott, H. Kam, R. Nathanael, J. Jeon, E. Alon and T.-J. K. Liu, Proc. IEEE 98, 2076 (2010). [6] A. Seabaugh and Q. Zhang, Proc. IEEE 98, 2095 (2010). [7] T. N. Theis and P. M. Solomon, Science 327,1591 (2010). [8] C. Lee, X. Wei, J. Kysar, & J. Hone, Science 321, 385–388 (2008). [9] M AbdelGhany, T Szkopek, Appl. Phys. Lett. 104, 013509 (2014).
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.001 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.001 | 0.000 |
| Scholarly communication | 0.001 | 0.002 |
| Open science | 0.001 | 0.001 |
| Research integrity | 0.002 | 0.002 |
| Insufficient payload (model declined to judge) | 0.032 | 0.011 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".